1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 ARM Ltd. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/kernel.h> 8 #include <linux/mm.h> 9 #include <linux/prctl.h> 10 #include <linux/sched.h> 11 #include <linux/sched/mm.h> 12 #include <linux/string.h> 13 #include <linux/swap.h> 14 #include <linux/swapops.h> 15 #include <linux/thread_info.h> 16 #include <linux/types.h> 17 #include <linux/uio.h> 18 19 #include <asm/barrier.h> 20 #include <asm/cpufeature.h> 21 #include <asm/mte.h> 22 #include <asm/ptrace.h> 23 #include <asm/sysreg.h> 24 25 u64 gcr_kernel_excl __ro_after_init; 26 27 static bool report_fault_once = true; 28 29 #ifdef CONFIG_KASAN_HW_TAGS 30 /* Whether the MTE asynchronous mode is enabled. */ 31 DEFINE_STATIC_KEY_FALSE(mte_async_mode); 32 EXPORT_SYMBOL_GPL(mte_async_mode); 33 #endif 34 35 static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) 36 { 37 pte_t old_pte = READ_ONCE(*ptep); 38 39 if (check_swap && is_swap_pte(old_pte)) { 40 swp_entry_t entry = pte_to_swp_entry(old_pte); 41 42 if (!non_swap_entry(entry) && mte_restore_tags(entry, page)) 43 return; 44 } 45 46 page_kasan_tag_reset(page); 47 /* 48 * We need smp_wmb() in between setting the flags and clearing the 49 * tags because if another thread reads page->flags and builds a 50 * tagged address out of it, there is an actual dependency to the 51 * memory access, but on the current thread we do not guarantee that 52 * the new page->flags are visible before the tags were updated. 53 */ 54 smp_wmb(); 55 mte_clear_page_tags(page_address(page)); 56 } 57 58 void mte_sync_tags(pte_t *ptep, pte_t pte) 59 { 60 struct page *page = pte_page(pte); 61 long i, nr_pages = compound_nr(page); 62 bool check_swap = nr_pages == 1; 63 64 /* if PG_mte_tagged is set, tags have already been initialised */ 65 for (i = 0; i < nr_pages; i++, page++) { 66 if (!test_and_set_bit(PG_mte_tagged, &page->flags)) 67 mte_sync_page_tags(page, ptep, check_swap); 68 } 69 } 70 71 int memcmp_pages(struct page *page1, struct page *page2) 72 { 73 char *addr1, *addr2; 74 int ret; 75 76 addr1 = page_address(page1); 77 addr2 = page_address(page2); 78 ret = memcmp(addr1, addr2, PAGE_SIZE); 79 80 if (!system_supports_mte() || ret) 81 return ret; 82 83 /* 84 * If the page content is identical but at least one of the pages is 85 * tagged, return non-zero to avoid KSM merging. If only one of the 86 * pages is tagged, set_pte_at() may zero or change the tags of the 87 * other page via mte_sync_tags(). 88 */ 89 if (test_bit(PG_mte_tagged, &page1->flags) || 90 test_bit(PG_mte_tagged, &page2->flags)) 91 return addr1 != addr2; 92 93 return ret; 94 } 95 96 void mte_init_tags(u64 max_tag) 97 { 98 static bool gcr_kernel_excl_initialized; 99 100 if (!gcr_kernel_excl_initialized) { 101 /* 102 * The format of the tags in KASAN is 0xFF and in MTE is 0xF. 103 * This conversion extracts an MTE tag from a KASAN tag. 104 */ 105 u64 incl = GENMASK(FIELD_GET(MTE_TAG_MASK >> MTE_TAG_SHIFT, 106 max_tag), 0); 107 108 gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK; 109 gcr_kernel_excl_initialized = true; 110 } 111 112 /* Enable the kernel exclude mask for random tags generation. */ 113 write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1); 114 } 115 116 static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) 117 { 118 /* Enable MTE Sync Mode for EL1. */ 119 sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf); 120 isb(); 121 122 pr_info_once("MTE: enabled in %s mode at EL1\n", mode); 123 } 124 125 #ifdef CONFIG_KASAN_HW_TAGS 126 void mte_enable_kernel_sync(void) 127 { 128 /* 129 * Make sure we enter this function when no PE has set 130 * async mode previously. 131 */ 132 WARN_ONCE(system_uses_mte_async_mode(), 133 "MTE async mode enabled system wide!"); 134 135 __mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC); 136 } 137 138 void mte_enable_kernel_async(void) 139 { 140 __mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC); 141 142 /* 143 * MTE async mode is set system wide by the first PE that 144 * executes this function. 145 * 146 * Note: If in future KASAN acquires a runtime switching 147 * mode in between sync and async, this strategy needs 148 * to be reviewed. 149 */ 150 if (!system_uses_mte_async_mode()) 151 static_branch_enable(&mte_async_mode); 152 } 153 #endif 154 155 void mte_set_report_once(bool state) 156 { 157 WRITE_ONCE(report_fault_once, state); 158 } 159 160 bool mte_report_once(void) 161 { 162 return READ_ONCE(report_fault_once); 163 } 164 165 #ifdef CONFIG_KASAN_HW_TAGS 166 void mte_check_tfsr_el1(void) 167 { 168 u64 tfsr_el1; 169 170 if (!system_supports_mte()) 171 return; 172 173 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1); 174 175 if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) { 176 /* 177 * Note: isb() is not required after this direct write 178 * because there is no indirect read subsequent to it 179 * (per ARM DDI 0487F.c table D13-1). 180 */ 181 write_sysreg_s(0, SYS_TFSR_EL1); 182 183 kasan_report_async(); 184 } 185 } 186 #endif 187 188 static void update_gcr_el1_excl(u64 excl) 189 { 190 191 /* 192 * Note that the mask controlled by the user via prctl() is an 193 * include while GCR_EL1 accepts an exclude mask. 194 * No need for ISB since this only affects EL0 currently, implicit 195 * with ERET. 196 */ 197 sysreg_clear_set_s(SYS_GCR_EL1, SYS_GCR_EL1_EXCL_MASK, excl); 198 } 199 200 static void set_gcr_el1_excl(u64 excl) 201 { 202 current->thread.gcr_user_excl = excl; 203 204 /* 205 * SYS_GCR_EL1 will be set to current->thread.gcr_user_excl value 206 * by mte_set_user_gcr() in kernel_exit, 207 */ 208 } 209 210 void mte_thread_init_user(void) 211 { 212 if (!system_supports_mte()) 213 return; 214 215 /* clear any pending asynchronous tag fault */ 216 dsb(ish); 217 write_sysreg_s(0, SYS_TFSRE0_EL1); 218 clear_thread_flag(TIF_MTE_ASYNC_FAULT); 219 /* disable tag checking */ 220 set_task_sctlr_el1((current->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK) | 221 SCTLR_EL1_TCF0_NONE); 222 /* reset tag generation mask */ 223 set_gcr_el1_excl(SYS_GCR_EL1_EXCL_MASK); 224 } 225 226 void mte_thread_switch(struct task_struct *next) 227 { 228 /* 229 * Check if an async tag exception occurred at EL1. 230 * 231 * Note: On the context switch path we rely on the dsb() present 232 * in __switch_to() to guarantee that the indirect writes to TFSR_EL1 233 * are synchronized before this point. 234 */ 235 isb(); 236 mte_check_tfsr_el1(); 237 } 238 239 void mte_suspend_enter(void) 240 { 241 if (!system_supports_mte()) 242 return; 243 244 /* 245 * The barriers are required to guarantee that the indirect writes 246 * to TFSR_EL1 are synchronized before we report the state. 247 */ 248 dsb(nsh); 249 isb(); 250 251 /* Report SYS_TFSR_EL1 before suspend entry */ 252 mte_check_tfsr_el1(); 253 } 254 255 void mte_suspend_exit(void) 256 { 257 if (!system_supports_mte()) 258 return; 259 260 update_gcr_el1_excl(gcr_kernel_excl); 261 } 262 263 long set_mte_ctrl(struct task_struct *task, unsigned long arg) 264 { 265 u64 sctlr = task->thread.sctlr_user & ~SCTLR_EL1_TCF0_MASK; 266 u64 gcr_excl = ~((arg & PR_MTE_TAG_MASK) >> PR_MTE_TAG_SHIFT) & 267 SYS_GCR_EL1_EXCL_MASK; 268 269 if (!system_supports_mte()) 270 return 0; 271 272 switch (arg & PR_MTE_TCF_MASK) { 273 case PR_MTE_TCF_NONE: 274 sctlr |= SCTLR_EL1_TCF0_NONE; 275 break; 276 case PR_MTE_TCF_SYNC: 277 sctlr |= SCTLR_EL1_TCF0_SYNC; 278 break; 279 case PR_MTE_TCF_ASYNC: 280 sctlr |= SCTLR_EL1_TCF0_ASYNC; 281 break; 282 default: 283 return -EINVAL; 284 } 285 286 if (task != current) { 287 task->thread.sctlr_user = sctlr; 288 task->thread.gcr_user_excl = gcr_excl; 289 } else { 290 set_task_sctlr_el1(sctlr); 291 set_gcr_el1_excl(gcr_excl); 292 } 293 294 return 0; 295 } 296 297 long get_mte_ctrl(struct task_struct *task) 298 { 299 unsigned long ret; 300 u64 incl = ~task->thread.gcr_user_excl & SYS_GCR_EL1_EXCL_MASK; 301 302 if (!system_supports_mte()) 303 return 0; 304 305 ret = incl << PR_MTE_TAG_SHIFT; 306 307 switch (task->thread.sctlr_user & SCTLR_EL1_TCF0_MASK) { 308 case SCTLR_EL1_TCF0_NONE: 309 ret |= PR_MTE_TCF_NONE; 310 break; 311 case SCTLR_EL1_TCF0_SYNC: 312 ret |= PR_MTE_TCF_SYNC; 313 break; 314 case SCTLR_EL1_TCF0_ASYNC: 315 ret |= PR_MTE_TCF_ASYNC; 316 break; 317 } 318 319 return ret; 320 } 321 322 /* 323 * Access MTE tags in another process' address space as given in mm. Update 324 * the number of tags copied. Return 0 if any tags copied, error otherwise. 325 * Inspired by __access_remote_vm(). 326 */ 327 static int __access_remote_tags(struct mm_struct *mm, unsigned long addr, 328 struct iovec *kiov, unsigned int gup_flags) 329 { 330 struct vm_area_struct *vma; 331 void __user *buf = kiov->iov_base; 332 size_t len = kiov->iov_len; 333 int ret; 334 int write = gup_flags & FOLL_WRITE; 335 336 if (!access_ok(buf, len)) 337 return -EFAULT; 338 339 if (mmap_read_lock_killable(mm)) 340 return -EIO; 341 342 while (len) { 343 unsigned long tags, offset; 344 void *maddr; 345 struct page *page = NULL; 346 347 ret = get_user_pages_remote(mm, addr, 1, gup_flags, &page, 348 &vma, NULL); 349 if (ret <= 0) 350 break; 351 352 /* 353 * Only copy tags if the page has been mapped as PROT_MTE 354 * (PG_mte_tagged set). Otherwise the tags are not valid and 355 * not accessible to user. Moreover, an mprotect(PROT_MTE) 356 * would cause the existing tags to be cleared if the page 357 * was never mapped with PROT_MTE. 358 */ 359 if (!(vma->vm_flags & VM_MTE)) { 360 ret = -EOPNOTSUPP; 361 put_page(page); 362 break; 363 } 364 WARN_ON_ONCE(!test_bit(PG_mte_tagged, &page->flags)); 365 366 /* limit access to the end of the page */ 367 offset = offset_in_page(addr); 368 tags = min(len, (PAGE_SIZE - offset) / MTE_GRANULE_SIZE); 369 370 maddr = page_address(page); 371 if (write) { 372 tags = mte_copy_tags_from_user(maddr + offset, buf, tags); 373 set_page_dirty_lock(page); 374 } else { 375 tags = mte_copy_tags_to_user(buf, maddr + offset, tags); 376 } 377 put_page(page); 378 379 /* error accessing the tracer's buffer */ 380 if (!tags) 381 break; 382 383 len -= tags; 384 buf += tags; 385 addr += tags * MTE_GRANULE_SIZE; 386 } 387 mmap_read_unlock(mm); 388 389 /* return an error if no tags copied */ 390 kiov->iov_len = buf - kiov->iov_base; 391 if (!kiov->iov_len) { 392 /* check for error accessing the tracee's address space */ 393 if (ret <= 0) 394 return -EIO; 395 else 396 return -EFAULT; 397 } 398 399 return 0; 400 } 401 402 /* 403 * Copy MTE tags in another process' address space at 'addr' to/from tracer's 404 * iovec buffer. Return 0 on success. Inspired by ptrace_access_vm(). 405 */ 406 static int access_remote_tags(struct task_struct *tsk, unsigned long addr, 407 struct iovec *kiov, unsigned int gup_flags) 408 { 409 struct mm_struct *mm; 410 int ret; 411 412 mm = get_task_mm(tsk); 413 if (!mm) 414 return -EPERM; 415 416 if (!tsk->ptrace || (current != tsk->parent) || 417 ((get_dumpable(mm) != SUID_DUMP_USER) && 418 !ptracer_capable(tsk, mm->user_ns))) { 419 mmput(mm); 420 return -EPERM; 421 } 422 423 ret = __access_remote_tags(mm, addr, kiov, gup_flags); 424 mmput(mm); 425 426 return ret; 427 } 428 429 int mte_ptrace_copy_tags(struct task_struct *child, long request, 430 unsigned long addr, unsigned long data) 431 { 432 int ret; 433 struct iovec kiov; 434 struct iovec __user *uiov = (void __user *)data; 435 unsigned int gup_flags = FOLL_FORCE; 436 437 if (!system_supports_mte()) 438 return -EIO; 439 440 if (get_user(kiov.iov_base, &uiov->iov_base) || 441 get_user(kiov.iov_len, &uiov->iov_len)) 442 return -EFAULT; 443 444 if (request == PTRACE_POKEMTETAGS) 445 gup_flags |= FOLL_WRITE; 446 447 /* align addr to the MTE tag granule */ 448 addr &= MTE_GRANULE_MASK; 449 450 ret = access_remote_tags(child, addr, &kiov, gup_flags); 451 if (!ret) 452 ret = put_user(kiov.iov_len, &uiov->iov_len); 453 454 return ret; 455 } 456