1 /* 2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 3 * using the CPU's debug registers. 4 * 5 * Copyright (C) 2012 ARM Limited 6 * Author: Will Deacon <will.deacon@arm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #define pr_fmt(fmt) "hw-breakpoint: " fmt 22 23 #include <linux/compat.h> 24 #include <linux/cpu_pm.h> 25 #include <linux/errno.h> 26 #include <linux/hw_breakpoint.h> 27 #include <linux/kprobes.h> 28 #include <linux/perf_event.h> 29 #include <linux/ptrace.h> 30 #include <linux/smp.h> 31 32 #include <asm/compat.h> 33 #include <asm/current.h> 34 #include <asm/debug-monitors.h> 35 #include <asm/hw_breakpoint.h> 36 #include <asm/traps.h> 37 #include <asm/cputype.h> 38 #include <asm/system_misc.h> 39 40 /* Breakpoint currently in use for each BRP. */ 41 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); 42 43 /* Watchpoint currently in use for each WRP. */ 44 static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); 45 46 /* Currently stepping a per-CPU kernel breakpoint. */ 47 static DEFINE_PER_CPU(int, stepping_kernel_bp); 48 49 /* Number of BRP/WRP registers on this CPU. */ 50 static int core_num_brps; 51 static int core_num_wrps; 52 53 int hw_breakpoint_slots(int type) 54 { 55 /* 56 * We can be called early, so don't rely on 57 * our static variables being initialised. 58 */ 59 switch (type) { 60 case TYPE_INST: 61 return get_num_brps(); 62 case TYPE_DATA: 63 return get_num_wrps(); 64 default: 65 pr_warning("unknown slot type: %d\n", type); 66 return 0; 67 } 68 } 69 70 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ 71 case (OFF + N): \ 72 AARCH64_DBG_READ(N, REG, VAL); \ 73 break 74 75 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ 76 case (OFF + N): \ 77 AARCH64_DBG_WRITE(N, REG, VAL); \ 78 break 79 80 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ 81 READ_WB_REG_CASE(OFF, 0, REG, VAL); \ 82 READ_WB_REG_CASE(OFF, 1, REG, VAL); \ 83 READ_WB_REG_CASE(OFF, 2, REG, VAL); \ 84 READ_WB_REG_CASE(OFF, 3, REG, VAL); \ 85 READ_WB_REG_CASE(OFF, 4, REG, VAL); \ 86 READ_WB_REG_CASE(OFF, 5, REG, VAL); \ 87 READ_WB_REG_CASE(OFF, 6, REG, VAL); \ 88 READ_WB_REG_CASE(OFF, 7, REG, VAL); \ 89 READ_WB_REG_CASE(OFF, 8, REG, VAL); \ 90 READ_WB_REG_CASE(OFF, 9, REG, VAL); \ 91 READ_WB_REG_CASE(OFF, 10, REG, VAL); \ 92 READ_WB_REG_CASE(OFF, 11, REG, VAL); \ 93 READ_WB_REG_CASE(OFF, 12, REG, VAL); \ 94 READ_WB_REG_CASE(OFF, 13, REG, VAL); \ 95 READ_WB_REG_CASE(OFF, 14, REG, VAL); \ 96 READ_WB_REG_CASE(OFF, 15, REG, VAL) 97 98 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ 99 WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \ 100 WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \ 101 WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \ 102 WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \ 103 WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \ 104 WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \ 105 WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \ 106 WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \ 107 WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \ 108 WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \ 109 WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \ 110 WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \ 111 WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \ 112 WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \ 113 WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ 114 WRITE_WB_REG_CASE(OFF, 15, REG, VAL) 115 116 static u64 read_wb_reg(int reg, int n) 117 { 118 u64 val = 0; 119 120 switch (reg + n) { 121 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); 122 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); 123 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); 124 GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); 125 default: 126 pr_warning("attempt to read from unknown breakpoint register %d\n", n); 127 } 128 129 return val; 130 } 131 NOKPROBE_SYMBOL(read_wb_reg); 132 133 static void write_wb_reg(int reg, int n, u64 val) 134 { 135 switch (reg + n) { 136 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); 137 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); 138 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); 139 GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); 140 default: 141 pr_warning("attempt to write to unknown breakpoint register %d\n", n); 142 } 143 isb(); 144 } 145 NOKPROBE_SYMBOL(write_wb_reg); 146 147 /* 148 * Convert a breakpoint privilege level to the corresponding exception 149 * level. 150 */ 151 static enum dbg_active_el debug_exception_level(int privilege) 152 { 153 switch (privilege) { 154 case AARCH64_BREAKPOINT_EL0: 155 return DBG_ACTIVE_EL0; 156 case AARCH64_BREAKPOINT_EL1: 157 return DBG_ACTIVE_EL1; 158 default: 159 pr_warning("invalid breakpoint privilege level %d\n", privilege); 160 return -EINVAL; 161 } 162 } 163 NOKPROBE_SYMBOL(debug_exception_level); 164 165 enum hw_breakpoint_ops { 166 HW_BREAKPOINT_INSTALL, 167 HW_BREAKPOINT_UNINSTALL, 168 HW_BREAKPOINT_RESTORE 169 }; 170 171 static int is_compat_bp(struct perf_event *bp) 172 { 173 struct task_struct *tsk = bp->hw.target; 174 175 /* 176 * tsk can be NULL for per-cpu (non-ptrace) breakpoints. 177 * In this case, use the native interface, since we don't have 178 * the notion of a "compat CPU" and could end up relying on 179 * deprecated behaviour if we use unaligned watchpoints in 180 * AArch64 state. 181 */ 182 return tsk && is_compat_thread(task_thread_info(tsk)); 183 } 184 185 /** 186 * hw_breakpoint_slot_setup - Find and setup a perf slot according to 187 * operations 188 * 189 * @slots: pointer to array of slots 190 * @max_slots: max number of slots 191 * @bp: perf_event to setup 192 * @ops: operation to be carried out on the slot 193 * 194 * Return: 195 * slot index on success 196 * -ENOSPC if no slot is available/matches 197 * -EINVAL on wrong operations parameter 198 */ 199 static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots, 200 struct perf_event *bp, 201 enum hw_breakpoint_ops ops) 202 { 203 int i; 204 struct perf_event **slot; 205 206 for (i = 0; i < max_slots; ++i) { 207 slot = &slots[i]; 208 switch (ops) { 209 case HW_BREAKPOINT_INSTALL: 210 if (!*slot) { 211 *slot = bp; 212 return i; 213 } 214 break; 215 case HW_BREAKPOINT_UNINSTALL: 216 if (*slot == bp) { 217 *slot = NULL; 218 return i; 219 } 220 break; 221 case HW_BREAKPOINT_RESTORE: 222 if (*slot == bp) 223 return i; 224 break; 225 default: 226 pr_warn_once("Unhandled hw breakpoint ops %d\n", ops); 227 return -EINVAL; 228 } 229 } 230 return -ENOSPC; 231 } 232 233 static int hw_breakpoint_control(struct perf_event *bp, 234 enum hw_breakpoint_ops ops) 235 { 236 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 237 struct perf_event **slots; 238 struct debug_info *debug_info = ¤t->thread.debug; 239 int i, max_slots, ctrl_reg, val_reg, reg_enable; 240 enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege); 241 u32 ctrl; 242 243 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 244 /* Breakpoint */ 245 ctrl_reg = AARCH64_DBG_REG_BCR; 246 val_reg = AARCH64_DBG_REG_BVR; 247 slots = this_cpu_ptr(bp_on_reg); 248 max_slots = core_num_brps; 249 reg_enable = !debug_info->bps_disabled; 250 } else { 251 /* Watchpoint */ 252 ctrl_reg = AARCH64_DBG_REG_WCR; 253 val_reg = AARCH64_DBG_REG_WVR; 254 slots = this_cpu_ptr(wp_on_reg); 255 max_slots = core_num_wrps; 256 reg_enable = !debug_info->wps_disabled; 257 } 258 259 i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops); 260 261 if (WARN_ONCE(i < 0, "Can't find any breakpoint slot")) 262 return i; 263 264 switch (ops) { 265 case HW_BREAKPOINT_INSTALL: 266 /* 267 * Ensure debug monitors are enabled at the correct exception 268 * level. 269 */ 270 enable_debug_monitors(dbg_el); 271 /* Fall through */ 272 case HW_BREAKPOINT_RESTORE: 273 /* Setup the address register. */ 274 write_wb_reg(val_reg, i, info->address); 275 276 /* Setup the control register. */ 277 ctrl = encode_ctrl_reg(info->ctrl); 278 write_wb_reg(ctrl_reg, i, 279 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); 280 break; 281 case HW_BREAKPOINT_UNINSTALL: 282 /* Reset the control register. */ 283 write_wb_reg(ctrl_reg, i, 0); 284 285 /* 286 * Release the debug monitors for the correct exception 287 * level. 288 */ 289 disable_debug_monitors(dbg_el); 290 break; 291 } 292 293 return 0; 294 } 295 296 /* 297 * Install a perf counter breakpoint. 298 */ 299 int arch_install_hw_breakpoint(struct perf_event *bp) 300 { 301 return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL); 302 } 303 304 void arch_uninstall_hw_breakpoint(struct perf_event *bp) 305 { 306 hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL); 307 } 308 309 static int get_hbp_len(u8 hbp_len) 310 { 311 unsigned int len_in_bytes = 0; 312 313 switch (hbp_len) { 314 case ARM_BREAKPOINT_LEN_1: 315 len_in_bytes = 1; 316 break; 317 case ARM_BREAKPOINT_LEN_2: 318 len_in_bytes = 2; 319 break; 320 case ARM_BREAKPOINT_LEN_3: 321 len_in_bytes = 3; 322 break; 323 case ARM_BREAKPOINT_LEN_4: 324 len_in_bytes = 4; 325 break; 326 case ARM_BREAKPOINT_LEN_5: 327 len_in_bytes = 5; 328 break; 329 case ARM_BREAKPOINT_LEN_6: 330 len_in_bytes = 6; 331 break; 332 case ARM_BREAKPOINT_LEN_7: 333 len_in_bytes = 7; 334 break; 335 case ARM_BREAKPOINT_LEN_8: 336 len_in_bytes = 8; 337 break; 338 } 339 340 return len_in_bytes; 341 } 342 343 /* 344 * Check whether bp virtual address is in kernel space. 345 */ 346 int arch_check_bp_in_kernelspace(struct perf_event *bp) 347 { 348 unsigned int len; 349 unsigned long va; 350 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 351 352 va = info->address; 353 len = get_hbp_len(info->ctrl.len); 354 355 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 356 } 357 358 /* 359 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. 360 * Hopefully this will disappear when ptrace can bypass the conversion 361 * to generic breakpoint descriptions. 362 */ 363 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 364 int *gen_len, int *gen_type, int *offset) 365 { 366 /* Type */ 367 switch (ctrl.type) { 368 case ARM_BREAKPOINT_EXECUTE: 369 *gen_type = HW_BREAKPOINT_X; 370 break; 371 case ARM_BREAKPOINT_LOAD: 372 *gen_type = HW_BREAKPOINT_R; 373 break; 374 case ARM_BREAKPOINT_STORE: 375 *gen_type = HW_BREAKPOINT_W; 376 break; 377 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: 378 *gen_type = HW_BREAKPOINT_RW; 379 break; 380 default: 381 return -EINVAL; 382 } 383 384 if (!ctrl.len) 385 return -EINVAL; 386 *offset = __ffs(ctrl.len); 387 388 /* Len */ 389 switch (ctrl.len >> *offset) { 390 case ARM_BREAKPOINT_LEN_1: 391 *gen_len = HW_BREAKPOINT_LEN_1; 392 break; 393 case ARM_BREAKPOINT_LEN_2: 394 *gen_len = HW_BREAKPOINT_LEN_2; 395 break; 396 case ARM_BREAKPOINT_LEN_3: 397 *gen_len = HW_BREAKPOINT_LEN_3; 398 break; 399 case ARM_BREAKPOINT_LEN_4: 400 *gen_len = HW_BREAKPOINT_LEN_4; 401 break; 402 case ARM_BREAKPOINT_LEN_5: 403 *gen_len = HW_BREAKPOINT_LEN_5; 404 break; 405 case ARM_BREAKPOINT_LEN_6: 406 *gen_len = HW_BREAKPOINT_LEN_6; 407 break; 408 case ARM_BREAKPOINT_LEN_7: 409 *gen_len = HW_BREAKPOINT_LEN_7; 410 break; 411 case ARM_BREAKPOINT_LEN_8: 412 *gen_len = HW_BREAKPOINT_LEN_8; 413 break; 414 default: 415 return -EINVAL; 416 } 417 418 return 0; 419 } 420 421 /* 422 * Construct an arch_hw_breakpoint from a perf_event. 423 */ 424 static int arch_build_bp_info(struct perf_event *bp) 425 { 426 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 427 428 /* Type */ 429 switch (bp->attr.bp_type) { 430 case HW_BREAKPOINT_X: 431 info->ctrl.type = ARM_BREAKPOINT_EXECUTE; 432 break; 433 case HW_BREAKPOINT_R: 434 info->ctrl.type = ARM_BREAKPOINT_LOAD; 435 break; 436 case HW_BREAKPOINT_W: 437 info->ctrl.type = ARM_BREAKPOINT_STORE; 438 break; 439 case HW_BREAKPOINT_RW: 440 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; 441 break; 442 default: 443 return -EINVAL; 444 } 445 446 /* Len */ 447 switch (bp->attr.bp_len) { 448 case HW_BREAKPOINT_LEN_1: 449 info->ctrl.len = ARM_BREAKPOINT_LEN_1; 450 break; 451 case HW_BREAKPOINT_LEN_2: 452 info->ctrl.len = ARM_BREAKPOINT_LEN_2; 453 break; 454 case HW_BREAKPOINT_LEN_3: 455 info->ctrl.len = ARM_BREAKPOINT_LEN_3; 456 break; 457 case HW_BREAKPOINT_LEN_4: 458 info->ctrl.len = ARM_BREAKPOINT_LEN_4; 459 break; 460 case HW_BREAKPOINT_LEN_5: 461 info->ctrl.len = ARM_BREAKPOINT_LEN_5; 462 break; 463 case HW_BREAKPOINT_LEN_6: 464 info->ctrl.len = ARM_BREAKPOINT_LEN_6; 465 break; 466 case HW_BREAKPOINT_LEN_7: 467 info->ctrl.len = ARM_BREAKPOINT_LEN_7; 468 break; 469 case HW_BREAKPOINT_LEN_8: 470 info->ctrl.len = ARM_BREAKPOINT_LEN_8; 471 break; 472 default: 473 return -EINVAL; 474 } 475 476 /* 477 * On AArch64, we only permit breakpoints of length 4, whereas 478 * AArch32 also requires breakpoints of length 2 for Thumb. 479 * Watchpoints can be of length 1, 2, 4 or 8 bytes. 480 */ 481 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 482 if (is_compat_bp(bp)) { 483 if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 && 484 info->ctrl.len != ARM_BREAKPOINT_LEN_4) 485 return -EINVAL; 486 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) { 487 /* 488 * FIXME: Some tools (I'm looking at you perf) assume 489 * that breakpoints should be sizeof(long). This 490 * is nonsense. For now, we fix up the parameter 491 * but we should probably return -EINVAL instead. 492 */ 493 info->ctrl.len = ARM_BREAKPOINT_LEN_4; 494 } 495 } 496 497 /* Address */ 498 info->address = bp->attr.bp_addr; 499 500 /* 501 * Privilege 502 * Note that we disallow combined EL0/EL1 breakpoints because 503 * that would complicate the stepping code. 504 */ 505 if (arch_check_bp_in_kernelspace(bp)) 506 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1; 507 else 508 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0; 509 510 /* Enabled? */ 511 info->ctrl.enabled = !bp->attr.disabled; 512 513 return 0; 514 } 515 516 /* 517 * Validate the arch-specific HW Breakpoint register settings. 518 */ 519 int arch_validate_hwbkpt_settings(struct perf_event *bp) 520 { 521 struct arch_hw_breakpoint *info = counter_arch_bp(bp); 522 int ret; 523 u64 alignment_mask, offset; 524 525 /* Build the arch_hw_breakpoint. */ 526 ret = arch_build_bp_info(bp); 527 if (ret) 528 return ret; 529 530 /* 531 * Check address alignment. 532 * We don't do any clever alignment correction for watchpoints 533 * because using 64-bit unaligned addresses is deprecated for 534 * AArch64. 535 * 536 * AArch32 tasks expect some simple alignment fixups, so emulate 537 * that here. 538 */ 539 if (is_compat_bp(bp)) { 540 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 541 alignment_mask = 0x7; 542 else 543 alignment_mask = 0x3; 544 offset = info->address & alignment_mask; 545 switch (offset) { 546 case 0: 547 /* Aligned */ 548 break; 549 case 1: 550 /* Allow single byte watchpoint. */ 551 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) 552 break; 553 case 2: 554 /* Allow halfword watchpoints and breakpoints. */ 555 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) 556 break; 557 default: 558 return -EINVAL; 559 } 560 } else { 561 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) 562 alignment_mask = 0x3; 563 else 564 alignment_mask = 0x7; 565 offset = info->address & alignment_mask; 566 } 567 568 info->address &= ~alignment_mask; 569 info->ctrl.len <<= offset; 570 571 /* 572 * Disallow per-task kernel breakpoints since these would 573 * complicate the stepping code. 574 */ 575 if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target) 576 return -EINVAL; 577 578 return 0; 579 } 580 581 /* 582 * Enable/disable all of the breakpoints active at the specified 583 * exception level at the register level. 584 * This is used when single-stepping after a breakpoint exception. 585 */ 586 static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable) 587 { 588 int i, max_slots, privilege; 589 u32 ctrl; 590 struct perf_event **slots; 591 592 switch (reg) { 593 case AARCH64_DBG_REG_BCR: 594 slots = this_cpu_ptr(bp_on_reg); 595 max_slots = core_num_brps; 596 break; 597 case AARCH64_DBG_REG_WCR: 598 slots = this_cpu_ptr(wp_on_reg); 599 max_slots = core_num_wrps; 600 break; 601 default: 602 return; 603 } 604 605 for (i = 0; i < max_slots; ++i) { 606 if (!slots[i]) 607 continue; 608 609 privilege = counter_arch_bp(slots[i])->ctrl.privilege; 610 if (debug_exception_level(privilege) != el) 611 continue; 612 613 ctrl = read_wb_reg(reg, i); 614 if (enable) 615 ctrl |= 0x1; 616 else 617 ctrl &= ~0x1; 618 write_wb_reg(reg, i, ctrl); 619 } 620 } 621 NOKPROBE_SYMBOL(toggle_bp_registers); 622 623 /* 624 * Debug exception handlers. 625 */ 626 static int breakpoint_handler(unsigned long unused, unsigned int esr, 627 struct pt_regs *regs) 628 { 629 int i, step = 0, *kernel_step; 630 u32 ctrl_reg; 631 u64 addr, val; 632 struct perf_event *bp, **slots; 633 struct debug_info *debug_info; 634 struct arch_hw_breakpoint_ctrl ctrl; 635 636 slots = this_cpu_ptr(bp_on_reg); 637 addr = instruction_pointer(regs); 638 debug_info = ¤t->thread.debug; 639 640 for (i = 0; i < core_num_brps; ++i) { 641 rcu_read_lock(); 642 643 bp = slots[i]; 644 645 if (bp == NULL) 646 goto unlock; 647 648 /* Check if the breakpoint value matches. */ 649 val = read_wb_reg(AARCH64_DBG_REG_BVR, i); 650 if (val != (addr & ~0x3)) 651 goto unlock; 652 653 /* Possible match, check the byte address select to confirm. */ 654 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i); 655 decode_ctrl_reg(ctrl_reg, &ctrl); 656 if (!((1 << (addr & 0x3)) & ctrl.len)) 657 goto unlock; 658 659 counter_arch_bp(bp)->trigger = addr; 660 perf_bp_event(bp, regs); 661 662 /* Do we need to handle the stepping? */ 663 if (is_default_overflow_handler(bp)) 664 step = 1; 665 unlock: 666 rcu_read_unlock(); 667 } 668 669 if (!step) 670 return 0; 671 672 if (user_mode(regs)) { 673 debug_info->bps_disabled = 1; 674 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0); 675 676 /* If we're already stepping a watchpoint, just return. */ 677 if (debug_info->wps_disabled) 678 return 0; 679 680 if (test_thread_flag(TIF_SINGLESTEP)) 681 debug_info->suspended_step = 1; 682 else 683 user_enable_single_step(current); 684 } else { 685 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0); 686 kernel_step = this_cpu_ptr(&stepping_kernel_bp); 687 688 if (*kernel_step != ARM_KERNEL_STEP_NONE) 689 return 0; 690 691 if (kernel_active_single_step()) { 692 *kernel_step = ARM_KERNEL_STEP_SUSPEND; 693 } else { 694 *kernel_step = ARM_KERNEL_STEP_ACTIVE; 695 kernel_enable_single_step(regs); 696 } 697 } 698 699 return 0; 700 } 701 NOKPROBE_SYMBOL(breakpoint_handler); 702 703 /* 704 * Arm64 hardware does not always report a watchpoint hit address that matches 705 * one of the watchpoints set. It can also report an address "near" the 706 * watchpoint if a single instruction access both watched and unwatched 707 * addresses. There is no straight-forward way, short of disassembling the 708 * offending instruction, to map that address back to the watchpoint. This 709 * function computes the distance of the memory access from the watchpoint as a 710 * heuristic for the likelyhood that a given access triggered the watchpoint. 711 * 712 * See Section D2.10.5 "Determining the memory location that caused a Watchpoint 713 * exception" of ARMv8 Architecture Reference Manual for details. 714 * 715 * The function returns the distance of the address from the bytes watched by 716 * the watchpoint. In case of an exact match, it returns 0. 717 */ 718 static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, 719 struct arch_hw_breakpoint_ctrl *ctrl) 720 { 721 u64 wp_low, wp_high; 722 u32 lens, lene; 723 724 lens = __ffs(ctrl->len); 725 lene = __fls(ctrl->len); 726 727 wp_low = val + lens; 728 wp_high = val + lene; 729 if (addr < wp_low) 730 return wp_low - addr; 731 else if (addr > wp_high) 732 return addr - wp_high; 733 else 734 return 0; 735 } 736 737 static int watchpoint_handler(unsigned long addr, unsigned int esr, 738 struct pt_regs *regs) 739 { 740 int i, step = 0, *kernel_step, access, closest_match = 0; 741 u64 min_dist = -1, dist; 742 u32 ctrl_reg; 743 u64 val; 744 struct perf_event *wp, **slots; 745 struct debug_info *debug_info; 746 struct arch_hw_breakpoint *info; 747 struct arch_hw_breakpoint_ctrl ctrl; 748 749 slots = this_cpu_ptr(wp_on_reg); 750 debug_info = ¤t->thread.debug; 751 752 /* 753 * Find all watchpoints that match the reported address. If no exact 754 * match is found. Attribute the hit to the closest watchpoint. 755 */ 756 rcu_read_lock(); 757 for (i = 0; i < core_num_wrps; ++i) { 758 wp = slots[i]; 759 if (wp == NULL) 760 continue; 761 762 /* 763 * Check that the access type matches. 764 * 0 => load, otherwise => store 765 */ 766 access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W : 767 HW_BREAKPOINT_R; 768 if (!(access & hw_breakpoint_type(wp))) 769 continue; 770 771 /* Check if the watchpoint value and byte select match. */ 772 val = read_wb_reg(AARCH64_DBG_REG_WVR, i); 773 ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i); 774 decode_ctrl_reg(ctrl_reg, &ctrl); 775 dist = get_distance_from_watchpoint(addr, val, &ctrl); 776 if (dist < min_dist) { 777 min_dist = dist; 778 closest_match = i; 779 } 780 /* Is this an exact match? */ 781 if (dist != 0) 782 continue; 783 784 info = counter_arch_bp(wp); 785 info->trigger = addr; 786 perf_bp_event(wp, regs); 787 788 /* Do we need to handle the stepping? */ 789 if (is_default_overflow_handler(wp)) 790 step = 1; 791 } 792 if (min_dist > 0 && min_dist != -1) { 793 /* No exact match found. */ 794 wp = slots[closest_match]; 795 info = counter_arch_bp(wp); 796 info->trigger = addr; 797 perf_bp_event(wp, regs); 798 799 /* Do we need to handle the stepping? */ 800 if (is_default_overflow_handler(wp)) 801 step = 1; 802 } 803 rcu_read_unlock(); 804 805 if (!step) 806 return 0; 807 808 /* 809 * We always disable EL0 watchpoints because the kernel can 810 * cause these to fire via an unprivileged access. 811 */ 812 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0); 813 814 if (user_mode(regs)) { 815 debug_info->wps_disabled = 1; 816 817 /* If we're already stepping a breakpoint, just return. */ 818 if (debug_info->bps_disabled) 819 return 0; 820 821 if (test_thread_flag(TIF_SINGLESTEP)) 822 debug_info->suspended_step = 1; 823 else 824 user_enable_single_step(current); 825 } else { 826 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0); 827 kernel_step = this_cpu_ptr(&stepping_kernel_bp); 828 829 if (*kernel_step != ARM_KERNEL_STEP_NONE) 830 return 0; 831 832 if (kernel_active_single_step()) { 833 *kernel_step = ARM_KERNEL_STEP_SUSPEND; 834 } else { 835 *kernel_step = ARM_KERNEL_STEP_ACTIVE; 836 kernel_enable_single_step(regs); 837 } 838 } 839 840 return 0; 841 } 842 NOKPROBE_SYMBOL(watchpoint_handler); 843 844 /* 845 * Handle single-step exception. 846 */ 847 int reinstall_suspended_bps(struct pt_regs *regs) 848 { 849 struct debug_info *debug_info = ¤t->thread.debug; 850 int handled_exception = 0, *kernel_step; 851 852 kernel_step = this_cpu_ptr(&stepping_kernel_bp); 853 854 /* 855 * Called from single-step exception handler. 856 * Return 0 if execution can resume, 1 if a SIGTRAP should be 857 * reported. 858 */ 859 if (user_mode(regs)) { 860 if (debug_info->bps_disabled) { 861 debug_info->bps_disabled = 0; 862 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1); 863 handled_exception = 1; 864 } 865 866 if (debug_info->wps_disabled) { 867 debug_info->wps_disabled = 0; 868 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1); 869 handled_exception = 1; 870 } 871 872 if (handled_exception) { 873 if (debug_info->suspended_step) { 874 debug_info->suspended_step = 0; 875 /* Allow exception handling to fall-through. */ 876 handled_exception = 0; 877 } else { 878 user_disable_single_step(current); 879 } 880 } 881 } else if (*kernel_step != ARM_KERNEL_STEP_NONE) { 882 toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1); 883 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1); 884 885 if (!debug_info->wps_disabled) 886 toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1); 887 888 if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) { 889 kernel_disable_single_step(); 890 handled_exception = 1; 891 } else { 892 handled_exception = 0; 893 } 894 895 *kernel_step = ARM_KERNEL_STEP_NONE; 896 } 897 898 return !handled_exception; 899 } 900 NOKPROBE_SYMBOL(reinstall_suspended_bps); 901 902 /* 903 * Context-switcher for restoring suspended breakpoints. 904 */ 905 void hw_breakpoint_thread_switch(struct task_struct *next) 906 { 907 /* 908 * current next 909 * disabled: 0 0 => The usual case, NOTIFY_DONE 910 * 0 1 => Disable the registers 911 * 1 0 => Enable the registers 912 * 1 1 => NOTIFY_DONE. per-task bps will 913 * get taken care of by perf. 914 */ 915 916 struct debug_info *current_debug_info, *next_debug_info; 917 918 current_debug_info = ¤t->thread.debug; 919 next_debug_info = &next->thread.debug; 920 921 /* Update breakpoints. */ 922 if (current_debug_info->bps_disabled != next_debug_info->bps_disabled) 923 toggle_bp_registers(AARCH64_DBG_REG_BCR, 924 DBG_ACTIVE_EL0, 925 !next_debug_info->bps_disabled); 926 927 /* Update watchpoints. */ 928 if (current_debug_info->wps_disabled != next_debug_info->wps_disabled) 929 toggle_bp_registers(AARCH64_DBG_REG_WCR, 930 DBG_ACTIVE_EL0, 931 !next_debug_info->wps_disabled); 932 } 933 934 /* 935 * CPU initialisation. 936 */ 937 static int hw_breakpoint_reset(unsigned int cpu) 938 { 939 int i; 940 struct perf_event **slots; 941 /* 942 * When a CPU goes through cold-boot, it does not have any installed 943 * slot, so it is safe to share the same function for restoring and 944 * resetting breakpoints; when a CPU is hotplugged in, it goes 945 * through the slots, which are all empty, hence it just resets control 946 * and value for debug registers. 947 * When this function is triggered on warm-boot through a CPU PM 948 * notifier some slots might be initialized; if so they are 949 * reprogrammed according to the debug slots content. 950 */ 951 for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) { 952 if (slots[i]) { 953 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE); 954 } else { 955 write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL); 956 write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL); 957 } 958 } 959 960 for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) { 961 if (slots[i]) { 962 hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE); 963 } else { 964 write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL); 965 write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL); 966 } 967 } 968 969 return 0; 970 } 971 972 #ifdef CONFIG_CPU_PM 973 extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int)); 974 #else 975 static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int)) 976 { 977 } 978 #endif 979 980 /* 981 * One-time initialisation. 982 */ 983 static int __init arch_hw_breakpoint_init(void) 984 { 985 int ret; 986 987 core_num_brps = get_num_brps(); 988 core_num_wrps = get_num_wrps(); 989 990 pr_info("found %d breakpoint and %d watchpoint registers.\n", 991 core_num_brps, core_num_wrps); 992 993 /* Register debug fault handlers. */ 994 hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP, 995 TRAP_HWBKPT, "hw-breakpoint handler"); 996 hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP, 997 TRAP_HWBKPT, "hw-watchpoint handler"); 998 999 /* 1000 * Reset the breakpoint resources. We assume that a halting 1001 * debugger will leave the world in a nice state for us. 1002 */ 1003 ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING, 1004 "perf/arm64/hw_breakpoint:starting", 1005 hw_breakpoint_reset, NULL); 1006 if (ret) 1007 pr_err("failed to register CPU hotplug notifier: %d\n", ret); 1008 1009 /* Register cpu_suspend hw breakpoint restore hook */ 1010 cpu_suspend_set_dbg_restorer(hw_breakpoint_reset); 1011 1012 return ret; 1013 } 1014 arch_initcall(arch_hw_breakpoint_init); 1015 1016 void hw_breakpoint_pmu_read(struct perf_event *bp) 1017 { 1018 } 1019 1020 /* 1021 * Dummy function to register with die_notifier. 1022 */ 1023 int hw_breakpoint_exceptions_notify(struct notifier_block *unused, 1024 unsigned long val, void *data) 1025 { 1026 return NOTIFY_DONE; 1027 } 1028