1/* 2 * Hibernate low-level support 3 * 4 * Copyright (C) 2016 ARM Ltd. 5 * Author: James Morse <james.morse@arm.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19#include <linux/linkage.h> 20#include <linux/errno.h> 21 22#include <asm/asm-offsets.h> 23#include <asm/assembler.h> 24#include <asm/cputype.h> 25#include <asm/memory.h> 26#include <asm/page.h> 27#include <asm/virt.h> 28 29/* 30 * To prevent the possibility of old and new partial table walks being visible 31 * in the tlb, switch the ttbr to a zero page when we invalidate the old 32 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i 33 * Even switching to our copied tables will cause a changed output address at 34 * each stage of the walk. 35 */ 36.macro break_before_make_ttbr_switch zero_page, page_table, tmp 37 phys_to_ttbr \zero_page, \tmp 38 msr ttbr1_el1, \tmp 39 isb 40 tlbi vmalle1 41 dsb nsh 42 phys_to_ttbr \page_table, \tmp 43 msr ttbr1_el1, \tmp 44 isb 45.endm 46 47 48/* 49 * Resume from hibernate 50 * 51 * Loads temporary page tables then restores the memory image. 52 * Finally branches to cpu_resume() to restore the state saved by 53 * swsusp_arch_suspend(). 54 * 55 * Because this code has to be copied to a 'safe' page, it can't call out to 56 * other functions by PC-relative address. Also remember that it may be 57 * mid-way through over-writing other functions. For this reason it contains 58 * code from flush_icache_range() and uses the copy_page() macro. 59 * 60 * This 'safe' page is mapped via ttbr0, and executed from there. This function 61 * switches to a copy of the linear map in ttbr1, performs the restore, then 62 * switches ttbr1 to the original kernel's swapper_pg_dir. 63 * 64 * All of memory gets written to, including code. We need to clean the kernel 65 * text to the Point of Coherence (PoC) before secondary cores can be booted. 66 * Because the kernel modules and executable pages mapped to user space are 67 * also written as data, we clean all pages we touch to the Point of 68 * Unification (PoU). 69 * 70 * x0: physical address of temporary page tables 71 * x1: physical address of swapper page tables 72 * x2: address of cpu_resume 73 * x3: linear map address of restore_pblist in the current kernel 74 * x4: physical address of __hyp_stub_vectors, or 0 75 * x5: physical address of a zero page that remains zero after resume 76 */ 77.pushsection ".hibernate_exit.text", "ax" 78ENTRY(swsusp_arch_suspend_exit) 79 /* 80 * We execute from ttbr0, change ttbr1 to our copied linear map tables 81 * with a break-before-make via the zero page 82 */ 83 break_before_make_ttbr_switch x5, x0, x6 84 85 mov x21, x1 86 mov x30, x2 87 mov x24, x4 88 mov x25, x5 89 90 /* walk the restore_pblist and use copy_page() to over-write memory */ 91 mov x19, x3 92 931: ldr x10, [x19, #HIBERN_PBE_ORIG] 94 mov x0, x10 95 ldr x1, [x19, #HIBERN_PBE_ADDR] 96 97 copy_page x0, x1, x2, x3, x4, x5, x6, x7, x8, x9 98 99 add x1, x10, #PAGE_SIZE 100 /* Clean the copied page to PoU - based on flush_icache_range() */ 101 raw_dcache_line_size x2, x3 102 sub x3, x2, #1 103 bic x4, x10, x3 1042: dc cvau, x4 /* clean D line / unified line */ 105 add x4, x4, x2 106 cmp x4, x1 107 b.lo 2b 108 109 ldr x19, [x19, #HIBERN_PBE_NEXT] 110 cbnz x19, 1b 111 dsb ish /* wait for PoU cleaning to finish */ 112 113 /* switch to the restored kernels page tables */ 114 break_before_make_ttbr_switch x25, x21, x6 115 116 ic ialluis 117 dsb ish 118 isb 119 120 cbz x24, 3f /* Do we need to re-initialise EL2? */ 121 hvc #0 1223: ret 123 124 .ltorg 125ENDPROC(swsusp_arch_suspend_exit) 126 127/* 128 * Restore the hyp stub. 129 * This must be done before the hibernate page is unmapped by _cpu_resume(), 130 * but happens before any of the hyp-stub's code is cleaned to PoC. 131 * 132 * x24: The physical address of __hyp_stub_vectors 133 */ 134el1_sync: 135 msr vbar_el2, x24 136 eret 137ENDPROC(el1_sync) 138 139.macro invalid_vector label 140\label: 141 b \label 142ENDPROC(\label) 143.endm 144 145 invalid_vector el2_sync_invalid 146 invalid_vector el2_irq_invalid 147 invalid_vector el2_fiq_invalid 148 invalid_vector el2_error_invalid 149 invalid_vector el1_sync_invalid 150 invalid_vector el1_irq_invalid 151 invalid_vector el1_fiq_invalid 152 invalid_vector el1_error_invalid 153 154/* el2 vectors - switch el2 here while we restore the memory image. */ 155 .align 11 156ENTRY(hibernate_el2_vectors) 157 ventry el2_sync_invalid // Synchronous EL2t 158 ventry el2_irq_invalid // IRQ EL2t 159 ventry el2_fiq_invalid // FIQ EL2t 160 ventry el2_error_invalid // Error EL2t 161 162 ventry el2_sync_invalid // Synchronous EL2h 163 ventry el2_irq_invalid // IRQ EL2h 164 ventry el2_fiq_invalid // FIQ EL2h 165 ventry el2_error_invalid // Error EL2h 166 167 ventry el1_sync // Synchronous 64-bit EL1 168 ventry el1_irq_invalid // IRQ 64-bit EL1 169 ventry el1_fiq_invalid // FIQ 64-bit EL1 170 ventry el1_error_invalid // Error 64-bit EL1 171 172 ventry el1_sync_invalid // Synchronous 32-bit EL1 173 ventry el1_irq_invalid // IRQ 32-bit EL1 174 ventry el1_fiq_invalid // FIQ 32-bit EL1 175 ventry el1_error_invalid // Error 32-bit EL1 176END(hibernate_el2_vectors) 177 178.popsection 179