1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/bug.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/cache.h> 23#include <asm/cputype.h> 24#include <asm/el2_setup.h> 25#include <asm/elf.h> 26#include <asm/image.h> 27#include <asm/kernel-pgtable.h> 28#include <asm/kvm_arm.h> 29#include <asm/memory.h> 30#include <asm/pgtable-hwdef.h> 31#include <asm/page.h> 32#include <asm/scs.h> 33#include <asm/smp.h> 34#include <asm/sysreg.h> 35#include <asm/thread_info.h> 36#include <asm/virt.h> 37 38#include "efi-header.S" 39 40#if (PAGE_OFFSET & 0x1fffff) != 0 41#error PAGE_OFFSET must be at least 2MB aligned 42#endif 43 44/* 45 * Kernel startup entry point. 46 * --------------------------- 47 * 48 * The requirements are: 49 * MMU = off, D-cache = off, I-cache = on or off, 50 * x0 = physical address to the FDT blob. 51 * 52 * Note that the callee-saved registers are used for storing variables 53 * that are useful before the MMU is enabled. The allocations are described 54 * in the entry routines. 55 */ 56 __HEAD 57 /* 58 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 59 */ 60 efi_signature_nop // special NOP to identity as PE/COFF executable 61 b primary_entry // branch to kernel start, magic 62 .quad 0 // Image load offset from start of RAM, little-endian 63 le64sym _kernel_size_le // Effective size of kernel image, little-endian 64 le64sym _kernel_flags_le // Informative flags, little-endian 65 .quad 0 // reserved 66 .quad 0 // reserved 67 .quad 0 // reserved 68 .ascii ARM64_IMAGE_MAGIC // Magic number 69 .long .Lpe_header_offset // Offset to the PE header. 70 71 __EFI_PE_HEADER 72 73 __INIT 74 75 /* 76 * The following callee saved general purpose registers are used on the 77 * primary lowlevel boot path: 78 * 79 * Register Scope Purpose 80 * x20 primary_entry() .. __primary_switch() CPU boot mode 81 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 82 * x22 create_idmap() .. start_kernel() ID map VA of the DT blob 83 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 84 * x24 __primary_switch() linear map KASLR seed 85 * x25 primary_entry() .. start_kernel() supported VA size 86 * x28 create_idmap() callee preserved temp register 87 */ 88SYM_CODE_START(primary_entry) 89 bl preserve_boot_args 90 bl init_kernel_el // w0=cpu_boot_mode 91 mov x20, x0 92 bl create_idmap 93 94 /* 95 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 96 * details. 97 * On return, the CPU will be ready for the MMU to be turned on and 98 * the TCR will have been set. 99 */ 100#if VA_BITS > 48 101 mrs_s x0, SYS_ID_AA64MMFR2_EL1 102 tst x0, #0xf << ID_AA64MMFR2_LVA_SHIFT 103 mov x0, #VA_BITS 104 mov x25, #VA_BITS_MIN 105 csel x25, x25, x0, eq 106 mov x0, x25 107#endif 108 bl __cpu_setup // initialise processor 109 b __primary_switch 110SYM_CODE_END(primary_entry) 111 112/* 113 * Preserve the arguments passed by the bootloader in x0 .. x3 114 */ 115SYM_CODE_START_LOCAL(preserve_boot_args) 116 mov x21, x0 // x21=FDT 117 118 adr_l x0, boot_args // record the contents of 119 stp x21, x1, [x0] // x0 .. x3 at kernel entry 120 stp x2, x3, [x0, #16] 121 122 dmb sy // needed before dc ivac with 123 // MMU off 124 125 add x1, x0, #0x20 // 4 x 8 bytes 126 b dcache_inval_poc // tail call 127SYM_CODE_END(preserve_boot_args) 128 129SYM_FUNC_START_LOCAL(clear_page_tables) 130 /* 131 * Clear the init page tables. 132 */ 133 adrp x0, init_pg_dir 134 adrp x1, init_pg_end 135 sub x2, x1, x0 136 mov x1, xzr 137 b __pi_memset // tail call 138SYM_FUNC_END(clear_page_tables) 139 140/* 141 * Macro to populate page table entries, these entries can be pointers to the next level 142 * or last level entries pointing to physical memory. 143 * 144 * tbl: page table address 145 * rtbl: pointer to page table or physical memory 146 * index: start index to write 147 * eindex: end index to write - [index, eindex] written to 148 * flags: flags for pagetable entry to or in 149 * inc: increment to rtbl between each entry 150 * tmp1: temporary variable 151 * 152 * Preserves: tbl, eindex, flags, inc 153 * Corrupts: index, tmp1 154 * Returns: rtbl 155 */ 156 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 157.Lpe\@: phys_to_pte \tmp1, \rtbl 158 orr \tmp1, \tmp1, \flags // tmp1 = table entry 159 str \tmp1, [\tbl, \index, lsl #3] 160 add \rtbl, \rtbl, \inc // rtbl = pa next level 161 add \index, \index, #1 162 cmp \index, \eindex 163 b.ls .Lpe\@ 164 .endm 165 166/* 167 * Compute indices of table entries from virtual address range. If multiple entries 168 * were needed in the previous page table level then the next page table level is assumed 169 * to be composed of multiple pages. (This effectively scales the end index). 170 * 171 * vstart: virtual address of start of range 172 * vend: virtual address of end of range - we map [vstart, vend] 173 * shift: shift used to transform virtual address into index 174 * order: #imm 2log(number of entries in page table) 175 * istart: index in table corresponding to vstart 176 * iend: index in table corresponding to vend 177 * count: On entry: how many extra entries were required in previous level, scales 178 * our end index. 179 * On exit: returns how many extra entries required for next page table level 180 * 181 * Preserves: vstart, vend 182 * Returns: istart, iend, count 183 */ 184 .macro compute_indices, vstart, vend, shift, order, istart, iend, count 185 ubfx \istart, \vstart, \shift, \order 186 ubfx \iend, \vend, \shift, \order 187 add \iend, \iend, \count, lsl \order 188 sub \count, \iend, \istart 189 .endm 190 191/* 192 * Map memory for specified virtual address range. Each level of page table needed supports 193 * multiple entries. If a level requires n entries the next page table level is assumed to be 194 * formed from n pages. 195 * 196 * tbl: location of page table 197 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 198 * vstart: virtual address of start of range 199 * vend: virtual address of end of range - we map [vstart, vend - 1] 200 * flags: flags to use to map last level entries 201 * phys: physical address corresponding to vstart - physical memory is contiguous 202 * order: #imm 2log(number of entries in PGD table) 203 * 204 * If extra_shift is set, an extra level will be populated if the end address does 205 * not fit in 'extra_shift' bits. This assumes vend is in the TTBR0 range. 206 * 207 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 208 * Preserves: vstart, flags 209 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv 210 */ 211 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv, extra_shift 212 sub \vend, \vend, #1 213 add \rtbl, \tbl, #PAGE_SIZE 214 mov \count, #0 215 216 .ifnb \extra_shift 217 tst \vend, #~((1 << (\extra_shift)) - 1) 218 b.eq .L_\@ 219 compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count 220 mov \sv, \rtbl 221 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 222 mov \tbl, \sv 223 .endif 224.L_\@: 225 compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count 226 mov \sv, \rtbl 227 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 228 mov \tbl, \sv 229 230#if SWAPPER_PGTABLE_LEVELS > 3 231 compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 232 mov \sv, \rtbl 233 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 234 mov \tbl, \sv 235#endif 236 237#if SWAPPER_PGTABLE_LEVELS > 2 238 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 239 mov \sv, \rtbl 240 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 241 mov \tbl, \sv 242#endif 243 244 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 245 bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1 246 populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 247 .endm 248 249/* 250 * Remap a subregion created with the map_memory macro with modified attributes 251 * or output address. The entire remapped region must have been covered in the 252 * invocation of map_memory. 253 * 254 * x0: last level table address (returned in first argument to map_memory) 255 * x1: start VA of the existing mapping 256 * x2: start VA of the region to update 257 * x3: end VA of the region to update (exclusive) 258 * x4: start PA associated with the region to update 259 * x5: attributes to set on the updated region 260 * x6: order of the last level mappings 261 */ 262SYM_FUNC_START_LOCAL(remap_region) 263 sub x3, x3, #1 // make end inclusive 264 265 // Get the index offset for the start of the last level table 266 lsr x1, x1, x6 267 bfi x1, xzr, #0, #PAGE_SHIFT - 3 268 269 // Derive the start and end indexes into the last level table 270 // associated with the provided region 271 lsr x2, x2, x6 272 lsr x3, x3, x6 273 sub x2, x2, x1 274 sub x3, x3, x1 275 276 mov x1, #1 277 lsl x6, x1, x6 // block size at this level 278 279 populate_entries x0, x4, x2, x3, x5, x6, x7 280 ret 281SYM_FUNC_END(remap_region) 282 283SYM_FUNC_START_LOCAL(create_idmap) 284 mov x28, lr 285 /* 286 * The ID map carries a 1:1 mapping of the physical address range 287 * covered by the loaded image, which could be anywhere in DRAM. This 288 * means that the required size of the VA (== PA) space is decided at 289 * boot time, and could be more than the configured size of the VA 290 * space for ordinary kernel and user space mappings. 291 * 292 * There are three cases to consider here: 293 * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover 294 * the placement of the image. In this case, we configure one extra 295 * level of translation on the fly for the ID map only. (This case 296 * also covers 42-bit VA/52-bit PA on 64k pages). 297 * 298 * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can 299 * only happen when using 64k pages, in which case we need to extend 300 * the root level table rather than add a level. Note that we can 301 * treat this case as 'always extended' as long as we take care not 302 * to program an unsupported T0SZ value into the TCR register. 303 * 304 * - Combinations that would require two additional levels of 305 * translation are not supported, e.g., VA_BITS==36 on 16k pages, or 306 * VA_BITS==39/4k pages with 5-level paging, where the input address 307 * requires more than 47 or 48 bits, respectively. 308 */ 309#if (VA_BITS < 48) 310#define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT) 311#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 312 313 /* 314 * If VA_BITS < 48, we have to configure an additional table level. 315 * First, we have to verify our assumption that the current value of 316 * VA_BITS was chosen such that all translation levels are fully 317 * utilised, and that lowering T0SZ will always result in an additional 318 * translation level to be configured. 319 */ 320#if VA_BITS != EXTRA_SHIFT 321#error "Mismatch between VA_BITS and page size/number of translation levels" 322#endif 323#else 324#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT) 325#define EXTRA_SHIFT 326 /* 327 * If VA_BITS == 48, we don't have to configure an additional 328 * translation level, but the top-level table has more entries. 329 */ 330#endif 331 adrp x0, init_idmap_pg_dir 332 adrp x3, _text 333 adrp x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE 334 mov x7, SWAPPER_RX_MMUFLAGS 335 336 map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT 337 338 /* Remap the kernel page tables r/w in the ID map */ 339 adrp x1, _text 340 adrp x2, init_pg_dir 341 adrp x3, init_pg_end 342 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1 343 mov x5, SWAPPER_RW_MMUFLAGS 344 mov x6, #SWAPPER_BLOCK_SHIFT 345 bl remap_region 346 347 /* Remap the FDT after the kernel image */ 348 adrp x1, _text 349 adrp x22, _end + SWAPPER_BLOCK_SIZE 350 bic x2, x22, #SWAPPER_BLOCK_SIZE - 1 351 bfi x22, x21, #0, #SWAPPER_BLOCK_SHIFT // remapped FDT address 352 add x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE 353 bic x4, x21, #SWAPPER_BLOCK_SIZE - 1 354 mov x5, SWAPPER_RW_MMUFLAGS 355 mov x6, #SWAPPER_BLOCK_SHIFT 356 bl remap_region 357 358 /* 359 * Since the page tables have been populated with non-cacheable 360 * accesses (MMU disabled), invalidate those tables again to 361 * remove any speculatively loaded cache lines. 362 */ 363 dmb sy 364 365 adrp x0, init_idmap_pg_dir 366 adrp x1, init_idmap_pg_end 367 bl dcache_inval_poc 368 ret x28 369SYM_FUNC_END(create_idmap) 370 371SYM_FUNC_START_LOCAL(create_kernel_mapping) 372 adrp x0, init_pg_dir 373 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 374 add x5, x5, x23 // add KASLR displacement 375 adrp x6, _end // runtime __pa(_end) 376 adrp x3, _text // runtime __pa(_text) 377 sub x6, x6, x3 // _end - _text 378 add x6, x6, x5 // runtime __va(_end) 379 mov x7, SWAPPER_RW_MMUFLAGS 380 381 map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14 382 383 dsb ishst // sync with page table walker 384 ret 385SYM_FUNC_END(create_kernel_mapping) 386 387 /* 388 * Initialize CPU registers with task-specific and cpu-specific context. 389 * 390 * Create a final frame record at task_pt_regs(current)->stackframe, so 391 * that the unwinder can identify the final frame record of any task by 392 * its location in the task stack. We reserve the entire pt_regs space 393 * for consistency with user tasks and kthreads. 394 */ 395 .macro init_cpu_task tsk, tmp1, tmp2 396 msr sp_el0, \tsk 397 398 ldr \tmp1, [\tsk, #TSK_STACK] 399 add sp, \tmp1, #THREAD_SIZE 400 sub sp, sp, #PT_REGS_SIZE 401 402 stp xzr, xzr, [sp, #S_STACKFRAME] 403 add x29, sp, #S_STACKFRAME 404 405 scs_load \tsk 406 407 adr_l \tmp1, __per_cpu_offset 408 ldr w\tmp2, [\tsk, #TSK_TI_CPU] 409 ldr \tmp1, [\tmp1, \tmp2, lsl #3] 410 set_this_cpu_offset \tmp1 411 .endm 412 413/* 414 * The following fragment of code is executed with the MMU enabled. 415 * 416 * x0 = __pa(KERNEL_START) 417 */ 418SYM_FUNC_START_LOCAL(__primary_switched) 419 adr_l x4, init_task 420 init_cpu_task x4, x5, x6 421 422 adr_l x8, vectors // load VBAR_EL1 with virtual 423 msr vbar_el1, x8 // vector table address 424 isb 425 426 stp x29, x30, [sp, #-16]! 427 mov x29, sp 428 429 str_l x21, __fdt_pointer, x5 // Save FDT pointer 430 431 ldr_l x4, kimage_vaddr // Save the offset between 432 sub x4, x4, x0 // the kernel virtual and 433 str_l x4, kimage_voffset, x5 // physical mappings 434 435 mov x0, x20 436 bl set_cpu_boot_mode_flag 437 438 // Clear BSS 439 adr_l x0, __bss_start 440 mov x1, xzr 441 adr_l x2, __bss_stop 442 sub x2, x2, x0 443 bl __pi_memset 444 dsb ishst // Make zero page visible to PTW 445 446#if VA_BITS > 48 447 adr_l x8, vabits_actual // Set this early so KASAN early init 448 str x25, [x8] // ... observes the correct value 449 dc civac, x8 // Make visible to booting secondaries 450#endif 451 452#ifdef CONFIG_RANDOMIZE_BASE 453 adrp x5, memstart_offset_seed // Save KASLR linear map seed 454 strh w24, [x5, :lo12:memstart_offset_seed] 455#endif 456#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 457 bl kasan_early_init 458#endif 459 mov x0, x21 // pass FDT address in x0 460 bl early_fdt_map // Try mapping the FDT early 461 mov x0, x20 // pass the full boot status 462 bl init_feature_override // Parse cpu feature overrides 463 mov x0, x20 464 bl finalise_el2 // Prefer VHE if possible 465 ldp x29, x30, [sp], #16 466 bl start_kernel 467 ASM_BUG() 468SYM_FUNC_END(__primary_switched) 469 470/* 471 * end early head section, begin head code that is also used for 472 * hotplug and needs to have the same protections as the text region 473 */ 474 .section ".idmap.text","awx" 475 476/* 477 * Starting from EL2 or EL1, configure the CPU to execute at the highest 478 * reachable EL supported by the kernel in a chosen default state. If dropping 479 * from EL2 to EL1, configure EL2 before configuring EL1. 480 * 481 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 482 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 483 * 484 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if 485 * booted in EL1 or EL2 respectively, with the top 32 bits containing 486 * potential context flags. These flags are *not* stored in __boot_cpu_mode. 487 */ 488SYM_FUNC_START(init_kernel_el) 489 mrs x0, CurrentEL 490 cmp x0, #CurrentEL_EL2 491 b.eq init_el2 492 493SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 494 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 495 msr sctlr_el1, x0 496 isb 497 mov_q x0, INIT_PSTATE_EL1 498 msr spsr_el1, x0 499 msr elr_el1, lr 500 mov w0, #BOOT_CPU_MODE_EL1 501 eret 502 503SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 504 mov_q x0, HCR_HOST_NVHE_FLAGS 505 msr hcr_el2, x0 506 isb 507 508 init_el2_state 509 510 /* Hypervisor stub */ 511 adr_l x0, __hyp_stub_vectors 512 msr vbar_el2, x0 513 isb 514 515 mov_q x1, INIT_SCTLR_EL1_MMU_OFF 516 517 /* 518 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, 519 * making it impossible to start in nVHE mode. Is that 520 * compliant with the architecture? Absolutely not! 521 */ 522 mrs x0, hcr_el2 523 and x0, x0, #HCR_E2H 524 cbz x0, 1f 525 526 /* Set a sane SCTLR_EL1, the VHE way */ 527 msr_s SYS_SCTLR_EL12, x1 528 mov x2, #BOOT_CPU_FLAG_E2H 529 b 2f 530 5311: 532 msr sctlr_el1, x1 533 mov x2, xzr 5342: 535 msr elr_el2, lr 536 mov w0, #BOOT_CPU_MODE_EL2 537 orr x0, x0, x2 538 eret 539SYM_FUNC_END(init_kernel_el) 540 541/* 542 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 543 * in w0. See arch/arm64/include/asm/virt.h for more info. 544 */ 545SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 546 adr_l x1, __boot_cpu_mode 547 cmp w0, #BOOT_CPU_MODE_EL2 548 b.ne 1f 549 add x1, x1, #4 5501: str w0, [x1] // Save CPU boot mode 551 ret 552SYM_FUNC_END(set_cpu_boot_mode_flag) 553 554 /* 555 * This provides a "holding pen" for platforms to hold all secondary 556 * cores are held until we're ready for them to initialise. 557 */ 558SYM_FUNC_START(secondary_holding_pen) 559 bl init_kernel_el // w0=cpu_boot_mode 560 mrs x2, mpidr_el1 561 mov_q x1, MPIDR_HWID_BITMASK 562 and x2, x2, x1 563 adr_l x3, secondary_holding_pen_release 564pen: ldr x4, [x3] 565 cmp x4, x2 566 b.eq secondary_startup 567 wfe 568 b pen 569SYM_FUNC_END(secondary_holding_pen) 570 571 /* 572 * Secondary entry point that jumps straight into the kernel. Only to 573 * be used where CPUs are brought online dynamically by the kernel. 574 */ 575SYM_FUNC_START(secondary_entry) 576 bl init_kernel_el // w0=cpu_boot_mode 577 b secondary_startup 578SYM_FUNC_END(secondary_entry) 579 580SYM_FUNC_START_LOCAL(secondary_startup) 581 /* 582 * Common entry point for secondary CPUs. 583 */ 584 mov x20, x0 // preserve boot mode 585 bl finalise_el2 586 bl __cpu_secondary_check52bitva 587#if VA_BITS > 48 588 ldr_l x0, vabits_actual 589#endif 590 bl __cpu_setup // initialise processor 591 adrp x1, swapper_pg_dir 592 adrp x2, idmap_pg_dir 593 bl __enable_mmu 594 ldr x8, =__secondary_switched 595 br x8 596SYM_FUNC_END(secondary_startup) 597 598SYM_FUNC_START_LOCAL(__secondary_switched) 599 mov x0, x20 600 bl set_cpu_boot_mode_flag 601 str_l xzr, __early_cpu_boot_status, x3 602 adr_l x5, vectors 603 msr vbar_el1, x5 604 isb 605 606 adr_l x0, secondary_data 607 ldr x2, [x0, #CPU_BOOT_TASK] 608 cbz x2, __secondary_too_slow 609 610 init_cpu_task x2, x1, x3 611 612#ifdef CONFIG_ARM64_PTR_AUTH 613 ptrauth_keys_init_cpu x2, x3, x4, x5 614#endif 615 616 bl secondary_start_kernel 617 ASM_BUG() 618SYM_FUNC_END(__secondary_switched) 619 620SYM_FUNC_START_LOCAL(__secondary_too_slow) 621 wfe 622 wfi 623 b __secondary_too_slow 624SYM_FUNC_END(__secondary_too_slow) 625 626/* 627 * The booting CPU updates the failed status @__early_cpu_boot_status, 628 * with MMU turned off. 629 * 630 * update_early_cpu_boot_status tmp, status 631 * - Corrupts tmp1, tmp2 632 * - Writes 'status' to __early_cpu_boot_status and makes sure 633 * it is committed to memory. 634 */ 635 636 .macro update_early_cpu_boot_status status, tmp1, tmp2 637 mov \tmp2, #\status 638 adr_l \tmp1, __early_cpu_boot_status 639 str \tmp2, [\tmp1] 640 dmb sy 641 dc ivac, \tmp1 // Invalidate potentially stale cache line 642 .endm 643 644/* 645 * Enable the MMU. 646 * 647 * x0 = SCTLR_EL1 value for turning on the MMU. 648 * x1 = TTBR1_EL1 value 649 * x2 = ID map root table address 650 * 651 * Returns to the caller via x30/lr. This requires the caller to be covered 652 * by the .idmap.text section. 653 * 654 * Checks if the selected granule size is supported by the CPU. 655 * If it isn't, park the CPU 656 */ 657SYM_FUNC_START(__enable_mmu) 658 mrs x3, ID_AA64MMFR0_EL1 659 ubfx x3, x3, #ID_AA64MMFR0_TGRAN_SHIFT, 4 660 cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN 661 b.lt __no_granule_support 662 cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 663 b.gt __no_granule_support 664 phys_to_ttbr x2, x2 665 msr ttbr0_el1, x2 // load TTBR0 666 load_ttbr1 x1, x1, x3 667 668 set_sctlr_el1 x0 669 670 ret 671SYM_FUNC_END(__enable_mmu) 672 673SYM_FUNC_START(__cpu_secondary_check52bitva) 674#if VA_BITS > 48 675 ldr_l x0, vabits_actual 676 cmp x0, #52 677 b.ne 2f 678 679 mrs_s x0, SYS_ID_AA64MMFR2_EL1 680 and x0, x0, #(0xf << ID_AA64MMFR2_LVA_SHIFT) 681 cbnz x0, 2f 682 683 update_early_cpu_boot_status \ 684 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 6851: wfe 686 wfi 687 b 1b 688 689#endif 6902: ret 691SYM_FUNC_END(__cpu_secondary_check52bitva) 692 693SYM_FUNC_START_LOCAL(__no_granule_support) 694 /* Indicate that this CPU can't boot and is stuck in the kernel */ 695 update_early_cpu_boot_status \ 696 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 6971: 698 wfe 699 wfi 700 b 1b 701SYM_FUNC_END(__no_granule_support) 702 703#ifdef CONFIG_RELOCATABLE 704SYM_FUNC_START_LOCAL(__relocate_kernel) 705 /* 706 * Iterate over each entry in the relocation table, and apply the 707 * relocations in place. 708 */ 709 adr_l x9, __rela_start 710 adr_l x10, __rela_end 711 mov_q x11, KIMAGE_VADDR // default virtual offset 712 add x11, x11, x23 // actual virtual offset 713 7140: cmp x9, x10 715 b.hs 1f 716 ldp x12, x13, [x9], #24 717 ldr x14, [x9, #-8] 718 cmp w13, #R_AARCH64_RELATIVE 719 b.ne 0b 720 add x14, x14, x23 // relocate 721 str x14, [x12, x23] 722 b 0b 723 7241: 725#ifdef CONFIG_RELR 726 /* 727 * Apply RELR relocations. 728 * 729 * RELR is a compressed format for storing relative relocations. The 730 * encoded sequence of entries looks like: 731 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 732 * 733 * i.e. start with an address, followed by any number of bitmaps. The 734 * address entry encodes 1 relocation. The subsequent bitmap entries 735 * encode up to 63 relocations each, at subsequent offsets following 736 * the last address entry. 737 * 738 * The bitmap entries must have 1 in the least significant bit. The 739 * assumption here is that an address cannot have 1 in lsb. Odd 740 * addresses are not supported. Any odd addresses are stored in the RELA 741 * section, which is handled above. 742 * 743 * Excluding the least significant bit in the bitmap, each non-zero 744 * bit in the bitmap represents a relocation to be applied to 745 * a corresponding machine word that follows the base address 746 * word. The second least significant bit represents the machine 747 * word immediately following the initial address, and each bit 748 * that follows represents the next word, in linear order. As such, 749 * a single bitmap can encode up to 63 relocations in a 64-bit object. 750 * 751 * In this implementation we store the address of the next RELR table 752 * entry in x9, the address being relocated by the current address or 753 * bitmap entry in x13 and the address being relocated by the current 754 * bit in x14. 755 */ 756 adr_l x9, __relr_start 757 adr_l x10, __relr_end 758 7592: cmp x9, x10 760 b.hs 7f 761 ldr x11, [x9], #8 762 tbnz x11, #0, 3f // branch to handle bitmaps 763 add x13, x11, x23 764 ldr x12, [x13] // relocate address entry 765 add x12, x12, x23 766 str x12, [x13], #8 // adjust to start of bitmap 767 b 2b 768 7693: mov x14, x13 7704: lsr x11, x11, #1 771 cbz x11, 6f 772 tbz x11, #0, 5f // skip bit if not set 773 ldr x12, [x14] // relocate bit 774 add x12, x12, x23 775 str x12, [x14] 776 7775: add x14, x14, #8 // move to next bit's address 778 b 4b 779 7806: /* 781 * Move to the next bitmap's address. 8 is the word size, and 63 is the 782 * number of significant bits in a bitmap entry. 783 */ 784 add x13, x13, #(8 * 63) 785 b 2b 786 7877: 788#endif 789 ret 790 791SYM_FUNC_END(__relocate_kernel) 792#endif 793 794SYM_FUNC_START_LOCAL(__primary_switch) 795 adrp x1, reserved_pg_dir 796 adrp x2, init_idmap_pg_dir 797 bl __enable_mmu 798#ifdef CONFIG_RELOCATABLE 799 adrp x23, KERNEL_START 800 and x23, x23, MIN_KIMG_ALIGN - 1 801#ifdef CONFIG_RANDOMIZE_BASE 802 mov x0, x22 803 adrp x1, init_pg_end 804 mov sp, x1 805 mov x29, xzr 806 bl __pi_kaslr_early_init 807 and x24, x0, #SZ_2M - 1 // capture memstart offset seed 808 bic x0, x0, #SZ_2M - 1 809 orr x23, x23, x0 // record kernel offset 810#endif 811#endif 812 bl clear_page_tables 813 bl create_kernel_mapping 814 815 adrp x1, init_pg_dir 816 load_ttbr1 x1, x1, x2 817#ifdef CONFIG_RELOCATABLE 818 bl __relocate_kernel 819#endif 820 ldr x8, =__primary_switched 821 adrp x0, KERNEL_START // __pa(KERNEL_START) 822 br x8 823SYM_FUNC_END(__primary_switch) 824