1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <linux/irqchip/arm-gic-v3.h> 26 27#include <asm/assembler.h> 28#include <asm/boot.h> 29#include <asm/ptrace.h> 30#include <asm/asm-offsets.h> 31#include <asm/cache.h> 32#include <asm/cputype.h> 33#include <asm/elf.h> 34#include <asm/kernel-pgtable.h> 35#include <asm/kvm_arm.h> 36#include <asm/memory.h> 37#include <asm/pgtable-hwdef.h> 38#include <asm/pgtable.h> 39#include <asm/page.h> 40#include <asm/smp.h> 41#include <asm/sysreg.h> 42#include <asm/thread_info.h> 43#include <asm/virt.h> 44 45#include "efi-header.S" 46 47#define __PHYS_OFFSET (KERNEL_START - TEXT_OFFSET) 48 49#if (TEXT_OFFSET & 0xfff) != 0 50#error TEXT_OFFSET must be at least 4KB aligned 51#elif (PAGE_OFFSET & 0x1fffff) != 0 52#error PAGE_OFFSET must be at least 2MB aligned 53#elif TEXT_OFFSET > 0x1fffff 54#error TEXT_OFFSET must be less than 2MB 55#endif 56 57/* 58 * Kernel startup entry point. 59 * --------------------------- 60 * 61 * The requirements are: 62 * MMU = off, D-cache = off, I-cache = on or off, 63 * x0 = physical address to the FDT blob. 64 * 65 * This code is mostly position independent so you call this at 66 * __pa(PAGE_OFFSET + TEXT_OFFSET). 67 * 68 * Note that the callee-saved registers are used for storing variables 69 * that are useful before the MMU is enabled. The allocations are described 70 * in the entry routines. 71 */ 72 __HEAD 73_head: 74 /* 75 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 76 */ 77#ifdef CONFIG_EFI 78 /* 79 * This add instruction has no meaningful effect except that 80 * its opcode forms the magic "MZ" signature required by UEFI. 81 */ 82 add x13, x18, #0x16 83 b stext 84#else 85 b stext // branch to kernel start, magic 86 .long 0 // reserved 87#endif 88 le64sym _kernel_offset_le // Image load offset from start of RAM, little-endian 89 le64sym _kernel_size_le // Effective size of kernel image, little-endian 90 le64sym _kernel_flags_le // Informative flags, little-endian 91 .quad 0 // reserved 92 .quad 0 // reserved 93 .quad 0 // reserved 94 .ascii "ARM\x64" // Magic number 95#ifdef CONFIG_EFI 96 .long pe_header - _head // Offset to the PE header. 97 98pe_header: 99 __EFI_PE_HEADER 100#else 101 .long 0 // reserved 102#endif 103 104 __INIT 105 106 /* 107 * The following callee saved general purpose registers are used on the 108 * primary lowlevel boot path: 109 * 110 * Register Scope Purpose 111 * x21 stext() .. start_kernel() FDT pointer passed at boot in x0 112 * x23 stext() .. start_kernel() physical misalignment/KASLR offset 113 * x28 __create_page_tables() callee preserved temp register 114 * x19/x20 __primary_switch() callee preserved temp registers 115 */ 116ENTRY(stext) 117 bl preserve_boot_args 118 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 119 adrp x23, __PHYS_OFFSET 120 and x23, x23, MIN_KIMG_ALIGN - 1 // KASLR offset, defaults to 0 121 bl set_cpu_boot_mode_flag 122 bl __create_page_tables 123 /* 124 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 125 * details. 126 * On return, the CPU will be ready for the MMU to be turned on and 127 * the TCR will have been set. 128 */ 129 bl __cpu_setup // initialise processor 130 b __primary_switch 131ENDPROC(stext) 132 133/* 134 * Preserve the arguments passed by the bootloader in x0 .. x3 135 */ 136preserve_boot_args: 137 mov x21, x0 // x21=FDT 138 139 adr_l x0, boot_args // record the contents of 140 stp x21, x1, [x0] // x0 .. x3 at kernel entry 141 stp x2, x3, [x0, #16] 142 143 dmb sy // needed before dc ivac with 144 // MMU off 145 146 mov x1, #0x20 // 4 x 8 bytes 147 b __inval_dcache_area // tail call 148ENDPROC(preserve_boot_args) 149 150/* 151 * Macro to arrange a physical address in a page table entry, taking care of 152 * 52-bit addresses. 153 * 154 * Preserves: phys 155 * Returns: pte 156 */ 157 .macro phys_to_pte, phys, pte 158#ifdef CONFIG_ARM64_PA_BITS_52 159 /* 160 * We assume \phys is 64K aligned and this is guaranteed by only 161 * supporting this configuration with 64K pages. 162 */ 163 orr \pte, \phys, \phys, lsr #36 164 and \pte, \pte, #PTE_ADDR_MASK 165#else 166 mov \pte, \phys 167#endif 168 .endm 169 170/* 171 * Macro to create a table entry to the next page. 172 * 173 * tbl: page table address 174 * virt: virtual address 175 * shift: #imm page table shift 176 * ptrs: #imm pointers per table page 177 * 178 * Preserves: virt 179 * Corrupts: ptrs, tmp1, tmp2 180 * Returns: tbl -> next level table page address 181 */ 182 .macro create_table_entry, tbl, virt, shift, ptrs, tmp1, tmp2 183 add \tmp1, \tbl, #PAGE_SIZE 184 phys_to_pte \tmp1, \tmp2 185 orr \tmp2, \tmp2, #PMD_TYPE_TABLE // address of next table and entry type 186 lsr \tmp1, \virt, #\shift 187 sub \ptrs, \ptrs, #1 188 and \tmp1, \tmp1, \ptrs // table index 189 str \tmp2, [\tbl, \tmp1, lsl #3] 190 add \tbl, \tbl, #PAGE_SIZE // next level table page 191 .endm 192 193/* 194 * Macro to populate page table entries, these entries can be pointers to the next level 195 * or last level entries pointing to physical memory. 196 * 197 * tbl: page table address 198 * rtbl: pointer to page table or physical memory 199 * index: start index to write 200 * eindex: end index to write - [index, eindex] written to 201 * flags: flags for pagetable entry to or in 202 * inc: increment to rtbl between each entry 203 * tmp1: temporary variable 204 * 205 * Preserves: tbl, eindex, flags, inc 206 * Corrupts: index, tmp1 207 * Returns: rtbl 208 */ 209 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 210.Lpe\@: phys_to_pte \rtbl, \tmp1 211 orr \tmp1, \tmp1, \flags // tmp1 = table entry 212 str \tmp1, [\tbl, \index, lsl #3] 213 add \rtbl, \rtbl, \inc // rtbl = pa next level 214 add \index, \index, #1 215 cmp \index, \eindex 216 b.ls .Lpe\@ 217 .endm 218 219/* 220 * Compute indices of table entries from virtual address range. If multiple entries 221 * were needed in the previous page table level then the next page table level is assumed 222 * to be composed of multiple pages. (This effectively scales the end index). 223 * 224 * vstart: virtual address of start of range 225 * vend: virtual address of end of range 226 * shift: shift used to transform virtual address into index 227 * ptrs: number of entries in page table 228 * istart: index in table corresponding to vstart 229 * iend: index in table corresponding to vend 230 * count: On entry: how many extra entries were required in previous level, scales 231 * our end index. 232 * On exit: returns how many extra entries required for next page table level 233 * 234 * Preserves: vstart, vend, shift, ptrs 235 * Returns: istart, iend, count 236 */ 237 .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count 238 lsr \iend, \vend, \shift 239 mov \istart, \ptrs 240 sub \istart, \istart, #1 241 and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) 242 mov \istart, \ptrs 243 mul \istart, \istart, \count 244 add \iend, \iend, \istart // iend += (count - 1) * ptrs 245 // our entries span multiple tables 246 247 lsr \istart, \vstart, \shift 248 mov \count, \ptrs 249 sub \count, \count, #1 250 and \istart, \istart, \count 251 252 sub \count, \iend, \istart 253 .endm 254 255/* 256 * Map memory for specified virtual address range. Each level of page table needed supports 257 * multiple entries. If a level requires n entries the next page table level is assumed to be 258 * formed from n pages. 259 * 260 * tbl: location of page table 261 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 262 * vstart: start address to map 263 * vend: end address to map - we map [vstart, vend] 264 * flags: flags to use to map last level entries 265 * phys: physical address corresponding to vstart - physical memory is contiguous 266 * pgds: the number of pgd entries 267 * 268 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 269 * Preserves: vstart, vend, flags 270 * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv 271 */ 272 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv 273 add \rtbl, \tbl, #PAGE_SIZE 274 mov \sv, \rtbl 275 mov \count, #0 276 compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count 277 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 278 mov \tbl, \sv 279 mov \sv, \rtbl 280 281#if SWAPPER_PGTABLE_LEVELS > 3 282 compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count 283 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 284 mov \tbl, \sv 285 mov \sv, \rtbl 286#endif 287 288#if SWAPPER_PGTABLE_LEVELS > 2 289 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count 290 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 291 mov \tbl, \sv 292#endif 293 294 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count 295 bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 296 populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 297 .endm 298 299/* 300 * Setup the initial page tables. We only setup the barest amount which is 301 * required to get the kernel running. The following sections are required: 302 * - identity mapping to enable the MMU (low address, TTBR0) 303 * - first few MB of the kernel linear mapping to jump to once the MMU has 304 * been enabled 305 */ 306__create_page_tables: 307 mov x28, lr 308 309 /* 310 * Invalidate the idmap and swapper page tables to avoid potential 311 * dirty cache lines being evicted. 312 */ 313 adrp x0, idmap_pg_dir 314 adrp x1, swapper_pg_end 315 sub x1, x1, x0 316 bl __inval_dcache_area 317 318 /* 319 * Clear the idmap and swapper page tables. 320 */ 321 adrp x0, idmap_pg_dir 322 adrp x1, swapper_pg_end 323 sub x1, x1, x0 3241: stp xzr, xzr, [x0], #16 325 stp xzr, xzr, [x0], #16 326 stp xzr, xzr, [x0], #16 327 stp xzr, xzr, [x0], #16 328 subs x1, x1, #64 329 b.ne 1b 330 331 mov x7, SWAPPER_MM_MMUFLAGS 332 333 /* 334 * Create the identity mapping. 335 */ 336 adrp x0, idmap_pg_dir 337 adrp x3, __idmap_text_start // __pa(__idmap_text_start) 338 339 /* 340 * VA_BITS may be too small to allow for an ID mapping to be created 341 * that covers system RAM if that is located sufficiently high in the 342 * physical address space. So for the ID map, use an extended virtual 343 * range in that case, and configure an additional translation level 344 * if needed. 345 * 346 * Calculate the maximum allowed value for TCR_EL1.T0SZ so that the 347 * entire ID map region can be mapped. As T0SZ == (64 - #bits used), 348 * this number conveniently equals the number of leading zeroes in 349 * the physical address of __idmap_text_end. 350 */ 351 adrp x5, __idmap_text_end 352 clz x5, x5 353 cmp x5, TCR_T0SZ(VA_BITS) // default T0SZ small enough? 354 b.ge 1f // .. then skip VA range extension 355 356 adr_l x6, idmap_t0sz 357 str x5, [x6] 358 dmb sy 359 dc ivac, x6 // Invalidate potentially stale cache line 360 361#if (VA_BITS < 48) 362#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 363#define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) 364 365 /* 366 * If VA_BITS < 48, we have to configure an additional table level. 367 * First, we have to verify our assumption that the current value of 368 * VA_BITS was chosen such that all translation levels are fully 369 * utilised, and that lowering T0SZ will always result in an additional 370 * translation level to be configured. 371 */ 372#if VA_BITS != EXTRA_SHIFT 373#error "Mismatch between VA_BITS and page size/number of translation levels" 374#endif 375 376 mov x4, EXTRA_PTRS 377 create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 378#else 379 /* 380 * If VA_BITS == 48, we don't have to configure an additional 381 * translation level, but the top-level table has more entries. 382 */ 383 mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) 384 str_l x4, idmap_ptrs_per_pgd, x5 385#endif 3861: 387 ldr_l x4, idmap_ptrs_per_pgd 388 mov x5, x3 // __pa(__idmap_text_start) 389 adr_l x6, __idmap_text_end // __pa(__idmap_text_end) 390 391 map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 392 393 /* 394 * Map the kernel image (starting with PHYS_OFFSET). 395 */ 396 adrp x0, swapper_pg_dir 397 mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text) 398 add x5, x5, x23 // add KASLR displacement 399 mov x4, PTRS_PER_PGD 400 adrp x6, _end // runtime __pa(_end) 401 adrp x3, _text // runtime __pa(_text) 402 sub x6, x6, x3 // _end - _text 403 add x6, x6, x5 // runtime __va(_end) 404 405 map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 406 407 /* 408 * Since the page tables have been populated with non-cacheable 409 * accesses (MMU disabled), invalidate the idmap and swapper page 410 * tables again to remove any speculatively loaded cache lines. 411 */ 412 adrp x0, idmap_pg_dir 413 adrp x1, swapper_pg_end 414 sub x1, x1, x0 415 dmb sy 416 bl __inval_dcache_area 417 418 ret x28 419ENDPROC(__create_page_tables) 420 .ltorg 421 422/* 423 * The following fragment of code is executed with the MMU enabled. 424 * 425 * x0 = __PHYS_OFFSET 426 */ 427__primary_switched: 428 adrp x4, init_thread_union 429 add sp, x4, #THREAD_SIZE 430 adr_l x5, init_task 431 msr sp_el0, x5 // Save thread_info 432 433 adr_l x8, vectors // load VBAR_EL1 with virtual 434 msr vbar_el1, x8 // vector table address 435 isb 436 437 stp xzr, x30, [sp, #-16]! 438 mov x29, sp 439 440 str_l x21, __fdt_pointer, x5 // Save FDT pointer 441 442 ldr_l x4, kimage_vaddr // Save the offset between 443 sub x4, x4, x0 // the kernel virtual and 444 str_l x4, kimage_voffset, x5 // physical mappings 445 446 // Clear BSS 447 adr_l x0, __bss_start 448 mov x1, xzr 449 adr_l x2, __bss_stop 450 sub x2, x2, x0 451 bl __pi_memset 452 dsb ishst // Make zero page visible to PTW 453 454#ifdef CONFIG_KASAN 455 bl kasan_early_init 456#endif 457#ifdef CONFIG_RANDOMIZE_BASE 458 tst x23, ~(MIN_KIMG_ALIGN - 1) // already running randomized? 459 b.ne 0f 460 mov x0, x21 // pass FDT address in x0 461 bl kaslr_early_init // parse FDT for KASLR options 462 cbz x0, 0f // KASLR disabled? just proceed 463 orr x23, x23, x0 // record KASLR offset 464 ldp x29, x30, [sp], #16 // we must enable KASLR, return 465 ret // to __primary_switch() 4660: 467#endif 468 add sp, sp, #16 469 mov x29, #0 470 mov x30, #0 471 b start_kernel 472ENDPROC(__primary_switched) 473 474/* 475 * end early head section, begin head code that is also used for 476 * hotplug and needs to have the same protections as the text region 477 */ 478 .section ".idmap.text","ax" 479 480ENTRY(kimage_vaddr) 481 .quad _text - TEXT_OFFSET 482 483/* 484 * If we're fortunate enough to boot at EL2, ensure that the world is 485 * sane before dropping to EL1. 486 * 487 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in w0 if 488 * booted in EL1 or EL2 respectively. 489 */ 490ENTRY(el2_setup) 491 msr SPsel, #1 // We want to use SP_EL{1,2} 492 mrs x0, CurrentEL 493 cmp x0, #CurrentEL_EL2 494 b.eq 1f 495 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 496 msr sctlr_el1, x0 497 mov w0, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 498 isb 499 ret 500 5011: mov_q x0, (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 502 msr sctlr_el2, x0 503 504#ifdef CONFIG_ARM64_VHE 505 /* 506 * Check for VHE being present. For the rest of the EL2 setup, 507 * x2 being non-zero indicates that we do have VHE, and that the 508 * kernel is intended to run at EL2. 509 */ 510 mrs x2, id_aa64mmfr1_el1 511 ubfx x2, x2, #8, #4 512#else 513 mov x2, xzr 514#endif 515 516 /* Hyp configuration. */ 517 mov x0, #HCR_RW // 64-bit EL1 518 cbz x2, set_hcr 519 orr x0, x0, #HCR_TGE // Enable Host Extensions 520 orr x0, x0, #HCR_E2H 521set_hcr: 522 msr hcr_el2, x0 523 isb 524 525 /* 526 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 527 * This is not necessary for VHE, since the host kernel runs in EL2, 528 * and EL0 accesses are configured in the later stage of boot process. 529 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 530 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 531 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 532 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 533 * EL2. 534 */ 535 cbnz x2, 1f 536 mrs x0, cnthctl_el2 537 orr x0, x0, #3 // Enable EL1 physical timers 538 msr cnthctl_el2, x0 5391: 540 msr cntvoff_el2, xzr // Clear virtual offset 541 542#ifdef CONFIG_ARM_GIC_V3 543 /* GICv3 system register access */ 544 mrs x0, id_aa64pfr0_el1 545 ubfx x0, x0, #24, #4 546 cmp x0, #1 547 b.ne 3f 548 549 mrs_s x0, SYS_ICC_SRE_EL2 550 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 551 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 552 msr_s SYS_ICC_SRE_EL2, x0 553 isb // Make sure SRE is now set 554 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 555 tbz x0, #0, 3f // and check that it sticks 556 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 557 5583: 559#endif 560 561 /* Populate ID registers. */ 562 mrs x0, midr_el1 563 mrs x1, mpidr_el1 564 msr vpidr_el2, x0 565 msr vmpidr_el2, x1 566 567#ifdef CONFIG_COMPAT 568 msr hstr_el2, xzr // Disable CP15 traps to EL2 569#endif 570 571 /* EL2 debug */ 572 mrs x1, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 573 sbfx x0, x1, #8, #4 574 cmp x0, #1 575 b.lt 4f // Skip if no PMU present 576 mrs x0, pmcr_el0 // Disable debug access traps 577 ubfx x0, x0, #11, #5 // to EL2 and allow access to 5784: 579 csel x3, xzr, x0, lt // all PMU counters from EL1 580 581 /* Statistical profiling */ 582 ubfx x0, x1, #32, #4 // Check ID_AA64DFR0_EL1 PMSVer 583 cbz x0, 7f // Skip if SPE not present 584 cbnz x2, 6f // VHE? 585 mrs_s x4, SYS_PMBIDR_EL1 // If SPE available at EL2, 586 and x4, x4, #(1 << SYS_PMBIDR_EL1_P_SHIFT) 587 cbnz x4, 5f // then permit sampling of physical 588 mov x4, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ 589 1 << SYS_PMSCR_EL2_PA_SHIFT) 590 msr_s SYS_PMSCR_EL2, x4 // addresses and physical counter 5915: 592 mov x1, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 593 orr x3, x3, x1 // If we don't have VHE, then 594 b 7f // use EL1&0 translation. 5956: // For VHE, use EL2 translation 596 orr x3, x3, #MDCR_EL2_TPMS // and disable access from EL1 5977: 598 msr mdcr_el2, x3 // Configure debug traps 599 600 /* Stage-2 translation */ 601 msr vttbr_el2, xzr 602 603 cbz x2, install_el2_stub 604 605 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 606 isb 607 ret 608 609install_el2_stub: 610 /* 611 * When VHE is not in use, early init of EL2 and EL1 needs to be 612 * done here. 613 * When VHE _is_ in use, EL1 will not be used in the host and 614 * requires no configuration, and all non-hyp-specific EL2 setup 615 * will be done via the _EL1 system register aliases in __cpu_setup. 616 */ 617 mov_q x0, (SCTLR_EL1_RES1 | ENDIAN_SET_EL1) 618 msr sctlr_el1, x0 619 620 /* Coprocessor traps. */ 621 mov x0, #0x33ff 622 msr cptr_el2, x0 // Disable copro. traps to EL2 623 624 /* SVE register access */ 625 mrs x1, id_aa64pfr0_el1 626 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 627 cbz x1, 7f 628 629 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps 630 msr cptr_el2, x0 // Disable copro. traps to EL2 631 isb 632 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 633 msr_s SYS_ZCR_EL2, x1 // length for EL1. 634 635 /* Hypervisor stub */ 6367: adr_l x0, __hyp_stub_vectors 637 msr vbar_el2, x0 638 639 /* spsr */ 640 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 641 PSR_MODE_EL1h) 642 msr spsr_el2, x0 643 msr elr_el2, lr 644 mov w0, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 645 eret 646ENDPROC(el2_setup) 647 648/* 649 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 650 * in w0. See arch/arm64/include/asm/virt.h for more info. 651 */ 652set_cpu_boot_mode_flag: 653 adr_l x1, __boot_cpu_mode 654 cmp w0, #BOOT_CPU_MODE_EL2 655 b.ne 1f 656 add x1, x1, #4 6571: str w0, [x1] // This CPU has booted in EL1 658 dmb sy 659 dc ivac, x1 // Invalidate potentially stale cache line 660 ret 661ENDPROC(set_cpu_boot_mode_flag) 662 663/* 664 * These values are written with the MMU off, but read with the MMU on. 665 * Writers will invalidate the corresponding address, discarding up to a 666 * 'Cache Writeback Granule' (CWG) worth of data. The linker script ensures 667 * sufficient alignment that the CWG doesn't overlap another section. 668 */ 669 .pushsection ".mmuoff.data.write", "aw" 670/* 671 * We need to find out the CPU boot mode long after boot, so we need to 672 * store it in a writable variable. 673 * 674 * This is not in .bss, because we set it sufficiently early that the boot-time 675 * zeroing of .bss would clobber it. 676 */ 677ENTRY(__boot_cpu_mode) 678 .long BOOT_CPU_MODE_EL2 679 .long BOOT_CPU_MODE_EL1 680/* 681 * The booting CPU updates the failed status @__early_cpu_boot_status, 682 * with MMU turned off. 683 */ 684ENTRY(__early_cpu_boot_status) 685 .long 0 686 687 .popsection 688 689 /* 690 * This provides a "holding pen" for platforms to hold all secondary 691 * cores are held until we're ready for them to initialise. 692 */ 693ENTRY(secondary_holding_pen) 694 bl el2_setup // Drop to EL1, w0=cpu_boot_mode 695 bl set_cpu_boot_mode_flag 696 mrs x0, mpidr_el1 697 mov_q x1, MPIDR_HWID_BITMASK 698 and x0, x0, x1 699 adr_l x3, secondary_holding_pen_release 700pen: ldr x4, [x3] 701 cmp x4, x0 702 b.eq secondary_startup 703 wfe 704 b pen 705ENDPROC(secondary_holding_pen) 706 707 /* 708 * Secondary entry point that jumps straight into the kernel. Only to 709 * be used where CPUs are brought online dynamically by the kernel. 710 */ 711ENTRY(secondary_entry) 712 bl el2_setup // Drop to EL1 713 bl set_cpu_boot_mode_flag 714 b secondary_startup 715ENDPROC(secondary_entry) 716 717secondary_startup: 718 /* 719 * Common entry point for secondary CPUs. 720 */ 721 bl __cpu_setup // initialise processor 722 bl __enable_mmu 723 ldr x8, =__secondary_switched 724 br x8 725ENDPROC(secondary_startup) 726 727__secondary_switched: 728 adr_l x5, vectors 729 msr vbar_el1, x5 730 isb 731 732 adr_l x0, secondary_data 733 ldr x1, [x0, #CPU_BOOT_STACK] // get secondary_data.stack 734 mov sp, x1 735 ldr x2, [x0, #CPU_BOOT_TASK] 736 msr sp_el0, x2 737 mov x29, #0 738 mov x30, #0 739 b secondary_start_kernel 740ENDPROC(__secondary_switched) 741 742/* 743 * The booting CPU updates the failed status @__early_cpu_boot_status, 744 * with MMU turned off. 745 * 746 * update_early_cpu_boot_status tmp, status 747 * - Corrupts tmp1, tmp2 748 * - Writes 'status' to __early_cpu_boot_status and makes sure 749 * it is committed to memory. 750 */ 751 752 .macro update_early_cpu_boot_status status, tmp1, tmp2 753 mov \tmp2, #\status 754 adr_l \tmp1, __early_cpu_boot_status 755 str \tmp2, [\tmp1] 756 dmb sy 757 dc ivac, \tmp1 // Invalidate potentially stale cache line 758 .endm 759 760/* 761 * Enable the MMU. 762 * 763 * x0 = SCTLR_EL1 value for turning on the MMU. 764 * 765 * Returns to the caller via x30/lr. This requires the caller to be covered 766 * by the .idmap.text section. 767 * 768 * Checks if the selected granule size is supported by the CPU. 769 * If it isn't, park the CPU 770 */ 771ENTRY(__enable_mmu) 772 mrs x1, ID_AA64MMFR0_EL1 773 ubfx x2, x1, #ID_AA64MMFR0_TGRAN_SHIFT, 4 774 cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED 775 b.ne __no_granule_support 776 update_early_cpu_boot_status 0, x1, x2 777 adrp x1, idmap_pg_dir 778 adrp x2, swapper_pg_dir 779 phys_to_ttbr x1, x3 780 phys_to_ttbr x2, x4 781 msr ttbr0_el1, x3 // load TTBR0 782 msr ttbr1_el1, x4 // load TTBR1 783 isb 784 msr sctlr_el1, x0 785 isb 786 /* 787 * Invalidate the local I-cache so that any instructions fetched 788 * speculatively from the PoC are discarded, since they may have 789 * been dynamically patched at the PoU. 790 */ 791 ic iallu 792 dsb nsh 793 isb 794 ret 795ENDPROC(__enable_mmu) 796 797__no_granule_support: 798 /* Indicate that this CPU can't boot and is stuck in the kernel */ 799 update_early_cpu_boot_status CPU_STUCK_IN_KERNEL, x1, x2 8001: 801 wfe 802 wfi 803 b 1b 804ENDPROC(__no_granule_support) 805 806#ifdef CONFIG_RELOCATABLE 807__relocate_kernel: 808 /* 809 * Iterate over each entry in the relocation table, and apply the 810 * relocations in place. 811 */ 812 ldr w9, =__rela_offset // offset to reloc table 813 ldr w10, =__rela_size // size of reloc table 814 815 mov_q x11, KIMAGE_VADDR // default virtual offset 816 add x11, x11, x23 // actual virtual offset 817 add x9, x9, x11 // __va(.rela) 818 add x10, x9, x10 // __va(.rela) + sizeof(.rela) 819 8200: cmp x9, x10 821 b.hs 1f 822 ldp x11, x12, [x9], #24 823 ldr x13, [x9, #-8] 824 cmp w12, #R_AARCH64_RELATIVE 825 b.ne 0b 826 add x13, x13, x23 // relocate 827 str x13, [x11, x23] 828 b 0b 8291: ret 830ENDPROC(__relocate_kernel) 831#endif 832 833__primary_switch: 834#ifdef CONFIG_RANDOMIZE_BASE 835 mov x19, x0 // preserve new SCTLR_EL1 value 836 mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value 837#endif 838 839 bl __enable_mmu 840#ifdef CONFIG_RELOCATABLE 841 bl __relocate_kernel 842#ifdef CONFIG_RANDOMIZE_BASE 843 ldr x8, =__primary_switched 844 adrp x0, __PHYS_OFFSET 845 blr x8 846 847 /* 848 * If we return here, we have a KASLR displacement in x23 which we need 849 * to take into account by discarding the current kernel mapping and 850 * creating a new one. 851 */ 852 pre_disable_mmu_workaround 853 msr sctlr_el1, x20 // disable the MMU 854 isb 855 bl __create_page_tables // recreate kernel mapping 856 857 tlbi vmalle1 // Remove any stale TLB entries 858 dsb nsh 859 860 msr sctlr_el1, x19 // re-enable the MMU 861 isb 862 ic iallu // flush instructions fetched 863 dsb nsh // via old mapping 864 isb 865 866 bl __relocate_kernel 867#endif 868#endif 869 ldr x8, =__primary_switched 870 adrp x0, __PHYS_OFFSET 871 br x8 872ENDPROC(__primary_switch) 873