1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level CPU initialisation 4 * Based on arch/arm/kernel/head.S 5 * 6 * Copyright (C) 1994-2002 Russell King 7 * Copyright (C) 2003-2012 ARM Ltd. 8 * Authors: Catalin Marinas <catalin.marinas@arm.com> 9 * Will Deacon <will.deacon@arm.com> 10 */ 11 12#include <linux/linkage.h> 13#include <linux/init.h> 14#include <linux/pgtable.h> 15 16#include <asm/asm_pointer_auth.h> 17#include <asm/assembler.h> 18#include <asm/boot.h> 19#include <asm/bug.h> 20#include <asm/ptrace.h> 21#include <asm/asm-offsets.h> 22#include <asm/cache.h> 23#include <asm/cputype.h> 24#include <asm/el2_setup.h> 25#include <asm/elf.h> 26#include <asm/image.h> 27#include <asm/kernel-pgtable.h> 28#include <asm/kvm_arm.h> 29#include <asm/memory.h> 30#include <asm/pgtable-hwdef.h> 31#include <asm/page.h> 32#include <asm/scs.h> 33#include <asm/smp.h> 34#include <asm/sysreg.h> 35#include <asm/thread_info.h> 36#include <asm/virt.h> 37 38#include "efi-header.S" 39 40#if (PAGE_OFFSET & 0x1fffff) != 0 41#error PAGE_OFFSET must be at least 2MB aligned 42#endif 43 44/* 45 * Kernel startup entry point. 46 * --------------------------- 47 * 48 * The requirements are: 49 * MMU = off, D-cache = off, I-cache = on or off, 50 * x0 = physical address to the FDT blob. 51 * 52 * Note that the callee-saved registers are used for storing variables 53 * that are useful before the MMU is enabled. The allocations are described 54 * in the entry routines. 55 */ 56 __HEAD 57 /* 58 * DO NOT MODIFY. Image header expected by Linux boot-loaders. 59 */ 60 efi_signature_nop // special NOP to identity as PE/COFF executable 61 b primary_entry // branch to kernel start, magic 62 .quad 0 // Image load offset from start of RAM, little-endian 63 le64sym _kernel_size_le // Effective size of kernel image, little-endian 64 le64sym _kernel_flags_le // Informative flags, little-endian 65 .quad 0 // reserved 66 .quad 0 // reserved 67 .quad 0 // reserved 68 .ascii ARM64_IMAGE_MAGIC // Magic number 69 .long .Lpe_header_offset // Offset to the PE header. 70 71 __EFI_PE_HEADER 72 73 .section ".idmap.text","awx" 74 75 /* 76 * The following callee saved general purpose registers are used on the 77 * primary lowlevel boot path: 78 * 79 * Register Scope Purpose 80 * x19 primary_entry() .. start_kernel() whether we entered with the MMU on 81 * x20 primary_entry() .. __primary_switch() CPU boot mode 82 * x21 primary_entry() .. start_kernel() FDT pointer passed at boot in x0 83 * x22 create_idmap() .. start_kernel() ID map VA of the DT blob 84 * x23 primary_entry() .. start_kernel() physical misalignment/KASLR offset 85 * x24 __primary_switch() linear map KASLR seed 86 * x25 primary_entry() .. start_kernel() supported VA size 87 * x28 create_idmap() callee preserved temp register 88 */ 89SYM_CODE_START(primary_entry) 90 bl record_mmu_state 91 bl preserve_boot_args 92 bl create_idmap 93 94 /* 95 * If we entered with the MMU and caches on, clean the ID mapped part 96 * of the primary boot code to the PoC so we can safely execute it with 97 * the MMU off. 98 */ 99 cbz x19, 0f 100 adrp x0, __idmap_text_start 101 adr_l x1, __idmap_text_end 102 bl dcache_clean_poc 1030: mov x0, x19 104 bl init_kernel_el // w0=cpu_boot_mode 105 mov x20, x0 106 107 /* 108 * The following calls CPU setup code, see arch/arm64/mm/proc.S for 109 * details. 110 * On return, the CPU will be ready for the MMU to be turned on and 111 * the TCR will have been set. 112 */ 113#if VA_BITS > 48 114 mrs_s x0, SYS_ID_AA64MMFR2_EL1 115 tst x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT 116 mov x0, #VA_BITS 117 mov x25, #VA_BITS_MIN 118 csel x25, x25, x0, eq 119 mov x0, x25 120#endif 121 bl __cpu_setup // initialise processor 122 b __primary_switch 123SYM_CODE_END(primary_entry) 124 125 __INIT 126SYM_CODE_START_LOCAL(record_mmu_state) 127 mrs x19, CurrentEL 128 cmp x19, #CurrentEL_EL2 129 mrs x19, sctlr_el1 130 b.ne 0f 131 mrs x19, sctlr_el2 1320: 133CPU_LE( tbnz x19, #SCTLR_ELx_EE_SHIFT, 1f ) 134CPU_BE( tbz x19, #SCTLR_ELx_EE_SHIFT, 1f ) 135 tst x19, #SCTLR_ELx_C // Z := (C == 0) 136 and x19, x19, #SCTLR_ELx_M // isolate M bit 137 csel x19, xzr, x19, eq // clear x19 if Z 138 ret 139 140 /* 141 * Set the correct endianness early so all memory accesses issued 142 * before init_kernel_el() occur in the correct byte order. Note that 143 * this means the MMU must be disabled, or the active ID map will end 144 * up getting interpreted with the wrong byte order. 145 */ 1461: eor x19, x19, #SCTLR_ELx_EE 147 bic x19, x19, #SCTLR_ELx_M 148 b.ne 2f 149 pre_disable_mmu_workaround 150 msr sctlr_el2, x19 151 b 3f 152 pre_disable_mmu_workaround 1532: msr sctlr_el1, x19 1543: isb 155 mov x19, xzr 156 ret 157SYM_CODE_END(record_mmu_state) 158 159/* 160 * Preserve the arguments passed by the bootloader in x0 .. x3 161 */ 162SYM_CODE_START_LOCAL(preserve_boot_args) 163 mov x21, x0 // x21=FDT 164 165 adr_l x0, boot_args // record the contents of 166 stp x21, x1, [x0] // x0 .. x3 at kernel entry 167 stp x2, x3, [x0, #16] 168 169 cbnz x19, 0f // skip cache invalidation if MMU is on 170 dmb sy // needed before dc ivac with 171 // MMU off 172 173 add x1, x0, #0x20 // 4 x 8 bytes 174 b dcache_inval_poc // tail call 1750: str_l x19, mmu_enabled_at_boot, x0 176 ret 177SYM_CODE_END(preserve_boot_args) 178 179SYM_FUNC_START_LOCAL(clear_page_tables) 180 /* 181 * Clear the init page tables. 182 */ 183 adrp x0, init_pg_dir 184 adrp x1, init_pg_end 185 sub x2, x1, x0 186 mov x1, xzr 187 b __pi_memset // tail call 188SYM_FUNC_END(clear_page_tables) 189 190/* 191 * Macro to populate page table entries, these entries can be pointers to the next level 192 * or last level entries pointing to physical memory. 193 * 194 * tbl: page table address 195 * rtbl: pointer to page table or physical memory 196 * index: start index to write 197 * eindex: end index to write - [index, eindex] written to 198 * flags: flags for pagetable entry to or in 199 * inc: increment to rtbl between each entry 200 * tmp1: temporary variable 201 * 202 * Preserves: tbl, eindex, flags, inc 203 * Corrupts: index, tmp1 204 * Returns: rtbl 205 */ 206 .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1 207.Lpe\@: phys_to_pte \tmp1, \rtbl 208 orr \tmp1, \tmp1, \flags // tmp1 = table entry 209 str \tmp1, [\tbl, \index, lsl #3] 210 add \rtbl, \rtbl, \inc // rtbl = pa next level 211 add \index, \index, #1 212 cmp \index, \eindex 213 b.ls .Lpe\@ 214 .endm 215 216/* 217 * Compute indices of table entries from virtual address range. If multiple entries 218 * were needed in the previous page table level then the next page table level is assumed 219 * to be composed of multiple pages. (This effectively scales the end index). 220 * 221 * vstart: virtual address of start of range 222 * vend: virtual address of end of range - we map [vstart, vend] 223 * shift: shift used to transform virtual address into index 224 * order: #imm 2log(number of entries in page table) 225 * istart: index in table corresponding to vstart 226 * iend: index in table corresponding to vend 227 * count: On entry: how many extra entries were required in previous level, scales 228 * our end index. 229 * On exit: returns how many extra entries required for next page table level 230 * 231 * Preserves: vstart, vend 232 * Returns: istart, iend, count 233 */ 234 .macro compute_indices, vstart, vend, shift, order, istart, iend, count 235 ubfx \istart, \vstart, \shift, \order 236 ubfx \iend, \vend, \shift, \order 237 add \iend, \iend, \count, lsl \order 238 sub \count, \iend, \istart 239 .endm 240 241/* 242 * Map memory for specified virtual address range. Each level of page table needed supports 243 * multiple entries. If a level requires n entries the next page table level is assumed to be 244 * formed from n pages. 245 * 246 * tbl: location of page table 247 * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) 248 * vstart: virtual address of start of range 249 * vend: virtual address of end of range - we map [vstart, vend - 1] 250 * flags: flags to use to map last level entries 251 * phys: physical address corresponding to vstart - physical memory is contiguous 252 * order: #imm 2log(number of entries in PGD table) 253 * 254 * If extra_shift is set, an extra level will be populated if the end address does 255 * not fit in 'extra_shift' bits. This assumes vend is in the TTBR0 range. 256 * 257 * Temporaries: istart, iend, tmp, count, sv - these need to be different registers 258 * Preserves: vstart, flags 259 * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv 260 */ 261 .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv, extra_shift 262 sub \vend, \vend, #1 263 add \rtbl, \tbl, #PAGE_SIZE 264 mov \count, #0 265 266 .ifnb \extra_shift 267 tst \vend, #~((1 << (\extra_shift)) - 1) 268 b.eq .L_\@ 269 compute_indices \vstart, \vend, #\extra_shift, #(PAGE_SHIFT - 3), \istart, \iend, \count 270 mov \sv, \rtbl 271 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 272 mov \tbl, \sv 273 .endif 274.L_\@: 275 compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count 276 mov \sv, \rtbl 277 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 278 mov \tbl, \sv 279 280#if SWAPPER_PGTABLE_LEVELS > 3 281 compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 282 mov \sv, \rtbl 283 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 284 mov \tbl, \sv 285#endif 286 287#if SWAPPER_PGTABLE_LEVELS > 2 288 compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 289 mov \sv, \rtbl 290 populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp 291 mov \tbl, \sv 292#endif 293 294 compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count 295 bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1 296 populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp 297 .endm 298 299/* 300 * Remap a subregion created with the map_memory macro with modified attributes 301 * or output address. The entire remapped region must have been covered in the 302 * invocation of map_memory. 303 * 304 * x0: last level table address (returned in first argument to map_memory) 305 * x1: start VA of the existing mapping 306 * x2: start VA of the region to update 307 * x3: end VA of the region to update (exclusive) 308 * x4: start PA associated with the region to update 309 * x5: attributes to set on the updated region 310 * x6: order of the last level mappings 311 */ 312SYM_FUNC_START_LOCAL(remap_region) 313 sub x3, x3, #1 // make end inclusive 314 315 // Get the index offset for the start of the last level table 316 lsr x1, x1, x6 317 bfi x1, xzr, #0, #PAGE_SHIFT - 3 318 319 // Derive the start and end indexes into the last level table 320 // associated with the provided region 321 lsr x2, x2, x6 322 lsr x3, x3, x6 323 sub x2, x2, x1 324 sub x3, x3, x1 325 326 mov x1, #1 327 lsl x6, x1, x6 // block size at this level 328 329 populate_entries x0, x4, x2, x3, x5, x6, x7 330 ret 331SYM_FUNC_END(remap_region) 332 333SYM_FUNC_START_LOCAL(create_idmap) 334 mov x28, lr 335 /* 336 * The ID map carries a 1:1 mapping of the physical address range 337 * covered by the loaded image, which could be anywhere in DRAM. This 338 * means that the required size of the VA (== PA) space is decided at 339 * boot time, and could be more than the configured size of the VA 340 * space for ordinary kernel and user space mappings. 341 * 342 * There are three cases to consider here: 343 * - 39 <= VA_BITS < 48, and the ID map needs up to 48 VA bits to cover 344 * the placement of the image. In this case, we configure one extra 345 * level of translation on the fly for the ID map only. (This case 346 * also covers 42-bit VA/52-bit PA on 64k pages). 347 * 348 * - VA_BITS == 48, and the ID map needs more than 48 VA bits. This can 349 * only happen when using 64k pages, in which case we need to extend 350 * the root level table rather than add a level. Note that we can 351 * treat this case as 'always extended' as long as we take care not 352 * to program an unsupported T0SZ value into the TCR register. 353 * 354 * - Combinations that would require two additional levels of 355 * translation are not supported, e.g., VA_BITS==36 on 16k pages, or 356 * VA_BITS==39/4k pages with 5-level paging, where the input address 357 * requires more than 47 or 48 bits, respectively. 358 */ 359#if (VA_BITS < 48) 360#define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT) 361#define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) 362 363 /* 364 * If VA_BITS < 48, we have to configure an additional table level. 365 * First, we have to verify our assumption that the current value of 366 * VA_BITS was chosen such that all translation levels are fully 367 * utilised, and that lowering T0SZ will always result in an additional 368 * translation level to be configured. 369 */ 370#if VA_BITS != EXTRA_SHIFT 371#error "Mismatch between VA_BITS and page size/number of translation levels" 372#endif 373#else 374#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT) 375#define EXTRA_SHIFT 376 /* 377 * If VA_BITS == 48, we don't have to configure an additional 378 * translation level, but the top-level table has more entries. 379 */ 380#endif 381 adrp x0, init_idmap_pg_dir 382 adrp x3, _text 383 adrp x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE 384 mov x7, SWAPPER_RX_MMUFLAGS 385 386 map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT 387 388 /* Remap the kernel page tables r/w in the ID map */ 389 adrp x1, _text 390 adrp x2, init_pg_dir 391 adrp x3, init_pg_end 392 bic x4, x2, #SWAPPER_BLOCK_SIZE - 1 393 mov x5, SWAPPER_RW_MMUFLAGS 394 mov x6, #SWAPPER_BLOCK_SHIFT 395 bl remap_region 396 397 /* Remap the FDT after the kernel image */ 398 adrp x1, _text 399 adrp x22, _end + SWAPPER_BLOCK_SIZE 400 bic x2, x22, #SWAPPER_BLOCK_SIZE - 1 401 bfi x22, x21, #0, #SWAPPER_BLOCK_SHIFT // remapped FDT address 402 add x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE 403 bic x4, x21, #SWAPPER_BLOCK_SIZE - 1 404 mov x5, SWAPPER_RW_MMUFLAGS 405 mov x6, #SWAPPER_BLOCK_SHIFT 406 bl remap_region 407 408 /* 409 * Since the page tables have been populated with non-cacheable 410 * accesses (MMU disabled), invalidate those tables again to 411 * remove any speculatively loaded cache lines. 412 */ 413 cbnz x19, 0f // skip cache invalidation if MMU is on 414 dmb sy 415 416 adrp x0, init_idmap_pg_dir 417 adrp x1, init_idmap_pg_end 418 bl dcache_inval_poc 4190: ret x28 420SYM_FUNC_END(create_idmap) 421 422SYM_FUNC_START_LOCAL(create_kernel_mapping) 423 adrp x0, init_pg_dir 424 mov_q x5, KIMAGE_VADDR // compile time __va(_text) 425#ifdef CONFIG_RELOCATABLE 426 add x5, x5, x23 // add KASLR displacement 427#endif 428 adrp x6, _end // runtime __pa(_end) 429 adrp x3, _text // runtime __pa(_text) 430 sub x6, x6, x3 // _end - _text 431 add x6, x6, x5 // runtime __va(_end) 432 mov x7, SWAPPER_RW_MMUFLAGS 433 434 map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14 435 436 dsb ishst // sync with page table walker 437 ret 438SYM_FUNC_END(create_kernel_mapping) 439 440 /* 441 * Initialize CPU registers with task-specific and cpu-specific context. 442 * 443 * Create a final frame record at task_pt_regs(current)->stackframe, so 444 * that the unwinder can identify the final frame record of any task by 445 * its location in the task stack. We reserve the entire pt_regs space 446 * for consistency with user tasks and kthreads. 447 */ 448 .macro init_cpu_task tsk, tmp1, tmp2 449 msr sp_el0, \tsk 450 451 ldr \tmp1, [\tsk, #TSK_STACK] 452 add sp, \tmp1, #THREAD_SIZE 453 sub sp, sp, #PT_REGS_SIZE 454 455 stp xzr, xzr, [sp, #S_STACKFRAME] 456 add x29, sp, #S_STACKFRAME 457 458 scs_load_current 459 460 adr_l \tmp1, __per_cpu_offset 461 ldr w\tmp2, [\tsk, #TSK_TI_CPU] 462 ldr \tmp1, [\tmp1, \tmp2, lsl #3] 463 set_this_cpu_offset \tmp1 464 .endm 465 466/* 467 * The following fragment of code is executed with the MMU enabled. 468 * 469 * x0 = __pa(KERNEL_START) 470 */ 471SYM_FUNC_START_LOCAL(__primary_switched) 472 adr_l x4, init_task 473 init_cpu_task x4, x5, x6 474 475 adr_l x8, vectors // load VBAR_EL1 with virtual 476 msr vbar_el1, x8 // vector table address 477 isb 478 479 stp x29, x30, [sp, #-16]! 480 mov x29, sp 481 482 str_l x21, __fdt_pointer, x5 // Save FDT pointer 483 484 ldr_l x4, kimage_vaddr // Save the offset between 485 sub x4, x4, x0 // the kernel virtual and 486 str_l x4, kimage_voffset, x5 // physical mappings 487 488 mov x0, x20 489 bl set_cpu_boot_mode_flag 490 491 // Clear BSS 492 adr_l x0, __bss_start 493 mov x1, xzr 494 adr_l x2, __bss_stop 495 sub x2, x2, x0 496 bl __pi_memset 497 dsb ishst // Make zero page visible to PTW 498 499#if VA_BITS > 48 500 adr_l x8, vabits_actual // Set this early so KASAN early init 501 str x25, [x8] // ... observes the correct value 502 dc civac, x8 // Make visible to booting secondaries 503#endif 504 505#ifdef CONFIG_RANDOMIZE_BASE 506 adrp x5, memstart_offset_seed // Save KASLR linear map seed 507 strh w24, [x5, :lo12:memstart_offset_seed] 508#endif 509#if defined(CONFIG_KASAN_GENERIC) || defined(CONFIG_KASAN_SW_TAGS) 510 bl kasan_early_init 511#endif 512 mov x0, x21 // pass FDT address in x0 513 bl early_fdt_map // Try mapping the FDT early 514 mov x0, x20 // pass the full boot status 515 bl init_feature_override // Parse cpu feature overrides 516#ifdef CONFIG_UNWIND_PATCH_PAC_INTO_SCS 517 bl scs_patch_vmlinux 518#endif 519 mov x0, x20 520 bl finalise_el2 // Prefer VHE if possible 521 ldp x29, x30, [sp], #16 522 bl start_kernel 523 ASM_BUG() 524SYM_FUNC_END(__primary_switched) 525 526/* 527 * end early head section, begin head code that is also used for 528 * hotplug and needs to have the same protections as the text region 529 */ 530 .section ".idmap.text","awx" 531 532/* 533 * Starting from EL2 or EL1, configure the CPU to execute at the highest 534 * reachable EL supported by the kernel in a chosen default state. If dropping 535 * from EL2 to EL1, configure EL2 before configuring EL1. 536 * 537 * Since we cannot always rely on ERET synchronizing writes to sysregs (e.g. if 538 * SCTLR_ELx.EOS is clear), we place an ISB prior to ERET. 539 * 540 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x0 if 541 * booted in EL1 or EL2 respectively, with the top 32 bits containing 542 * potential context flags. These flags are *not* stored in __boot_cpu_mode. 543 * 544 * x0: whether we are being called from the primary boot path with the MMU on 545 */ 546SYM_FUNC_START(init_kernel_el) 547 mrs x1, CurrentEL 548 cmp x1, #CurrentEL_EL2 549 b.eq init_el2 550 551SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) 552 mov_q x0, INIT_SCTLR_EL1_MMU_OFF 553 pre_disable_mmu_workaround 554 msr sctlr_el1, x0 555 isb 556 mov_q x0, INIT_PSTATE_EL1 557 msr spsr_el1, x0 558 msr elr_el1, lr 559 mov w0, #BOOT_CPU_MODE_EL1 560 eret 561 562SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) 563 msr elr_el2, lr 564 565 // clean all HYP code to the PoC if we booted at EL2 with the MMU on 566 cbz x0, 0f 567 adrp x0, __hyp_idmap_text_start 568 adr_l x1, __hyp_text_end 569 bl dcache_clean_poc 5700: 571 mov_q x0, HCR_HOST_NVHE_FLAGS 572 msr hcr_el2, x0 573 isb 574 575 init_el2_state 576 577 /* Hypervisor stub */ 578 adr_l x0, __hyp_stub_vectors 579 msr vbar_el2, x0 580 isb 581 582 mov_q x1, INIT_SCTLR_EL1_MMU_OFF 583 584 /* 585 * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, 586 * making it impossible to start in nVHE mode. Is that 587 * compliant with the architecture? Absolutely not! 588 */ 589 mrs x0, hcr_el2 590 and x0, x0, #HCR_E2H 591 cbz x0, 1f 592 593 /* Set a sane SCTLR_EL1, the VHE way */ 594 pre_disable_mmu_workaround 595 msr_s SYS_SCTLR_EL12, x1 596 mov x2, #BOOT_CPU_FLAG_E2H 597 b 2f 598 5991: 600 pre_disable_mmu_workaround 601 msr sctlr_el1, x1 602 mov x2, xzr 6032: 604 mov w0, #BOOT_CPU_MODE_EL2 605 orr x0, x0, x2 606 eret 607SYM_FUNC_END(init_kernel_el) 608 609 /* 610 * This provides a "holding pen" for platforms to hold all secondary 611 * cores are held until we're ready for them to initialise. 612 */ 613SYM_FUNC_START(secondary_holding_pen) 614 mov x0, xzr 615 bl init_kernel_el // w0=cpu_boot_mode 616 mrs x2, mpidr_el1 617 mov_q x1, MPIDR_HWID_BITMASK 618 and x2, x2, x1 619 adr_l x3, secondary_holding_pen_release 620pen: ldr x4, [x3] 621 cmp x4, x2 622 b.eq secondary_startup 623 wfe 624 b pen 625SYM_FUNC_END(secondary_holding_pen) 626 627 /* 628 * Secondary entry point that jumps straight into the kernel. Only to 629 * be used where CPUs are brought online dynamically by the kernel. 630 */ 631SYM_FUNC_START(secondary_entry) 632 mov x0, xzr 633 bl init_kernel_el // w0=cpu_boot_mode 634 b secondary_startup 635SYM_FUNC_END(secondary_entry) 636 637SYM_FUNC_START_LOCAL(secondary_startup) 638 /* 639 * Common entry point for secondary CPUs. 640 */ 641 mov x20, x0 // preserve boot mode 642 bl __cpu_secondary_check52bitva 643#if VA_BITS > 48 644 ldr_l x0, vabits_actual 645#endif 646 bl __cpu_setup // initialise processor 647 adrp x1, swapper_pg_dir 648 adrp x2, idmap_pg_dir 649 bl __enable_mmu 650 ldr x8, =__secondary_switched 651 br x8 652SYM_FUNC_END(secondary_startup) 653 654 .text 655SYM_FUNC_START_LOCAL(__secondary_switched) 656 mov x0, x20 657 bl set_cpu_boot_mode_flag 658 659 mov x0, x20 660 bl finalise_el2 661 662 str_l xzr, __early_cpu_boot_status, x3 663 adr_l x5, vectors 664 msr vbar_el1, x5 665 isb 666 667 adr_l x0, secondary_data 668 ldr x2, [x0, #CPU_BOOT_TASK] 669 cbz x2, __secondary_too_slow 670 671 init_cpu_task x2, x1, x3 672 673#ifdef CONFIG_ARM64_PTR_AUTH 674 ptrauth_keys_init_cpu x2, x3, x4, x5 675#endif 676 677 bl secondary_start_kernel 678 ASM_BUG() 679SYM_FUNC_END(__secondary_switched) 680 681SYM_FUNC_START_LOCAL(__secondary_too_slow) 682 wfe 683 wfi 684 b __secondary_too_slow 685SYM_FUNC_END(__secondary_too_slow) 686 687/* 688 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 689 * in w0. See arch/arm64/include/asm/virt.h for more info. 690 */ 691SYM_FUNC_START_LOCAL(set_cpu_boot_mode_flag) 692 adr_l x1, __boot_cpu_mode 693 cmp w0, #BOOT_CPU_MODE_EL2 694 b.ne 1f 695 add x1, x1, #4 6961: str w0, [x1] // Save CPU boot mode 697 ret 698SYM_FUNC_END(set_cpu_boot_mode_flag) 699 700/* 701 * The booting CPU updates the failed status @__early_cpu_boot_status, 702 * with MMU turned off. 703 * 704 * update_early_cpu_boot_status tmp, status 705 * - Corrupts tmp1, tmp2 706 * - Writes 'status' to __early_cpu_boot_status and makes sure 707 * it is committed to memory. 708 */ 709 710 .macro update_early_cpu_boot_status status, tmp1, tmp2 711 mov \tmp2, #\status 712 adr_l \tmp1, __early_cpu_boot_status 713 str \tmp2, [\tmp1] 714 dmb sy 715 dc ivac, \tmp1 // Invalidate potentially stale cache line 716 .endm 717 718/* 719 * Enable the MMU. 720 * 721 * x0 = SCTLR_EL1 value for turning on the MMU. 722 * x1 = TTBR1_EL1 value 723 * x2 = ID map root table address 724 * 725 * Returns to the caller via x30/lr. This requires the caller to be covered 726 * by the .idmap.text section. 727 * 728 * Checks if the selected granule size is supported by the CPU. 729 * If it isn't, park the CPU 730 */ 731 .section ".idmap.text","awx" 732SYM_FUNC_START(__enable_mmu) 733 mrs x3, ID_AA64MMFR0_EL1 734 ubfx x3, x3, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4 735 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN 736 b.lt __no_granule_support 737 cmp x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX 738 b.gt __no_granule_support 739 phys_to_ttbr x2, x2 740 msr ttbr0_el1, x2 // load TTBR0 741 load_ttbr1 x1, x1, x3 742 743 set_sctlr_el1 x0 744 745 ret 746SYM_FUNC_END(__enable_mmu) 747 748SYM_FUNC_START(__cpu_secondary_check52bitva) 749#if VA_BITS > 48 750 ldr_l x0, vabits_actual 751 cmp x0, #52 752 b.ne 2f 753 754 mrs_s x0, SYS_ID_AA64MMFR2_EL1 755 and x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT) 756 cbnz x0, 2f 757 758 update_early_cpu_boot_status \ 759 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_52_BIT_VA, x0, x1 7601: wfe 761 wfi 762 b 1b 763 764#endif 7652: ret 766SYM_FUNC_END(__cpu_secondary_check52bitva) 767 768SYM_FUNC_START_LOCAL(__no_granule_support) 769 /* Indicate that this CPU can't boot and is stuck in the kernel */ 770 update_early_cpu_boot_status \ 771 CPU_STUCK_IN_KERNEL | CPU_STUCK_REASON_NO_GRAN, x1, x2 7721: 773 wfe 774 wfi 775 b 1b 776SYM_FUNC_END(__no_granule_support) 777 778#ifdef CONFIG_RELOCATABLE 779SYM_FUNC_START_LOCAL(__relocate_kernel) 780 /* 781 * Iterate over each entry in the relocation table, and apply the 782 * relocations in place. 783 */ 784 adr_l x9, __rela_start 785 adr_l x10, __rela_end 786 mov_q x11, KIMAGE_VADDR // default virtual offset 787 add x11, x11, x23 // actual virtual offset 788 7890: cmp x9, x10 790 b.hs 1f 791 ldp x12, x13, [x9], #24 792 ldr x14, [x9, #-8] 793 cmp w13, #R_AARCH64_RELATIVE 794 b.ne 0b 795 add x14, x14, x23 // relocate 796 str x14, [x12, x23] 797 b 0b 798 7991: 800#ifdef CONFIG_RELR 801 /* 802 * Apply RELR relocations. 803 * 804 * RELR is a compressed format for storing relative relocations. The 805 * encoded sequence of entries looks like: 806 * [ AAAAAAAA BBBBBBB1 BBBBBBB1 ... AAAAAAAA BBBBBB1 ... ] 807 * 808 * i.e. start with an address, followed by any number of bitmaps. The 809 * address entry encodes 1 relocation. The subsequent bitmap entries 810 * encode up to 63 relocations each, at subsequent offsets following 811 * the last address entry. 812 * 813 * The bitmap entries must have 1 in the least significant bit. The 814 * assumption here is that an address cannot have 1 in lsb. Odd 815 * addresses are not supported. Any odd addresses are stored in the RELA 816 * section, which is handled above. 817 * 818 * Excluding the least significant bit in the bitmap, each non-zero 819 * bit in the bitmap represents a relocation to be applied to 820 * a corresponding machine word that follows the base address 821 * word. The second least significant bit represents the machine 822 * word immediately following the initial address, and each bit 823 * that follows represents the next word, in linear order. As such, 824 * a single bitmap can encode up to 63 relocations in a 64-bit object. 825 * 826 * In this implementation we store the address of the next RELR table 827 * entry in x9, the address being relocated by the current address or 828 * bitmap entry in x13 and the address being relocated by the current 829 * bit in x14. 830 */ 831 adr_l x9, __relr_start 832 adr_l x10, __relr_end 833 8342: cmp x9, x10 835 b.hs 7f 836 ldr x11, [x9], #8 837 tbnz x11, #0, 3f // branch to handle bitmaps 838 add x13, x11, x23 839 ldr x12, [x13] // relocate address entry 840 add x12, x12, x23 841 str x12, [x13], #8 // adjust to start of bitmap 842 b 2b 843 8443: mov x14, x13 8454: lsr x11, x11, #1 846 cbz x11, 6f 847 tbz x11, #0, 5f // skip bit if not set 848 ldr x12, [x14] // relocate bit 849 add x12, x12, x23 850 str x12, [x14] 851 8525: add x14, x14, #8 // move to next bit's address 853 b 4b 854 8556: /* 856 * Move to the next bitmap's address. 8 is the word size, and 63 is the 857 * number of significant bits in a bitmap entry. 858 */ 859 add x13, x13, #(8 * 63) 860 b 2b 861 8627: 863#endif 864 ret 865 866SYM_FUNC_END(__relocate_kernel) 867#endif 868 869SYM_FUNC_START_LOCAL(__primary_switch) 870 adrp x1, reserved_pg_dir 871 adrp x2, init_idmap_pg_dir 872 bl __enable_mmu 873#ifdef CONFIG_RELOCATABLE 874 adrp x23, KERNEL_START 875 and x23, x23, MIN_KIMG_ALIGN - 1 876#ifdef CONFIG_RANDOMIZE_BASE 877 mov x0, x22 878 adrp x1, init_pg_end 879 mov sp, x1 880 mov x29, xzr 881 bl __pi_kaslr_early_init 882 and x24, x0, #SZ_2M - 1 // capture memstart offset seed 883 bic x0, x0, #SZ_2M - 1 884 orr x23, x23, x0 // record kernel offset 885#endif 886#endif 887 bl clear_page_tables 888 bl create_kernel_mapping 889 890 adrp x1, init_pg_dir 891 load_ttbr1 x1, x1, x2 892#ifdef CONFIG_RELOCATABLE 893 bl __relocate_kernel 894#endif 895 ldr x8, =__primary_switched 896 adrp x0, KERNEL_START // __pa(KERNEL_START) 897 br x8 898SYM_FUNC_END(__primary_switch) 899