1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FP/SIMD context switching and fault handling 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bottom_half.h> 12 #include <linux/bug.h> 13 #include <linux/cache.h> 14 #include <linux/compat.h> 15 #include <linux/compiler.h> 16 #include <linux/cpu.h> 17 #include <linux/cpu_pm.h> 18 #include <linux/ctype.h> 19 #include <linux/kernel.h> 20 #include <linux/linkage.h> 21 #include <linux/irqflags.h> 22 #include <linux/init.h> 23 #include <linux/percpu.h> 24 #include <linux/prctl.h> 25 #include <linux/preempt.h> 26 #include <linux/ptrace.h> 27 #include <linux/sched/signal.h> 28 #include <linux/sched/task_stack.h> 29 #include <linux/signal.h> 30 #include <linux/slab.h> 31 #include <linux/stddef.h> 32 #include <linux/sysctl.h> 33 #include <linux/swab.h> 34 35 #include <asm/esr.h> 36 #include <asm/exception.h> 37 #include <asm/fpsimd.h> 38 #include <asm/cpufeature.h> 39 #include <asm/cputype.h> 40 #include <asm/neon.h> 41 #include <asm/processor.h> 42 #include <asm/simd.h> 43 #include <asm/sigcontext.h> 44 #include <asm/sysreg.h> 45 #include <asm/traps.h> 46 #include <asm/virt.h> 47 48 #define FPEXC_IOF (1 << 0) 49 #define FPEXC_DZF (1 << 1) 50 #define FPEXC_OFF (1 << 2) 51 #define FPEXC_UFF (1 << 3) 52 #define FPEXC_IXF (1 << 4) 53 #define FPEXC_IDF (1 << 7) 54 55 /* 56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.) 57 * 58 * In order to reduce the number of times the FPSIMD state is needlessly saved 59 * and restored, we need to keep track of two things: 60 * (a) for each task, we need to remember which CPU was the last one to have 61 * the task's FPSIMD state loaded into its FPSIMD registers; 62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has 63 * been loaded into its FPSIMD registers most recently, or whether it has 64 * been used to perform kernel mode NEON in the meantime. 65 * 66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to 67 * the id of the current CPU every time the state is loaded onto a CPU. For (b), 68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the 69 * address of the userland FPSIMD state of the task that was loaded onto the CPU 70 * the most recently, or NULL if kernel mode NEON has been performed after that. 71 * 72 * With this in place, we no longer have to restore the next FPSIMD state right 73 * when switching between tasks. Instead, we can defer this check to userland 74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the 75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we 76 * can omit the FPSIMD restore. 77 * 78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to 79 * indicate whether or not the userland FPSIMD state of the current task is 80 * present in the registers. The flag is set unless the FPSIMD registers of this 81 * CPU currently contain the most recent userland FPSIMD state of the current 82 * task. If the task is behaving as a VMM, then this is will be managed by 83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently 84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware 85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and 86 * flag the register state as invalid. 87 * 88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may 89 * save the task's FPSIMD context back to task_struct from softirq context. 90 * To prevent this from racing with the manipulation of the task's FPSIMD state 91 * from task context and thereby corrupting the state, it is necessary to 92 * protect any manipulation of a task's fpsimd_state or TIF_FOREIGN_FPSTATE 93 * flag with {, __}get_cpu_fpsimd_context(). This will still allow softirqs to 94 * run but prevent them to use FPSIMD. 95 * 96 * For a certain task, the sequence may look something like this: 97 * - the task gets scheduled in; if both the task's fpsimd_cpu field 98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu 99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is 100 * cleared, otherwise it is set; 101 * 102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's 103 * userland FPSIMD state is copied from memory to the registers, the task's 104 * fpsimd_cpu field is set to the id of the current CPU, the current 105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the 106 * TIF_FOREIGN_FPSTATE flag is cleared; 107 * 108 * - the task executes an ordinary syscall; upon return to userland, the 109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is 110 * restored; 111 * 112 * - the task executes a syscall which executes some NEON instructions; this is 113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD 114 * register contents to memory, clears the fpsimd_last_state per-cpu variable 115 * and sets the TIF_FOREIGN_FPSTATE flag; 116 * 117 * - the task gets preempted after kernel_neon_end() is called; as we have not 118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so 119 * whatever is in the FPSIMD registers is not saved to memory, but discarded. 120 */ 121 struct fpsimd_last_state_struct { 122 struct user_fpsimd_state *st; 123 void *sve_state; 124 void *za_state; 125 u64 *svcr; 126 unsigned int sve_vl; 127 unsigned int sme_vl; 128 }; 129 130 static DEFINE_PER_CPU(struct fpsimd_last_state_struct, fpsimd_last_state); 131 132 __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = { 133 #ifdef CONFIG_ARM64_SVE 134 [ARM64_VEC_SVE] = { 135 .type = ARM64_VEC_SVE, 136 .name = "SVE", 137 .min_vl = SVE_VL_MIN, 138 .max_vl = SVE_VL_MIN, 139 .max_virtualisable_vl = SVE_VL_MIN, 140 }, 141 #endif 142 #ifdef CONFIG_ARM64_SME 143 [ARM64_VEC_SME] = { 144 .type = ARM64_VEC_SME, 145 .name = "SME", 146 }, 147 #endif 148 }; 149 150 static unsigned int vec_vl_inherit_flag(enum vec_type type) 151 { 152 switch (type) { 153 case ARM64_VEC_SVE: 154 return TIF_SVE_VL_INHERIT; 155 case ARM64_VEC_SME: 156 return TIF_SME_VL_INHERIT; 157 default: 158 WARN_ON_ONCE(1); 159 return 0; 160 } 161 } 162 163 struct vl_config { 164 int __default_vl; /* Default VL for tasks */ 165 }; 166 167 static struct vl_config vl_config[ARM64_VEC_MAX]; 168 169 static inline int get_default_vl(enum vec_type type) 170 { 171 return READ_ONCE(vl_config[type].__default_vl); 172 } 173 174 #ifdef CONFIG_ARM64_SVE 175 176 static inline int get_sve_default_vl(void) 177 { 178 return get_default_vl(ARM64_VEC_SVE); 179 } 180 181 static inline void set_default_vl(enum vec_type type, int val) 182 { 183 WRITE_ONCE(vl_config[type].__default_vl, val); 184 } 185 186 static inline void set_sve_default_vl(int val) 187 { 188 set_default_vl(ARM64_VEC_SVE, val); 189 } 190 191 static void __percpu *efi_sve_state; 192 193 #else /* ! CONFIG_ARM64_SVE */ 194 195 /* Dummy declaration for code that will be optimised out: */ 196 extern void __percpu *efi_sve_state; 197 198 #endif /* ! CONFIG_ARM64_SVE */ 199 200 #ifdef CONFIG_ARM64_SME 201 202 static int get_sme_default_vl(void) 203 { 204 return get_default_vl(ARM64_VEC_SME); 205 } 206 207 static void set_sme_default_vl(int val) 208 { 209 set_default_vl(ARM64_VEC_SME, val); 210 } 211 212 static void sme_free(struct task_struct *); 213 214 #else 215 216 static inline void sme_free(struct task_struct *t) { } 217 218 #endif 219 220 DEFINE_PER_CPU(bool, fpsimd_context_busy); 221 EXPORT_PER_CPU_SYMBOL(fpsimd_context_busy); 222 223 static void fpsimd_bind_task_to_cpu(void); 224 225 static void __get_cpu_fpsimd_context(void) 226 { 227 bool busy = __this_cpu_xchg(fpsimd_context_busy, true); 228 229 WARN_ON(busy); 230 } 231 232 /* 233 * Claim ownership of the CPU FPSIMD context for use by the calling context. 234 * 235 * The caller may freely manipulate the FPSIMD context metadata until 236 * put_cpu_fpsimd_context() is called. 237 * 238 * The double-underscore version must only be called if you know the task 239 * can't be preempted. 240 */ 241 static void get_cpu_fpsimd_context(void) 242 { 243 local_bh_disable(); 244 __get_cpu_fpsimd_context(); 245 } 246 247 static void __put_cpu_fpsimd_context(void) 248 { 249 bool busy = __this_cpu_xchg(fpsimd_context_busy, false); 250 251 WARN_ON(!busy); /* No matching get_cpu_fpsimd_context()? */ 252 } 253 254 /* 255 * Release the CPU FPSIMD context. 256 * 257 * Must be called from a context in which get_cpu_fpsimd_context() was 258 * previously called, with no call to put_cpu_fpsimd_context() in the 259 * meantime. 260 */ 261 static void put_cpu_fpsimd_context(void) 262 { 263 __put_cpu_fpsimd_context(); 264 local_bh_enable(); 265 } 266 267 static bool have_cpu_fpsimd_context(void) 268 { 269 return !preemptible() && __this_cpu_read(fpsimd_context_busy); 270 } 271 272 /* 273 * Call __sve_free() directly only if you know task can't be scheduled 274 * or preempted. 275 */ 276 static void __sve_free(struct task_struct *task) 277 { 278 kfree(task->thread.sve_state); 279 task->thread.sve_state = NULL; 280 } 281 282 static void sve_free(struct task_struct *task) 283 { 284 WARN_ON(test_tsk_thread_flag(task, TIF_SVE)); 285 286 __sve_free(task); 287 } 288 289 unsigned int task_get_vl(const struct task_struct *task, enum vec_type type) 290 { 291 return task->thread.vl[type]; 292 } 293 294 void task_set_vl(struct task_struct *task, enum vec_type type, 295 unsigned long vl) 296 { 297 task->thread.vl[type] = vl; 298 } 299 300 unsigned int task_get_vl_onexec(const struct task_struct *task, 301 enum vec_type type) 302 { 303 return task->thread.vl_onexec[type]; 304 } 305 306 void task_set_vl_onexec(struct task_struct *task, enum vec_type type, 307 unsigned long vl) 308 { 309 task->thread.vl_onexec[type] = vl; 310 } 311 312 /* 313 * TIF_SME controls whether a task can use SME without trapping while 314 * in userspace, when TIF_SME is set then we must have storage 315 * alocated in sve_state and za_state to store the contents of both ZA 316 * and the SVE registers for both streaming and non-streaming modes. 317 * 318 * If both SVCR.ZA and SVCR.SM are disabled then at any point we 319 * may disable TIF_SME and reenable traps. 320 */ 321 322 323 /* 324 * TIF_SVE controls whether a task can use SVE without trapping while 325 * in userspace, and also (together with TIF_SME) the way a task's 326 * FPSIMD/SVE state is stored in thread_struct. 327 * 328 * The kernel uses this flag to track whether a user task is actively 329 * using SVE, and therefore whether full SVE register state needs to 330 * be tracked. If not, the cheaper FPSIMD context handling code can 331 * be used instead of the more costly SVE equivalents. 332 * 333 * * TIF_SVE or SVCR.SM set: 334 * 335 * The task can execute SVE instructions while in userspace without 336 * trapping to the kernel. 337 * 338 * When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the 339 * corresponding Zn), P0-P15 and FFR are encoded in in 340 * task->thread.sve_state, formatted appropriately for vector 341 * length task->thread.sve_vl or, if SVCR.SM is set, 342 * task->thread.sme_vl. 343 * 344 * task->thread.sve_state must point to a valid buffer at least 345 * sve_state_size(task) bytes in size. 346 * 347 * During any syscall, the kernel may optionally clear TIF_SVE and 348 * discard the vector state except for the FPSIMD subset. 349 * 350 * * TIF_SVE clear: 351 * 352 * An attempt by the user task to execute an SVE instruction causes 353 * do_sve_acc() to be called, which does some preparation and then 354 * sets TIF_SVE. 355 * 356 * When stored, FPSIMD registers V0-V31 are encoded in 357 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are 358 * logically zero but not stored anywhere; P0-P15 and FFR are not 359 * stored and have unspecified values from userspace's point of 360 * view. For hygiene purposes, the kernel zeroes them on next use, 361 * but userspace is discouraged from relying on this. 362 * 363 * task->thread.sve_state does not need to be non-NULL, valid or any 364 * particular size: it must not be dereferenced. 365 * 366 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state 367 * irrespective of whether TIF_SVE is clear or set, since these are 368 * not vector length dependent. 369 */ 370 371 /* 372 * Update current's FPSIMD/SVE registers from thread_struct. 373 * 374 * This function should be called only when the FPSIMD/SVE state in 375 * thread_struct is known to be up to date, when preparing to enter 376 * userspace. 377 */ 378 static void task_fpsimd_load(void) 379 { 380 bool restore_sve_regs = false; 381 bool restore_ffr; 382 383 WARN_ON(!system_supports_fpsimd()); 384 WARN_ON(!have_cpu_fpsimd_context()); 385 386 /* Check if we should restore SVE first */ 387 if (IS_ENABLED(CONFIG_ARM64_SVE) && test_thread_flag(TIF_SVE)) { 388 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1); 389 restore_sve_regs = true; 390 restore_ffr = true; 391 } 392 393 /* Restore SME, override SVE register configuration if needed */ 394 if (system_supports_sme()) { 395 unsigned long sme_vl = task_get_sme_vl(current); 396 397 /* Ensure VL is set up for restoring data */ 398 if (test_thread_flag(TIF_SME)) 399 sme_set_vq(sve_vq_from_vl(sme_vl) - 1); 400 401 write_sysreg_s(current->thread.svcr, SYS_SVCR_EL0); 402 403 if (thread_za_enabled(¤t->thread)) 404 za_load_state(current->thread.za_state); 405 406 if (thread_sm_enabled(¤t->thread)) { 407 restore_sve_regs = true; 408 restore_ffr = system_supports_fa64(); 409 } 410 } 411 412 if (restore_sve_regs) 413 sve_load_state(sve_pffr(¤t->thread), 414 ¤t->thread.uw.fpsimd_state.fpsr, 415 restore_ffr); 416 else 417 fpsimd_load_state(¤t->thread.uw.fpsimd_state); 418 } 419 420 /* 421 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to 422 * date with respect to the CPU registers. Note carefully that the 423 * current context is the context last bound to the CPU stored in 424 * last, if KVM is involved this may be the guest VM context rather 425 * than the host thread for the VM pointed to by current. This means 426 * that we must always reference the state storage via last rather 427 * than via current, other than the TIF_ flags which KVM will 428 * carefully maintain for us. 429 */ 430 static void fpsimd_save(void) 431 { 432 struct fpsimd_last_state_struct const *last = 433 this_cpu_ptr(&fpsimd_last_state); 434 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ 435 bool save_sve_regs = false; 436 bool save_ffr; 437 unsigned int vl; 438 439 WARN_ON(!system_supports_fpsimd()); 440 WARN_ON(!have_cpu_fpsimd_context()); 441 442 if (test_thread_flag(TIF_FOREIGN_FPSTATE)) 443 return; 444 445 if (test_thread_flag(TIF_SVE)) { 446 save_sve_regs = true; 447 save_ffr = true; 448 vl = last->sve_vl; 449 } 450 451 if (system_supports_sme()) { 452 u64 *svcr = last->svcr; 453 *svcr = read_sysreg_s(SYS_SVCR_EL0); 454 455 *svcr = read_sysreg_s(SYS_SVCR_EL0); 456 457 if (*svcr & SYS_SVCR_EL0_ZA_MASK) 458 za_save_state(last->za_state); 459 460 /* If we are in streaming mode override regular SVE. */ 461 if (*svcr & SYS_SVCR_EL0_SM_MASK) { 462 save_sve_regs = true; 463 save_ffr = system_supports_fa64(); 464 vl = last->sme_vl; 465 } 466 } 467 468 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) { 469 /* Get the configured VL from RDVL, will account for SM */ 470 if (WARN_ON(sve_get_vl() != vl)) { 471 /* 472 * Can't save the user regs, so current would 473 * re-enter user with corrupt state. 474 * There's no way to recover, so kill it: 475 */ 476 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0); 477 return; 478 } 479 480 sve_save_state((char *)last->sve_state + 481 sve_ffr_offset(vl), 482 &last->st->fpsr, save_ffr); 483 } else { 484 fpsimd_save_state(last->st); 485 } 486 } 487 488 /* 489 * All vector length selection from userspace comes through here. 490 * We're on a slow path, so some sanity-checks are included. 491 * If things go wrong there's a bug somewhere, but try to fall back to a 492 * safe choice. 493 */ 494 static unsigned int find_supported_vector_length(enum vec_type type, 495 unsigned int vl) 496 { 497 struct vl_info *info = &vl_info[type]; 498 int bit; 499 int max_vl = info->max_vl; 500 501 if (WARN_ON(!sve_vl_valid(vl))) 502 vl = info->min_vl; 503 504 if (WARN_ON(!sve_vl_valid(max_vl))) 505 max_vl = info->min_vl; 506 507 if (vl > max_vl) 508 vl = max_vl; 509 if (vl < info->min_vl) 510 vl = info->min_vl; 511 512 bit = find_next_bit(info->vq_map, SVE_VQ_MAX, 513 __vq_to_bit(sve_vq_from_vl(vl))); 514 return sve_vl_from_vq(__bit_to_vq(bit)); 515 } 516 517 #if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL) 518 519 static int vec_proc_do_default_vl(struct ctl_table *table, int write, 520 void *buffer, size_t *lenp, loff_t *ppos) 521 { 522 struct vl_info *info = table->extra1; 523 enum vec_type type = info->type; 524 int ret; 525 int vl = get_default_vl(type); 526 struct ctl_table tmp_table = { 527 .data = &vl, 528 .maxlen = sizeof(vl), 529 }; 530 531 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos); 532 if (ret || !write) 533 return ret; 534 535 /* Writing -1 has the special meaning "set to max": */ 536 if (vl == -1) 537 vl = info->max_vl; 538 539 if (!sve_vl_valid(vl)) 540 return -EINVAL; 541 542 set_default_vl(type, find_supported_vector_length(type, vl)); 543 return 0; 544 } 545 546 static struct ctl_table sve_default_vl_table[] = { 547 { 548 .procname = "sve_default_vector_length", 549 .mode = 0644, 550 .proc_handler = vec_proc_do_default_vl, 551 .extra1 = &vl_info[ARM64_VEC_SVE], 552 }, 553 { } 554 }; 555 556 static int __init sve_sysctl_init(void) 557 { 558 if (system_supports_sve()) 559 if (!register_sysctl("abi", sve_default_vl_table)) 560 return -EINVAL; 561 562 return 0; 563 } 564 565 #else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 566 static int __init sve_sysctl_init(void) { return 0; } 567 #endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */ 568 569 #if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL) 570 static struct ctl_table sme_default_vl_table[] = { 571 { 572 .procname = "sme_default_vector_length", 573 .mode = 0644, 574 .proc_handler = vec_proc_do_default_vl, 575 .extra1 = &vl_info[ARM64_VEC_SME], 576 }, 577 { } 578 }; 579 580 static int __init sme_sysctl_init(void) 581 { 582 if (system_supports_sme()) 583 if (!register_sysctl("abi", sme_default_vl_table)) 584 return -EINVAL; 585 586 return 0; 587 } 588 589 #else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 590 static int __init sme_sysctl_init(void) { return 0; } 591 #endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */ 592 593 #define ZREG(sve_state, vq, n) ((char *)(sve_state) + \ 594 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET)) 595 596 #ifdef CONFIG_CPU_BIG_ENDIAN 597 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 598 { 599 u64 a = swab64(x); 600 u64 b = swab64(x >> 64); 601 602 return ((__uint128_t)a << 64) | b; 603 } 604 #else 605 static __uint128_t arm64_cpu_to_le128(__uint128_t x) 606 { 607 return x; 608 } 609 #endif 610 611 #define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x) 612 613 static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst, 614 unsigned int vq) 615 { 616 unsigned int i; 617 __uint128_t *p; 618 619 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 620 p = (__uint128_t *)ZREG(sst, vq, i); 621 *p = arm64_cpu_to_le128(fst->vregs[i]); 622 } 623 } 624 625 /* 626 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to 627 * task->thread.sve_state. 628 * 629 * Task can be a non-runnable task, or current. In the latter case, 630 * the caller must have ownership of the cpu FPSIMD context before calling 631 * this function. 632 * task->thread.sve_state must point to at least sve_state_size(task) 633 * bytes of allocated kernel memory. 634 * task->thread.uw.fpsimd_state must be up to date before calling this 635 * function. 636 */ 637 static void fpsimd_to_sve(struct task_struct *task) 638 { 639 unsigned int vq; 640 void *sst = task->thread.sve_state; 641 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 642 643 if (!system_supports_sve()) 644 return; 645 646 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 647 __fpsimd_to_sve(sst, fst, vq); 648 } 649 650 /* 651 * Transfer the SVE state in task->thread.sve_state to 652 * task->thread.uw.fpsimd_state. 653 * 654 * Task can be a non-runnable task, or current. In the latter case, 655 * the caller must have ownership of the cpu FPSIMD context before calling 656 * this function. 657 * task->thread.sve_state must point to at least sve_state_size(task) 658 * bytes of allocated kernel memory. 659 * task->thread.sve_state must be up to date before calling this function. 660 */ 661 static void sve_to_fpsimd(struct task_struct *task) 662 { 663 unsigned int vq, vl; 664 void const *sst = task->thread.sve_state; 665 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state; 666 unsigned int i; 667 __uint128_t const *p; 668 669 if (!system_supports_sve()) 670 return; 671 672 vl = thread_get_cur_vl(&task->thread); 673 vq = sve_vq_from_vl(vl); 674 for (i = 0; i < SVE_NUM_ZREGS; ++i) { 675 p = (__uint128_t const *)ZREG(sst, vq, i); 676 fst->vregs[i] = arm64_le128_to_cpu(*p); 677 } 678 } 679 680 #ifdef CONFIG_ARM64_SVE 681 682 /* 683 * Return how many bytes of memory are required to store the full SVE 684 * state for task, given task's currently configured vector length. 685 */ 686 size_t sve_state_size(struct task_struct const *task) 687 { 688 unsigned int vl = 0; 689 690 if (system_supports_sve()) 691 vl = task_get_sve_vl(task); 692 if (system_supports_sme()) 693 vl = max(vl, task_get_sme_vl(task)); 694 695 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl)); 696 } 697 698 /* 699 * Ensure that task->thread.sve_state is allocated and sufficiently large. 700 * 701 * This function should be used only in preparation for replacing 702 * task->thread.sve_state with new data. The memory is always zeroed 703 * here to prevent stale data from showing through: this is done in 704 * the interest of testability and predictability: except in the 705 * do_sve_acc() case, there is no ABI requirement to hide stale data 706 * written previously be task. 707 */ 708 void sve_alloc(struct task_struct *task) 709 { 710 if (task->thread.sve_state) { 711 memset(task->thread.sve_state, 0, sve_state_size(task)); 712 return; 713 } 714 715 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */ 716 task->thread.sve_state = 717 kzalloc(sve_state_size(task), GFP_KERNEL); 718 } 719 720 721 /* 722 * Force the FPSIMD state shared with SVE to be updated in the SVE state 723 * even if the SVE state is the current active state. 724 * 725 * This should only be called by ptrace. task must be non-runnable. 726 * task->thread.sve_state must point to at least sve_state_size(task) 727 * bytes of allocated kernel memory. 728 */ 729 void fpsimd_force_sync_to_sve(struct task_struct *task) 730 { 731 fpsimd_to_sve(task); 732 } 733 734 /* 735 * Ensure that task->thread.sve_state is up to date with respect to 736 * the user task, irrespective of when SVE is in use or not. 737 * 738 * This should only be called by ptrace. task must be non-runnable. 739 * task->thread.sve_state must point to at least sve_state_size(task) 740 * bytes of allocated kernel memory. 741 */ 742 void fpsimd_sync_to_sve(struct task_struct *task) 743 { 744 if (!test_tsk_thread_flag(task, TIF_SVE) && 745 !thread_sm_enabled(&task->thread)) 746 fpsimd_to_sve(task); 747 } 748 749 /* 750 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to 751 * the user task, irrespective of whether SVE is in use or not. 752 * 753 * This should only be called by ptrace. task must be non-runnable. 754 * task->thread.sve_state must point to at least sve_state_size(task) 755 * bytes of allocated kernel memory. 756 */ 757 void sve_sync_to_fpsimd(struct task_struct *task) 758 { 759 if (test_tsk_thread_flag(task, TIF_SVE) || 760 thread_sm_enabled(&task->thread)) 761 sve_to_fpsimd(task); 762 } 763 764 /* 765 * Ensure that task->thread.sve_state is up to date with respect to 766 * the task->thread.uw.fpsimd_state. 767 * 768 * This should only be called by ptrace to merge new FPSIMD register 769 * values into a task for which SVE is currently active. 770 * task must be non-runnable. 771 * task->thread.sve_state must point to at least sve_state_size(task) 772 * bytes of allocated kernel memory. 773 * task->thread.uw.fpsimd_state must already have been initialised with 774 * the new FPSIMD register values to be merged in. 775 */ 776 void sve_sync_from_fpsimd_zeropad(struct task_struct *task) 777 { 778 unsigned int vq; 779 void *sst = task->thread.sve_state; 780 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state; 781 782 if (!test_tsk_thread_flag(task, TIF_SVE)) 783 return; 784 785 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread)); 786 787 memset(sst, 0, SVE_SIG_REGS_SIZE(vq)); 788 __fpsimd_to_sve(sst, fst, vq); 789 } 790 791 int vec_set_vector_length(struct task_struct *task, enum vec_type type, 792 unsigned long vl, unsigned long flags) 793 { 794 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | 795 PR_SVE_SET_VL_ONEXEC)) 796 return -EINVAL; 797 798 if (!sve_vl_valid(vl)) 799 return -EINVAL; 800 801 /* 802 * Clamp to the maximum vector length that VL-agnostic code 803 * can work with. A flag may be assigned in the future to 804 * allow setting of larger vector lengths without confusing 805 * older software. 806 */ 807 if (vl > VL_ARCH_MAX) 808 vl = VL_ARCH_MAX; 809 810 vl = find_supported_vector_length(type, vl); 811 812 if (flags & (PR_SVE_VL_INHERIT | 813 PR_SVE_SET_VL_ONEXEC)) 814 task_set_vl_onexec(task, type, vl); 815 else 816 /* Reset VL to system default on next exec: */ 817 task_set_vl_onexec(task, type, 0); 818 819 /* Only actually set the VL if not deferred: */ 820 if (flags & PR_SVE_SET_VL_ONEXEC) 821 goto out; 822 823 if (vl == task_get_vl(task, type)) 824 goto out; 825 826 /* 827 * To ensure the FPSIMD bits of the SVE vector registers are preserved, 828 * write any live register state back to task_struct, and convert to a 829 * regular FPSIMD thread. 830 */ 831 if (task == current) { 832 get_cpu_fpsimd_context(); 833 834 fpsimd_save(); 835 } 836 837 fpsimd_flush_task_state(task); 838 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) || 839 thread_sm_enabled(&task->thread)) 840 sve_to_fpsimd(task); 841 842 if (system_supports_sme() && type == ARM64_VEC_SME) { 843 task->thread.svcr &= ~(SYS_SVCR_EL0_SM_MASK | 844 SYS_SVCR_EL0_ZA_MASK); 845 clear_thread_flag(TIF_SME); 846 } 847 848 if (task == current) 849 put_cpu_fpsimd_context(); 850 851 /* 852 * Force reallocation of task SVE and SME state to the correct 853 * size on next use: 854 */ 855 sve_free(task); 856 if (system_supports_sme() && type == ARM64_VEC_SME) 857 sme_free(task); 858 859 task_set_vl(task, type, vl); 860 861 out: 862 update_tsk_thread_flag(task, vec_vl_inherit_flag(type), 863 flags & PR_SVE_VL_INHERIT); 864 865 return 0; 866 } 867 868 /* 869 * Encode the current vector length and flags for return. 870 * This is only required for prctl(): ptrace has separate fields. 871 * SVE and SME use the same bits for _ONEXEC and _INHERIT. 872 * 873 * flags are as for vec_set_vector_length(). 874 */ 875 static int vec_prctl_status(enum vec_type type, unsigned long flags) 876 { 877 int ret; 878 879 if (flags & PR_SVE_SET_VL_ONEXEC) 880 ret = task_get_vl_onexec(current, type); 881 else 882 ret = task_get_vl(current, type); 883 884 if (test_thread_flag(vec_vl_inherit_flag(type))) 885 ret |= PR_SVE_VL_INHERIT; 886 887 return ret; 888 } 889 890 /* PR_SVE_SET_VL */ 891 int sve_set_current_vl(unsigned long arg) 892 { 893 unsigned long vl, flags; 894 int ret; 895 896 vl = arg & PR_SVE_VL_LEN_MASK; 897 flags = arg & ~vl; 898 899 if (!system_supports_sve() || is_compat_task()) 900 return -EINVAL; 901 902 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags); 903 if (ret) 904 return ret; 905 906 return vec_prctl_status(ARM64_VEC_SVE, flags); 907 } 908 909 /* PR_SVE_GET_VL */ 910 int sve_get_current_vl(void) 911 { 912 if (!system_supports_sve() || is_compat_task()) 913 return -EINVAL; 914 915 return vec_prctl_status(ARM64_VEC_SVE, 0); 916 } 917 918 #ifdef CONFIG_ARM64_SME 919 /* PR_SME_SET_VL */ 920 int sme_set_current_vl(unsigned long arg) 921 { 922 unsigned long vl, flags; 923 int ret; 924 925 vl = arg & PR_SME_VL_LEN_MASK; 926 flags = arg & ~vl; 927 928 if (!system_supports_sme() || is_compat_task()) 929 return -EINVAL; 930 931 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags); 932 if (ret) 933 return ret; 934 935 return vec_prctl_status(ARM64_VEC_SME, flags); 936 } 937 938 /* PR_SME_GET_VL */ 939 int sme_get_current_vl(void) 940 { 941 if (!system_supports_sme() || is_compat_task()) 942 return -EINVAL; 943 944 return vec_prctl_status(ARM64_VEC_SME, 0); 945 } 946 #endif /* CONFIG_ARM64_SME */ 947 948 static void vec_probe_vqs(struct vl_info *info, 949 DECLARE_BITMAP(map, SVE_VQ_MAX)) 950 { 951 unsigned int vq, vl; 952 953 bitmap_zero(map, SVE_VQ_MAX); 954 955 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) { 956 write_vl(info->type, vq - 1); /* self-syncing */ 957 958 switch (info->type) { 959 case ARM64_VEC_SVE: 960 vl = sve_get_vl(); 961 break; 962 case ARM64_VEC_SME: 963 vl = sme_get_vl(); 964 break; 965 default: 966 vl = 0; 967 break; 968 } 969 970 /* Minimum VL identified? */ 971 if (sve_vq_from_vl(vl) > vq) 972 break; 973 974 vq = sve_vq_from_vl(vl); /* skip intervening lengths */ 975 set_bit(__vq_to_bit(vq), map); 976 } 977 } 978 979 /* 980 * Initialise the set of known supported VQs for the boot CPU. 981 * This is called during kernel boot, before secondary CPUs are brought up. 982 */ 983 void __init vec_init_vq_map(enum vec_type type) 984 { 985 struct vl_info *info = &vl_info[type]; 986 vec_probe_vqs(info, info->vq_map); 987 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX); 988 } 989 990 /* 991 * If we haven't committed to the set of supported VQs yet, filter out 992 * those not supported by the current CPU. 993 * This function is called during the bring-up of early secondary CPUs only. 994 */ 995 void vec_update_vq_map(enum vec_type type) 996 { 997 struct vl_info *info = &vl_info[type]; 998 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 999 1000 vec_probe_vqs(info, tmp_map); 1001 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX); 1002 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map, 1003 SVE_VQ_MAX); 1004 } 1005 1006 /* 1007 * Check whether the current CPU supports all VQs in the committed set. 1008 * This function is called during the bring-up of late secondary CPUs only. 1009 */ 1010 int vec_verify_vq_map(enum vec_type type) 1011 { 1012 struct vl_info *info = &vl_info[type]; 1013 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1014 unsigned long b; 1015 1016 vec_probe_vqs(info, tmp_map); 1017 1018 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1019 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) { 1020 pr_warn("%s: cpu%d: Required vector length(s) missing\n", 1021 info->name, smp_processor_id()); 1022 return -EINVAL; 1023 } 1024 1025 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) 1026 return 0; 1027 1028 /* 1029 * For KVM, it is necessary to ensure that this CPU doesn't 1030 * support any vector length that guests may have probed as 1031 * unsupported. 1032 */ 1033 1034 /* Recover the set of supported VQs: */ 1035 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX); 1036 /* Find VQs supported that are not globally supported: */ 1037 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX); 1038 1039 /* Find the lowest such VQ, if any: */ 1040 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1041 if (b >= SVE_VQ_MAX) 1042 return 0; /* no mismatches */ 1043 1044 /* 1045 * Mismatches above sve_max_virtualisable_vl are fine, since 1046 * no guest is allowed to configure ZCR_EL2.LEN to exceed this: 1047 */ 1048 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) { 1049 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n", 1050 info->name, smp_processor_id()); 1051 return -EINVAL; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static void __init sve_efi_setup(void) 1058 { 1059 int max_vl = 0; 1060 int i; 1061 1062 if (!IS_ENABLED(CONFIG_EFI)) 1063 return; 1064 1065 for (i = 0; i < ARRAY_SIZE(vl_info); i++) 1066 max_vl = max(vl_info[i].max_vl, max_vl); 1067 1068 /* 1069 * alloc_percpu() warns and prints a backtrace if this goes wrong. 1070 * This is evidence of a crippled system and we are returning void, 1071 * so no attempt is made to handle this situation here. 1072 */ 1073 if (!sve_vl_valid(max_vl)) 1074 goto fail; 1075 1076 efi_sve_state = __alloc_percpu( 1077 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES); 1078 if (!efi_sve_state) 1079 goto fail; 1080 1081 return; 1082 1083 fail: 1084 panic("Cannot allocate percpu memory for EFI SVE save/restore"); 1085 } 1086 1087 /* 1088 * Enable SVE for EL1. 1089 * Intended for use by the cpufeatures code during CPU boot. 1090 */ 1091 void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1092 { 1093 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); 1094 isb(); 1095 } 1096 1097 /* 1098 * Read the pseudo-ZCR used by cpufeatures to identify the supported SVE 1099 * vector length. 1100 * 1101 * Use only if SVE is present. 1102 * This function clobbers the SVE vector length. 1103 */ 1104 u64 read_zcr_features(void) 1105 { 1106 u64 zcr; 1107 unsigned int vq_max; 1108 1109 /* 1110 * Set the maximum possible VL, and write zeroes to all other 1111 * bits to see if they stick. 1112 */ 1113 sve_kernel_enable(NULL); 1114 write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1); 1115 1116 zcr = read_sysreg_s(SYS_ZCR_EL1); 1117 zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */ 1118 vq_max = sve_vq_from_vl(sve_get_vl()); 1119 zcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1120 1121 return zcr; 1122 } 1123 1124 void __init sve_setup(void) 1125 { 1126 struct vl_info *info = &vl_info[ARM64_VEC_SVE]; 1127 u64 zcr; 1128 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); 1129 unsigned long b; 1130 1131 if (!system_supports_sve()) 1132 return; 1133 1134 /* 1135 * The SVE architecture mandates support for 128-bit vectors, 1136 * so sve_vq_map must have at least SVE_VQ_MIN set. 1137 * If something went wrong, at least try to patch it up: 1138 */ 1139 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map))) 1140 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map); 1141 1142 zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1143 info->max_vl = sve_vl_from_vq((zcr & ZCR_ELx_LEN_MASK) + 1); 1144 1145 /* 1146 * Sanity-check that the max VL we determined through CPU features 1147 * corresponds properly to sve_vq_map. If not, do our best: 1148 */ 1149 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SVE, 1150 info->max_vl))) 1151 info->max_vl = find_supported_vector_length(ARM64_VEC_SVE, 1152 info->max_vl); 1153 1154 /* 1155 * For the default VL, pick the maximum supported value <= 64. 1156 * VL == 64 is guaranteed not to grow the signal frame. 1157 */ 1158 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64)); 1159 1160 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map, 1161 SVE_VQ_MAX); 1162 1163 b = find_last_bit(tmp_map, SVE_VQ_MAX); 1164 if (b >= SVE_VQ_MAX) 1165 /* No non-virtualisable VLs found */ 1166 info->max_virtualisable_vl = SVE_VQ_MAX; 1167 else if (WARN_ON(b == SVE_VQ_MAX - 1)) 1168 /* No virtualisable VLs? This is architecturally forbidden. */ 1169 info->max_virtualisable_vl = SVE_VQ_MIN; 1170 else /* b + 1 < SVE_VQ_MAX */ 1171 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1)); 1172 1173 if (info->max_virtualisable_vl > info->max_vl) 1174 info->max_virtualisable_vl = info->max_vl; 1175 1176 pr_info("%s: maximum available vector length %u bytes per vector\n", 1177 info->name, info->max_vl); 1178 pr_info("%s: default vector length %u bytes per vector\n", 1179 info->name, get_sve_default_vl()); 1180 1181 /* KVM decides whether to support mismatched systems. Just warn here: */ 1182 if (sve_max_virtualisable_vl() < sve_max_vl()) 1183 pr_warn("%s: unvirtualisable vector lengths present\n", 1184 info->name); 1185 1186 sve_efi_setup(); 1187 } 1188 1189 /* 1190 * Called from the put_task_struct() path, which cannot get here 1191 * unless dead_task is really dead and not schedulable. 1192 */ 1193 void fpsimd_release_task(struct task_struct *dead_task) 1194 { 1195 __sve_free(dead_task); 1196 sme_free(dead_task); 1197 } 1198 1199 #endif /* CONFIG_ARM64_SVE */ 1200 1201 #ifdef CONFIG_ARM64_SME 1202 1203 /* 1204 * Ensure that task->thread.za_state is allocated and sufficiently large. 1205 * 1206 * This function should be used only in preparation for replacing 1207 * task->thread.za_state with new data. The memory is always zeroed 1208 * here to prevent stale data from showing through: this is done in 1209 * the interest of testability and predictability, the architecture 1210 * guarantees that when ZA is enabled it will be zeroed. 1211 */ 1212 void sme_alloc(struct task_struct *task) 1213 { 1214 if (task->thread.za_state) { 1215 memset(task->thread.za_state, 0, za_state_size(task)); 1216 return; 1217 } 1218 1219 /* This could potentially be up to 64K. */ 1220 task->thread.za_state = 1221 kzalloc(za_state_size(task), GFP_KERNEL); 1222 } 1223 1224 static void sme_free(struct task_struct *task) 1225 { 1226 kfree(task->thread.za_state); 1227 task->thread.za_state = NULL; 1228 } 1229 1230 void sme_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1231 { 1232 /* Set priority for all PEs to architecturally defined minimum */ 1233 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK, 1234 SYS_SMPRI_EL1); 1235 1236 /* Allow SME in kernel */ 1237 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1); 1238 isb(); 1239 1240 /* Allow EL0 to access TPIDR2 */ 1241 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1); 1242 isb(); 1243 } 1244 1245 /* 1246 * This must be called after sme_kernel_enable(), we rely on the 1247 * feature table being sorted to ensure this. 1248 */ 1249 void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) 1250 { 1251 /* Allow use of FA64 */ 1252 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK, 1253 SYS_SMCR_EL1); 1254 } 1255 1256 /* 1257 * Read the pseudo-SMCR used by cpufeatures to identify the supported 1258 * vector length. 1259 * 1260 * Use only if SME is present. 1261 * This function clobbers the SME vector length. 1262 */ 1263 u64 read_smcr_features(void) 1264 { 1265 u64 smcr; 1266 unsigned int vq_max; 1267 1268 sme_kernel_enable(NULL); 1269 sme_smstart_sm(); 1270 1271 /* 1272 * Set the maximum possible VL. 1273 */ 1274 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK, 1275 SYS_SMCR_EL1); 1276 1277 smcr = read_sysreg_s(SYS_SMCR_EL1); 1278 smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */ 1279 vq_max = sve_vq_from_vl(sve_get_vl()); 1280 smcr |= vq_max - 1; /* set LEN field to maximum effective value */ 1281 1282 sme_smstop_sm(); 1283 1284 return smcr; 1285 } 1286 1287 void __init sme_setup(void) 1288 { 1289 struct vl_info *info = &vl_info[ARM64_VEC_SME]; 1290 u64 smcr; 1291 int min_bit; 1292 1293 if (!system_supports_sme()) 1294 return; 1295 1296 /* 1297 * SME doesn't require any particular vector length be 1298 * supported but it does require at least one. We should have 1299 * disabled the feature entirely while bringing up CPUs but 1300 * let's double check here. 1301 */ 1302 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX)); 1303 1304 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX); 1305 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit)); 1306 1307 smcr = read_sanitised_ftr_reg(SYS_SMCR_EL1); 1308 info->max_vl = sve_vl_from_vq((smcr & SMCR_ELx_LEN_MASK) + 1); 1309 1310 /* 1311 * Sanity-check that the max VL we determined through CPU features 1312 * corresponds properly to sme_vq_map. If not, do our best: 1313 */ 1314 if (WARN_ON(info->max_vl != find_supported_vector_length(ARM64_VEC_SME, 1315 info->max_vl))) 1316 info->max_vl = find_supported_vector_length(ARM64_VEC_SME, 1317 info->max_vl); 1318 1319 WARN_ON(info->min_vl > info->max_vl); 1320 1321 /* 1322 * For the default VL, pick the maximum supported value <= 32 1323 * (256 bits) if there is one since this is guaranteed not to 1324 * grow the signal frame when in streaming mode, otherwise the 1325 * minimum available VL will be used. 1326 */ 1327 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32)); 1328 1329 pr_info("SME: minimum available vector length %u bytes per vector\n", 1330 info->min_vl); 1331 pr_info("SME: maximum available vector length %u bytes per vector\n", 1332 info->max_vl); 1333 pr_info("SME: default vector length %u bytes per vector\n", 1334 get_sme_default_vl()); 1335 } 1336 1337 #endif /* CONFIG_ARM64_SME */ 1338 1339 static void sve_init_regs(void) 1340 { 1341 /* 1342 * Convert the FPSIMD state to SVE, zeroing all the state that 1343 * is not shared with FPSIMD. If (as is likely) the current 1344 * state is live in the registers then do this there and 1345 * update our metadata for the current task including 1346 * disabling the trap, otherwise update our in-memory copy. 1347 * We are guaranteed to not be in streaming mode, we can only 1348 * take a SVE trap when not in streaming mode and we can't be 1349 * in streaming mode when taking a SME trap. 1350 */ 1351 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1352 unsigned long vq_minus_one = 1353 sve_vq_from_vl(task_get_sve_vl(current)) - 1; 1354 sve_set_vq(vq_minus_one); 1355 sve_flush_live(true, vq_minus_one); 1356 fpsimd_bind_task_to_cpu(); 1357 } else { 1358 fpsimd_to_sve(current); 1359 } 1360 } 1361 1362 /* 1363 * Trapped SVE access 1364 * 1365 * Storage is allocated for the full SVE state, the current FPSIMD 1366 * register contents are migrated across, and the access trap is 1367 * disabled. 1368 * 1369 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state() 1370 * would have disabled the SVE access trap for userspace during 1371 * ret_to_user, making an SVE access trap impossible in that case. 1372 */ 1373 void do_sve_acc(unsigned int esr, struct pt_regs *regs) 1374 { 1375 /* Even if we chose not to use SVE, the hardware could still trap: */ 1376 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) { 1377 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1378 return; 1379 } 1380 1381 sve_alloc(current); 1382 if (!current->thread.sve_state) { 1383 force_sig(SIGKILL); 1384 return; 1385 } 1386 1387 get_cpu_fpsimd_context(); 1388 1389 if (test_and_set_thread_flag(TIF_SVE)) 1390 WARN_ON(1); /* SVE access shouldn't have trapped */ 1391 1392 /* 1393 * Even if the task can have used streaming mode we can only 1394 * generate SVE access traps in normal SVE mode and 1395 * transitioning out of streaming mode may discard any 1396 * streaming mode state. Always clear the high bits to avoid 1397 * any potential errors tracking what is properly initialised. 1398 */ 1399 sve_init_regs(); 1400 1401 put_cpu_fpsimd_context(); 1402 } 1403 1404 /* 1405 * Trapped SME access 1406 * 1407 * Storage is allocated for the full SVE and SME state, the current 1408 * FPSIMD register contents are migrated to SVE if SVE is not already 1409 * active, and the access trap is disabled. 1410 * 1411 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state() 1412 * would have disabled the SME access trap for userspace during 1413 * ret_to_user, making an SVE access trap impossible in that case. 1414 */ 1415 void do_sme_acc(unsigned int esr, struct pt_regs *regs) 1416 { 1417 /* Even if we chose not to use SME, the hardware could still trap: */ 1418 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) { 1419 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1420 return; 1421 } 1422 1423 /* 1424 * If this not a trap due to SME being disabled then something 1425 * is being used in the wrong mode, report as SIGILL. 1426 */ 1427 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) { 1428 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); 1429 return; 1430 } 1431 1432 sve_alloc(current); 1433 sme_alloc(current); 1434 if (!current->thread.sve_state || !current->thread.za_state) { 1435 force_sig(SIGKILL); 1436 return; 1437 } 1438 1439 get_cpu_fpsimd_context(); 1440 1441 /* With TIF_SME userspace shouldn't generate any traps */ 1442 if (test_and_set_thread_flag(TIF_SME)) 1443 WARN_ON(1); 1444 1445 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { 1446 unsigned long vq_minus_one = 1447 sve_vq_from_vl(task_get_sme_vl(current)) - 1; 1448 sme_set_vq(vq_minus_one); 1449 1450 fpsimd_bind_task_to_cpu(); 1451 } 1452 1453 /* 1454 * If SVE was not already active initialise the SVE registers, 1455 * any non-shared state between the streaming and regular SVE 1456 * registers is architecturally guaranteed to be zeroed when 1457 * we enter streaming mode. We do not need to initialize ZA 1458 * since ZA must be disabled at this point and enabling ZA is 1459 * architecturally defined to zero ZA. 1460 */ 1461 if (system_supports_sve() && !test_thread_flag(TIF_SVE)) 1462 sve_init_regs(); 1463 1464 put_cpu_fpsimd_context(); 1465 } 1466 1467 /* 1468 * Trapped FP/ASIMD access. 1469 */ 1470 void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs) 1471 { 1472 /* TODO: implement lazy context saving/restoring */ 1473 WARN_ON(1); 1474 } 1475 1476 /* 1477 * Raise a SIGFPE for the current process. 1478 */ 1479 void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs) 1480 { 1481 unsigned int si_code = FPE_FLTUNK; 1482 1483 if (esr & ESR_ELx_FP_EXC_TFV) { 1484 if (esr & FPEXC_IOF) 1485 si_code = FPE_FLTINV; 1486 else if (esr & FPEXC_DZF) 1487 si_code = FPE_FLTDIV; 1488 else if (esr & FPEXC_OFF) 1489 si_code = FPE_FLTOVF; 1490 else if (esr & FPEXC_UFF) 1491 si_code = FPE_FLTUND; 1492 else if (esr & FPEXC_IXF) 1493 si_code = FPE_FLTRES; 1494 } 1495 1496 send_sig_fault(SIGFPE, si_code, 1497 (void __user *)instruction_pointer(regs), 1498 current); 1499 } 1500 1501 void fpsimd_thread_switch(struct task_struct *next) 1502 { 1503 bool wrong_task, wrong_cpu; 1504 1505 if (!system_supports_fpsimd()) 1506 return; 1507 1508 __get_cpu_fpsimd_context(); 1509 1510 /* Save unsaved fpsimd state, if any: */ 1511 fpsimd_save(); 1512 1513 /* 1514 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's 1515 * state. For kernel threads, FPSIMD registers are never loaded 1516 * and wrong_task and wrong_cpu will always be true. 1517 */ 1518 wrong_task = __this_cpu_read(fpsimd_last_state.st) != 1519 &next->thread.uw.fpsimd_state; 1520 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id(); 1521 1522 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE, 1523 wrong_task || wrong_cpu); 1524 1525 __put_cpu_fpsimd_context(); 1526 } 1527 1528 static void fpsimd_flush_thread_vl(enum vec_type type) 1529 { 1530 int vl, supported_vl; 1531 1532 /* 1533 * Reset the task vector length as required. This is where we 1534 * ensure that all user tasks have a valid vector length 1535 * configured: no kernel task can become a user task without 1536 * an exec and hence a call to this function. By the time the 1537 * first call to this function is made, all early hardware 1538 * probing is complete, so __sve_default_vl should be valid. 1539 * If a bug causes this to go wrong, we make some noise and 1540 * try to fudge thread.sve_vl to a safe value here. 1541 */ 1542 vl = task_get_vl_onexec(current, type); 1543 if (!vl) 1544 vl = get_default_vl(type); 1545 1546 if (WARN_ON(!sve_vl_valid(vl))) 1547 vl = vl_info[type].min_vl; 1548 1549 supported_vl = find_supported_vector_length(type, vl); 1550 if (WARN_ON(supported_vl != vl)) 1551 vl = supported_vl; 1552 1553 task_set_vl(current, type, vl); 1554 1555 /* 1556 * If the task is not set to inherit, ensure that the vector 1557 * length will be reset by a subsequent exec: 1558 */ 1559 if (!test_thread_flag(vec_vl_inherit_flag(type))) 1560 task_set_vl_onexec(current, type, 0); 1561 } 1562 1563 void fpsimd_flush_thread(void) 1564 { 1565 if (!system_supports_fpsimd()) 1566 return; 1567 1568 get_cpu_fpsimd_context(); 1569 1570 fpsimd_flush_task_state(current); 1571 memset(¤t->thread.uw.fpsimd_state, 0, 1572 sizeof(current->thread.uw.fpsimd_state)); 1573 1574 if (system_supports_sve()) { 1575 clear_thread_flag(TIF_SVE); 1576 sve_free(current); 1577 fpsimd_flush_thread_vl(ARM64_VEC_SVE); 1578 } 1579 1580 if (system_supports_sme()) { 1581 clear_thread_flag(TIF_SME); 1582 sme_free(current); 1583 fpsimd_flush_thread_vl(ARM64_VEC_SME); 1584 current->thread.svcr = 0; 1585 } 1586 1587 put_cpu_fpsimd_context(); 1588 } 1589 1590 /* 1591 * Save the userland FPSIMD state of 'current' to memory, but only if the state 1592 * currently held in the registers does in fact belong to 'current' 1593 */ 1594 void fpsimd_preserve_current_state(void) 1595 { 1596 if (!system_supports_fpsimd()) 1597 return; 1598 1599 get_cpu_fpsimd_context(); 1600 fpsimd_save(); 1601 put_cpu_fpsimd_context(); 1602 } 1603 1604 /* 1605 * Like fpsimd_preserve_current_state(), but ensure that 1606 * current->thread.uw.fpsimd_state is updated so that it can be copied to 1607 * the signal frame. 1608 */ 1609 void fpsimd_signal_preserve_current_state(void) 1610 { 1611 fpsimd_preserve_current_state(); 1612 if (test_thread_flag(TIF_SVE)) 1613 sve_to_fpsimd(current); 1614 } 1615 1616 /* 1617 * Associate current's FPSIMD context with this cpu 1618 * The caller must have ownership of the cpu FPSIMD context before calling 1619 * this function. 1620 */ 1621 static void fpsimd_bind_task_to_cpu(void) 1622 { 1623 struct fpsimd_last_state_struct *last = 1624 this_cpu_ptr(&fpsimd_last_state); 1625 1626 WARN_ON(!system_supports_fpsimd()); 1627 last->st = ¤t->thread.uw.fpsimd_state; 1628 last->sve_state = current->thread.sve_state; 1629 last->za_state = current->thread.za_state; 1630 last->sve_vl = task_get_sve_vl(current); 1631 last->sme_vl = task_get_sme_vl(current); 1632 last->svcr = ¤t->thread.svcr; 1633 current->thread.fpsimd_cpu = smp_processor_id(); 1634 1635 /* 1636 * Toggle SVE and SME trapping for userspace if needed, these 1637 * are serialsied by ret_to_user(). 1638 */ 1639 if (system_supports_sme()) { 1640 if (test_thread_flag(TIF_SME)) 1641 sme_user_enable(); 1642 else 1643 sme_user_disable(); 1644 } 1645 1646 if (system_supports_sve()) { 1647 if (test_thread_flag(TIF_SVE)) 1648 sve_user_enable(); 1649 else 1650 sve_user_disable(); 1651 } 1652 } 1653 1654 void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *st, void *sve_state, 1655 unsigned int sve_vl, void *za_state, 1656 unsigned int sme_vl, u64 *svcr) 1657 { 1658 struct fpsimd_last_state_struct *last = 1659 this_cpu_ptr(&fpsimd_last_state); 1660 1661 WARN_ON(!system_supports_fpsimd()); 1662 WARN_ON(!in_softirq() && !irqs_disabled()); 1663 1664 last->st = st; 1665 last->svcr = svcr; 1666 last->sve_state = sve_state; 1667 last->za_state = za_state; 1668 last->sve_vl = sve_vl; 1669 last->sme_vl = sme_vl; 1670 } 1671 1672 /* 1673 * Load the userland FPSIMD state of 'current' from memory, but only if the 1674 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD 1675 * state of 'current'. This is called when we are preparing to return to 1676 * userspace to ensure that userspace sees a good register state. 1677 */ 1678 void fpsimd_restore_current_state(void) 1679 { 1680 /* 1681 * For the tasks that were created before we detected the absence of 1682 * FP/SIMD, the TIF_FOREIGN_FPSTATE could be set via fpsimd_thread_switch(), 1683 * e.g, init. This could be then inherited by the children processes. 1684 * If we later detect that the system doesn't support FP/SIMD, 1685 * we must clear the flag for all the tasks to indicate that the 1686 * FPSTATE is clean (as we can't have one) to avoid looping for ever in 1687 * do_notify_resume(). 1688 */ 1689 if (!system_supports_fpsimd()) { 1690 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1691 return; 1692 } 1693 1694 get_cpu_fpsimd_context(); 1695 1696 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) { 1697 task_fpsimd_load(); 1698 fpsimd_bind_task_to_cpu(); 1699 } 1700 1701 put_cpu_fpsimd_context(); 1702 } 1703 1704 /* 1705 * Load an updated userland FPSIMD state for 'current' from memory and set the 1706 * flag that indicates that the FPSIMD register contents are the most recent 1707 * FPSIMD state of 'current'. This is used by the signal code to restore the 1708 * register state when returning from a signal handler in FPSIMD only cases, 1709 * any SVE context will be discarded. 1710 */ 1711 void fpsimd_update_current_state(struct user_fpsimd_state const *state) 1712 { 1713 if (WARN_ON(!system_supports_fpsimd())) 1714 return; 1715 1716 get_cpu_fpsimd_context(); 1717 1718 current->thread.uw.fpsimd_state = *state; 1719 if (test_thread_flag(TIF_SVE)) 1720 fpsimd_to_sve(current); 1721 1722 task_fpsimd_load(); 1723 fpsimd_bind_task_to_cpu(); 1724 1725 clear_thread_flag(TIF_FOREIGN_FPSTATE); 1726 1727 put_cpu_fpsimd_context(); 1728 } 1729 1730 /* 1731 * Invalidate live CPU copies of task t's FPSIMD state 1732 * 1733 * This function may be called with preemption enabled. The barrier() 1734 * ensures that the assignment to fpsimd_cpu is visible to any 1735 * preemption/softirq that could race with set_tsk_thread_flag(), so 1736 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared. 1737 * 1738 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1739 * subsequent code. 1740 */ 1741 void fpsimd_flush_task_state(struct task_struct *t) 1742 { 1743 t->thread.fpsimd_cpu = NR_CPUS; 1744 /* 1745 * If we don't support fpsimd, bail out after we have 1746 * reset the fpsimd_cpu for this task and clear the 1747 * FPSTATE. 1748 */ 1749 if (!system_supports_fpsimd()) 1750 return; 1751 barrier(); 1752 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE); 1753 1754 barrier(); 1755 } 1756 1757 /* 1758 * Invalidate any task's FPSIMD state that is present on this cpu. 1759 * The FPSIMD context should be acquired with get_cpu_fpsimd_context() 1760 * before calling this function. 1761 */ 1762 static void fpsimd_flush_cpu_state(void) 1763 { 1764 WARN_ON(!system_supports_fpsimd()); 1765 __this_cpu_write(fpsimd_last_state.st, NULL); 1766 1767 /* 1768 * Leaving streaming mode enabled will cause issues for any kernel 1769 * NEON and leaving streaming mode or ZA enabled may increase power 1770 * consumption. 1771 */ 1772 if (system_supports_sme()) 1773 sme_smstop(); 1774 1775 set_thread_flag(TIF_FOREIGN_FPSTATE); 1776 } 1777 1778 /* 1779 * Save the FPSIMD state to memory and invalidate cpu view. 1780 * This function must be called with preemption disabled. 1781 */ 1782 void fpsimd_save_and_flush_cpu_state(void) 1783 { 1784 if (!system_supports_fpsimd()) 1785 return; 1786 WARN_ON(preemptible()); 1787 __get_cpu_fpsimd_context(); 1788 fpsimd_save(); 1789 fpsimd_flush_cpu_state(); 1790 __put_cpu_fpsimd_context(); 1791 } 1792 1793 #ifdef CONFIG_KERNEL_MODE_NEON 1794 1795 /* 1796 * Kernel-side NEON support functions 1797 */ 1798 1799 /* 1800 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling 1801 * context 1802 * 1803 * Must not be called unless may_use_simd() returns true. 1804 * Task context in the FPSIMD registers is saved back to memory as necessary. 1805 * 1806 * A matching call to kernel_neon_end() must be made before returning from the 1807 * calling context. 1808 * 1809 * The caller may freely use the FPSIMD registers until kernel_neon_end() is 1810 * called. 1811 */ 1812 void kernel_neon_begin(void) 1813 { 1814 if (WARN_ON(!system_supports_fpsimd())) 1815 return; 1816 1817 BUG_ON(!may_use_simd()); 1818 1819 get_cpu_fpsimd_context(); 1820 1821 /* Save unsaved fpsimd state, if any: */ 1822 fpsimd_save(); 1823 1824 /* Invalidate any task state remaining in the fpsimd regs: */ 1825 fpsimd_flush_cpu_state(); 1826 } 1827 EXPORT_SYMBOL(kernel_neon_begin); 1828 1829 /* 1830 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task 1831 * 1832 * Must be called from a context in which kernel_neon_begin() was previously 1833 * called, with no call to kernel_neon_end() in the meantime. 1834 * 1835 * The caller must not use the FPSIMD registers after this function is called, 1836 * unless kernel_neon_begin() is called again in the meantime. 1837 */ 1838 void kernel_neon_end(void) 1839 { 1840 if (!system_supports_fpsimd()) 1841 return; 1842 1843 put_cpu_fpsimd_context(); 1844 } 1845 EXPORT_SYMBOL(kernel_neon_end); 1846 1847 #ifdef CONFIG_EFI 1848 1849 static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state); 1850 static DEFINE_PER_CPU(bool, efi_fpsimd_state_used); 1851 static DEFINE_PER_CPU(bool, efi_sve_state_used); 1852 static DEFINE_PER_CPU(bool, efi_sm_state); 1853 1854 /* 1855 * EFI runtime services support functions 1856 * 1857 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call. 1858 * This means that for EFI (and only for EFI), we have to assume that FPSIMD 1859 * is always used rather than being an optional accelerator. 1860 * 1861 * These functions provide the necessary support for ensuring FPSIMD 1862 * save/restore in the contexts from which EFI is used. 1863 * 1864 * Do not use them for any other purpose -- if tempted to do so, you are 1865 * either doing something wrong or you need to propose some refactoring. 1866 */ 1867 1868 /* 1869 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call 1870 */ 1871 void __efi_fpsimd_begin(void) 1872 { 1873 if (!system_supports_fpsimd()) 1874 return; 1875 1876 WARN_ON(preemptible()); 1877 1878 if (may_use_simd()) { 1879 kernel_neon_begin(); 1880 } else { 1881 /* 1882 * If !efi_sve_state, SVE can't be in use yet and doesn't need 1883 * preserving: 1884 */ 1885 if (system_supports_sve() && likely(efi_sve_state)) { 1886 char *sve_state = this_cpu_ptr(efi_sve_state); 1887 bool ffr = true; 1888 u64 svcr; 1889 1890 __this_cpu_write(efi_sve_state_used, true); 1891 1892 if (system_supports_sme()) { 1893 svcr = read_sysreg_s(SYS_SVCR_EL0); 1894 1895 if (!system_supports_fa64()) 1896 ffr = svcr & SYS_SVCR_EL0_SM_MASK; 1897 1898 __this_cpu_write(efi_sm_state, ffr); 1899 } 1900 1901 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()), 1902 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1903 ffr); 1904 1905 if (system_supports_sme()) 1906 sysreg_clear_set_s(SYS_SVCR_EL0, 1907 SYS_SVCR_EL0_SM_MASK, 0); 1908 1909 } else { 1910 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); 1911 } 1912 1913 __this_cpu_write(efi_fpsimd_state_used, true); 1914 } 1915 } 1916 1917 /* 1918 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call 1919 */ 1920 void __efi_fpsimd_end(void) 1921 { 1922 if (!system_supports_fpsimd()) 1923 return; 1924 1925 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) { 1926 kernel_neon_end(); 1927 } else { 1928 if (system_supports_sve() && 1929 likely(__this_cpu_read(efi_sve_state_used))) { 1930 char const *sve_state = this_cpu_ptr(efi_sve_state); 1931 bool ffr = true; 1932 1933 /* 1934 * Restore streaming mode; EFI calls are 1935 * normal function calls so should not return in 1936 * streaming mode. 1937 */ 1938 if (system_supports_sme()) { 1939 if (__this_cpu_read(efi_sm_state)) { 1940 sysreg_clear_set_s(SYS_SVCR_EL0, 1941 0, 1942 SYS_SVCR_EL0_SM_MASK); 1943 if (!system_supports_fa64()) 1944 ffr = efi_sm_state; 1945 } 1946 } 1947 1948 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()), 1949 &this_cpu_ptr(&efi_fpsimd_state)->fpsr, 1950 ffr); 1951 1952 __this_cpu_write(efi_sve_state_used, false); 1953 } else { 1954 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); 1955 } 1956 } 1957 } 1958 1959 #endif /* CONFIG_EFI */ 1960 1961 #endif /* CONFIG_KERNEL_MODE_NEON */ 1962 1963 #ifdef CONFIG_CPU_PM 1964 static int fpsimd_cpu_pm_notifier(struct notifier_block *self, 1965 unsigned long cmd, void *v) 1966 { 1967 switch (cmd) { 1968 case CPU_PM_ENTER: 1969 fpsimd_save_and_flush_cpu_state(); 1970 break; 1971 case CPU_PM_EXIT: 1972 break; 1973 case CPU_PM_ENTER_FAILED: 1974 default: 1975 return NOTIFY_DONE; 1976 } 1977 return NOTIFY_OK; 1978 } 1979 1980 static struct notifier_block fpsimd_cpu_pm_notifier_block = { 1981 .notifier_call = fpsimd_cpu_pm_notifier, 1982 }; 1983 1984 static void __init fpsimd_pm_init(void) 1985 { 1986 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block); 1987 } 1988 1989 #else 1990 static inline void fpsimd_pm_init(void) { } 1991 #endif /* CONFIG_CPU_PM */ 1992 1993 #ifdef CONFIG_HOTPLUG_CPU 1994 static int fpsimd_cpu_dead(unsigned int cpu) 1995 { 1996 per_cpu(fpsimd_last_state.st, cpu) = NULL; 1997 return 0; 1998 } 1999 2000 static inline void fpsimd_hotplug_init(void) 2001 { 2002 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead", 2003 NULL, fpsimd_cpu_dead); 2004 } 2005 2006 #else 2007 static inline void fpsimd_hotplug_init(void) { } 2008 #endif 2009 2010 /* 2011 * FP/SIMD support code initialisation. 2012 */ 2013 static int __init fpsimd_init(void) 2014 { 2015 if (cpu_have_named_feature(FP)) { 2016 fpsimd_pm_init(); 2017 fpsimd_hotplug_init(); 2018 } else { 2019 pr_notice("Floating-point is not implemented\n"); 2020 } 2021 2022 if (!cpu_have_named_feature(ASIMD)) 2023 pr_notice("Advanced SIMD is not implemented\n"); 2024 2025 2026 if (cpu_have_named_feature(SME) && !cpu_have_named_feature(SVE)) 2027 pr_notice("SME is implemented but not SVE\n"); 2028 2029 sve_sysctl_init(); 2030 sme_sysctl_init(); 2031 2032 return 0; 2033 } 2034 core_initcall(fpsimd_init); 2035