1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32 .macro clear_gp_regs 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 34 mov x\n, xzr 35 .endr 36 .endm 37 38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 39 .align 7 40.Lventry_start\@: 41 .if \el == 0 42 /* 43 * This must be the first instruction of the EL0 vector entries. It is 44 * skipped by the trampoline vectors, to trigger the cleanup. 45 */ 46 b .Lskip_tramp_vectors_cleanup\@ 47 .if \regsize == 64 48 mrs x30, tpidrro_el0 49 msr tpidrro_el0, xzr 50 .else 51 mov x30, xzr 52 .endif 53.Lskip_tramp_vectors_cleanup\@: 54 .endif 55 56 sub sp, sp, #PT_REGS_SIZE 57#ifdef CONFIG_VMAP_STACK 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99#endif 100 b el\el\ht\()_\regsize\()_\label 101.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 102 .endm 103 104 .macro tramp_alias, dst, sym, tmp 105 mov_q \dst, TRAMP_VALIAS 106 adr_l \tmp, \sym 107 add \dst, \dst, \tmp 108 adr_l \tmp, .entry.tramp.text 109 sub \dst, \dst, \tmp 110 .endm 111 112 /* 113 * This macro corrupts x0-x3. It is the caller's duty to save/restore 114 * them if required. 115 */ 116 .macro apply_ssbd, state, tmp1, tmp2 117alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable 118 b .L__asm_ssbd_skip\@ // Patched to NOP 119alternative_cb_end 120 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 121 cbz \tmp2, .L__asm_ssbd_skip\@ 122 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 123 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 124 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 125 mov w1, #\state 126alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 127 nop // Patched to SMC/HVC #0 128alternative_cb_end 129.L__asm_ssbd_skip\@: 130 .endm 131 132 /* Check for MTE asynchronous tag check faults */ 133 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 134#ifdef CONFIG_ARM64_MTE 135 .arch_extension lse 136alternative_if_not ARM64_MTE 137 b 1f 138alternative_else_nop_endif 139 /* 140 * Asynchronous tag check faults are only possible in ASYNC (2) or 141 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 142 * set, so skip the check if it is unset. 143 */ 144 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 145 mrs_s \tmp, SYS_TFSRE0_EL1 146 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 147 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 148 mov \tmp, #_TIF_MTE_ASYNC_FAULT 149 add \ti_flags, tsk, #TSK_TI_FLAGS 150 stset \tmp, [\ti_flags] 1511: 152#endif 153 .endm 154 155 /* Clear the MTE asynchronous tag check faults */ 156 .macro clear_mte_async_tcf thread_sctlr 157#ifdef CONFIG_ARM64_MTE 158alternative_if ARM64_MTE 159 /* See comment in check_mte_async_tcf above. */ 160 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 161 dsb ish 162 msr_s SYS_TFSRE0_EL1, xzr 1631: 164alternative_else_nop_endif 165#endif 166 .endm 167 168 .macro mte_set_gcr, mte_ctrl, tmp 169#ifdef CONFIG_ARM64_MTE 170 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 171 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 172 msr_s SYS_GCR_EL1, \tmp 173#endif 174 .endm 175 176 .macro mte_set_kernel_gcr, tmp, tmp2 177#ifdef CONFIG_KASAN_HW_TAGS 178alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 179 b 1f 180alternative_cb_end 181 mov \tmp, KERNEL_GCR_EL1 182 msr_s SYS_GCR_EL1, \tmp 1831: 184#endif 185 .endm 186 187 .macro mte_set_user_gcr, tsk, tmp, tmp2 188#ifdef CONFIG_KASAN_HW_TAGS 189alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 190 b 1f 191alternative_cb_end 192 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 193 194 mte_set_gcr \tmp, \tmp2 1951: 196#endif 197 .endm 198 199 .macro kernel_entry, el, regsize = 64 200 .if \el == 0 201 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT 202 .endif 203 .if \regsize == 32 204 mov w0, w0 // zero upper 32 bits of x0 205 .endif 206 stp x0, x1, [sp, #16 * 0] 207 stp x2, x3, [sp, #16 * 1] 208 stp x4, x5, [sp, #16 * 2] 209 stp x6, x7, [sp, #16 * 3] 210 stp x8, x9, [sp, #16 * 4] 211 stp x10, x11, [sp, #16 * 5] 212 stp x12, x13, [sp, #16 * 6] 213 stp x14, x15, [sp, #16 * 7] 214 stp x16, x17, [sp, #16 * 8] 215 stp x18, x19, [sp, #16 * 9] 216 stp x20, x21, [sp, #16 * 10] 217 stp x22, x23, [sp, #16 * 11] 218 stp x24, x25, [sp, #16 * 12] 219 stp x26, x27, [sp, #16 * 13] 220 stp x28, x29, [sp, #16 * 14] 221 222 .if \el == 0 223 clear_gp_regs 224 mrs x21, sp_el0 225 ldr_this_cpu tsk, __entry_task, x20 226 msr sp_el0, tsk 227 228 /* 229 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 230 * when scheduling. 231 */ 232 ldr x19, [tsk, #TSK_TI_FLAGS] 233 disable_step_tsk x19, x20 234 235 /* Check for asynchronous tag check faults in user space */ 236 ldr x0, [tsk, THREAD_SCTLR_USER] 237 check_mte_async_tcf x22, x23, x0 238 239#ifdef CONFIG_ARM64_PTR_AUTH 240alternative_if ARM64_HAS_ADDRESS_AUTH 241 /* 242 * Enable IA for in-kernel PAC if the task had it disabled. Although 243 * this could be implemented with an unconditional MRS which would avoid 244 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 245 * 246 * Install the kernel IA key only if IA was enabled in the task. If IA 247 * was disabled on kernel exit then we would have left the kernel IA 248 * installed so there is no need to install it again. 249 */ 250 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 251 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 252 b 2f 2531: 254 mrs x0, sctlr_el1 255 orr x0, x0, SCTLR_ELx_ENIA 256 msr sctlr_el1, x0 2572: 258alternative_else_nop_endif 259#endif 260 261 apply_ssbd 1, x22, x23 262 263 mte_set_kernel_gcr x22, x23 264 265 /* 266 * Any non-self-synchronizing system register updates required for 267 * kernel entry should be placed before this point. 268 */ 269alternative_if ARM64_MTE 270 isb 271 b 1f 272alternative_else_nop_endif 273alternative_if ARM64_HAS_ADDRESS_AUTH 274 isb 275alternative_else_nop_endif 2761: 277 278 scs_load tsk 279 .else 280 add x21, sp, #PT_REGS_SIZE 281 get_current_task tsk 282 .endif /* \el == 0 */ 283 mrs x22, elr_el1 284 mrs x23, spsr_el1 285 stp lr, x21, [sp, #S_LR] 286 287 /* 288 * For exceptions from EL0, create a final frame record. 289 * For exceptions from EL1, create a synthetic frame record so the 290 * interrupted code shows up in the backtrace. 291 */ 292 .if \el == 0 293 stp xzr, xzr, [sp, #S_STACKFRAME] 294 .else 295 stp x29, x22, [sp, #S_STACKFRAME] 296 .endif 297 add x29, sp, #S_STACKFRAME 298 299#ifdef CONFIG_ARM64_SW_TTBR0_PAN 300alternative_if_not ARM64_HAS_PAN 301 bl __swpan_entry_el\el 302alternative_else_nop_endif 303#endif 304 305 stp x22, x23, [sp, #S_PC] 306 307 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 308 .if \el == 0 309 mov w21, #NO_SYSCALL 310 str w21, [sp, #S_SYSCALLNO] 311 .endif 312 313#ifdef CONFIG_ARM64_PSEUDO_NMI 314 /* Save pmr */ 315alternative_if ARM64_HAS_IRQ_PRIO_MASKING 316 mrs_s x20, SYS_ICC_PMR_EL1 317 str x20, [sp, #S_PMR_SAVE] 318 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 319 msr_s SYS_ICC_PMR_EL1, x20 320alternative_else_nop_endif 321#endif 322 323 /* 324 * Registers that may be useful after this macro is invoked: 325 * 326 * x20 - ICC_PMR_EL1 327 * x21 - aborted SP 328 * x22 - aborted PC 329 * x23 - aborted PSTATE 330 */ 331 .endm 332 333 .macro kernel_exit, el 334 .if \el != 0 335 disable_daif 336 .endif 337 338#ifdef CONFIG_ARM64_PSEUDO_NMI 339 /* Restore pmr */ 340alternative_if ARM64_HAS_IRQ_PRIO_MASKING 341 ldr x20, [sp, #S_PMR_SAVE] 342 msr_s SYS_ICC_PMR_EL1, x20 343 mrs_s x21, SYS_ICC_CTLR_EL1 344 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 345 dsb sy // Ensure priority change is seen by redistributor 346.L__skip_pmr_sync\@: 347alternative_else_nop_endif 348#endif 349 350 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 351 352#ifdef CONFIG_ARM64_SW_TTBR0_PAN 353alternative_if_not ARM64_HAS_PAN 354 bl __swpan_exit_el\el 355alternative_else_nop_endif 356#endif 357 358 .if \el == 0 359 ldr x23, [sp, #S_SP] // load return stack pointer 360 msr sp_el0, x23 361 tst x22, #PSR_MODE32_BIT // native task? 362 b.eq 3f 363 364#ifdef CONFIG_ARM64_ERRATUM_845719 365alternative_if ARM64_WORKAROUND_845719 366#ifdef CONFIG_PID_IN_CONTEXTIDR 367 mrs x29, contextidr_el1 368 msr contextidr_el1, x29 369#else 370 msr contextidr_el1, xzr 371#endif 372alternative_else_nop_endif 373#endif 3743: 375 scs_save tsk 376 377 /* Ignore asynchronous tag check faults in the uaccess routines */ 378 ldr x0, [tsk, THREAD_SCTLR_USER] 379 clear_mte_async_tcf x0 380 381#ifdef CONFIG_ARM64_PTR_AUTH 382alternative_if ARM64_HAS_ADDRESS_AUTH 383 /* 384 * IA was enabled for in-kernel PAC. Disable it now if needed, or 385 * alternatively install the user's IA. All other per-task keys and 386 * SCTLR bits were updated on task switch. 387 * 388 * No kernel C function calls after this. 389 */ 390 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 391 __ptrauth_keys_install_user tsk, x0, x1, x2 392 b 2f 3931: 394 mrs x0, sctlr_el1 395 bic x0, x0, SCTLR_ELx_ENIA 396 msr sctlr_el1, x0 3972: 398alternative_else_nop_endif 399#endif 400 401 mte_set_user_gcr tsk, x0, x1 402 403 apply_ssbd 0, x0, x1 404 .endif 405 406 msr elr_el1, x21 // set up the return data 407 msr spsr_el1, x22 408 ldp x0, x1, [sp, #16 * 0] 409 ldp x2, x3, [sp, #16 * 1] 410 ldp x4, x5, [sp, #16 * 2] 411 ldp x6, x7, [sp, #16 * 3] 412 ldp x8, x9, [sp, #16 * 4] 413 ldp x10, x11, [sp, #16 * 5] 414 ldp x12, x13, [sp, #16 * 6] 415 ldp x14, x15, [sp, #16 * 7] 416 ldp x16, x17, [sp, #16 * 8] 417 ldp x18, x19, [sp, #16 * 9] 418 ldp x20, x21, [sp, #16 * 10] 419 ldp x22, x23, [sp, #16 * 11] 420 ldp x24, x25, [sp, #16 * 12] 421 ldp x26, x27, [sp, #16 * 13] 422 ldp x28, x29, [sp, #16 * 14] 423 424 .if \el == 0 425alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 426 ldr lr, [sp, #S_LR] 427 add sp, sp, #PT_REGS_SIZE // restore sp 428 eret 429alternative_else_nop_endif 430#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 431 bne 4f 432 msr far_el1, x29 433 tramp_alias x30, tramp_exit_native, x29 434 br x30 4354: 436 tramp_alias x30, tramp_exit_compat, x29 437 br x30 438#endif 439 .else 440 ldr lr, [sp, #S_LR] 441 add sp, sp, #PT_REGS_SIZE // restore sp 442 443 /* Ensure any device/NC reads complete */ 444 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 445 446 eret 447 .endif 448 sb 449 .endm 450 451#ifdef CONFIG_ARM64_SW_TTBR0_PAN 452 /* 453 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 454 * EL0, there is no need to check the state of TTBR0_EL1 since 455 * accesses are always enabled. 456 * Note that the meaning of this bit differs from the ARMv8.1 PAN 457 * feature as all TTBR0_EL1 accesses are disabled, not just those to 458 * user mappings. 459 */ 460SYM_CODE_START_LOCAL(__swpan_entry_el1) 461 mrs x21, ttbr0_el1 462 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 463 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 464 b.eq 1f // TTBR0 access already disabled 465 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 466SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 467 __uaccess_ttbr0_disable x21 4681: ret 469SYM_CODE_END(__swpan_entry_el1) 470 471 /* 472 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 473 * PAN bit checking. 474 */ 475SYM_CODE_START_LOCAL(__swpan_exit_el1) 476 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 477 __uaccess_ttbr0_enable x0, x1 4781: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 479 ret 480SYM_CODE_END(__swpan_exit_el1) 481 482SYM_CODE_START_LOCAL(__swpan_exit_el0) 483 __uaccess_ttbr0_enable x0, x1 484 /* 485 * Enable errata workarounds only if returning to user. The only 486 * workaround currently required for TTBR0_EL1 changes are for the 487 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 488 * corruption). 489 */ 490 b post_ttbr_update_workaround 491SYM_CODE_END(__swpan_exit_el0) 492#endif 493 494/* GPRs used by entry code */ 495tsk .req x28 // current thread_info 496 497 .text 498 499/* 500 * Exception vectors. 501 */ 502 .pushsection ".entry.text", "ax" 503 504 .align 11 505SYM_CODE_START(vectors) 506 kernel_ventry 1, t, 64, sync // Synchronous EL1t 507 kernel_ventry 1, t, 64, irq // IRQ EL1t 508 kernel_ventry 1, t, 64, fiq // FIQ EL1t 509 kernel_ventry 1, t, 64, error // Error EL1t 510 511 kernel_ventry 1, h, 64, sync // Synchronous EL1h 512 kernel_ventry 1, h, 64, irq // IRQ EL1h 513 kernel_ventry 1, h, 64, fiq // FIQ EL1h 514 kernel_ventry 1, h, 64, error // Error EL1h 515 516 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 517 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 518 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 519 kernel_ventry 0, t, 64, error // Error 64-bit EL0 520 521 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 522 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 523 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 524 kernel_ventry 0, t, 32, error // Error 32-bit EL0 525SYM_CODE_END(vectors) 526 527#ifdef CONFIG_VMAP_STACK 528SYM_CODE_START_LOCAL(__bad_stack) 529 /* 530 * We detected an overflow in kernel_ventry, which switched to the 531 * overflow stack. Stash the exception regs, and head to our overflow 532 * handler. 533 */ 534 535 /* Restore the original x0 value */ 536 mrs x0, tpidrro_el0 537 538 /* 539 * Store the original GPRs to the new stack. The orginal SP (minus 540 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 541 */ 542 sub sp, sp, #PT_REGS_SIZE 543 kernel_entry 1 544 mrs x0, tpidr_el0 545 add x0, x0, #PT_REGS_SIZE 546 str x0, [sp, #S_SP] 547 548 /* Stash the regs for handle_bad_stack */ 549 mov x0, sp 550 551 /* Time to die */ 552 bl handle_bad_stack 553 ASM_BUG() 554SYM_CODE_END(__bad_stack) 555#endif /* CONFIG_VMAP_STACK */ 556 557 558 .macro entry_handler el:req, ht:req, regsize:req, label:req 559SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 560 kernel_entry \el, \regsize 561 mov x0, sp 562 bl el\el\ht\()_\regsize\()_\label\()_handler 563 .if \el == 0 564 b ret_to_user 565 .else 566 b ret_to_kernel 567 .endif 568SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 569 .endm 570 571/* 572 * Early exception handlers 573 */ 574 entry_handler 1, t, 64, sync 575 entry_handler 1, t, 64, irq 576 entry_handler 1, t, 64, fiq 577 entry_handler 1, t, 64, error 578 579 entry_handler 1, h, 64, sync 580 entry_handler 1, h, 64, irq 581 entry_handler 1, h, 64, fiq 582 entry_handler 1, h, 64, error 583 584 entry_handler 0, t, 64, sync 585 entry_handler 0, t, 64, irq 586 entry_handler 0, t, 64, fiq 587 entry_handler 0, t, 64, error 588 589 entry_handler 0, t, 32, sync 590 entry_handler 0, t, 32, irq 591 entry_handler 0, t, 32, fiq 592 entry_handler 0, t, 32, error 593 594SYM_CODE_START_LOCAL(ret_to_kernel) 595 kernel_exit 1 596SYM_CODE_END(ret_to_kernel) 597 598SYM_CODE_START_LOCAL(ret_to_user) 599 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 600 enable_step_tsk x19, x2 601#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 602 bl stackleak_erase_on_task_stack 603#endif 604 kernel_exit 0 605SYM_CODE_END(ret_to_user) 606 607 .popsection // .entry.text 608 609 // Move from tramp_pg_dir to swapper_pg_dir 610 .macro tramp_map_kernel, tmp 611 mrs \tmp, ttbr1_el1 612 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 613 bic \tmp, \tmp, #USER_ASID_FLAG 614 msr ttbr1_el1, \tmp 615#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 616alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 617 /* ASID already in \tmp[63:48] */ 618 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 619 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 620 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 621 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 622 isb 623 tlbi vae1, \tmp 624 dsb nsh 625alternative_else_nop_endif 626#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 627 .endm 628 629 // Move from swapper_pg_dir to tramp_pg_dir 630 .macro tramp_unmap_kernel, tmp 631 mrs \tmp, ttbr1_el1 632 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 633 orr \tmp, \tmp, #USER_ASID_FLAG 634 msr ttbr1_el1, \tmp 635 /* 636 * We avoid running the post_ttbr_update_workaround here because 637 * it's only needed by Cavium ThunderX, which requires KPTI to be 638 * disabled. 639 */ 640 .endm 641 642 .macro tramp_data_read_var dst, var 643#ifdef CONFIG_RELOCATABLE 644 ldr \dst, .L__tramp_data_\var 645 .ifndef .L__tramp_data_\var 646 .pushsection ".entry.tramp.rodata", "a", %progbits 647 .align 3 648.L__tramp_data_\var: 649 .quad \var 650 .popsection 651 .endif 652#else 653 /* 654 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a 655 * compile time constant (and hence not secret and not worth hiding). 656 * 657 * As statically allocated kernel code and data always live in the top 658 * 47 bits of the address space we can sign-extend bit 47 and avoid an 659 * instruction to load the upper 16 bits (which must be 0xFFFF). 660 */ 661 movz \dst, :abs_g2_s:\var 662 movk \dst, :abs_g1_nc:\var 663 movk \dst, :abs_g0_nc:\var 664#endif 665 .endm 666 667#define BHB_MITIGATION_NONE 0 668#define BHB_MITIGATION_LOOP 1 669#define BHB_MITIGATION_FW 2 670#define BHB_MITIGATION_INSN 3 671 672 .macro tramp_ventry, vector_start, regsize, kpti, bhb 673 .align 7 6741: 675 .if \regsize == 64 676 msr tpidrro_el0, x30 // Restored in kernel_ventry 677 .endif 678 679 .if \bhb == BHB_MITIGATION_LOOP 680 /* 681 * This sequence must appear before the first indirect branch. i.e. the 682 * ret out of tramp_ventry. It appears here because x30 is free. 683 */ 684 __mitigate_spectre_bhb_loop x30 685 .endif // \bhb == BHB_MITIGATION_LOOP 686 687 .if \bhb == BHB_MITIGATION_INSN 688 clearbhb 689 isb 690 .endif // \bhb == BHB_MITIGATION_INSN 691 692 .if \kpti == 1 693 /* 694 * Defend against branch aliasing attacks by pushing a dummy 695 * entry onto the return stack and using a RET instruction to 696 * enter the full-fat kernel vectors. 697 */ 698 bl 2f 699 b . 7002: 701 tramp_map_kernel x30 702alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 703 tramp_data_read_var x30, vectors 704alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 705 prfm plil1strm, [x30, #(1b - \vector_start)] 706alternative_else_nop_endif 707 708 msr vbar_el1, x30 709 isb 710 .else 711 adr_l x30, vectors 712 .endif // \kpti == 1 713 714 .if \bhb == BHB_MITIGATION_FW 715 /* 716 * The firmware sequence must appear before the first indirect branch. 717 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 718 * mapped to save/restore the registers the SMC clobbers. 719 */ 720 __mitigate_spectre_bhb_fw 721 .endif // \bhb == BHB_MITIGATION_FW 722 723 add x30, x30, #(1b - \vector_start + 4) 724 ret 725.org 1b + 128 // Did we overflow the ventry slot? 726 .endm 727 728 .macro tramp_exit, regsize = 64 729 tramp_data_read_var x30, this_cpu_vector 730 get_this_cpu_offset x29 731 ldr x30, [x30, x29] 732 733 msr vbar_el1, x30 734 ldr lr, [sp, #S_LR] 735 tramp_unmap_kernel x29 736 .if \regsize == 64 737 mrs x29, far_el1 738 .endif 739 add sp, sp, #PT_REGS_SIZE // restore sp 740 eret 741 sb 742 .endm 743 744 .macro generate_tramp_vector, kpti, bhb 745.Lvector_start\@: 746 .space 0x400 747 748 .rept 4 749 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 750 .endr 751 .rept 4 752 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 753 .endr 754 .endm 755 756#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 757/* 758 * Exception vectors trampoline. 759 * The order must match __bp_harden_el1_vectors and the 760 * arm64_bp_harden_el1_vectors enum. 761 */ 762 .pushsection ".entry.tramp.text", "ax" 763 .align 11 764SYM_CODE_START_NOALIGN(tramp_vectors) 765#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 766 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 767 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 768 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 769#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 770 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 771SYM_CODE_END(tramp_vectors) 772 773SYM_CODE_START(tramp_exit_native) 774 tramp_exit 775SYM_CODE_END(tramp_exit_native) 776 777SYM_CODE_START(tramp_exit_compat) 778 tramp_exit 32 779SYM_CODE_END(tramp_exit_compat) 780 .popsection // .entry.tramp.text 781#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 782 783/* 784 * Exception vectors for spectre mitigations on entry from EL1 when 785 * kpti is not in use. 786 */ 787 .macro generate_el1_vector, bhb 788.Lvector_start\@: 789 kernel_ventry 1, t, 64, sync // Synchronous EL1t 790 kernel_ventry 1, t, 64, irq // IRQ EL1t 791 kernel_ventry 1, t, 64, fiq // FIQ EL1h 792 kernel_ventry 1, t, 64, error // Error EL1t 793 794 kernel_ventry 1, h, 64, sync // Synchronous EL1h 795 kernel_ventry 1, h, 64, irq // IRQ EL1h 796 kernel_ventry 1, h, 64, fiq // FIQ EL1h 797 kernel_ventry 1, h, 64, error // Error EL1h 798 799 .rept 4 800 tramp_ventry .Lvector_start\@, 64, 0, \bhb 801 .endr 802 .rept 4 803 tramp_ventry .Lvector_start\@, 32, 0, \bhb 804 .endr 805 .endm 806 807/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 808 .pushsection ".entry.text", "ax" 809 .align 11 810SYM_CODE_START(__bp_harden_el1_vectors) 811#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 812 generate_el1_vector bhb=BHB_MITIGATION_LOOP 813 generate_el1_vector bhb=BHB_MITIGATION_FW 814 generate_el1_vector bhb=BHB_MITIGATION_INSN 815#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 816SYM_CODE_END(__bp_harden_el1_vectors) 817 .popsection 818 819 820/* 821 * Register switch for AArch64. The callee-saved registers need to be saved 822 * and restored. On entry: 823 * x0 = previous task_struct (must be preserved across the switch) 824 * x1 = next task_struct 825 * Previous and next are guaranteed not to be the same. 826 * 827 */ 828SYM_FUNC_START(cpu_switch_to) 829 mov x10, #THREAD_CPU_CONTEXT 830 add x8, x0, x10 831 mov x9, sp 832 stp x19, x20, [x8], #16 // store callee-saved registers 833 stp x21, x22, [x8], #16 834 stp x23, x24, [x8], #16 835 stp x25, x26, [x8], #16 836 stp x27, x28, [x8], #16 837 stp x29, x9, [x8], #16 838 str lr, [x8] 839 add x8, x1, x10 840 ldp x19, x20, [x8], #16 // restore callee-saved registers 841 ldp x21, x22, [x8], #16 842 ldp x23, x24, [x8], #16 843 ldp x25, x26, [x8], #16 844 ldp x27, x28, [x8], #16 845 ldp x29, x9, [x8], #16 846 ldr lr, [x8] 847 mov sp, x9 848 msr sp_el0, x1 849 ptrauth_keys_install_kernel x1, x8, x9, x10 850 scs_save x0 851 scs_load x1 852 ret 853SYM_FUNC_END(cpu_switch_to) 854NOKPROBE(cpu_switch_to) 855 856/* 857 * This is how we return from a fork. 858 */ 859SYM_CODE_START(ret_from_fork) 860 bl schedule_tail 861 cbz x19, 1f // not a kernel thread 862 mov x0, x20 863 blr x19 8641: get_current_task tsk 865 mov x0, sp 866 bl asm_exit_to_user_mode 867 b ret_to_user 868SYM_CODE_END(ret_from_fork) 869NOKPROBE(ret_from_fork) 870 871/* 872 * void call_on_irq_stack(struct pt_regs *regs, 873 * void (*func)(struct pt_regs *)); 874 * 875 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 876 */ 877SYM_FUNC_START(call_on_irq_stack) 878#ifdef CONFIG_SHADOW_CALL_STACK 879 stp scs_sp, xzr, [sp, #-16]! 880 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 881#endif 882 /* Create a frame record to save our LR and SP (implicit in FP) */ 883 stp x29, x30, [sp, #-16]! 884 mov x29, sp 885 886 ldr_this_cpu x16, irq_stack_ptr, x17 887 mov x15, #IRQ_STACK_SIZE 888 add x16, x16, x15 889 890 /* Move to the new stack and call the function there */ 891 mov sp, x16 892 blr x1 893 894 /* 895 * Restore the SP from the FP, and restore the FP and LR from the frame 896 * record. 897 */ 898 mov sp, x29 899 ldp x29, x30, [sp], #16 900#ifdef CONFIG_SHADOW_CALL_STACK 901 ldp scs_sp, xzr, [sp], #16 902#endif 903 ret 904SYM_FUNC_END(call_on_irq_stack) 905NOKPROBE(call_on_irq_stack) 906 907#ifdef CONFIG_ARM_SDE_INTERFACE 908 909#include <asm/sdei.h> 910#include <uapi/linux/arm_sdei.h> 911 912.macro sdei_handler_exit exit_mode 913 /* On success, this call never returns... */ 914 cmp \exit_mode, #SDEI_EXIT_SMC 915 b.ne 99f 916 smc #0 917 b . 91899: hvc #0 919 b . 920.endm 921 922#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 923/* 924 * The regular SDEI entry point may have been unmapped along with the rest of 925 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 926 * argument accessible. 927 * 928 * This clobbers x4, __sdei_handler() will restore this from firmware's 929 * copy. 930 */ 931.pushsection ".entry.tramp.text", "ax" 932SYM_CODE_START(__sdei_asm_entry_trampoline) 933 mrs x4, ttbr1_el1 934 tbz x4, #USER_ASID_BIT, 1f 935 936 tramp_map_kernel tmp=x4 937 isb 938 mov x4, xzr 939 940 /* 941 * Remember whether to unmap the kernel on exit. 942 */ 9431: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 944 tramp_data_read_var x4, __sdei_asm_handler 945 br x4 946SYM_CODE_END(__sdei_asm_entry_trampoline) 947NOKPROBE(__sdei_asm_entry_trampoline) 948 949/* 950 * Make the exit call and restore the original ttbr1_el1 951 * 952 * x0 & x1: setup for the exit API call 953 * x2: exit_mode 954 * x4: struct sdei_registered_event argument from registration time. 955 */ 956SYM_CODE_START(__sdei_asm_exit_trampoline) 957 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 958 cbnz x4, 1f 959 960 tramp_unmap_kernel tmp=x4 961 9621: sdei_handler_exit exit_mode=x2 963SYM_CODE_END(__sdei_asm_exit_trampoline) 964NOKPROBE(__sdei_asm_exit_trampoline) 965.popsection // .entry.tramp.text 966#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 967 968/* 969 * Software Delegated Exception entry point. 970 * 971 * x0: Event number 972 * x1: struct sdei_registered_event argument from registration time. 973 * x2: interrupted PC 974 * x3: interrupted PSTATE 975 * x4: maybe clobbered by the trampoline 976 * 977 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 978 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 979 * want them. 980 */ 981SYM_CODE_START(__sdei_asm_handler) 982 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 983 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 984 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 985 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 986 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 987 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 988 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 989 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 990 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 991 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 992 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 993 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 994 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 995 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 996 mov x4, sp 997 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 998 999 mov x19, x1 1000 1001#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1002 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1003#endif 1004 1005#ifdef CONFIG_VMAP_STACK 1006 /* 1007 * entry.S may have been using sp as a scratch register, find whether 1008 * this is a normal or critical event and switch to the appropriate 1009 * stack for this CPU. 1010 */ 1011 cbnz w4, 1f 1012 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1013 b 2f 10141: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10152: mov x6, #SDEI_STACK_SIZE 1016 add x5, x5, x6 1017 mov sp, x5 1018#endif 1019 1020#ifdef CONFIG_SHADOW_CALL_STACK 1021 /* Use a separate shadow call stack for normal and critical events */ 1022 cbnz w4, 3f 1023 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1024 b 4f 10253: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10264: 1027#endif 1028 1029 /* 1030 * We may have interrupted userspace, or a guest, or exit-from or 1031 * return-to either of these. We can't trust sp_el0, restore it. 1032 */ 1033 mrs x28, sp_el0 1034 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1035 msr sp_el0, x0 1036 1037 /* If we interrupted the kernel point to the previous stack/frame. */ 1038 and x0, x3, #0xc 1039 mrs x1, CurrentEL 1040 cmp x0, x1 1041 csel x29, x29, xzr, eq // fp, or zero 1042 csel x4, x2, xzr, eq // elr, or zero 1043 1044 stp x29, x4, [sp, #-16]! 1045 mov x29, sp 1046 1047 add x0, x19, #SDEI_EVENT_INTREGS 1048 mov x1, x19 1049 bl __sdei_handler 1050 1051 msr sp_el0, x28 1052 /* restore regs >x17 that we clobbered */ 1053 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1054 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1055 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1056 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1057 mov sp, x1 1058 1059 mov x1, x0 // address to complete_and_resume 1060 /* x0 = (x0 <= SDEI_EV_FAILED) ? 1061 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME 1062 */ 1063 cmp x0, #SDEI_EV_FAILED 1064 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1065 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1066 csel x0, x2, x3, ls 1067 1068 ldr_l x2, sdei_exit_mode 1069 1070alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1071 sdei_handler_exit exit_mode=x2 1072alternative_else_nop_endif 1073 1074#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1075 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3 1076 br x5 1077#endif 1078SYM_CODE_END(__sdei_asm_handler) 1079NOKPROBE(__sdei_asm_handler) 1080#endif /* CONFIG_ARM_SDE_INTERFACE */ 1081