1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking subsystem. Used to instrument transitions 34 * between user and kernel mode. 35 */ 36 .macro ct_user_exit_irqoff 37#ifdef CONFIG_CONTEXT_TRACKING 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro ct_user_enter 43#ifdef CONFIG_CONTEXT_TRACKING 44 bl context_tracking_user_enter 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #S_FRAME_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 /* 131 * This macro corrupts x0-x3. It is the caller's duty to save/restore 132 * them if required. 133 */ 134 .macro apply_ssbd, state, tmp1, tmp2 135#ifdef CONFIG_ARM64_SSBD 136alternative_cb arm64_enable_wa2_handling 137 b .L__asm_ssbd_skip\@ 138alternative_cb_end 139 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 140 cbz \tmp2, .L__asm_ssbd_skip\@ 141 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 142 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 143 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 144 mov w1, #\state 145alternative_cb arm64_update_smccc_conduit 146 nop // Patched to SMC/HVC #0 147alternative_cb_end 148.L__asm_ssbd_skip\@: 149#endif 150 .endm 151 152 .macro kernel_entry, el, regsize = 64 153 .if \regsize == 32 154 mov w0, w0 // zero upper 32 bits of x0 155 .endif 156 stp x0, x1, [sp, #16 * 0] 157 stp x2, x3, [sp, #16 * 1] 158 stp x4, x5, [sp, #16 * 2] 159 stp x6, x7, [sp, #16 * 3] 160 stp x8, x9, [sp, #16 * 4] 161 stp x10, x11, [sp, #16 * 5] 162 stp x12, x13, [sp, #16 * 6] 163 stp x14, x15, [sp, #16 * 7] 164 stp x16, x17, [sp, #16 * 8] 165 stp x18, x19, [sp, #16 * 9] 166 stp x20, x21, [sp, #16 * 10] 167 stp x22, x23, [sp, #16 * 11] 168 stp x24, x25, [sp, #16 * 12] 169 stp x26, x27, [sp, #16 * 13] 170 stp x28, x29, [sp, #16 * 14] 171 172 .if \el == 0 173 clear_gp_regs 174 mrs x21, sp_el0 175 ldr_this_cpu tsk, __entry_task, x20 176 msr sp_el0, tsk 177 178 /* 179 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 180 * when scheduling. 181 */ 182 ldr x19, [tsk, #TSK_TI_FLAGS] 183 disable_step_tsk x19, x20 184 185 apply_ssbd 1, x22, x23 186 187 ptrauth_keys_install_kernel tsk, x20, x22, x23 188 189 scs_load tsk, x20 190 .else 191 add x21, sp, #S_FRAME_SIZE 192 get_current_task tsk 193 /* Save the task's original addr_limit and set USER_DS */ 194 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 195 str x20, [sp, #S_ORIG_ADDR_LIMIT] 196 mov x20, #USER_DS 197 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 198 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 199 .endif /* \el == 0 */ 200 mrs x22, elr_el1 201 mrs x23, spsr_el1 202 stp lr, x21, [sp, #S_LR] 203 204 /* 205 * In order to be able to dump the contents of struct pt_regs at the 206 * time the exception was taken (in case we attempt to walk the call 207 * stack later), chain it together with the stack frames. 208 */ 209 .if \el == 0 210 stp xzr, xzr, [sp, #S_STACKFRAME] 211 .else 212 stp x29, x22, [sp, #S_STACKFRAME] 213 .endif 214 add x29, sp, #S_STACKFRAME 215 216#ifdef CONFIG_ARM64_SW_TTBR0_PAN 217alternative_if_not ARM64_HAS_PAN 218 bl __swpan_entry_el\el 219alternative_else_nop_endif 220#endif 221 222 stp x22, x23, [sp, #S_PC] 223 224 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 225 .if \el == 0 226 mov w21, #NO_SYSCALL 227 str w21, [sp, #S_SYSCALLNO] 228 .endif 229 230 /* Save pmr */ 231alternative_if ARM64_HAS_IRQ_PRIO_MASKING 232 mrs_s x20, SYS_ICC_PMR_EL1 233 str x20, [sp, #S_PMR_SAVE] 234alternative_else_nop_endif 235 236 /* 237 * Registers that may be useful after this macro is invoked: 238 * 239 * x20 - ICC_PMR_EL1 240 * x21 - aborted SP 241 * x22 - aborted PC 242 * x23 - aborted PSTATE 243 */ 244 .endm 245 246 .macro kernel_exit, el 247 .if \el != 0 248 disable_daif 249 250 /* Restore the task's original addr_limit. */ 251 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 252 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 253 254 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 255 .endif 256 257 /* Restore pmr */ 258alternative_if ARM64_HAS_IRQ_PRIO_MASKING 259 ldr x20, [sp, #S_PMR_SAVE] 260 msr_s SYS_ICC_PMR_EL1, x20 261 mrs_s x21, SYS_ICC_CTLR_EL1 262 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 263 dsb sy // Ensure priority change is seen by redistributor 264.L__skip_pmr_sync\@: 265alternative_else_nop_endif 266 267 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 268 .if \el == 0 269 ct_user_enter 270 .endif 271 272#ifdef CONFIG_ARM64_SW_TTBR0_PAN 273alternative_if_not ARM64_HAS_PAN 274 bl __swpan_exit_el\el 275alternative_else_nop_endif 276#endif 277 278 .if \el == 0 279 ldr x23, [sp, #S_SP] // load return stack pointer 280 msr sp_el0, x23 281 tst x22, #PSR_MODE32_BIT // native task? 282 b.eq 3f 283 284#ifdef CONFIG_ARM64_ERRATUM_845719 285alternative_if ARM64_WORKAROUND_845719 286#ifdef CONFIG_PID_IN_CONTEXTIDR 287 mrs x29, contextidr_el1 288 msr contextidr_el1, x29 289#else 290 msr contextidr_el1, xzr 291#endif 292alternative_else_nop_endif 293#endif 2943: 295 scs_save tsk, x0 296 297 /* No kernel C function calls after this as user keys are set. */ 298 ptrauth_keys_install_user tsk, x0, x1, x2 299 300 apply_ssbd 0, x0, x1 301 .endif 302 303 msr elr_el1, x21 // set up the return data 304 msr spsr_el1, x22 305 ldp x0, x1, [sp, #16 * 0] 306 ldp x2, x3, [sp, #16 * 1] 307 ldp x4, x5, [sp, #16 * 2] 308 ldp x6, x7, [sp, #16 * 3] 309 ldp x8, x9, [sp, #16 * 4] 310 ldp x10, x11, [sp, #16 * 5] 311 ldp x12, x13, [sp, #16 * 6] 312 ldp x14, x15, [sp, #16 * 7] 313 ldp x16, x17, [sp, #16 * 8] 314 ldp x18, x19, [sp, #16 * 9] 315 ldp x20, x21, [sp, #16 * 10] 316 ldp x22, x23, [sp, #16 * 11] 317 ldp x24, x25, [sp, #16 * 12] 318 ldp x26, x27, [sp, #16 * 13] 319 ldp x28, x29, [sp, #16 * 14] 320 ldr lr, [sp, #S_LR] 321 add sp, sp, #S_FRAME_SIZE // restore sp 322 323 .if \el == 0 324alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 325#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 326 bne 4f 327 msr far_el1, x30 328 tramp_alias x30, tramp_exit_native 329 br x30 3304: 331 tramp_alias x30, tramp_exit_compat 332 br x30 333#endif 334 .else 335 eret 336 .endif 337 sb 338 .endm 339 340#ifdef CONFIG_ARM64_SW_TTBR0_PAN 341 /* 342 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 343 * EL0, there is no need to check the state of TTBR0_EL1 since 344 * accesses are always enabled. 345 * Note that the meaning of this bit differs from the ARMv8.1 PAN 346 * feature as all TTBR0_EL1 accesses are disabled, not just those to 347 * user mappings. 348 */ 349SYM_CODE_START_LOCAL(__swpan_entry_el1) 350 mrs x21, ttbr0_el1 351 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 352 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 353 b.eq 1f // TTBR0 access already disabled 354 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 355SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 356 __uaccess_ttbr0_disable x21 3571: ret 358SYM_CODE_END(__swpan_entry_el1) 359 360 /* 361 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 362 * PAN bit checking. 363 */ 364SYM_CODE_START_LOCAL(__swpan_exit_el1) 365 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 366 __uaccess_ttbr0_enable x0, x1 3671: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 368 ret 369SYM_CODE_END(__swpan_exit_el1) 370 371SYM_CODE_START_LOCAL(__swpan_exit_el0) 372 __uaccess_ttbr0_enable x0, x1 373 /* 374 * Enable errata workarounds only if returning to user. The only 375 * workaround currently required for TTBR0_EL1 changes are for the 376 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 377 * corruption). 378 */ 379 b post_ttbr_update_workaround 380SYM_CODE_END(__swpan_exit_el0) 381#endif 382 383 .macro irq_stack_entry 384 mov x19, sp // preserve the original sp 385#ifdef CONFIG_SHADOW_CALL_STACK 386 mov x24, scs_sp // preserve the original shadow stack 387#endif 388 389 /* 390 * Compare sp with the base of the task stack. 391 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 392 * and should switch to the irq stack. 393 */ 394 ldr x25, [tsk, TSK_STACK] 395 eor x25, x25, x19 396 and x25, x25, #~(THREAD_SIZE - 1) 397 cbnz x25, 9998f 398 399 ldr_this_cpu x25, irq_stack_ptr, x26 400 mov x26, #IRQ_STACK_SIZE 401 add x26, x25, x26 402 403 /* switch to the irq stack */ 404 mov sp, x26 405 406#ifdef CONFIG_SHADOW_CALL_STACK 407 /* also switch to the irq shadow stack */ 408 adr_this_cpu scs_sp, irq_shadow_call_stack, x26 409#endif 410 4119998: 412 .endm 413 414 /* 415 * The callee-saved regs (x19-x29) should be preserved between 416 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 417 * uses x20-x23 to store data for later use. 418 */ 419 .macro irq_stack_exit 420 mov sp, x19 421#ifdef CONFIG_SHADOW_CALL_STACK 422 mov scs_sp, x24 423#endif 424 .endm 425 426/* GPRs used by entry code */ 427tsk .req x28 // current thread_info 428 429/* 430 * Interrupt handling. 431 */ 432 .macro irq_handler 433 ldr_l x1, handle_arch_irq 434 mov x0, sp 435 irq_stack_entry 436 blr x1 437 irq_stack_exit 438 .endm 439 440#ifdef CONFIG_ARM64_PSEUDO_NMI 441 /* 442 * Set res to 0 if irqs were unmasked in interrupted context. 443 * Otherwise set res to non-0 value. 444 */ 445 .macro test_irqs_unmasked res:req, pmr:req 446alternative_if ARM64_HAS_IRQ_PRIO_MASKING 447 sub \res, \pmr, #GIC_PRIO_IRQON 448alternative_else 449 mov \res, xzr 450alternative_endif 451 .endm 452#endif 453 454 .macro gic_prio_kentry_setup, tmp:req 455#ifdef CONFIG_ARM64_PSEUDO_NMI 456 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 457 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 458 msr_s SYS_ICC_PMR_EL1, \tmp 459 alternative_else_nop_endif 460#endif 461 .endm 462 463 .macro gic_prio_irq_setup, pmr:req, tmp:req 464#ifdef CONFIG_ARM64_PSEUDO_NMI 465 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 466 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 467 msr_s SYS_ICC_PMR_EL1, \tmp 468 alternative_else_nop_endif 469#endif 470 .endm 471 472 .text 473 474/* 475 * Exception vectors. 476 */ 477 .pushsection ".entry.text", "ax" 478 479 .align 11 480SYM_CODE_START(vectors) 481 kernel_ventry 1, sync_invalid // Synchronous EL1t 482 kernel_ventry 1, irq_invalid // IRQ EL1t 483 kernel_ventry 1, fiq_invalid // FIQ EL1t 484 kernel_ventry 1, error_invalid // Error EL1t 485 486 kernel_ventry 1, sync // Synchronous EL1h 487 kernel_ventry 1, irq // IRQ EL1h 488 kernel_ventry 1, fiq_invalid // FIQ EL1h 489 kernel_ventry 1, error // Error EL1h 490 491 kernel_ventry 0, sync // Synchronous 64-bit EL0 492 kernel_ventry 0, irq // IRQ 64-bit EL0 493 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 494 kernel_ventry 0, error // Error 64-bit EL0 495 496#ifdef CONFIG_COMPAT 497 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 498 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 499 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 500 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 501#else 502 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 503 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 504 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 505 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 506#endif 507SYM_CODE_END(vectors) 508 509#ifdef CONFIG_VMAP_STACK 510 /* 511 * We detected an overflow in kernel_ventry, which switched to the 512 * overflow stack. Stash the exception regs, and head to our overflow 513 * handler. 514 */ 515__bad_stack: 516 /* Restore the original x0 value */ 517 mrs x0, tpidrro_el0 518 519 /* 520 * Store the original GPRs to the new stack. The orginal SP (minus 521 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 522 */ 523 sub sp, sp, #S_FRAME_SIZE 524 kernel_entry 1 525 mrs x0, tpidr_el0 526 add x0, x0, #S_FRAME_SIZE 527 str x0, [sp, #S_SP] 528 529 /* Stash the regs for handle_bad_stack */ 530 mov x0, sp 531 532 /* Time to die */ 533 bl handle_bad_stack 534 ASM_BUG() 535#endif /* CONFIG_VMAP_STACK */ 536 537/* 538 * Invalid mode handlers 539 */ 540 .macro inv_entry, el, reason, regsize = 64 541 kernel_entry \el, \regsize 542 mov x0, sp 543 mov x1, #\reason 544 mrs x2, esr_el1 545 bl bad_mode 546 ASM_BUG() 547 .endm 548 549SYM_CODE_START_LOCAL(el0_sync_invalid) 550 inv_entry 0, BAD_SYNC 551SYM_CODE_END(el0_sync_invalid) 552 553SYM_CODE_START_LOCAL(el0_irq_invalid) 554 inv_entry 0, BAD_IRQ 555SYM_CODE_END(el0_irq_invalid) 556 557SYM_CODE_START_LOCAL(el0_fiq_invalid) 558 inv_entry 0, BAD_FIQ 559SYM_CODE_END(el0_fiq_invalid) 560 561SYM_CODE_START_LOCAL(el0_error_invalid) 562 inv_entry 0, BAD_ERROR 563SYM_CODE_END(el0_error_invalid) 564 565#ifdef CONFIG_COMPAT 566SYM_CODE_START_LOCAL(el0_fiq_invalid_compat) 567 inv_entry 0, BAD_FIQ, 32 568SYM_CODE_END(el0_fiq_invalid_compat) 569#endif 570 571SYM_CODE_START_LOCAL(el1_sync_invalid) 572 inv_entry 1, BAD_SYNC 573SYM_CODE_END(el1_sync_invalid) 574 575SYM_CODE_START_LOCAL(el1_irq_invalid) 576 inv_entry 1, BAD_IRQ 577SYM_CODE_END(el1_irq_invalid) 578 579SYM_CODE_START_LOCAL(el1_fiq_invalid) 580 inv_entry 1, BAD_FIQ 581SYM_CODE_END(el1_fiq_invalid) 582 583SYM_CODE_START_LOCAL(el1_error_invalid) 584 inv_entry 1, BAD_ERROR 585SYM_CODE_END(el1_error_invalid) 586 587/* 588 * EL1 mode handlers. 589 */ 590 .align 6 591SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 592 kernel_entry 1 593 mov x0, sp 594 bl el1_sync_handler 595 kernel_exit 1 596SYM_CODE_END(el1_sync) 597 598 .align 6 599SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 600 kernel_entry 1 601 gic_prio_irq_setup pmr=x20, tmp=x1 602 enable_da_f 603 604#ifdef CONFIG_ARM64_PSEUDO_NMI 605 test_irqs_unmasked res=x0, pmr=x20 606 cbz x0, 1f 607 bl asm_nmi_enter 6081: 609#endif 610 611#ifdef CONFIG_TRACE_IRQFLAGS 612 bl trace_hardirqs_off 613#endif 614 615 irq_handler 616 617#ifdef CONFIG_PREEMPTION 618 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 619alternative_if ARM64_HAS_IRQ_PRIO_MASKING 620 /* 621 * DA_F were cleared at start of handling. If anything is set in DAIF, 622 * we come back from an NMI, so skip preemption 623 */ 624 mrs x0, daif 625 orr x24, x24, x0 626alternative_else_nop_endif 627 cbnz x24, 1f // preempt count != 0 || NMI return path 628 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6291: 630#endif 631 632#ifdef CONFIG_ARM64_PSEUDO_NMI 633 /* 634 * When using IRQ priority masking, we can get spurious interrupts while 635 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a 636 * section with interrupts disabled. Skip tracing in those cases. 637 */ 638 test_irqs_unmasked res=x0, pmr=x20 639 cbz x0, 1f 640 bl asm_nmi_exit 6411: 642#endif 643 644#ifdef CONFIG_TRACE_IRQFLAGS 645#ifdef CONFIG_ARM64_PSEUDO_NMI 646 test_irqs_unmasked res=x0, pmr=x20 647 cbnz x0, 1f 648#endif 649 bl trace_hardirqs_on 6501: 651#endif 652 653 kernel_exit 1 654SYM_CODE_END(el1_irq) 655 656/* 657 * EL0 mode handlers. 658 */ 659 .align 6 660SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 661 kernel_entry 0 662 mov x0, sp 663 bl el0_sync_handler 664 b ret_to_user 665SYM_CODE_END(el0_sync) 666 667#ifdef CONFIG_COMPAT 668 .align 6 669SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 670 kernel_entry 0, 32 671 mov x0, sp 672 bl el0_sync_compat_handler 673 b ret_to_user 674SYM_CODE_END(el0_sync_compat) 675 676 .align 6 677SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 678 kernel_entry 0, 32 679 b el0_irq_naked 680SYM_CODE_END(el0_irq_compat) 681 682SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 683 kernel_entry 0, 32 684 b el0_error_naked 685SYM_CODE_END(el0_error_compat) 686#endif 687 688 .align 6 689SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 690 kernel_entry 0 691el0_irq_naked: 692 gic_prio_irq_setup pmr=x20, tmp=x0 693 ct_user_exit_irqoff 694 enable_da_f 695 696#ifdef CONFIG_TRACE_IRQFLAGS 697 bl trace_hardirqs_off 698#endif 699 700#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR 701 tbz x22, #55, 1f 702 bl do_el0_irq_bp_hardening 7031: 704#endif 705 irq_handler 706 707#ifdef CONFIG_TRACE_IRQFLAGS 708 bl trace_hardirqs_on 709#endif 710 b ret_to_user 711SYM_CODE_END(el0_irq) 712 713SYM_CODE_START_LOCAL(el1_error) 714 kernel_entry 1 715 mrs x1, esr_el1 716 gic_prio_kentry_setup tmp=x2 717 enable_dbg 718 mov x0, sp 719 bl do_serror 720 kernel_exit 1 721SYM_CODE_END(el1_error) 722 723SYM_CODE_START_LOCAL(el0_error) 724 kernel_entry 0 725el0_error_naked: 726 mrs x25, esr_el1 727 gic_prio_kentry_setup tmp=x2 728 ct_user_exit_irqoff 729 enable_dbg 730 mov x0, sp 731 mov x1, x25 732 bl do_serror 733 enable_da_f 734 b ret_to_user 735SYM_CODE_END(el0_error) 736 737/* 738 * "slow" syscall return path. 739 */ 740SYM_CODE_START_LOCAL(ret_to_user) 741 disable_daif 742 gic_prio_kentry_setup tmp=x3 743 ldr x1, [tsk, #TSK_TI_FLAGS] 744 and x2, x1, #_TIF_WORK_MASK 745 cbnz x2, work_pending 746finish_ret_to_user: 747 enable_step_tsk x1, x2 748#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 749 bl stackleak_erase 750#endif 751 kernel_exit 0 752 753/* 754 * Ok, we need to do extra processing, enter the slow path. 755 */ 756work_pending: 757 mov x0, sp // 'regs' 758 bl do_notify_resume 759#ifdef CONFIG_TRACE_IRQFLAGS 760 bl trace_hardirqs_on // enabled while in userspace 761#endif 762 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step 763 b finish_ret_to_user 764SYM_CODE_END(ret_to_user) 765 766 .popsection // .entry.text 767 768#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 769/* 770 * Exception vectors trampoline. 771 */ 772 .pushsection ".entry.tramp.text", "ax" 773 774 .macro tramp_map_kernel, tmp 775 mrs \tmp, ttbr1_el1 776 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 777 bic \tmp, \tmp, #USER_ASID_FLAG 778 msr ttbr1_el1, \tmp 779#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 780alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 781 /* ASID already in \tmp[63:48] */ 782 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 783 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 784 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 785 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 786 isb 787 tlbi vae1, \tmp 788 dsb nsh 789alternative_else_nop_endif 790#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 791 .endm 792 793 .macro tramp_unmap_kernel, tmp 794 mrs \tmp, ttbr1_el1 795 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 796 orr \tmp, \tmp, #USER_ASID_FLAG 797 msr ttbr1_el1, \tmp 798 /* 799 * We avoid running the post_ttbr_update_workaround here because 800 * it's only needed by Cavium ThunderX, which requires KPTI to be 801 * disabled. 802 */ 803 .endm 804 805 .macro tramp_ventry, regsize = 64 806 .align 7 8071: 808 .if \regsize == 64 809 msr tpidrro_el0, x30 // Restored in kernel_ventry 810 .endif 811 /* 812 * Defend against branch aliasing attacks by pushing a dummy 813 * entry onto the return stack and using a RET instruction to 814 * enter the full-fat kernel vectors. 815 */ 816 bl 2f 817 b . 8182: 819 tramp_map_kernel x30 820#ifdef CONFIG_RANDOMIZE_BASE 821 adr x30, tramp_vectors + PAGE_SIZE 822alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 823 ldr x30, [x30] 824#else 825 ldr x30, =vectors 826#endif 827alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 828 prfm plil1strm, [x30, #(1b - tramp_vectors)] 829alternative_else_nop_endif 830 msr vbar_el1, x30 831 add x30, x30, #(1b - tramp_vectors) 832 isb 833 ret 834 .endm 835 836 .macro tramp_exit, regsize = 64 837 adr x30, tramp_vectors 838 msr vbar_el1, x30 839 tramp_unmap_kernel x30 840 .if \regsize == 64 841 mrs x30, far_el1 842 .endif 843 eret 844 sb 845 .endm 846 847 .align 11 848SYM_CODE_START_NOALIGN(tramp_vectors) 849 .space 0x400 850 851 tramp_ventry 852 tramp_ventry 853 tramp_ventry 854 tramp_ventry 855 856 tramp_ventry 32 857 tramp_ventry 32 858 tramp_ventry 32 859 tramp_ventry 32 860SYM_CODE_END(tramp_vectors) 861 862SYM_CODE_START(tramp_exit_native) 863 tramp_exit 864SYM_CODE_END(tramp_exit_native) 865 866SYM_CODE_START(tramp_exit_compat) 867 tramp_exit 32 868SYM_CODE_END(tramp_exit_compat) 869 870 .ltorg 871 .popsection // .entry.tramp.text 872#ifdef CONFIG_RANDOMIZE_BASE 873 .pushsection ".rodata", "a" 874 .align PAGE_SHIFT 875SYM_DATA_START(__entry_tramp_data_start) 876 .quad vectors 877SYM_DATA_END(__entry_tramp_data_start) 878 .popsection // .rodata 879#endif /* CONFIG_RANDOMIZE_BASE */ 880#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 881 882/* 883 * Register switch for AArch64. The callee-saved registers need to be saved 884 * and restored. On entry: 885 * x0 = previous task_struct (must be preserved across the switch) 886 * x1 = next task_struct 887 * Previous and next are guaranteed not to be the same. 888 * 889 */ 890SYM_FUNC_START(cpu_switch_to) 891 mov x10, #THREAD_CPU_CONTEXT 892 add x8, x0, x10 893 mov x9, sp 894 stp x19, x20, [x8], #16 // store callee-saved registers 895 stp x21, x22, [x8], #16 896 stp x23, x24, [x8], #16 897 stp x25, x26, [x8], #16 898 stp x27, x28, [x8], #16 899 stp x29, x9, [x8], #16 900 str lr, [x8] 901 add x8, x1, x10 902 ldp x19, x20, [x8], #16 // restore callee-saved registers 903 ldp x21, x22, [x8], #16 904 ldp x23, x24, [x8], #16 905 ldp x25, x26, [x8], #16 906 ldp x27, x28, [x8], #16 907 ldp x29, x9, [x8], #16 908 ldr lr, [x8] 909 mov sp, x9 910 msr sp_el0, x1 911 ptrauth_keys_install_kernel x1, x8, x9, x10 912 scs_save x0, x8 913 scs_load x1, x8 914 ret 915SYM_FUNC_END(cpu_switch_to) 916NOKPROBE(cpu_switch_to) 917 918/* 919 * This is how we return from a fork. 920 */ 921SYM_CODE_START(ret_from_fork) 922 bl schedule_tail 923 cbz x19, 1f // not a kernel thread 924 mov x0, x20 925 blr x19 9261: get_current_task tsk 927 b ret_to_user 928SYM_CODE_END(ret_from_fork) 929NOKPROBE(ret_from_fork) 930 931#ifdef CONFIG_ARM_SDE_INTERFACE 932 933#include <asm/sdei.h> 934#include <uapi/linux/arm_sdei.h> 935 936.macro sdei_handler_exit exit_mode 937 /* On success, this call never returns... */ 938 cmp \exit_mode, #SDEI_EXIT_SMC 939 b.ne 99f 940 smc #0 941 b . 94299: hvc #0 943 b . 944.endm 945 946#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 947/* 948 * The regular SDEI entry point may have been unmapped along with the rest of 949 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 950 * argument accessible. 951 * 952 * This clobbers x4, __sdei_handler() will restore this from firmware's 953 * copy. 954 */ 955.ltorg 956.pushsection ".entry.tramp.text", "ax" 957SYM_CODE_START(__sdei_asm_entry_trampoline) 958 mrs x4, ttbr1_el1 959 tbz x4, #USER_ASID_BIT, 1f 960 961 tramp_map_kernel tmp=x4 962 isb 963 mov x4, xzr 964 965 /* 966 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 967 * the kernel on exit. 968 */ 9691: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 970 971#ifdef CONFIG_RANDOMIZE_BASE 972 adr x4, tramp_vectors + PAGE_SIZE 973 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 974 ldr x4, [x4] 975#else 976 ldr x4, =__sdei_asm_handler 977#endif 978 br x4 979SYM_CODE_END(__sdei_asm_entry_trampoline) 980NOKPROBE(__sdei_asm_entry_trampoline) 981 982/* 983 * Make the exit call and restore the original ttbr1_el1 984 * 985 * x0 & x1: setup for the exit API call 986 * x2: exit_mode 987 * x4: struct sdei_registered_event argument from registration time. 988 */ 989SYM_CODE_START(__sdei_asm_exit_trampoline) 990 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 991 cbnz x4, 1f 992 993 tramp_unmap_kernel tmp=x4 994 9951: sdei_handler_exit exit_mode=x2 996SYM_CODE_END(__sdei_asm_exit_trampoline) 997NOKPROBE(__sdei_asm_exit_trampoline) 998 .ltorg 999.popsection // .entry.tramp.text 1000#ifdef CONFIG_RANDOMIZE_BASE 1001.pushsection ".rodata", "a" 1002SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1003 .quad __sdei_asm_handler 1004SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1005.popsection // .rodata 1006#endif /* CONFIG_RANDOMIZE_BASE */ 1007#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1008 1009/* 1010 * Software Delegated Exception entry point. 1011 * 1012 * x0: Event number 1013 * x1: struct sdei_registered_event argument from registration time. 1014 * x2: interrupted PC 1015 * x3: interrupted PSTATE 1016 * x4: maybe clobbered by the trampoline 1017 * 1018 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1019 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1020 * want them. 1021 */ 1022SYM_CODE_START(__sdei_asm_handler) 1023 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1024 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1025 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1026 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1027 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1028 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1029 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1030 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1031 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1032 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1033 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1034 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1035 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1036 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1037 mov x4, sp 1038 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1039 1040 mov x19, x1 1041 1042#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1043 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1044#endif 1045 1046#ifdef CONFIG_VMAP_STACK 1047 /* 1048 * entry.S may have been using sp as a scratch register, find whether 1049 * this is a normal or critical event and switch to the appropriate 1050 * stack for this CPU. 1051 */ 1052 cbnz w4, 1f 1053 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1054 b 2f 10551: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10562: mov x6, #SDEI_STACK_SIZE 1057 add x5, x5, x6 1058 mov sp, x5 1059#endif 1060 1061#ifdef CONFIG_SHADOW_CALL_STACK 1062 /* Use a separate shadow call stack for normal and critical events */ 1063 cbnz w4, 3f 1064 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6 1065 b 4f 10663: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6 10674: 1068#endif 1069 1070 /* 1071 * We may have interrupted userspace, or a guest, or exit-from or 1072 * return-to either of these. We can't trust sp_el0, restore it. 1073 */ 1074 mrs x28, sp_el0 1075 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1076 msr sp_el0, x0 1077 1078 /* If we interrupted the kernel point to the previous stack/frame. */ 1079 and x0, x3, #0xc 1080 mrs x1, CurrentEL 1081 cmp x0, x1 1082 csel x29, x29, xzr, eq // fp, or zero 1083 csel x4, x2, xzr, eq // elr, or zero 1084 1085 stp x29, x4, [sp, #-16]! 1086 mov x29, sp 1087 1088 add x0, x19, #SDEI_EVENT_INTREGS 1089 mov x1, x19 1090 bl __sdei_handler 1091 1092 msr sp_el0, x28 1093 /* restore regs >x17 that we clobbered */ 1094 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1095 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1096 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1097 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1098 mov sp, x1 1099 1100 mov x1, x0 // address to complete_and_resume 1101 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1102 cmp x0, #1 1103 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1104 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1105 csel x0, x2, x3, ls 1106 1107 ldr_l x2, sdei_exit_mode 1108 1109alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1110 sdei_handler_exit exit_mode=x2 1111alternative_else_nop_endif 1112 1113#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1114 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1115 br x5 1116#endif 1117SYM_CODE_END(__sdei_asm_handler) 1118NOKPROBE(__sdei_asm_handler) 1119#endif /* CONFIG_ARM_SDE_INTERFACE */ 1120