1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/cpufeature.h> 18#include <asm/errno.h> 19#include <asm/esr.h> 20#include <asm/irq.h> 21#include <asm/memory.h> 22#include <asm/mmu.h> 23#include <asm/processor.h> 24#include <asm/ptrace.h> 25#include <asm/thread_info.h> 26#include <asm/asm-uaccess.h> 27#include <asm/unistd.h> 28 29/* 30 * Context tracking subsystem. Used to instrument transitions 31 * between user and kernel mode. 32 */ 33 .macro ct_user_exit_irqoff 34#ifdef CONFIG_CONTEXT_TRACKING 35 bl enter_from_user_mode 36#endif 37 .endm 38 39 .macro ct_user_enter 40#ifdef CONFIG_CONTEXT_TRACKING 41 bl context_tracking_user_enter 42#endif 43 .endm 44 45 .macro clear_gp_regs 46 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 47 mov x\n, xzr 48 .endr 49 .endm 50 51/* 52 * Bad Abort numbers 53 *----------------- 54 */ 55#define BAD_SYNC 0 56#define BAD_IRQ 1 57#define BAD_FIQ 2 58#define BAD_ERROR 3 59 60 .macro kernel_ventry, el, label, regsize = 64 61 .align 7 62#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 63alternative_if ARM64_UNMAP_KERNEL_AT_EL0 64 .if \el == 0 65 .if \regsize == 64 66 mrs x30, tpidrro_el0 67 msr tpidrro_el0, xzr 68 .else 69 mov x30, xzr 70 .endif 71 .endif 72alternative_else_nop_endif 73#endif 74 75 sub sp, sp, #S_FRAME_SIZE 76#ifdef CONFIG_VMAP_STACK 77 /* 78 * Test whether the SP has overflowed, without corrupting a GPR. 79 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT). 80 */ 81 add sp, sp, x0 // sp' = sp + x0 82 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 83 tbnz x0, #THREAD_SHIFT, 0f 84 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 85 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 86 b el\()\el\()_\label 87 880: 89 /* 90 * Either we've just detected an overflow, or we've taken an exception 91 * while on the overflow stack. Either way, we won't return to 92 * userspace, and can clobber EL0 registers to free up GPRs. 93 */ 94 95 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 96 msr tpidr_el0, x0 97 98 /* Recover the original x0 value and stash it in tpidrro_el0 */ 99 sub x0, sp, x0 100 msr tpidrro_el0, x0 101 102 /* Switch to the overflow stack */ 103 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 104 105 /* 106 * Check whether we were already on the overflow stack. This may happen 107 * after panic() re-enables interrupts. 108 */ 109 mrs x0, tpidr_el0 // sp of interrupted context 110 sub x0, sp, x0 // delta with top of overflow stack 111 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 112 b.ne __bad_stack // no? -> bad stack pointer 113 114 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 115 sub sp, sp, x0 116 mrs x0, tpidrro_el0 117#endif 118 b el\()\el\()_\label 119 .endm 120 121 .macro tramp_alias, dst, sym 122 mov_q \dst, TRAMP_VALIAS 123 add \dst, \dst, #(\sym - .entry.tramp.text) 124 .endm 125 126 // This macro corrupts x0-x3. It is the caller's duty 127 // to save/restore them if required. 128 .macro apply_ssbd, state, tmp1, tmp2 129#ifdef CONFIG_ARM64_SSBD 130alternative_cb arm64_enable_wa2_handling 131 b .L__asm_ssbd_skip\@ 132alternative_cb_end 133 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 134 cbz \tmp2, .L__asm_ssbd_skip\@ 135 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 136 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 137 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 138 mov w1, #\state 139alternative_cb arm64_update_smccc_conduit 140 nop // Patched to SMC/HVC #0 141alternative_cb_end 142.L__asm_ssbd_skip\@: 143#endif 144 .endm 145 146 .macro kernel_entry, el, regsize = 64 147 .if \regsize == 32 148 mov w0, w0 // zero upper 32 bits of x0 149 .endif 150 stp x0, x1, [sp, #16 * 0] 151 stp x2, x3, [sp, #16 * 1] 152 stp x4, x5, [sp, #16 * 2] 153 stp x6, x7, [sp, #16 * 3] 154 stp x8, x9, [sp, #16 * 4] 155 stp x10, x11, [sp, #16 * 5] 156 stp x12, x13, [sp, #16 * 6] 157 stp x14, x15, [sp, #16 * 7] 158 stp x16, x17, [sp, #16 * 8] 159 stp x18, x19, [sp, #16 * 9] 160 stp x20, x21, [sp, #16 * 10] 161 stp x22, x23, [sp, #16 * 11] 162 stp x24, x25, [sp, #16 * 12] 163 stp x26, x27, [sp, #16 * 13] 164 stp x28, x29, [sp, #16 * 14] 165 166 .if \el == 0 167 clear_gp_regs 168 mrs x21, sp_el0 169 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear, 170 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug 171 disable_step_tsk x19, x20 // exceptions when scheduling. 172 173 apply_ssbd 1, x22, x23 174 175 .else 176 add x21, sp, #S_FRAME_SIZE 177 get_current_task tsk 178 /* Save the task's original addr_limit and set USER_DS */ 179 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 180 str x20, [sp, #S_ORIG_ADDR_LIMIT] 181 mov x20, #USER_DS 182 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 183 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 184 .endif /* \el == 0 */ 185 mrs x22, elr_el1 186 mrs x23, spsr_el1 187 stp lr, x21, [sp, #S_LR] 188 189 /* 190 * In order to be able to dump the contents of struct pt_regs at the 191 * time the exception was taken (in case we attempt to walk the call 192 * stack later), chain it together with the stack frames. 193 */ 194 .if \el == 0 195 stp xzr, xzr, [sp, #S_STACKFRAME] 196 .else 197 stp x29, x22, [sp, #S_STACKFRAME] 198 .endif 199 add x29, sp, #S_STACKFRAME 200 201#ifdef CONFIG_ARM64_SW_TTBR0_PAN 202 /* 203 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 204 * EL0, there is no need to check the state of TTBR0_EL1 since 205 * accesses are always enabled. 206 * Note that the meaning of this bit differs from the ARMv8.1 PAN 207 * feature as all TTBR0_EL1 accesses are disabled, not just those to 208 * user mappings. 209 */ 210alternative_if ARM64_HAS_PAN 211 b 1f // skip TTBR0 PAN 212alternative_else_nop_endif 213 214 .if \el != 0 215 mrs x21, ttbr0_el1 216 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 217 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 218 b.eq 1f // TTBR0 access already disabled 219 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 220 .endif 221 222 __uaccess_ttbr0_disable x21 2231: 224#endif 225 226 stp x22, x23, [sp, #S_PC] 227 228 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 229 .if \el == 0 230 mov w21, #NO_SYSCALL 231 str w21, [sp, #S_SYSCALLNO] 232 .endif 233 234 /* 235 * Set sp_el0 to current thread_info. 236 */ 237 .if \el == 0 238 msr sp_el0, tsk 239 .endif 240 241 /* Save pmr */ 242alternative_if ARM64_HAS_IRQ_PRIO_MASKING 243 mrs_s x20, SYS_ICC_PMR_EL1 244 str x20, [sp, #S_PMR_SAVE] 245alternative_else_nop_endif 246 247 /* 248 * Registers that may be useful after this macro is invoked: 249 * 250 * x20 - ICC_PMR_EL1 251 * x21 - aborted SP 252 * x22 - aborted PC 253 * x23 - aborted PSTATE 254 */ 255 .endm 256 257 .macro kernel_exit, el 258 .if \el != 0 259 disable_daif 260 261 /* Restore the task's original addr_limit. */ 262 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 263 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 264 265 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 266 .endif 267 268 /* Restore pmr */ 269alternative_if ARM64_HAS_IRQ_PRIO_MASKING 270 ldr x20, [sp, #S_PMR_SAVE] 271 msr_s SYS_ICC_PMR_EL1, x20 272 mrs_s x21, SYS_ICC_CTLR_EL1 273 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 274 dsb sy // Ensure priority change is seen by redistributor 275.L__skip_pmr_sync\@: 276alternative_else_nop_endif 277 278 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 279 .if \el == 0 280 ct_user_enter 281 .endif 282 283#ifdef CONFIG_ARM64_SW_TTBR0_PAN 284 /* 285 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 286 * PAN bit checking. 287 */ 288alternative_if ARM64_HAS_PAN 289 b 2f // skip TTBR0 PAN 290alternative_else_nop_endif 291 292 .if \el != 0 293 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 294 .endif 295 296 __uaccess_ttbr0_enable x0, x1 297 298 .if \el == 0 299 /* 300 * Enable errata workarounds only if returning to user. The only 301 * workaround currently required for TTBR0_EL1 changes are for the 302 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 303 * corruption). 304 */ 305 bl post_ttbr_update_workaround 306 .endif 3071: 308 .if \el != 0 309 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 310 .endif 3112: 312#endif 313 314 .if \el == 0 315 ldr x23, [sp, #S_SP] // load return stack pointer 316 msr sp_el0, x23 317 tst x22, #PSR_MODE32_BIT // native task? 318 b.eq 3f 319 320#ifdef CONFIG_ARM64_ERRATUM_845719 321alternative_if ARM64_WORKAROUND_845719 322#ifdef CONFIG_PID_IN_CONTEXTIDR 323 mrs x29, contextidr_el1 324 msr contextidr_el1, x29 325#else 326 msr contextidr_el1, xzr 327#endif 328alternative_else_nop_endif 329#endif 3303: 331#ifdef CONFIG_ARM64_ERRATUM_1418040 332alternative_if_not ARM64_WORKAROUND_1418040 333 b 4f 334alternative_else_nop_endif 335 /* 336 * if (x22.mode32 == cntkctl_el1.el0vcten) 337 * cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten 338 */ 339 mrs x1, cntkctl_el1 340 eon x0, x1, x22, lsr #3 341 tbz x0, #1, 4f 342 eor x1, x1, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN 343 msr cntkctl_el1, x1 3444: 345#endif 346 apply_ssbd 0, x0, x1 347 .endif 348 349 msr elr_el1, x21 // set up the return data 350 msr spsr_el1, x22 351 ldp x0, x1, [sp, #16 * 0] 352 ldp x2, x3, [sp, #16 * 1] 353 ldp x4, x5, [sp, #16 * 2] 354 ldp x6, x7, [sp, #16 * 3] 355 ldp x8, x9, [sp, #16 * 4] 356 ldp x10, x11, [sp, #16 * 5] 357 ldp x12, x13, [sp, #16 * 6] 358 ldp x14, x15, [sp, #16 * 7] 359 ldp x16, x17, [sp, #16 * 8] 360 ldp x18, x19, [sp, #16 * 9] 361 ldp x20, x21, [sp, #16 * 10] 362 ldp x22, x23, [sp, #16 * 11] 363 ldp x24, x25, [sp, #16 * 12] 364 ldp x26, x27, [sp, #16 * 13] 365 ldp x28, x29, [sp, #16 * 14] 366 ldr lr, [sp, #S_LR] 367 add sp, sp, #S_FRAME_SIZE // restore sp 368 369 .if \el == 0 370alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 371#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 372 bne 5f 373 msr far_el1, x30 374 tramp_alias x30, tramp_exit_native 375 br x30 3765: 377 tramp_alias x30, tramp_exit_compat 378 br x30 379#endif 380 .else 381 eret 382 .endif 383 sb 384 .endm 385 386 .macro irq_stack_entry 387 mov x19, sp // preserve the original sp 388 389 /* 390 * Compare sp with the base of the task stack. 391 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 392 * and should switch to the irq stack. 393 */ 394 ldr x25, [tsk, TSK_STACK] 395 eor x25, x25, x19 396 and x25, x25, #~(THREAD_SIZE - 1) 397 cbnz x25, 9998f 398 399 ldr_this_cpu x25, irq_stack_ptr, x26 400 mov x26, #IRQ_STACK_SIZE 401 add x26, x25, x26 402 403 /* switch to the irq stack */ 404 mov sp, x26 4059998: 406 .endm 407 408 /* 409 * x19 should be preserved between irq_stack_entry and 410 * irq_stack_exit. 411 */ 412 .macro irq_stack_exit 413 mov sp, x19 414 .endm 415 416/* GPRs used by entry code */ 417tsk .req x28 // current thread_info 418 419/* 420 * Interrupt handling. 421 */ 422 .macro irq_handler 423 ldr_l x1, handle_arch_irq 424 mov x0, sp 425 irq_stack_entry 426 blr x1 427 irq_stack_exit 428 .endm 429 430#ifdef CONFIG_ARM64_PSEUDO_NMI 431 /* 432 * Set res to 0 if irqs were unmasked in interrupted context. 433 * Otherwise set res to non-0 value. 434 */ 435 .macro test_irqs_unmasked res:req, pmr:req 436alternative_if ARM64_HAS_IRQ_PRIO_MASKING 437 sub \res, \pmr, #GIC_PRIO_IRQON 438alternative_else 439 mov \res, xzr 440alternative_endif 441 .endm 442#endif 443 444 .macro gic_prio_kentry_setup, tmp:req 445#ifdef CONFIG_ARM64_PSEUDO_NMI 446 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 447 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 448 msr_s SYS_ICC_PMR_EL1, \tmp 449 alternative_else_nop_endif 450#endif 451 .endm 452 453 .macro gic_prio_irq_setup, pmr:req, tmp:req 454#ifdef CONFIG_ARM64_PSEUDO_NMI 455 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 456 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 457 msr_s SYS_ICC_PMR_EL1, \tmp 458 alternative_else_nop_endif 459#endif 460 .endm 461 462 .text 463 464/* 465 * Exception vectors. 466 */ 467 .pushsection ".entry.text", "ax" 468 469 .align 11 470ENTRY(vectors) 471 kernel_ventry 1, sync_invalid // Synchronous EL1t 472 kernel_ventry 1, irq_invalid // IRQ EL1t 473 kernel_ventry 1, fiq_invalid // FIQ EL1t 474 kernel_ventry 1, error_invalid // Error EL1t 475 476 kernel_ventry 1, sync // Synchronous EL1h 477 kernel_ventry 1, irq // IRQ EL1h 478 kernel_ventry 1, fiq_invalid // FIQ EL1h 479 kernel_ventry 1, error // Error EL1h 480 481 kernel_ventry 0, sync // Synchronous 64-bit EL0 482 kernel_ventry 0, irq // IRQ 64-bit EL0 483 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 484 kernel_ventry 0, error // Error 64-bit EL0 485 486#ifdef CONFIG_COMPAT 487 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 488 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 489 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 490 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 491#else 492 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 493 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 494 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 495 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 496#endif 497END(vectors) 498 499#ifdef CONFIG_VMAP_STACK 500 /* 501 * We detected an overflow in kernel_ventry, which switched to the 502 * overflow stack. Stash the exception regs, and head to our overflow 503 * handler. 504 */ 505__bad_stack: 506 /* Restore the original x0 value */ 507 mrs x0, tpidrro_el0 508 509 /* 510 * Store the original GPRs to the new stack. The orginal SP (minus 511 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 512 */ 513 sub sp, sp, #S_FRAME_SIZE 514 kernel_entry 1 515 mrs x0, tpidr_el0 516 add x0, x0, #S_FRAME_SIZE 517 str x0, [sp, #S_SP] 518 519 /* Stash the regs for handle_bad_stack */ 520 mov x0, sp 521 522 /* Time to die */ 523 bl handle_bad_stack 524 ASM_BUG() 525#endif /* CONFIG_VMAP_STACK */ 526 527/* 528 * Invalid mode handlers 529 */ 530 .macro inv_entry, el, reason, regsize = 64 531 kernel_entry \el, \regsize 532 mov x0, sp 533 mov x1, #\reason 534 mrs x2, esr_el1 535 bl bad_mode 536 ASM_BUG() 537 .endm 538 539el0_sync_invalid: 540 inv_entry 0, BAD_SYNC 541ENDPROC(el0_sync_invalid) 542 543el0_irq_invalid: 544 inv_entry 0, BAD_IRQ 545ENDPROC(el0_irq_invalid) 546 547el0_fiq_invalid: 548 inv_entry 0, BAD_FIQ 549ENDPROC(el0_fiq_invalid) 550 551el0_error_invalid: 552 inv_entry 0, BAD_ERROR 553ENDPROC(el0_error_invalid) 554 555#ifdef CONFIG_COMPAT 556el0_fiq_invalid_compat: 557 inv_entry 0, BAD_FIQ, 32 558ENDPROC(el0_fiq_invalid_compat) 559#endif 560 561el1_sync_invalid: 562 inv_entry 1, BAD_SYNC 563ENDPROC(el1_sync_invalid) 564 565el1_irq_invalid: 566 inv_entry 1, BAD_IRQ 567ENDPROC(el1_irq_invalid) 568 569el1_fiq_invalid: 570 inv_entry 1, BAD_FIQ 571ENDPROC(el1_fiq_invalid) 572 573el1_error_invalid: 574 inv_entry 1, BAD_ERROR 575ENDPROC(el1_error_invalid) 576 577/* 578 * EL1 mode handlers. 579 */ 580 .align 6 581el1_sync: 582 kernel_entry 1 583 mov x0, sp 584 bl el1_sync_handler 585 kernel_exit 1 586ENDPROC(el1_sync) 587 588 .align 6 589el1_irq: 590 kernel_entry 1 591 gic_prio_irq_setup pmr=x20, tmp=x1 592 enable_da_f 593 594#ifdef CONFIG_ARM64_PSEUDO_NMI 595 test_irqs_unmasked res=x0, pmr=x20 596 cbz x0, 1f 597 bl asm_nmi_enter 5981: 599#endif 600 601#ifdef CONFIG_TRACE_IRQFLAGS 602 bl trace_hardirqs_off 603#endif 604 605 irq_handler 606 607#ifdef CONFIG_PREEMPT 608 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 609alternative_if ARM64_HAS_IRQ_PRIO_MASKING 610 /* 611 * DA_F were cleared at start of handling. If anything is set in DAIF, 612 * we come back from an NMI, so skip preemption 613 */ 614 mrs x0, daif 615 orr x24, x24, x0 616alternative_else_nop_endif 617 cbnz x24, 1f // preempt count != 0 || NMI return path 618 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6191: 620#endif 621 622#ifdef CONFIG_ARM64_PSEUDO_NMI 623 /* 624 * When using IRQ priority masking, we can get spurious interrupts while 625 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a 626 * section with interrupts disabled. Skip tracing in those cases. 627 */ 628 test_irqs_unmasked res=x0, pmr=x20 629 cbz x0, 1f 630 bl asm_nmi_exit 6311: 632#endif 633 634#ifdef CONFIG_TRACE_IRQFLAGS 635#ifdef CONFIG_ARM64_PSEUDO_NMI 636 test_irqs_unmasked res=x0, pmr=x20 637 cbnz x0, 1f 638#endif 639 bl trace_hardirqs_on 6401: 641#endif 642 643 kernel_exit 1 644ENDPROC(el1_irq) 645 646/* 647 * EL0 mode handlers. 648 */ 649 .align 6 650el0_sync: 651 kernel_entry 0 652 mov x0, sp 653 bl el0_sync_handler 654 b ret_to_user 655 656#ifdef CONFIG_COMPAT 657 .align 6 658el0_sync_compat: 659 kernel_entry 0, 32 660 mov x0, sp 661 bl el0_sync_compat_handler 662 b ret_to_user 663ENDPROC(el0_sync) 664 665 .align 6 666el0_irq_compat: 667 kernel_entry 0, 32 668 b el0_irq_naked 669 670el0_error_compat: 671 kernel_entry 0, 32 672 b el0_error_naked 673#endif 674 675 .align 6 676el0_irq: 677 kernel_entry 0 678el0_irq_naked: 679 gic_prio_irq_setup pmr=x20, tmp=x0 680 ct_user_exit_irqoff 681 enable_da_f 682 683#ifdef CONFIG_TRACE_IRQFLAGS 684 bl trace_hardirqs_off 685#endif 686 687#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR 688 tbz x22, #55, 1f 689 bl do_el0_irq_bp_hardening 6901: 691#endif 692 irq_handler 693 694#ifdef CONFIG_TRACE_IRQFLAGS 695 bl trace_hardirqs_on 696#endif 697 b ret_to_user 698ENDPROC(el0_irq) 699 700el1_error: 701 kernel_entry 1 702 mrs x1, esr_el1 703 gic_prio_kentry_setup tmp=x2 704 enable_dbg 705 mov x0, sp 706 bl do_serror 707 kernel_exit 1 708ENDPROC(el1_error) 709 710el0_error: 711 kernel_entry 0 712el0_error_naked: 713 mrs x25, esr_el1 714 gic_prio_kentry_setup tmp=x2 715 ct_user_exit_irqoff 716 enable_dbg 717 mov x0, sp 718 mov x1, x25 719 bl do_serror 720 enable_da_f 721 b ret_to_user 722ENDPROC(el0_error) 723 724/* 725 * Ok, we need to do extra processing, enter the slow path. 726 */ 727work_pending: 728 mov x0, sp // 'regs' 729 bl do_notify_resume 730#ifdef CONFIG_TRACE_IRQFLAGS 731 bl trace_hardirqs_on // enabled while in userspace 732#endif 733 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step 734 b finish_ret_to_user 735/* 736 * "slow" syscall return path. 737 */ 738ret_to_user: 739 disable_daif 740 gic_prio_kentry_setup tmp=x3 741 ldr x1, [tsk, #TSK_TI_FLAGS] 742 and x2, x1, #_TIF_WORK_MASK 743 cbnz x2, work_pending 744finish_ret_to_user: 745 enable_step_tsk x1, x2 746#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 747 bl stackleak_erase 748#endif 749 kernel_exit 0 750ENDPROC(ret_to_user) 751 752 .popsection // .entry.text 753 754#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 755/* 756 * Exception vectors trampoline. 757 */ 758 .pushsection ".entry.tramp.text", "ax" 759 760 .macro tramp_map_kernel, tmp 761 mrs \tmp, ttbr1_el1 762 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 763 bic \tmp, \tmp, #USER_ASID_FLAG 764 msr ttbr1_el1, \tmp 765#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 766alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 767 /* ASID already in \tmp[63:48] */ 768 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 769 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 770 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 771 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 772 isb 773 tlbi vae1, \tmp 774 dsb nsh 775alternative_else_nop_endif 776#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 777 .endm 778 779 .macro tramp_unmap_kernel, tmp 780 mrs \tmp, ttbr1_el1 781 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 782 orr \tmp, \tmp, #USER_ASID_FLAG 783 msr ttbr1_el1, \tmp 784 /* 785 * We avoid running the post_ttbr_update_workaround here because 786 * it's only needed by Cavium ThunderX, which requires KPTI to be 787 * disabled. 788 */ 789 .endm 790 791 .macro tramp_ventry, regsize = 64 792 .align 7 7931: 794 .if \regsize == 64 795 msr tpidrro_el0, x30 // Restored in kernel_ventry 796 .endif 797 /* 798 * Defend against branch aliasing attacks by pushing a dummy 799 * entry onto the return stack and using a RET instruction to 800 * enter the full-fat kernel vectors. 801 */ 802 bl 2f 803 b . 8042: 805 tramp_map_kernel x30 806#ifdef CONFIG_RANDOMIZE_BASE 807 adr x30, tramp_vectors + PAGE_SIZE 808alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 809 ldr x30, [x30] 810#else 811 ldr x30, =vectors 812#endif 813alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 814 prfm plil1strm, [x30, #(1b - tramp_vectors)] 815alternative_else_nop_endif 816 msr vbar_el1, x30 817 add x30, x30, #(1b - tramp_vectors) 818 isb 819 ret 820 .endm 821 822 .macro tramp_exit, regsize = 64 823 adr x30, tramp_vectors 824 msr vbar_el1, x30 825 tramp_unmap_kernel x30 826 .if \regsize == 64 827 mrs x30, far_el1 828 .endif 829 eret 830 sb 831 .endm 832 833 .align 11 834ENTRY(tramp_vectors) 835 .space 0x400 836 837 tramp_ventry 838 tramp_ventry 839 tramp_ventry 840 tramp_ventry 841 842 tramp_ventry 32 843 tramp_ventry 32 844 tramp_ventry 32 845 tramp_ventry 32 846END(tramp_vectors) 847 848ENTRY(tramp_exit_native) 849 tramp_exit 850END(tramp_exit_native) 851 852ENTRY(tramp_exit_compat) 853 tramp_exit 32 854END(tramp_exit_compat) 855 856 .ltorg 857 .popsection // .entry.tramp.text 858#ifdef CONFIG_RANDOMIZE_BASE 859 .pushsection ".rodata", "a" 860 .align PAGE_SHIFT 861 .globl __entry_tramp_data_start 862__entry_tramp_data_start: 863 .quad vectors 864 .popsection // .rodata 865#endif /* CONFIG_RANDOMIZE_BASE */ 866#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 867 868/* 869 * Register switch for AArch64. The callee-saved registers need to be saved 870 * and restored. On entry: 871 * x0 = previous task_struct (must be preserved across the switch) 872 * x1 = next task_struct 873 * Previous and next are guaranteed not to be the same. 874 * 875 */ 876ENTRY(cpu_switch_to) 877 mov x10, #THREAD_CPU_CONTEXT 878 add x8, x0, x10 879 mov x9, sp 880 stp x19, x20, [x8], #16 // store callee-saved registers 881 stp x21, x22, [x8], #16 882 stp x23, x24, [x8], #16 883 stp x25, x26, [x8], #16 884 stp x27, x28, [x8], #16 885 stp x29, x9, [x8], #16 886 str lr, [x8] 887 add x8, x1, x10 888 ldp x19, x20, [x8], #16 // restore callee-saved registers 889 ldp x21, x22, [x8], #16 890 ldp x23, x24, [x8], #16 891 ldp x25, x26, [x8], #16 892 ldp x27, x28, [x8], #16 893 ldp x29, x9, [x8], #16 894 ldr lr, [x8] 895 mov sp, x9 896 msr sp_el0, x1 897 ret 898ENDPROC(cpu_switch_to) 899NOKPROBE(cpu_switch_to) 900 901/* 902 * This is how we return from a fork. 903 */ 904ENTRY(ret_from_fork) 905 bl schedule_tail 906 cbz x19, 1f // not a kernel thread 907 mov x0, x20 908 blr x19 9091: get_current_task tsk 910 b ret_to_user 911ENDPROC(ret_from_fork) 912NOKPROBE(ret_from_fork) 913 914#ifdef CONFIG_ARM_SDE_INTERFACE 915 916#include <asm/sdei.h> 917#include <uapi/linux/arm_sdei.h> 918 919.macro sdei_handler_exit exit_mode 920 /* On success, this call never returns... */ 921 cmp \exit_mode, #SDEI_EXIT_SMC 922 b.ne 99f 923 smc #0 924 b . 92599: hvc #0 926 b . 927.endm 928 929#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 930/* 931 * The regular SDEI entry point may have been unmapped along with the rest of 932 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 933 * argument accessible. 934 * 935 * This clobbers x4, __sdei_handler() will restore this from firmware's 936 * copy. 937 */ 938.ltorg 939.pushsection ".entry.tramp.text", "ax" 940ENTRY(__sdei_asm_entry_trampoline) 941 mrs x4, ttbr1_el1 942 tbz x4, #USER_ASID_BIT, 1f 943 944 tramp_map_kernel tmp=x4 945 isb 946 mov x4, xzr 947 948 /* 949 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 950 * the kernel on exit. 951 */ 9521: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 953 954#ifdef CONFIG_RANDOMIZE_BASE 955 adr x4, tramp_vectors + PAGE_SIZE 956 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 957 ldr x4, [x4] 958#else 959 ldr x4, =__sdei_asm_handler 960#endif 961 br x4 962ENDPROC(__sdei_asm_entry_trampoline) 963NOKPROBE(__sdei_asm_entry_trampoline) 964 965/* 966 * Make the exit call and restore the original ttbr1_el1 967 * 968 * x0 & x1: setup for the exit API call 969 * x2: exit_mode 970 * x4: struct sdei_registered_event argument from registration time. 971 */ 972ENTRY(__sdei_asm_exit_trampoline) 973 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 974 cbnz x4, 1f 975 976 tramp_unmap_kernel tmp=x4 977 9781: sdei_handler_exit exit_mode=x2 979ENDPROC(__sdei_asm_exit_trampoline) 980NOKPROBE(__sdei_asm_exit_trampoline) 981 .ltorg 982.popsection // .entry.tramp.text 983#ifdef CONFIG_RANDOMIZE_BASE 984.pushsection ".rodata", "a" 985__sdei_asm_trampoline_next_handler: 986 .quad __sdei_asm_handler 987.popsection // .rodata 988#endif /* CONFIG_RANDOMIZE_BASE */ 989#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 990 991/* 992 * Software Delegated Exception entry point. 993 * 994 * x0: Event number 995 * x1: struct sdei_registered_event argument from registration time. 996 * x2: interrupted PC 997 * x3: interrupted PSTATE 998 * x4: maybe clobbered by the trampoline 999 * 1000 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1001 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1002 * want them. 1003 */ 1004ENTRY(__sdei_asm_handler) 1005 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1006 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1007 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1008 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1009 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1010 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1011 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1012 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1013 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1014 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1015 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1016 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1017 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1018 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1019 mov x4, sp 1020 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1021 1022 mov x19, x1 1023 1024#ifdef CONFIG_VMAP_STACK 1025 /* 1026 * entry.S may have been using sp as a scratch register, find whether 1027 * this is a normal or critical event and switch to the appropriate 1028 * stack for this CPU. 1029 */ 1030 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1031 cbnz w4, 1f 1032 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1033 b 2f 10341: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10352: mov x6, #SDEI_STACK_SIZE 1036 add x5, x5, x6 1037 mov sp, x5 1038#endif 1039 1040 /* 1041 * We may have interrupted userspace, or a guest, or exit-from or 1042 * return-to either of these. We can't trust sp_el0, restore it. 1043 */ 1044 mrs x28, sp_el0 1045 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1046 msr sp_el0, x0 1047 1048 /* If we interrupted the kernel point to the previous stack/frame. */ 1049 and x0, x3, #0xc 1050 mrs x1, CurrentEL 1051 cmp x0, x1 1052 csel x29, x29, xzr, eq // fp, or zero 1053 csel x4, x2, xzr, eq // elr, or zero 1054 1055 stp x29, x4, [sp, #-16]! 1056 mov x29, sp 1057 1058 add x0, x19, #SDEI_EVENT_INTREGS 1059 mov x1, x19 1060 bl __sdei_handler 1061 1062 msr sp_el0, x28 1063 /* restore regs >x17 that we clobbered */ 1064 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1065 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1066 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1067 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1068 mov sp, x1 1069 1070 mov x1, x0 // address to complete_and_resume 1071 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1072 cmp x0, #1 1073 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1074 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1075 csel x0, x2, x3, ls 1076 1077 ldr_l x2, sdei_exit_mode 1078 1079alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1080 sdei_handler_exit exit_mode=x2 1081alternative_else_nop_endif 1082 1083#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1084 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1085 br x5 1086#endif 1087ENDPROC(__sdei_asm_handler) 1088NOKPROBE(__sdei_asm_handler) 1089#endif /* CONFIG_ARM_SDE_INTERFACE */ 1090