1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32 .macro clear_gp_regs 33 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 34 mov x\n, xzr 35 .endr 36 .endm 37 38 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 39 .align 7 40.Lventry_start\@: 41 .if \el == 0 42 /* 43 * This must be the first instruction of the EL0 vector entries. It is 44 * skipped by the trampoline vectors, to trigger the cleanup. 45 */ 46 b .Lskip_tramp_vectors_cleanup\@ 47 .if \regsize == 64 48 mrs x30, tpidrro_el0 49 msr tpidrro_el0, xzr 50 .else 51 mov x30, xzr 52 .endif 53.Lskip_tramp_vectors_cleanup\@: 54 .endif 55 56 sub sp, sp, #PT_REGS_SIZE 57#ifdef CONFIG_VMAP_STACK 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99#endif 100 b el\el\ht\()_\regsize\()_\label 101.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 102 .endm 103 104 .macro tramp_alias, dst, sym, tmp 105 mov_q \dst, TRAMP_VALIAS 106 adr_l \tmp, \sym 107 add \dst, \dst, \tmp 108 adr_l \tmp, .entry.tramp.text 109 sub \dst, \dst, \tmp 110 .endm 111 112 /* 113 * This macro corrupts x0-x3. It is the caller's duty to save/restore 114 * them if required. 115 */ 116 .macro apply_ssbd, state, tmp1, tmp2 117alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable 118 b .L__asm_ssbd_skip\@ // Patched to NOP 119alternative_cb_end 120 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 121 cbz \tmp2, .L__asm_ssbd_skip\@ 122 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 123 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 124 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 125 mov w1, #\state 126alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 127 nop // Patched to SMC/HVC #0 128alternative_cb_end 129.L__asm_ssbd_skip\@: 130 .endm 131 132 /* Check for MTE asynchronous tag check faults */ 133 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 134#ifdef CONFIG_ARM64_MTE 135 .arch_extension lse 136alternative_if_not ARM64_MTE 137 b 1f 138alternative_else_nop_endif 139 /* 140 * Asynchronous tag check faults are only possible in ASYNC (2) or 141 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 142 * set, so skip the check if it is unset. 143 */ 144 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 145 mrs_s \tmp, SYS_TFSRE0_EL1 146 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 147 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 148 mov \tmp, #_TIF_MTE_ASYNC_FAULT 149 add \ti_flags, tsk, #TSK_TI_FLAGS 150 stset \tmp, [\ti_flags] 1511: 152#endif 153 .endm 154 155 /* Clear the MTE asynchronous tag check faults */ 156 .macro clear_mte_async_tcf thread_sctlr 157#ifdef CONFIG_ARM64_MTE 158alternative_if ARM64_MTE 159 /* See comment in check_mte_async_tcf above. */ 160 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 161 dsb ish 162 msr_s SYS_TFSRE0_EL1, xzr 1631: 164alternative_else_nop_endif 165#endif 166 .endm 167 168 .macro mte_set_gcr, mte_ctrl, tmp 169#ifdef CONFIG_ARM64_MTE 170 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 171 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 172 msr_s SYS_GCR_EL1, \tmp 173#endif 174 .endm 175 176 .macro mte_set_kernel_gcr, tmp, tmp2 177#ifdef CONFIG_KASAN_HW_TAGS 178alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 179 b 1f 180alternative_cb_end 181 mov \tmp, KERNEL_GCR_EL1 182 msr_s SYS_GCR_EL1, \tmp 1831: 184#endif 185 .endm 186 187 .macro mte_set_user_gcr, tsk, tmp, tmp2 188#ifdef CONFIG_KASAN_HW_TAGS 189alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 190 b 1f 191alternative_cb_end 192 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 193 194 mte_set_gcr \tmp, \tmp2 1951: 196#endif 197 .endm 198 199 .macro kernel_entry, el, regsize = 64 200 .if \el == 0 201 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT 202 .endif 203 .if \regsize == 32 204 mov w0, w0 // zero upper 32 bits of x0 205 .endif 206 stp x0, x1, [sp, #16 * 0] 207 stp x2, x3, [sp, #16 * 1] 208 stp x4, x5, [sp, #16 * 2] 209 stp x6, x7, [sp, #16 * 3] 210 stp x8, x9, [sp, #16 * 4] 211 stp x10, x11, [sp, #16 * 5] 212 stp x12, x13, [sp, #16 * 6] 213 stp x14, x15, [sp, #16 * 7] 214 stp x16, x17, [sp, #16 * 8] 215 stp x18, x19, [sp, #16 * 9] 216 stp x20, x21, [sp, #16 * 10] 217 stp x22, x23, [sp, #16 * 11] 218 stp x24, x25, [sp, #16 * 12] 219 stp x26, x27, [sp, #16 * 13] 220 stp x28, x29, [sp, #16 * 14] 221 222 .if \el == 0 223 clear_gp_regs 224 mrs x21, sp_el0 225 ldr_this_cpu tsk, __entry_task, x20 226 msr sp_el0, tsk 227 228 /* 229 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 230 * when scheduling. 231 */ 232 ldr x19, [tsk, #TSK_TI_FLAGS] 233 disable_step_tsk x19, x20 234 235 /* Check for asynchronous tag check faults in user space */ 236 ldr x0, [tsk, THREAD_SCTLR_USER] 237 check_mte_async_tcf x22, x23, x0 238 239#ifdef CONFIG_ARM64_PTR_AUTH 240alternative_if ARM64_HAS_ADDRESS_AUTH 241 /* 242 * Enable IA for in-kernel PAC if the task had it disabled. Although 243 * this could be implemented with an unconditional MRS which would avoid 244 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 245 * 246 * Install the kernel IA key only if IA was enabled in the task. If IA 247 * was disabled on kernel exit then we would have left the kernel IA 248 * installed so there is no need to install it again. 249 */ 250 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 251 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 252 b 2f 2531: 254 mrs x0, sctlr_el1 255 orr x0, x0, SCTLR_ELx_ENIA 256 msr sctlr_el1, x0 2572: 258alternative_else_nop_endif 259#endif 260 261 apply_ssbd 1, x22, x23 262 263 mte_set_kernel_gcr x22, x23 264 265 /* 266 * Any non-self-synchronizing system register updates required for 267 * kernel entry should be placed before this point. 268 */ 269alternative_if ARM64_MTE 270 isb 271 b 1f 272alternative_else_nop_endif 273alternative_if ARM64_HAS_ADDRESS_AUTH 274 isb 275alternative_else_nop_endif 2761: 277 278 scs_load_current 279 .else 280 add x21, sp, #PT_REGS_SIZE 281 get_current_task tsk 282 .endif /* \el == 0 */ 283 mrs x22, elr_el1 284 mrs x23, spsr_el1 285 stp lr, x21, [sp, #S_LR] 286 287 /* 288 * For exceptions from EL0, create a final frame record. 289 * For exceptions from EL1, create a synthetic frame record so the 290 * interrupted code shows up in the backtrace. 291 */ 292 .if \el == 0 293 stp xzr, xzr, [sp, #S_STACKFRAME] 294 .else 295 stp x29, x22, [sp, #S_STACKFRAME] 296 .endif 297 add x29, sp, #S_STACKFRAME 298 299#ifdef CONFIG_ARM64_SW_TTBR0_PAN 300alternative_if_not ARM64_HAS_PAN 301 bl __swpan_entry_el\el 302alternative_else_nop_endif 303#endif 304 305 stp x22, x23, [sp, #S_PC] 306 307 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 308 .if \el == 0 309 mov w21, #NO_SYSCALL 310 str w21, [sp, #S_SYSCALLNO] 311 .endif 312 313#ifdef CONFIG_ARM64_PSEUDO_NMI 314alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 315 b .Lskip_pmr_save\@ 316alternative_else_nop_endif 317 318 mrs_s x20, SYS_ICC_PMR_EL1 319 str x20, [sp, #S_PMR_SAVE] 320 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 321 msr_s SYS_ICC_PMR_EL1, x20 322 323.Lskip_pmr_save\@: 324#endif 325 326 /* 327 * Registers that may be useful after this macro is invoked: 328 * 329 * x20 - ICC_PMR_EL1 330 * x21 - aborted SP 331 * x22 - aborted PC 332 * x23 - aborted PSTATE 333 */ 334 .endm 335 336 .macro kernel_exit, el 337 .if \el != 0 338 disable_daif 339 .endif 340 341#ifdef CONFIG_ARM64_PSEUDO_NMI 342alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 343 b .Lskip_pmr_restore\@ 344alternative_else_nop_endif 345 346 ldr x20, [sp, #S_PMR_SAVE] 347 msr_s SYS_ICC_PMR_EL1, x20 348 349 /* Ensure priority change is seen by redistributor */ 350alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC 351 dsb sy 352alternative_else_nop_endif 353 354.Lskip_pmr_restore\@: 355#endif 356 357 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 358 359#ifdef CONFIG_ARM64_SW_TTBR0_PAN 360alternative_if_not ARM64_HAS_PAN 361 bl __swpan_exit_el\el 362alternative_else_nop_endif 363#endif 364 365 .if \el == 0 366 ldr x23, [sp, #S_SP] // load return stack pointer 367 msr sp_el0, x23 368 tst x22, #PSR_MODE32_BIT // native task? 369 b.eq 3f 370 371#ifdef CONFIG_ARM64_ERRATUM_845719 372alternative_if ARM64_WORKAROUND_845719 373#ifdef CONFIG_PID_IN_CONTEXTIDR 374 mrs x29, contextidr_el1 375 msr contextidr_el1, x29 376#else 377 msr contextidr_el1, xzr 378#endif 379alternative_else_nop_endif 380#endif 3813: 382 scs_save tsk 383 384 /* Ignore asynchronous tag check faults in the uaccess routines */ 385 ldr x0, [tsk, THREAD_SCTLR_USER] 386 clear_mte_async_tcf x0 387 388#ifdef CONFIG_ARM64_PTR_AUTH 389alternative_if ARM64_HAS_ADDRESS_AUTH 390 /* 391 * IA was enabled for in-kernel PAC. Disable it now if needed, or 392 * alternatively install the user's IA. All other per-task keys and 393 * SCTLR bits were updated on task switch. 394 * 395 * No kernel C function calls after this. 396 */ 397 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 398 __ptrauth_keys_install_user tsk, x0, x1, x2 399 b 2f 4001: 401 mrs x0, sctlr_el1 402 bic x0, x0, SCTLR_ELx_ENIA 403 msr sctlr_el1, x0 4042: 405alternative_else_nop_endif 406#endif 407 408 mte_set_user_gcr tsk, x0, x1 409 410 apply_ssbd 0, x0, x1 411 .endif 412 413 msr elr_el1, x21 // set up the return data 414 msr spsr_el1, x22 415 ldp x0, x1, [sp, #16 * 0] 416 ldp x2, x3, [sp, #16 * 1] 417 ldp x4, x5, [sp, #16 * 2] 418 ldp x6, x7, [sp, #16 * 3] 419 ldp x8, x9, [sp, #16 * 4] 420 ldp x10, x11, [sp, #16 * 5] 421 ldp x12, x13, [sp, #16 * 6] 422 ldp x14, x15, [sp, #16 * 7] 423 ldp x16, x17, [sp, #16 * 8] 424 ldp x18, x19, [sp, #16 * 9] 425 ldp x20, x21, [sp, #16 * 10] 426 ldp x22, x23, [sp, #16 * 11] 427 ldp x24, x25, [sp, #16 * 12] 428 ldp x26, x27, [sp, #16 * 13] 429 ldp x28, x29, [sp, #16 * 14] 430 431 .if \el == 0 432alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 433 ldr lr, [sp, #S_LR] 434 add sp, sp, #PT_REGS_SIZE // restore sp 435 eret 436alternative_else_nop_endif 437#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 438 bne 4f 439 msr far_el1, x29 440 tramp_alias x30, tramp_exit_native, x29 441 br x30 4424: 443 tramp_alias x30, tramp_exit_compat, x29 444 br x30 445#endif 446 .else 447 ldr lr, [sp, #S_LR] 448 add sp, sp, #PT_REGS_SIZE // restore sp 449 450 /* Ensure any device/NC reads complete */ 451 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 452 453 eret 454 .endif 455 sb 456 .endm 457 458#ifdef CONFIG_ARM64_SW_TTBR0_PAN 459 /* 460 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 461 * EL0, there is no need to check the state of TTBR0_EL1 since 462 * accesses are always enabled. 463 * Note that the meaning of this bit differs from the ARMv8.1 PAN 464 * feature as all TTBR0_EL1 accesses are disabled, not just those to 465 * user mappings. 466 */ 467SYM_CODE_START_LOCAL(__swpan_entry_el1) 468 mrs x21, ttbr0_el1 469 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 470 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 471 b.eq 1f // TTBR0 access already disabled 472 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 473SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 474 __uaccess_ttbr0_disable x21 4751: ret 476SYM_CODE_END(__swpan_entry_el1) 477 478 /* 479 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 480 * PAN bit checking. 481 */ 482SYM_CODE_START_LOCAL(__swpan_exit_el1) 483 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 484 __uaccess_ttbr0_enable x0, x1 4851: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 486 ret 487SYM_CODE_END(__swpan_exit_el1) 488 489SYM_CODE_START_LOCAL(__swpan_exit_el0) 490 __uaccess_ttbr0_enable x0, x1 491 /* 492 * Enable errata workarounds only if returning to user. The only 493 * workaround currently required for TTBR0_EL1 changes are for the 494 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 495 * corruption). 496 */ 497 b post_ttbr_update_workaround 498SYM_CODE_END(__swpan_exit_el0) 499#endif 500 501/* GPRs used by entry code */ 502tsk .req x28 // current thread_info 503 504 .text 505 506/* 507 * Exception vectors. 508 */ 509 .pushsection ".entry.text", "ax" 510 511 .align 11 512SYM_CODE_START(vectors) 513 kernel_ventry 1, t, 64, sync // Synchronous EL1t 514 kernel_ventry 1, t, 64, irq // IRQ EL1t 515 kernel_ventry 1, t, 64, fiq // FIQ EL1t 516 kernel_ventry 1, t, 64, error // Error EL1t 517 518 kernel_ventry 1, h, 64, sync // Synchronous EL1h 519 kernel_ventry 1, h, 64, irq // IRQ EL1h 520 kernel_ventry 1, h, 64, fiq // FIQ EL1h 521 kernel_ventry 1, h, 64, error // Error EL1h 522 523 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 524 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 525 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 526 kernel_ventry 0, t, 64, error // Error 64-bit EL0 527 528 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 529 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 530 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 531 kernel_ventry 0, t, 32, error // Error 32-bit EL0 532SYM_CODE_END(vectors) 533 534#ifdef CONFIG_VMAP_STACK 535SYM_CODE_START_LOCAL(__bad_stack) 536 /* 537 * We detected an overflow in kernel_ventry, which switched to the 538 * overflow stack. Stash the exception regs, and head to our overflow 539 * handler. 540 */ 541 542 /* Restore the original x0 value */ 543 mrs x0, tpidrro_el0 544 545 /* 546 * Store the original GPRs to the new stack. The orginal SP (minus 547 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 548 */ 549 sub sp, sp, #PT_REGS_SIZE 550 kernel_entry 1 551 mrs x0, tpidr_el0 552 add x0, x0, #PT_REGS_SIZE 553 str x0, [sp, #S_SP] 554 555 /* Stash the regs for handle_bad_stack */ 556 mov x0, sp 557 558 /* Time to die */ 559 bl handle_bad_stack 560 ASM_BUG() 561SYM_CODE_END(__bad_stack) 562#endif /* CONFIG_VMAP_STACK */ 563 564 565 .macro entry_handler el:req, ht:req, regsize:req, label:req 566SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 567 kernel_entry \el, \regsize 568 mov x0, sp 569 bl el\el\ht\()_\regsize\()_\label\()_handler 570 .if \el == 0 571 b ret_to_user 572 .else 573 b ret_to_kernel 574 .endif 575SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 576 .endm 577 578/* 579 * Early exception handlers 580 */ 581 entry_handler 1, t, 64, sync 582 entry_handler 1, t, 64, irq 583 entry_handler 1, t, 64, fiq 584 entry_handler 1, t, 64, error 585 586 entry_handler 1, h, 64, sync 587 entry_handler 1, h, 64, irq 588 entry_handler 1, h, 64, fiq 589 entry_handler 1, h, 64, error 590 591 entry_handler 0, t, 64, sync 592 entry_handler 0, t, 64, irq 593 entry_handler 0, t, 64, fiq 594 entry_handler 0, t, 64, error 595 596 entry_handler 0, t, 32, sync 597 entry_handler 0, t, 32, irq 598 entry_handler 0, t, 32, fiq 599 entry_handler 0, t, 32, error 600 601SYM_CODE_START_LOCAL(ret_to_kernel) 602 kernel_exit 1 603SYM_CODE_END(ret_to_kernel) 604 605SYM_CODE_START_LOCAL(ret_to_user) 606 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 607 enable_step_tsk x19, x2 608#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 609 bl stackleak_erase_on_task_stack 610#endif 611 kernel_exit 0 612SYM_CODE_END(ret_to_user) 613 614 .popsection // .entry.text 615 616 // Move from tramp_pg_dir to swapper_pg_dir 617 .macro tramp_map_kernel, tmp 618 mrs \tmp, ttbr1_el1 619 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 620 bic \tmp, \tmp, #USER_ASID_FLAG 621 msr ttbr1_el1, \tmp 622#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 623alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 624 /* ASID already in \tmp[63:48] */ 625 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 626 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 627 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 628 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 629 isb 630 tlbi vae1, \tmp 631 dsb nsh 632alternative_else_nop_endif 633#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 634 .endm 635 636 // Move from swapper_pg_dir to tramp_pg_dir 637 .macro tramp_unmap_kernel, tmp 638 mrs \tmp, ttbr1_el1 639 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 640 orr \tmp, \tmp, #USER_ASID_FLAG 641 msr ttbr1_el1, \tmp 642 /* 643 * We avoid running the post_ttbr_update_workaround here because 644 * it's only needed by Cavium ThunderX, which requires KPTI to be 645 * disabled. 646 */ 647 .endm 648 649 .macro tramp_data_read_var dst, var 650#ifdef CONFIG_RELOCATABLE 651 ldr \dst, .L__tramp_data_\var 652 .ifndef .L__tramp_data_\var 653 .pushsection ".entry.tramp.rodata", "a", %progbits 654 .align 3 655.L__tramp_data_\var: 656 .quad \var 657 .popsection 658 .endif 659#else 660 /* 661 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a 662 * compile time constant (and hence not secret and not worth hiding). 663 * 664 * As statically allocated kernel code and data always live in the top 665 * 47 bits of the address space we can sign-extend bit 47 and avoid an 666 * instruction to load the upper 16 bits (which must be 0xFFFF). 667 */ 668 movz \dst, :abs_g2_s:\var 669 movk \dst, :abs_g1_nc:\var 670 movk \dst, :abs_g0_nc:\var 671#endif 672 .endm 673 674#define BHB_MITIGATION_NONE 0 675#define BHB_MITIGATION_LOOP 1 676#define BHB_MITIGATION_FW 2 677#define BHB_MITIGATION_INSN 3 678 679 .macro tramp_ventry, vector_start, regsize, kpti, bhb 680 .align 7 6811: 682 .if \regsize == 64 683 msr tpidrro_el0, x30 // Restored in kernel_ventry 684 .endif 685 686 .if \bhb == BHB_MITIGATION_LOOP 687 /* 688 * This sequence must appear before the first indirect branch. i.e. the 689 * ret out of tramp_ventry. It appears here because x30 is free. 690 */ 691 __mitigate_spectre_bhb_loop x30 692 .endif // \bhb == BHB_MITIGATION_LOOP 693 694 .if \bhb == BHB_MITIGATION_INSN 695 clearbhb 696 isb 697 .endif // \bhb == BHB_MITIGATION_INSN 698 699 .if \kpti == 1 700 /* 701 * Defend against branch aliasing attacks by pushing a dummy 702 * entry onto the return stack and using a RET instruction to 703 * enter the full-fat kernel vectors. 704 */ 705 bl 2f 706 b . 7072: 708 tramp_map_kernel x30 709alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 710 tramp_data_read_var x30, vectors 711alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 712 prfm plil1strm, [x30, #(1b - \vector_start)] 713alternative_else_nop_endif 714 715 msr vbar_el1, x30 716 isb 717 .else 718 adr_l x30, vectors 719 .endif // \kpti == 1 720 721 .if \bhb == BHB_MITIGATION_FW 722 /* 723 * The firmware sequence must appear before the first indirect branch. 724 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 725 * mapped to save/restore the registers the SMC clobbers. 726 */ 727 __mitigate_spectre_bhb_fw 728 .endif // \bhb == BHB_MITIGATION_FW 729 730 add x30, x30, #(1b - \vector_start + 4) 731 ret 732.org 1b + 128 // Did we overflow the ventry slot? 733 .endm 734 735 .macro tramp_exit, regsize = 64 736 tramp_data_read_var x30, this_cpu_vector 737 get_this_cpu_offset x29 738 ldr x30, [x30, x29] 739 740 msr vbar_el1, x30 741 ldr lr, [sp, #S_LR] 742 tramp_unmap_kernel x29 743 .if \regsize == 64 744 mrs x29, far_el1 745 .endif 746 add sp, sp, #PT_REGS_SIZE // restore sp 747 eret 748 sb 749 .endm 750 751 .macro generate_tramp_vector, kpti, bhb 752.Lvector_start\@: 753 .space 0x400 754 755 .rept 4 756 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 757 .endr 758 .rept 4 759 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 760 .endr 761 .endm 762 763#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 764/* 765 * Exception vectors trampoline. 766 * The order must match __bp_harden_el1_vectors and the 767 * arm64_bp_harden_el1_vectors enum. 768 */ 769 .pushsection ".entry.tramp.text", "ax" 770 .align 11 771SYM_CODE_START_NOALIGN(tramp_vectors) 772#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 773 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 774 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 775 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 776#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 777 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 778SYM_CODE_END(tramp_vectors) 779 780SYM_CODE_START(tramp_exit_native) 781 tramp_exit 782SYM_CODE_END(tramp_exit_native) 783 784SYM_CODE_START(tramp_exit_compat) 785 tramp_exit 32 786SYM_CODE_END(tramp_exit_compat) 787 .popsection // .entry.tramp.text 788#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 789 790/* 791 * Exception vectors for spectre mitigations on entry from EL1 when 792 * kpti is not in use. 793 */ 794 .macro generate_el1_vector, bhb 795.Lvector_start\@: 796 kernel_ventry 1, t, 64, sync // Synchronous EL1t 797 kernel_ventry 1, t, 64, irq // IRQ EL1t 798 kernel_ventry 1, t, 64, fiq // FIQ EL1h 799 kernel_ventry 1, t, 64, error // Error EL1t 800 801 kernel_ventry 1, h, 64, sync // Synchronous EL1h 802 kernel_ventry 1, h, 64, irq // IRQ EL1h 803 kernel_ventry 1, h, 64, fiq // FIQ EL1h 804 kernel_ventry 1, h, 64, error // Error EL1h 805 806 .rept 4 807 tramp_ventry .Lvector_start\@, 64, 0, \bhb 808 .endr 809 .rept 4 810 tramp_ventry .Lvector_start\@, 32, 0, \bhb 811 .endr 812 .endm 813 814/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 815 .pushsection ".entry.text", "ax" 816 .align 11 817SYM_CODE_START(__bp_harden_el1_vectors) 818#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 819 generate_el1_vector bhb=BHB_MITIGATION_LOOP 820 generate_el1_vector bhb=BHB_MITIGATION_FW 821 generate_el1_vector bhb=BHB_MITIGATION_INSN 822#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 823SYM_CODE_END(__bp_harden_el1_vectors) 824 .popsection 825 826 827/* 828 * Register switch for AArch64. The callee-saved registers need to be saved 829 * and restored. On entry: 830 * x0 = previous task_struct (must be preserved across the switch) 831 * x1 = next task_struct 832 * Previous and next are guaranteed not to be the same. 833 * 834 */ 835SYM_FUNC_START(cpu_switch_to) 836 mov x10, #THREAD_CPU_CONTEXT 837 add x8, x0, x10 838 mov x9, sp 839 stp x19, x20, [x8], #16 // store callee-saved registers 840 stp x21, x22, [x8], #16 841 stp x23, x24, [x8], #16 842 stp x25, x26, [x8], #16 843 stp x27, x28, [x8], #16 844 stp x29, x9, [x8], #16 845 str lr, [x8] 846 add x8, x1, x10 847 ldp x19, x20, [x8], #16 // restore callee-saved registers 848 ldp x21, x22, [x8], #16 849 ldp x23, x24, [x8], #16 850 ldp x25, x26, [x8], #16 851 ldp x27, x28, [x8], #16 852 ldp x29, x9, [x8], #16 853 ldr lr, [x8] 854 mov sp, x9 855 msr sp_el0, x1 856 ptrauth_keys_install_kernel x1, x8, x9, x10 857 scs_save x0 858 scs_load_current 859 ret 860SYM_FUNC_END(cpu_switch_to) 861NOKPROBE(cpu_switch_to) 862 863/* 864 * This is how we return from a fork. 865 */ 866SYM_CODE_START(ret_from_fork) 867 bl schedule_tail 868 cbz x19, 1f // not a kernel thread 869 mov x0, x20 870 blr x19 8711: get_current_task tsk 872 mov x0, sp 873 bl asm_exit_to_user_mode 874 b ret_to_user 875SYM_CODE_END(ret_from_fork) 876NOKPROBE(ret_from_fork) 877 878/* 879 * void call_on_irq_stack(struct pt_regs *regs, 880 * void (*func)(struct pt_regs *)); 881 * 882 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 883 */ 884SYM_FUNC_START(call_on_irq_stack) 885#ifdef CONFIG_SHADOW_CALL_STACK 886 get_current_task x16 887 scs_save x16 888 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 889#endif 890 891 /* Create a frame record to save our LR and SP (implicit in FP) */ 892 stp x29, x30, [sp, #-16]! 893 mov x29, sp 894 895 ldr_this_cpu x16, irq_stack_ptr, x17 896 897 /* Move to the new stack and call the function there */ 898 add sp, x16, #IRQ_STACK_SIZE 899 blr x1 900 901 /* 902 * Restore the SP from the FP, and restore the FP and LR from the frame 903 * record. 904 */ 905 mov sp, x29 906 ldp x29, x30, [sp], #16 907 scs_load_current 908 ret 909SYM_FUNC_END(call_on_irq_stack) 910NOKPROBE(call_on_irq_stack) 911 912#ifdef CONFIG_ARM_SDE_INTERFACE 913 914#include <asm/sdei.h> 915#include <uapi/linux/arm_sdei.h> 916 917.macro sdei_handler_exit exit_mode 918 /* On success, this call never returns... */ 919 cmp \exit_mode, #SDEI_EXIT_SMC 920 b.ne 99f 921 smc #0 922 b . 92399: hvc #0 924 b . 925.endm 926 927#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 928/* 929 * The regular SDEI entry point may have been unmapped along with the rest of 930 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 931 * argument accessible. 932 * 933 * This clobbers x4, __sdei_handler() will restore this from firmware's 934 * copy. 935 */ 936.pushsection ".entry.tramp.text", "ax" 937SYM_CODE_START(__sdei_asm_entry_trampoline) 938 mrs x4, ttbr1_el1 939 tbz x4, #USER_ASID_BIT, 1f 940 941 tramp_map_kernel tmp=x4 942 isb 943 mov x4, xzr 944 945 /* 946 * Remember whether to unmap the kernel on exit. 947 */ 9481: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 949 tramp_data_read_var x4, __sdei_asm_handler 950 br x4 951SYM_CODE_END(__sdei_asm_entry_trampoline) 952NOKPROBE(__sdei_asm_entry_trampoline) 953 954/* 955 * Make the exit call and restore the original ttbr1_el1 956 * 957 * x0 & x1: setup for the exit API call 958 * x2: exit_mode 959 * x4: struct sdei_registered_event argument from registration time. 960 */ 961SYM_CODE_START(__sdei_asm_exit_trampoline) 962 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 963 cbnz x4, 1f 964 965 tramp_unmap_kernel tmp=x4 966 9671: sdei_handler_exit exit_mode=x2 968SYM_CODE_END(__sdei_asm_exit_trampoline) 969NOKPROBE(__sdei_asm_exit_trampoline) 970.popsection // .entry.tramp.text 971#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 972 973/* 974 * Software Delegated Exception entry point. 975 * 976 * x0: Event number 977 * x1: struct sdei_registered_event argument from registration time. 978 * x2: interrupted PC 979 * x3: interrupted PSTATE 980 * x4: maybe clobbered by the trampoline 981 * 982 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 983 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 984 * want them. 985 */ 986SYM_CODE_START(__sdei_asm_handler) 987 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 988 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 989 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 990 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 991 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 992 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 993 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 994 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 995 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 996 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 997 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 998 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 999 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1000 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1001 mov x4, sp 1002 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1003 1004 mov x19, x1 1005 1006#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1007 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1008#endif 1009 1010#ifdef CONFIG_VMAP_STACK 1011 /* 1012 * entry.S may have been using sp as a scratch register, find whether 1013 * this is a normal or critical event and switch to the appropriate 1014 * stack for this CPU. 1015 */ 1016 cbnz w4, 1f 1017 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1018 b 2f 10191: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10202: mov x6, #SDEI_STACK_SIZE 1021 add x5, x5, x6 1022 mov sp, x5 1023#endif 1024 1025#ifdef CONFIG_SHADOW_CALL_STACK 1026 /* Use a separate shadow call stack for normal and critical events */ 1027 cbnz w4, 3f 1028 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1029 b 4f 10303: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10314: 1032#endif 1033 1034 /* 1035 * We may have interrupted userspace, or a guest, or exit-from or 1036 * return-to either of these. We can't trust sp_el0, restore it. 1037 */ 1038 mrs x28, sp_el0 1039 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1040 msr sp_el0, x0 1041 1042 /* If we interrupted the kernel point to the previous stack/frame. */ 1043 and x0, x3, #0xc 1044 mrs x1, CurrentEL 1045 cmp x0, x1 1046 csel x29, x29, xzr, eq // fp, or zero 1047 csel x4, x2, xzr, eq // elr, or zero 1048 1049 stp x29, x4, [sp, #-16]! 1050 mov x29, sp 1051 1052 add x0, x19, #SDEI_EVENT_INTREGS 1053 mov x1, x19 1054 bl __sdei_handler 1055 1056 msr sp_el0, x28 1057 /* restore regs >x17 that we clobbered */ 1058 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1059 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1060 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1061 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1062 mov sp, x1 1063 1064 mov x1, x0 // address to complete_and_resume 1065 /* x0 = (x0 <= SDEI_EV_FAILED) ? 1066 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME 1067 */ 1068 cmp x0, #SDEI_EV_FAILED 1069 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1070 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1071 csel x0, x2, x3, ls 1072 1073 ldr_l x2, sdei_exit_mode 1074 1075alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1076 sdei_handler_exit exit_mode=x2 1077alternative_else_nop_endif 1078 1079#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1080 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3 1081 br x5 1082#endif 1083SYM_CODE_END(__sdei_asm_handler) 1084NOKPROBE(__sdei_asm_handler) 1085#endif /* CONFIG_ARM_SDE_INTERFACE */ 1086