1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/stacktrace/frame.h> 29#include <asm/thread_info.h> 30#include <asm/asm-uaccess.h> 31#include <asm/unistd.h> 32 33 .macro clear_gp_regs 34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 35 mov x\n, xzr 36 .endr 37 .endm 38 39 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 40 .align 7 41.Lventry_start\@: 42 .if \el == 0 43 /* 44 * This must be the first instruction of the EL0 vector entries. It is 45 * skipped by the trampoline vectors, to trigger the cleanup. 46 */ 47 b .Lskip_tramp_vectors_cleanup\@ 48 .if \regsize == 64 49 mrs x30, tpidrro_el0 50 msr tpidrro_el0, xzr 51 .else 52 mov x30, xzr 53 .endif 54.Lskip_tramp_vectors_cleanup\@: 55 .endif 56 57 sub sp, sp, #PT_REGS_SIZE 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99 b el\el\ht\()_\regsize\()_\label 100.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 101 .endm 102 103 .macro tramp_alias, dst, sym 104 .set .Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text 105 movz \dst, :abs_g2_s:.Lalias\@ 106 movk \dst, :abs_g1_nc:.Lalias\@ 107 movk \dst, :abs_g0_nc:.Lalias\@ 108 .endm 109 110 /* 111 * This macro corrupts x0-x3. It is the caller's duty to save/restore 112 * them if required. 113 */ 114 .macro apply_ssbd, state, tmp1, tmp2 115alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable 116 b .L__asm_ssbd_skip\@ // Patched to NOP 117alternative_cb_end 118 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 119 cbz \tmp2, .L__asm_ssbd_skip\@ 120 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 121 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 122 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 123 mov w1, #\state 124alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 125 nop // Patched to SMC/HVC #0 126alternative_cb_end 127.L__asm_ssbd_skip\@: 128 .endm 129 130 /* Check for MTE asynchronous tag check faults */ 131 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 132#ifdef CONFIG_ARM64_MTE 133 .arch_extension lse 134alternative_if_not ARM64_MTE 135 b 1f 136alternative_else_nop_endif 137 /* 138 * Asynchronous tag check faults are only possible in ASYNC (2) or 139 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 140 * set, so skip the check if it is unset. 141 */ 142 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 143 mrs_s \tmp, SYS_TFSRE0_EL1 144 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 145 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 146 mov \tmp, #_TIF_MTE_ASYNC_FAULT 147 add \ti_flags, tsk, #TSK_TI_FLAGS 148 stset \tmp, [\ti_flags] 1491: 150#endif 151 .endm 152 153 /* Clear the MTE asynchronous tag check faults */ 154 .macro clear_mte_async_tcf thread_sctlr 155#ifdef CONFIG_ARM64_MTE 156alternative_if ARM64_MTE 157 /* See comment in check_mte_async_tcf above. */ 158 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 159 dsb ish 160 msr_s SYS_TFSRE0_EL1, xzr 1611: 162alternative_else_nop_endif 163#endif 164 .endm 165 166 .macro mte_set_gcr, mte_ctrl, tmp 167#ifdef CONFIG_ARM64_MTE 168 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 169 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 170 msr_s SYS_GCR_EL1, \tmp 171#endif 172 .endm 173 174 .macro mte_set_kernel_gcr, tmp, tmp2 175#ifdef CONFIG_KASAN_HW_TAGS 176alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 177 b 1f 178alternative_cb_end 179 mov \tmp, KERNEL_GCR_EL1 180 msr_s SYS_GCR_EL1, \tmp 1811: 182#endif 183 .endm 184 185 .macro mte_set_user_gcr, tsk, tmp, tmp2 186#ifdef CONFIG_KASAN_HW_TAGS 187alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 188 b 1f 189alternative_cb_end 190 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 191 192 mte_set_gcr \tmp, \tmp2 1931: 194#endif 195 .endm 196 197 .macro kernel_entry, el, regsize = 64 198 .if \el == 0 199 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT 200 .endif 201 .if \regsize == 32 202 mov w0, w0 // zero upper 32 bits of x0 203 .endif 204 stp x0, x1, [sp, #16 * 0] 205 stp x2, x3, [sp, #16 * 1] 206 stp x4, x5, [sp, #16 * 2] 207 stp x6, x7, [sp, #16 * 3] 208 stp x8, x9, [sp, #16 * 4] 209 stp x10, x11, [sp, #16 * 5] 210 stp x12, x13, [sp, #16 * 6] 211 stp x14, x15, [sp, #16 * 7] 212 stp x16, x17, [sp, #16 * 8] 213 stp x18, x19, [sp, #16 * 9] 214 stp x20, x21, [sp, #16 * 10] 215 stp x22, x23, [sp, #16 * 11] 216 stp x24, x25, [sp, #16 * 12] 217 stp x26, x27, [sp, #16 * 13] 218 stp x28, x29, [sp, #16 * 14] 219 220 .if \el == 0 221 clear_gp_regs 222 mrs x21, sp_el0 223 ldr_this_cpu tsk, __entry_task, x20 224 msr sp_el0, tsk 225 226 /* 227 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 228 * when scheduling. 229 */ 230 ldr x19, [tsk, #TSK_TI_FLAGS] 231 disable_step_tsk x19, x20 232 233 /* Check for asynchronous tag check faults in user space */ 234 ldr x0, [tsk, THREAD_SCTLR_USER] 235 check_mte_async_tcf x22, x23, x0 236 237#ifdef CONFIG_ARM64_PTR_AUTH 238alternative_if ARM64_HAS_ADDRESS_AUTH 239 /* 240 * Enable IA for in-kernel PAC if the task had it disabled. Although 241 * this could be implemented with an unconditional MRS which would avoid 242 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 243 * 244 * Install the kernel IA key only if IA was enabled in the task. If IA 245 * was disabled on kernel exit then we would have left the kernel IA 246 * installed so there is no need to install it again. 247 */ 248 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 249 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 250 b 2f 2511: 252 mrs x0, sctlr_el1 253 orr x0, x0, SCTLR_ELx_ENIA 254 msr sctlr_el1, x0 2552: 256alternative_else_nop_endif 257#endif 258 259 apply_ssbd 1, x22, x23 260 261 mte_set_kernel_gcr x22, x23 262 263 /* 264 * Any non-self-synchronizing system register updates required for 265 * kernel entry should be placed before this point. 266 */ 267alternative_if ARM64_MTE 268 isb 269 b 1f 270alternative_else_nop_endif 271alternative_if ARM64_HAS_ADDRESS_AUTH 272 isb 273alternative_else_nop_endif 2741: 275 276 scs_load_current_base 277 .else 278 add x21, sp, #PT_REGS_SIZE 279 get_current_task tsk 280 .endif /* \el == 0 */ 281 mrs x22, elr_el1 282 mrs x23, spsr_el1 283 stp lr, x21, [sp, #S_LR] 284 285 /* 286 * Create a metadata frame record. The unwinder will use this to 287 * identify and unwind exception boundaries. 288 */ 289 stp xzr, xzr, [sp, #S_STACKFRAME] 290 .if \el == 0 291 mov x0, #FRAME_META_TYPE_FINAL 292 .else 293 mov x0, #FRAME_META_TYPE_PT_REGS 294 .endif 295 str x0, [sp, #S_STACKFRAME_TYPE] 296 add x29, sp, #S_STACKFRAME 297 298#ifdef CONFIG_ARM64_SW_TTBR0_PAN 299alternative_if_not ARM64_HAS_PAN 300 bl __swpan_entry_el\el 301alternative_else_nop_endif 302#endif 303 304 stp x22, x23, [sp, #S_PC] 305 306 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 307 .if \el == 0 308 mov w21, #NO_SYSCALL 309 str w21, [sp, #S_SYSCALLNO] 310 .endif 311 312#ifdef CONFIG_ARM64_PSEUDO_NMI 313alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 314 b .Lskip_pmr_save\@ 315alternative_else_nop_endif 316 317 mrs_s x20, SYS_ICC_PMR_EL1 318 str w20, [sp, #S_PMR] 319 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 320 msr_s SYS_ICC_PMR_EL1, x20 321 322.Lskip_pmr_save\@: 323#endif 324 325 /* 326 * Registers that may be useful after this macro is invoked: 327 * 328 * x20 - ICC_PMR_EL1 329 * x21 - aborted SP 330 * x22 - aborted PC 331 * x23 - aborted PSTATE 332 */ 333 .endm 334 335 .macro kernel_exit, el 336#ifdef CONFIG_ARM64_PSEUDO_NMI 337alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 338 b .Lskip_pmr_restore\@ 339alternative_else_nop_endif 340 341 ldr w20, [sp, #S_PMR] 342 msr_s SYS_ICC_PMR_EL1, x20 343 344 /* Ensure priority change is seen by redistributor */ 345alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC 346 dsb sy 347alternative_else_nop_endif 348 349.Lskip_pmr_restore\@: 350#endif 351 352 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 353 354#ifdef CONFIG_ARM64_SW_TTBR0_PAN 355alternative_if_not ARM64_HAS_PAN 356 bl __swpan_exit_el\el 357alternative_else_nop_endif 358#endif 359 360 .if \el == 0 361 ldr x23, [sp, #S_SP] // load return stack pointer 362 msr sp_el0, x23 363 tst x22, #PSR_MODE32_BIT // native task? 364 b.eq 3f 365 366#ifdef CONFIG_ARM64_ERRATUM_845719 367alternative_if ARM64_WORKAROUND_845719 368#ifdef CONFIG_PID_IN_CONTEXTIDR 369 mrs x29, contextidr_el1 370 msr contextidr_el1, x29 371#else 372 msr contextidr_el1, xzr 373#endif 374alternative_else_nop_endif 375#endif 3763: 377 /* Ignore asynchronous tag check faults in the uaccess routines */ 378 ldr x0, [tsk, THREAD_SCTLR_USER] 379 clear_mte_async_tcf x0 380 381#ifdef CONFIG_ARM64_PTR_AUTH 382alternative_if ARM64_HAS_ADDRESS_AUTH 383 /* 384 * IA was enabled for in-kernel PAC. Disable it now if needed, or 385 * alternatively install the user's IA. All other per-task keys and 386 * SCTLR bits were updated on task switch. 387 * 388 * No kernel C function calls after this. 389 */ 390 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 391 __ptrauth_keys_install_user tsk, x0, x1, x2 392 b 2f 3931: 394 mrs x0, sctlr_el1 395 bic x0, x0, SCTLR_ELx_ENIA 396 msr sctlr_el1, x0 3972: 398alternative_else_nop_endif 399#endif 400 401 mte_set_user_gcr tsk, x0, x1 402 403 apply_ssbd 0, x0, x1 404 .endif 405 406 msr elr_el1, x21 // set up the return data 407 msr spsr_el1, x22 408 ldp x0, x1, [sp, #16 * 0] 409 ldp x2, x3, [sp, #16 * 1] 410 ldp x4, x5, [sp, #16 * 2] 411 ldp x6, x7, [sp, #16 * 3] 412 ldp x8, x9, [sp, #16 * 4] 413 ldp x10, x11, [sp, #16 * 5] 414 ldp x12, x13, [sp, #16 * 6] 415 ldp x14, x15, [sp, #16 * 7] 416 ldp x16, x17, [sp, #16 * 8] 417 ldp x18, x19, [sp, #16 * 9] 418 ldp x20, x21, [sp, #16 * 10] 419 ldp x22, x23, [sp, #16 * 11] 420 ldp x24, x25, [sp, #16 * 12] 421 ldp x26, x27, [sp, #16 * 13] 422 ldp x28, x29, [sp, #16 * 14] 423 424 .if \el == 0 425#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 426 alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 427 428 msr far_el1, x29 429 430 ldr_this_cpu x30, this_cpu_vector, x29 431 tramp_alias x29, tramp_exit 432 msr vbar_el1, x30 // install vector table 433 ldr lr, [sp, #S_LR] // restore x30 434 add sp, sp, #PT_REGS_SIZE // restore sp 435 br x29 436 437.L_skip_tramp_exit_\@: 438#endif 439 .endif 440 441 ldr lr, [sp, #S_LR] 442 add sp, sp, #PT_REGS_SIZE // restore sp 443 444 .if \el == 0 445 /* This must be after the last explicit memory access */ 446alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 447 tlbi vale1, xzr 448 dsb nsh 449alternative_else_nop_endif 450 .else 451 /* Ensure any device/NC reads complete */ 452 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 453 .endif 454 455 eret 456 sb 457 .endm 458 459#ifdef CONFIG_ARM64_SW_TTBR0_PAN 460 /* 461 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 462 * EL0, there is no need to check the state of TTBR0_EL1 since 463 * accesses are always enabled. 464 * Note that the meaning of this bit differs from the ARMv8.1 PAN 465 * feature as all TTBR0_EL1 accesses are disabled, not just those to 466 * user mappings. 467 */ 468SYM_CODE_START_LOCAL(__swpan_entry_el1) 469 mrs x21, ttbr0_el1 470 tst x21, #TTBRx_EL1_ASID_MASK // Check for the reserved ASID 471 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 472 b.eq 1f // TTBR0 access already disabled 473 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 474SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 475 __uaccess_ttbr0_disable x21 4761: ret 477SYM_CODE_END(__swpan_entry_el1) 478 479 /* 480 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 481 * PAN bit checking. 482 */ 483SYM_CODE_START_LOCAL(__swpan_exit_el1) 484 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 485 __uaccess_ttbr0_enable x0, x1 4861: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 487 ret 488SYM_CODE_END(__swpan_exit_el1) 489 490SYM_CODE_START_LOCAL(__swpan_exit_el0) 491 __uaccess_ttbr0_enable x0, x1 492 /* 493 * Enable errata workarounds only if returning to user. The only 494 * workaround currently required for TTBR0_EL1 changes are for the 495 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 496 * corruption). 497 */ 498 b post_ttbr_update_workaround 499SYM_CODE_END(__swpan_exit_el0) 500#endif 501 502/* GPRs used by entry code */ 503tsk .req x28 // current thread_info 504 505 .text 506 507/* 508 * Exception vectors. 509 */ 510 .pushsection ".entry.text", "ax" 511 512 .align 11 513SYM_CODE_START(vectors) 514 kernel_ventry 1, t, 64, sync // Synchronous EL1t 515 kernel_ventry 1, t, 64, irq // IRQ EL1t 516 kernel_ventry 1, t, 64, fiq // FIQ EL1t 517 kernel_ventry 1, t, 64, error // Error EL1t 518 519 kernel_ventry 1, h, 64, sync // Synchronous EL1h 520 kernel_ventry 1, h, 64, irq // IRQ EL1h 521 kernel_ventry 1, h, 64, fiq // FIQ EL1h 522 kernel_ventry 1, h, 64, error // Error EL1h 523 524 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 525 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 526 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 527 kernel_ventry 0, t, 64, error // Error 64-bit EL0 528 529 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 530 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 531 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 532 kernel_ventry 0, t, 32, error // Error 32-bit EL0 533SYM_CODE_END(vectors) 534 535SYM_CODE_START_LOCAL(__bad_stack) 536 /* 537 * We detected an overflow in kernel_ventry, which switched to the 538 * overflow stack. Stash the exception regs, and head to our overflow 539 * handler. 540 */ 541 542 /* Restore the original x0 value */ 543 mrs x0, tpidrro_el0 544 545 /* 546 * Store the original GPRs to the new stack. The orginal SP (minus 547 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 548 */ 549 sub sp, sp, #PT_REGS_SIZE 550 kernel_entry 1 551 mrs x0, tpidr_el0 552 add x0, x0, #PT_REGS_SIZE 553 str x0, [sp, #S_SP] 554 555 /* Stash the regs for handle_bad_stack */ 556 mov x0, sp 557 558 /* Time to die */ 559 bl handle_bad_stack 560 ASM_BUG() 561SYM_CODE_END(__bad_stack) 562 563 564 .macro entry_handler el:req, ht:req, regsize:req, label:req 565SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 566 kernel_entry \el, \regsize 567 mov x0, sp 568 bl el\el\ht\()_\regsize\()_\label\()_handler 569 .if \el == 0 570 b ret_to_user 571 .else 572 b ret_to_kernel 573 .endif 574SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 575 .endm 576 577/* 578 * Early exception handlers 579 */ 580 entry_handler 1, t, 64, sync 581 entry_handler 1, t, 64, irq 582 entry_handler 1, t, 64, fiq 583 entry_handler 1, t, 64, error 584 585 entry_handler 1, h, 64, sync 586 entry_handler 1, h, 64, irq 587 entry_handler 1, h, 64, fiq 588 entry_handler 1, h, 64, error 589 590 entry_handler 0, t, 64, sync 591 entry_handler 0, t, 64, irq 592 entry_handler 0, t, 64, fiq 593 entry_handler 0, t, 64, error 594 595 entry_handler 0, t, 32, sync 596 entry_handler 0, t, 32, irq 597 entry_handler 0, t, 32, fiq 598 entry_handler 0, t, 32, error 599 600SYM_CODE_START_LOCAL(ret_to_kernel) 601 kernel_exit 1 602SYM_CODE_END(ret_to_kernel) 603 604SYM_CODE_START_LOCAL(ret_to_user) 605 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 606 enable_step_tsk x19, x2 607#ifdef CONFIG_KSTACK_ERASE 608 bl stackleak_erase_on_task_stack 609#endif 610 kernel_exit 0 611SYM_CODE_END(ret_to_user) 612 613 .popsection // .entry.text 614 615 // Move from tramp_pg_dir to swapper_pg_dir 616 .macro tramp_map_kernel, tmp 617 mrs \tmp, ttbr1_el1 618 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 619 bic \tmp, \tmp, #USER_ASID_FLAG 620 msr ttbr1_el1, \tmp 621#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 622alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 623 /* ASID already in \tmp[63:48] */ 624 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 625 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 626 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 627 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 628 isb 629 tlbi vae1, \tmp 630 dsb nsh 631alternative_else_nop_endif 632#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 633 .endm 634 635 // Move from swapper_pg_dir to tramp_pg_dir 636 .macro tramp_unmap_kernel, tmp 637 mrs \tmp, ttbr1_el1 638 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 639 orr \tmp, \tmp, #USER_ASID_FLAG 640 msr ttbr1_el1, \tmp 641 /* 642 * We avoid running the post_ttbr_update_workaround here because 643 * it's only needed by Cavium ThunderX, which requires KPTI to be 644 * disabled. 645 */ 646 .endm 647 648 .macro tramp_data_read_var dst, var 649#ifdef CONFIG_RELOCATABLE 650 ldr \dst, .L__tramp_data_\var 651 .ifndef .L__tramp_data_\var 652 .pushsection ".entry.tramp.rodata", "a", %progbits 653 .align 3 654.L__tramp_data_\var: 655 .quad \var 656 .popsection 657 .endif 658#else 659 /* 660 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a 661 * compile time constant (and hence not secret and not worth hiding). 662 * 663 * As statically allocated kernel code and data always live in the top 664 * 47 bits of the address space we can sign-extend bit 47 and avoid an 665 * instruction to load the upper 16 bits (which must be 0xFFFF). 666 */ 667 movz \dst, :abs_g2_s:\var 668 movk \dst, :abs_g1_nc:\var 669 movk \dst, :abs_g0_nc:\var 670#endif 671 .endm 672 673#define BHB_MITIGATION_NONE 0 674#define BHB_MITIGATION_LOOP 1 675#define BHB_MITIGATION_FW 2 676#define BHB_MITIGATION_INSN 3 677 678 .macro tramp_ventry, vector_start, regsize, kpti, bhb 679 .align 7 6801: 681 .if \regsize == 64 682 msr tpidrro_el0, x30 // Restored in kernel_ventry 683 .endif 684 685 .if \bhb == BHB_MITIGATION_LOOP 686 /* 687 * This sequence must appear before the first indirect branch. i.e. the 688 * ret out of tramp_ventry. It appears here because x30 is free. 689 */ 690 __mitigate_spectre_bhb_loop x30 691 .endif // \bhb == BHB_MITIGATION_LOOP 692 693 .if \bhb == BHB_MITIGATION_INSN 694 clearbhb 695 isb 696 .endif // \bhb == BHB_MITIGATION_INSN 697 698 .if \kpti == 1 699 /* 700 * Defend against branch aliasing attacks by pushing a dummy 701 * entry onto the return stack and using a RET instruction to 702 * enter the full-fat kernel vectors. 703 */ 704 bl 2f 705 b . 7062: 707 tramp_map_kernel x30 708alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 709 tramp_data_read_var x30, vectors 710alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 711 prfm plil1strm, [x30, #(1b - \vector_start)] 712alternative_else_nop_endif 713 714 msr vbar_el1, x30 715 isb 716 .else 717 adr_l x30, vectors 718 .endif // \kpti == 1 719 720 .if \bhb == BHB_MITIGATION_FW 721 /* 722 * The firmware sequence must appear before the first indirect branch. 723 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 724 * mapped to save/restore the registers the SMC clobbers. 725 */ 726 __mitigate_spectre_bhb_fw 727 .endif // \bhb == BHB_MITIGATION_FW 728 729 add x30, x30, #(1b - \vector_start + 4) 730 ret 731.org 1b + 128 // Did we overflow the ventry slot? 732 .endm 733 734 .macro generate_tramp_vector, kpti, bhb 735.Lvector_start\@: 736 .space 0x400 737 738 .rept 4 739 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 740 .endr 741 .rept 4 742 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 743 .endr 744 .endm 745 746#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 747/* 748 * Exception vectors trampoline. 749 * The order must match __bp_harden_el1_vectors and the 750 * arm64_bp_harden_el1_vectors enum. 751 */ 752 .pushsection ".entry.tramp.text", "ax" 753 .align 11 754SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) 755#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 756 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 757 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 758 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 759#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 760 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 761SYM_CODE_END(tramp_vectors) 762 763SYM_CODE_START_LOCAL(tramp_exit) 764 tramp_unmap_kernel x29 765 mrs x29, far_el1 // restore x29 766 eret 767 sb 768SYM_CODE_END(tramp_exit) 769 .popsection // .entry.tramp.text 770#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 771 772/* 773 * Exception vectors for spectre mitigations on entry from EL1 when 774 * kpti is not in use. 775 */ 776 .macro generate_el1_vector, bhb 777.Lvector_start\@: 778 kernel_ventry 1, t, 64, sync // Synchronous EL1t 779 kernel_ventry 1, t, 64, irq // IRQ EL1t 780 kernel_ventry 1, t, 64, fiq // FIQ EL1h 781 kernel_ventry 1, t, 64, error // Error EL1t 782 783 kernel_ventry 1, h, 64, sync // Synchronous EL1h 784 kernel_ventry 1, h, 64, irq // IRQ EL1h 785 kernel_ventry 1, h, 64, fiq // FIQ EL1h 786 kernel_ventry 1, h, 64, error // Error EL1h 787 788 .rept 4 789 tramp_ventry .Lvector_start\@, 64, 0, \bhb 790 .endr 791 .rept 4 792 tramp_ventry .Lvector_start\@, 32, 0, \bhb 793 .endr 794 .endm 795 796/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 797 .pushsection ".entry.text", "ax" 798 .align 11 799SYM_CODE_START(__bp_harden_el1_vectors) 800#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 801 generate_el1_vector bhb=BHB_MITIGATION_LOOP 802 generate_el1_vector bhb=BHB_MITIGATION_FW 803 generate_el1_vector bhb=BHB_MITIGATION_INSN 804#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 805SYM_CODE_END(__bp_harden_el1_vectors) 806 .popsection 807 808 809/* 810 * Register switch for AArch64. The callee-saved registers need to be saved 811 * and restored. On entry: 812 * x0 = previous task_struct (must be preserved across the switch) 813 * x1 = next task_struct 814 * Previous and next are guaranteed not to be the same. 815 * 816 */ 817SYM_FUNC_START(cpu_switch_to) 818 save_and_disable_daif x11 819 mov x10, #THREAD_CPU_CONTEXT 820 add x8, x0, x10 821 mov x9, sp 822 stp x19, x20, [x8], #16 // store callee-saved registers 823 stp x21, x22, [x8], #16 824 stp x23, x24, [x8], #16 825 stp x25, x26, [x8], #16 826 stp x27, x28, [x8], #16 827 stp x29, x9, [x8], #16 828 str lr, [x8] 829 add x8, x1, x10 830 ldp x19, x20, [x8], #16 // restore callee-saved registers 831 ldp x21, x22, [x8], #16 832 ldp x23, x24, [x8], #16 833 ldp x25, x26, [x8], #16 834 ldp x27, x28, [x8], #16 835 ldp x29, x9, [x8], #16 836 ldr lr, [x8] 837 mov sp, x9 838 msr sp_el0, x1 839 ptrauth_keys_install_kernel x1, x8, x9, x10 840 scs_save x0 841 scs_load_current 842 restore_irq x11 843 ret 844SYM_FUNC_END(cpu_switch_to) 845NOKPROBE(cpu_switch_to) 846 847/* 848 * This is how we return from a fork. 849 */ 850SYM_CODE_START(ret_from_fork) 851 bl schedule_tail 852 cbz x19, 1f // not a kernel thread 853 mov x0, x20 854 blr x19 8551: get_current_task tsk 856 mov x0, sp 857 bl asm_exit_to_user_mode 858 b ret_to_user 859SYM_CODE_END(ret_from_fork) 860NOKPROBE(ret_from_fork) 861 862/* 863 * void call_on_irq_stack(struct pt_regs *regs, 864 * void (*func)(struct pt_regs *)); 865 * 866 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 867 */ 868SYM_FUNC_START(call_on_irq_stack) 869 save_and_disable_daif x9 870#ifdef CONFIG_SHADOW_CALL_STACK 871 get_current_task x16 872 scs_save x16 873 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 874#endif 875 876 /* Create a frame record to save our LR and SP (implicit in FP) */ 877 stp x29, x30, [sp, #-16]! 878 mov x29, sp 879 880 ldr_this_cpu x16, irq_stack_ptr, x17 881 882 /* Move to the new stack and call the function there */ 883 add sp, x16, #IRQ_STACK_SIZE 884 restore_irq x9 885 blr x1 886 887 save_and_disable_daif x9 888 /* 889 * Restore the SP from the FP, and restore the FP and LR from the frame 890 * record. 891 */ 892 mov sp, x29 893 ldp x29, x30, [sp], #16 894 scs_load_current 895 restore_irq x9 896 ret 897SYM_FUNC_END(call_on_irq_stack) 898NOKPROBE(call_on_irq_stack) 899 900#ifdef CONFIG_ARM_SDE_INTERFACE 901 902#include <asm/sdei.h> 903#include <uapi/linux/arm_sdei.h> 904 905.macro sdei_handler_exit exit_mode 906 /* On success, this call never returns... */ 907 cmp \exit_mode, #SDEI_EXIT_SMC 908 b.ne 99f 909 smc #0 910 b . 91199: hvc #0 912 b . 913.endm 914 915#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 916/* 917 * The regular SDEI entry point may have been unmapped along with the rest of 918 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 919 * argument accessible. 920 * 921 * This clobbers x4, __sdei_handler() will restore this from firmware's 922 * copy. 923 */ 924.pushsection ".entry.tramp.text", "ax" 925SYM_CODE_START(__sdei_asm_entry_trampoline) 926 mrs x4, ttbr1_el1 927 tbz x4, #USER_ASID_BIT, 1f 928 929 tramp_map_kernel tmp=x4 930 isb 931 mov x4, xzr 932 933 /* 934 * Remember whether to unmap the kernel on exit. 935 */ 9361: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 937 tramp_data_read_var x4, __sdei_asm_handler 938 br x4 939SYM_CODE_END(__sdei_asm_entry_trampoline) 940NOKPROBE(__sdei_asm_entry_trampoline) 941 942/* 943 * Make the exit call and restore the original ttbr1_el1 944 * 945 * x0 & x1: setup for the exit API call 946 * x2: exit_mode 947 * x4: struct sdei_registered_event argument from registration time. 948 */ 949SYM_CODE_START(__sdei_asm_exit_trampoline) 950 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 951 cbnz x4, 1f 952 953 tramp_unmap_kernel tmp=x4 954 9551: sdei_handler_exit exit_mode=x2 956SYM_CODE_END(__sdei_asm_exit_trampoline) 957NOKPROBE(__sdei_asm_exit_trampoline) 958.popsection // .entry.tramp.text 959#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 960 961/* 962 * Software Delegated Exception entry point. 963 * 964 * x0: Event number 965 * x1: struct sdei_registered_event argument from registration time. 966 * x2: interrupted PC 967 * x3: interrupted PSTATE 968 * x4: maybe clobbered by the trampoline 969 * 970 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 971 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 972 * want them. 973 */ 974SYM_CODE_START(__sdei_asm_handler) 975 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 976 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 977 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 978 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 979 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 980 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 981 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 982 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 983 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 984 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 985 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 986 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 987 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 988 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 989 mov x4, sp 990 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 991 992 mov x19, x1 993 994 /* Store the registered-event for crash_smp_send_stop() */ 995 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 996 cbnz w4, 1f 997 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 998 b 2f 9991: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10002: str x19, [x5] 1001 1002 /* 1003 * entry.S may have been using sp as a scratch register, find whether 1004 * this is a normal or critical event and switch to the appropriate 1005 * stack for this CPU. 1006 */ 1007 cbnz w4, 1f 1008 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1009 b 2f 10101: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10112: mov x6, #SDEI_STACK_SIZE 1012 add x5, x5, x6 1013 mov sp, x5 1014 1015#ifdef CONFIG_SHADOW_CALL_STACK 1016 /* Use a separate shadow call stack for normal and critical events */ 1017 cbnz w4, 3f 1018 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1019 b 4f 10203: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10214: 1022#endif 1023 1024 /* 1025 * We may have interrupted userspace, or a guest, or exit-from or 1026 * return-to either of these. We can't trust sp_el0, restore it. 1027 */ 1028 mrs x28, sp_el0 1029 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1030 msr sp_el0, x0 1031 1032 /* If we interrupted the kernel point to the previous stack/frame. */ 1033 and x0, x3, #0xc 1034 mrs x1, CurrentEL 1035 cmp x0, x1 1036 csel x29, x29, xzr, eq // fp, or zero 1037 csel x4, x2, xzr, eq // elr, or zero 1038 1039 stp x29, x4, [sp, #-16]! 1040 mov x29, sp 1041 1042 add x0, x19, #SDEI_EVENT_INTREGS 1043 mov x1, x19 1044 bl __sdei_handler 1045 1046 msr sp_el0, x28 1047 /* restore regs >x17 that we clobbered */ 1048 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1049 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1050 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1051 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1052 mov sp, x1 1053 1054 mov x1, x0 // address to complete_and_resume 1055 /* x0 = (x0 <= SDEI_EV_FAILED) ? 1056 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME 1057 */ 1058 cmp x0, #SDEI_EV_FAILED 1059 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1060 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1061 csel x0, x2, x3, ls 1062 1063 ldr_l x2, sdei_exit_mode 1064 1065 /* Clear the registered-event seen by crash_smp_send_stop() */ 1066 ldrb w3, [x4, #SDEI_EVENT_PRIORITY] 1067 cbnz w3, 1f 1068 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1069 b 2f 10701: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10712: str xzr, [x5] 1072 1073alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1074 sdei_handler_exit exit_mode=x2 1075alternative_else_nop_endif 1076 1077#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1078 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1079 br x5 1080#endif 1081SYM_CODE_END(__sdei_asm_handler) 1082NOKPROBE(__sdei_asm_handler) 1083 1084SYM_CODE_START(__sdei_handler_abort) 1085 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1086 adr x1, 1f 1087 ldr_l x2, sdei_exit_mode 1088 sdei_handler_exit exit_mode=x2 1089 // exit the handler and jump to the next instruction. 1090 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx. 10911: ret 1092SYM_CODE_END(__sdei_handler_abort) 1093NOKPROBE(__sdei_handler_abort) 1094#endif /* CONFIG_ARM_SDE_INTERFACE */ 1095