1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/thread_info.h> 29#include <asm/asm-uaccess.h> 30#include <asm/unistd.h> 31 32/* 33 * Context tracking subsystem. Used to instrument transitions 34 * between user and kernel mode. 35 */ 36 .macro ct_user_exit_irqoff 37#ifdef CONFIG_CONTEXT_TRACKING 38 bl enter_from_user_mode 39#endif 40 .endm 41 42 .macro ct_user_enter 43#ifdef CONFIG_CONTEXT_TRACKING 44 bl context_tracking_user_enter 45#endif 46 .endm 47 48 .macro clear_gp_regs 49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 50 mov x\n, xzr 51 .endr 52 .endm 53 54/* 55 * Bad Abort numbers 56 *----------------- 57 */ 58#define BAD_SYNC 0 59#define BAD_IRQ 1 60#define BAD_FIQ 2 61#define BAD_ERROR 3 62 63 .macro kernel_ventry, el, label, regsize = 64 64 .align 7 65#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 66 .if \el == 0 67alternative_if ARM64_UNMAP_KERNEL_AT_EL0 68 .if \regsize == 64 69 mrs x30, tpidrro_el0 70 msr tpidrro_el0, xzr 71 .else 72 mov x30, xzr 73 .endif 74alternative_else_nop_endif 75 .endif 76#endif 77 78 sub sp, sp, #S_FRAME_SIZE 79#ifdef CONFIG_VMAP_STACK 80 /* 81 * Test whether the SP has overflowed, without corrupting a GPR. 82 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 83 * should always be zero. 84 */ 85 add sp, sp, x0 // sp' = sp + x0 86 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 87 tbnz x0, #THREAD_SHIFT, 0f 88 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 89 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 90 b el\()\el\()_\label 91 920: 93 /* 94 * Either we've just detected an overflow, or we've taken an exception 95 * while on the overflow stack. Either way, we won't return to 96 * userspace, and can clobber EL0 registers to free up GPRs. 97 */ 98 99 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */ 100 msr tpidr_el0, x0 101 102 /* Recover the original x0 value and stash it in tpidrro_el0 */ 103 sub x0, sp, x0 104 msr tpidrro_el0, x0 105 106 /* Switch to the overflow stack */ 107 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 108 109 /* 110 * Check whether we were already on the overflow stack. This may happen 111 * after panic() re-enables interrupts. 112 */ 113 mrs x0, tpidr_el0 // sp of interrupted context 114 sub x0, sp, x0 // delta with top of overflow stack 115 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 116 b.ne __bad_stack // no? -> bad stack pointer 117 118 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 119 sub sp, sp, x0 120 mrs x0, tpidrro_el0 121#endif 122 b el\()\el\()_\label 123 .endm 124 125 .macro tramp_alias, dst, sym 126 mov_q \dst, TRAMP_VALIAS 127 add \dst, \dst, #(\sym - .entry.tramp.text) 128 .endm 129 130 // This macro corrupts x0-x3. It is the caller's duty 131 // to save/restore them if required. 132 .macro apply_ssbd, state, tmp1, tmp2 133#ifdef CONFIG_ARM64_SSBD 134alternative_cb arm64_enable_wa2_handling 135 b .L__asm_ssbd_skip\@ 136alternative_cb_end 137 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 138 cbz \tmp2, .L__asm_ssbd_skip\@ 139 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 140 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 141 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 142 mov w1, #\state 143alternative_cb arm64_update_smccc_conduit 144 nop // Patched to SMC/HVC #0 145alternative_cb_end 146.L__asm_ssbd_skip\@: 147#endif 148 .endm 149 150 .macro kernel_entry, el, regsize = 64 151 .if \regsize == 32 152 mov w0, w0 // zero upper 32 bits of x0 153 .endif 154 stp x0, x1, [sp, #16 * 0] 155 stp x2, x3, [sp, #16 * 1] 156 stp x4, x5, [sp, #16 * 2] 157 stp x6, x7, [sp, #16 * 3] 158 stp x8, x9, [sp, #16 * 4] 159 stp x10, x11, [sp, #16 * 5] 160 stp x12, x13, [sp, #16 * 6] 161 stp x14, x15, [sp, #16 * 7] 162 stp x16, x17, [sp, #16 * 8] 163 stp x18, x19, [sp, #16 * 9] 164 stp x20, x21, [sp, #16 * 10] 165 stp x22, x23, [sp, #16 * 11] 166 stp x24, x25, [sp, #16 * 12] 167 stp x26, x27, [sp, #16 * 13] 168 stp x28, x29, [sp, #16 * 14] 169 170 .if \el == 0 171 clear_gp_regs 172 mrs x21, sp_el0 173 ldr_this_cpu tsk, __entry_task, x20 174 msr sp_el0, tsk 175 176 // Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 177 // when scheduling. 178 ldr x19, [tsk, #TSK_TI_FLAGS] 179 disable_step_tsk x19, x20 180 181 apply_ssbd 1, x22, x23 182 183 ptrauth_keys_install_kernel tsk, x20, x22, x23 184 185 scs_load tsk, x20 186 .else 187 add x21, sp, #S_FRAME_SIZE 188 get_current_task tsk 189 /* Save the task's original addr_limit and set USER_DS */ 190 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT] 191 str x20, [sp, #S_ORIG_ADDR_LIMIT] 192 mov x20, #USER_DS 193 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 194 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */ 195 .endif /* \el == 0 */ 196 mrs x22, elr_el1 197 mrs x23, spsr_el1 198 stp lr, x21, [sp, #S_LR] 199 200 /* 201 * In order to be able to dump the contents of struct pt_regs at the 202 * time the exception was taken (in case we attempt to walk the call 203 * stack later), chain it together with the stack frames. 204 */ 205 .if \el == 0 206 stp xzr, xzr, [sp, #S_STACKFRAME] 207 .else 208 stp x29, x22, [sp, #S_STACKFRAME] 209 .endif 210 add x29, sp, #S_STACKFRAME 211 212#ifdef CONFIG_ARM64_SW_TTBR0_PAN 213alternative_if_not ARM64_HAS_PAN 214 bl __swpan_entry_el\el 215alternative_else_nop_endif 216#endif 217 218 stp x22, x23, [sp, #S_PC] 219 220 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 221 .if \el == 0 222 mov w21, #NO_SYSCALL 223 str w21, [sp, #S_SYSCALLNO] 224 .endif 225 226 /* Save pmr */ 227alternative_if ARM64_HAS_IRQ_PRIO_MASKING 228 mrs_s x20, SYS_ICC_PMR_EL1 229 str x20, [sp, #S_PMR_SAVE] 230alternative_else_nop_endif 231 232 /* 233 * Registers that may be useful after this macro is invoked: 234 * 235 * x20 - ICC_PMR_EL1 236 * x21 - aborted SP 237 * x22 - aborted PC 238 * x23 - aborted PSTATE 239 */ 240 .endm 241 242 .macro kernel_exit, el 243 .if \el != 0 244 disable_daif 245 246 /* Restore the task's original addr_limit. */ 247 ldr x20, [sp, #S_ORIG_ADDR_LIMIT] 248 str x20, [tsk, #TSK_TI_ADDR_LIMIT] 249 250 /* No need to restore UAO, it will be restored from SPSR_EL1 */ 251 .endif 252 253 /* Restore pmr */ 254alternative_if ARM64_HAS_IRQ_PRIO_MASKING 255 ldr x20, [sp, #S_PMR_SAVE] 256 msr_s SYS_ICC_PMR_EL1, x20 257 mrs_s x21, SYS_ICC_CTLR_EL1 258 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE 259 dsb sy // Ensure priority change is seen by redistributor 260.L__skip_pmr_sync\@: 261alternative_else_nop_endif 262 263 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 264 .if \el == 0 265 ct_user_enter 266 .endif 267 268#ifdef CONFIG_ARM64_SW_TTBR0_PAN 269alternative_if_not ARM64_HAS_PAN 270 bl __swpan_exit_el\el 271alternative_else_nop_endif 272#endif 273 274 .if \el == 0 275 ldr x23, [sp, #S_SP] // load return stack pointer 276 msr sp_el0, x23 277 tst x22, #PSR_MODE32_BIT // native task? 278 b.eq 3f 279 280#ifdef CONFIG_ARM64_ERRATUM_845719 281alternative_if ARM64_WORKAROUND_845719 282#ifdef CONFIG_PID_IN_CONTEXTIDR 283 mrs x29, contextidr_el1 284 msr contextidr_el1, x29 285#else 286 msr contextidr_el1, xzr 287#endif 288alternative_else_nop_endif 289#endif 2903: 291#ifdef CONFIG_ARM64_ERRATUM_1418040 292alternative_if_not ARM64_WORKAROUND_1418040 293 b 4f 294alternative_else_nop_endif 295 /* 296 * if (x22.mode32 == cntkctl_el1.el0vcten) 297 * cntkctl_el1.el0vcten = ~cntkctl_el1.el0vcten 298 */ 299 mrs x1, cntkctl_el1 300 eon x0, x1, x22, lsr #3 301 tbz x0, #1, 4f 302 eor x1, x1, #2 // ARCH_TIMER_USR_VCT_ACCESS_EN 303 msr cntkctl_el1, x1 3044: 305#endif 306 scs_save tsk, x0 307 308 /* No kernel C function calls after this as user keys are set. */ 309 ptrauth_keys_install_user tsk, x0, x1, x2 310 311 apply_ssbd 0, x0, x1 312 .endif 313 314 msr elr_el1, x21 // set up the return data 315 msr spsr_el1, x22 316 ldp x0, x1, [sp, #16 * 0] 317 ldp x2, x3, [sp, #16 * 1] 318 ldp x4, x5, [sp, #16 * 2] 319 ldp x6, x7, [sp, #16 * 3] 320 ldp x8, x9, [sp, #16 * 4] 321 ldp x10, x11, [sp, #16 * 5] 322 ldp x12, x13, [sp, #16 * 6] 323 ldp x14, x15, [sp, #16 * 7] 324 ldp x16, x17, [sp, #16 * 8] 325 ldp x18, x19, [sp, #16 * 9] 326 ldp x20, x21, [sp, #16 * 10] 327 ldp x22, x23, [sp, #16 * 11] 328 ldp x24, x25, [sp, #16 * 12] 329 ldp x26, x27, [sp, #16 * 13] 330 ldp x28, x29, [sp, #16 * 14] 331 ldr lr, [sp, #S_LR] 332 add sp, sp, #S_FRAME_SIZE // restore sp 333 334 .if \el == 0 335alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 336#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 337 bne 5f 338 msr far_el1, x30 339 tramp_alias x30, tramp_exit_native 340 br x30 3415: 342 tramp_alias x30, tramp_exit_compat 343 br x30 344#endif 345 .else 346 eret 347 .endif 348 sb 349 .endm 350 351#ifdef CONFIG_ARM64_SW_TTBR0_PAN 352 /* 353 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 354 * EL0, there is no need to check the state of TTBR0_EL1 since 355 * accesses are always enabled. 356 * Note that the meaning of this bit differs from the ARMv8.1 PAN 357 * feature as all TTBR0_EL1 accesses are disabled, not just those to 358 * user mappings. 359 */ 360SYM_CODE_START_LOCAL(__swpan_entry_el1) 361 mrs x21, ttbr0_el1 362 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID 363 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 364 b.eq 1f // TTBR0 access already disabled 365 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 366SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 367 __uaccess_ttbr0_disable x21 3681: ret 369SYM_CODE_END(__swpan_entry_el1) 370 371 /* 372 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 373 * PAN bit checking. 374 */ 375SYM_CODE_START_LOCAL(__swpan_exit_el1) 376 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 377 __uaccess_ttbr0_enable x0, x1 3781: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 379 ret 380SYM_CODE_END(__swpan_exit_el1) 381 382SYM_CODE_START_LOCAL(__swpan_exit_el0) 383 __uaccess_ttbr0_enable x0, x1 384 /* 385 * Enable errata workarounds only if returning to user. The only 386 * workaround currently required for TTBR0_EL1 changes are for the 387 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 388 * corruption). 389 */ 390 b post_ttbr_update_workaround 391SYM_CODE_END(__swpan_exit_el0) 392#endif 393 394 .macro irq_stack_entry 395 mov x19, sp // preserve the original sp 396#ifdef CONFIG_SHADOW_CALL_STACK 397 mov x24, scs_sp // preserve the original shadow stack 398#endif 399 400 /* 401 * Compare sp with the base of the task stack. 402 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack, 403 * and should switch to the irq stack. 404 */ 405 ldr x25, [tsk, TSK_STACK] 406 eor x25, x25, x19 407 and x25, x25, #~(THREAD_SIZE - 1) 408 cbnz x25, 9998f 409 410 ldr_this_cpu x25, irq_stack_ptr, x26 411 mov x26, #IRQ_STACK_SIZE 412 add x26, x25, x26 413 414 /* switch to the irq stack */ 415 mov sp, x26 416 417#ifdef CONFIG_SHADOW_CALL_STACK 418 /* also switch to the irq shadow stack */ 419 adr_this_cpu scs_sp, irq_shadow_call_stack, x26 420#endif 421 4229998: 423 .endm 424 425 /* 426 * The callee-saved regs (x19-x29) should be preserved between 427 * irq_stack_entry and irq_stack_exit, but note that kernel_entry 428 * uses x20-x23 to store data for later use. 429 */ 430 .macro irq_stack_exit 431 mov sp, x19 432#ifdef CONFIG_SHADOW_CALL_STACK 433 mov scs_sp, x24 434#endif 435 .endm 436 437/* GPRs used by entry code */ 438tsk .req x28 // current thread_info 439 440/* 441 * Interrupt handling. 442 */ 443 .macro irq_handler 444 ldr_l x1, handle_arch_irq 445 mov x0, sp 446 irq_stack_entry 447 blr x1 448 irq_stack_exit 449 .endm 450 451#ifdef CONFIG_ARM64_PSEUDO_NMI 452 /* 453 * Set res to 0 if irqs were unmasked in interrupted context. 454 * Otherwise set res to non-0 value. 455 */ 456 .macro test_irqs_unmasked res:req, pmr:req 457alternative_if ARM64_HAS_IRQ_PRIO_MASKING 458 sub \res, \pmr, #GIC_PRIO_IRQON 459alternative_else 460 mov \res, xzr 461alternative_endif 462 .endm 463#endif 464 465 .macro gic_prio_kentry_setup, tmp:req 466#ifdef CONFIG_ARM64_PSEUDO_NMI 467 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 468 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON) 469 msr_s SYS_ICC_PMR_EL1, \tmp 470 alternative_else_nop_endif 471#endif 472 .endm 473 474 .macro gic_prio_irq_setup, pmr:req, tmp:req 475#ifdef CONFIG_ARM64_PSEUDO_NMI 476 alternative_if ARM64_HAS_IRQ_PRIO_MASKING 477 orr \tmp, \pmr, #GIC_PRIO_PSR_I_SET 478 msr_s SYS_ICC_PMR_EL1, \tmp 479 alternative_else_nop_endif 480#endif 481 .endm 482 483 .text 484 485/* 486 * Exception vectors. 487 */ 488 .pushsection ".entry.text", "ax" 489 490 .align 11 491SYM_CODE_START(vectors) 492 kernel_ventry 1, sync_invalid // Synchronous EL1t 493 kernel_ventry 1, irq_invalid // IRQ EL1t 494 kernel_ventry 1, fiq_invalid // FIQ EL1t 495 kernel_ventry 1, error_invalid // Error EL1t 496 497 kernel_ventry 1, sync // Synchronous EL1h 498 kernel_ventry 1, irq // IRQ EL1h 499 kernel_ventry 1, fiq_invalid // FIQ EL1h 500 kernel_ventry 1, error // Error EL1h 501 502 kernel_ventry 0, sync // Synchronous 64-bit EL0 503 kernel_ventry 0, irq // IRQ 64-bit EL0 504 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0 505 kernel_ventry 0, error // Error 64-bit EL0 506 507#ifdef CONFIG_COMPAT 508 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0 509 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0 510 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0 511 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0 512#else 513 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0 514 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0 515 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0 516 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0 517#endif 518SYM_CODE_END(vectors) 519 520#ifdef CONFIG_VMAP_STACK 521 /* 522 * We detected an overflow in kernel_ventry, which switched to the 523 * overflow stack. Stash the exception regs, and head to our overflow 524 * handler. 525 */ 526__bad_stack: 527 /* Restore the original x0 value */ 528 mrs x0, tpidrro_el0 529 530 /* 531 * Store the original GPRs to the new stack. The orginal SP (minus 532 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry. 533 */ 534 sub sp, sp, #S_FRAME_SIZE 535 kernel_entry 1 536 mrs x0, tpidr_el0 537 add x0, x0, #S_FRAME_SIZE 538 str x0, [sp, #S_SP] 539 540 /* Stash the regs for handle_bad_stack */ 541 mov x0, sp 542 543 /* Time to die */ 544 bl handle_bad_stack 545 ASM_BUG() 546#endif /* CONFIG_VMAP_STACK */ 547 548/* 549 * Invalid mode handlers 550 */ 551 .macro inv_entry, el, reason, regsize = 64 552 kernel_entry \el, \regsize 553 mov x0, sp 554 mov x1, #\reason 555 mrs x2, esr_el1 556 bl bad_mode 557 ASM_BUG() 558 .endm 559 560SYM_CODE_START_LOCAL(el0_sync_invalid) 561 inv_entry 0, BAD_SYNC 562SYM_CODE_END(el0_sync_invalid) 563 564SYM_CODE_START_LOCAL(el0_irq_invalid) 565 inv_entry 0, BAD_IRQ 566SYM_CODE_END(el0_irq_invalid) 567 568SYM_CODE_START_LOCAL(el0_fiq_invalid) 569 inv_entry 0, BAD_FIQ 570SYM_CODE_END(el0_fiq_invalid) 571 572SYM_CODE_START_LOCAL(el0_error_invalid) 573 inv_entry 0, BAD_ERROR 574SYM_CODE_END(el0_error_invalid) 575 576#ifdef CONFIG_COMPAT 577SYM_CODE_START_LOCAL(el0_fiq_invalid_compat) 578 inv_entry 0, BAD_FIQ, 32 579SYM_CODE_END(el0_fiq_invalid_compat) 580#endif 581 582SYM_CODE_START_LOCAL(el1_sync_invalid) 583 inv_entry 1, BAD_SYNC 584SYM_CODE_END(el1_sync_invalid) 585 586SYM_CODE_START_LOCAL(el1_irq_invalid) 587 inv_entry 1, BAD_IRQ 588SYM_CODE_END(el1_irq_invalid) 589 590SYM_CODE_START_LOCAL(el1_fiq_invalid) 591 inv_entry 1, BAD_FIQ 592SYM_CODE_END(el1_fiq_invalid) 593 594SYM_CODE_START_LOCAL(el1_error_invalid) 595 inv_entry 1, BAD_ERROR 596SYM_CODE_END(el1_error_invalid) 597 598/* 599 * EL1 mode handlers. 600 */ 601 .align 6 602SYM_CODE_START_LOCAL_NOALIGN(el1_sync) 603 kernel_entry 1 604 mov x0, sp 605 bl el1_sync_handler 606 kernel_exit 1 607SYM_CODE_END(el1_sync) 608 609 .align 6 610SYM_CODE_START_LOCAL_NOALIGN(el1_irq) 611 kernel_entry 1 612 gic_prio_irq_setup pmr=x20, tmp=x1 613 enable_da_f 614 615#ifdef CONFIG_ARM64_PSEUDO_NMI 616 test_irqs_unmasked res=x0, pmr=x20 617 cbz x0, 1f 618 bl asm_nmi_enter 6191: 620#endif 621 622#ifdef CONFIG_TRACE_IRQFLAGS 623 bl trace_hardirqs_off 624#endif 625 626 irq_handler 627 628#ifdef CONFIG_PREEMPTION 629 ldr x24, [tsk, #TSK_TI_PREEMPT] // get preempt count 630alternative_if ARM64_HAS_IRQ_PRIO_MASKING 631 /* 632 * DA_F were cleared at start of handling. If anything is set in DAIF, 633 * we come back from an NMI, so skip preemption 634 */ 635 mrs x0, daif 636 orr x24, x24, x0 637alternative_else_nop_endif 638 cbnz x24, 1f // preempt count != 0 || NMI return path 639 bl arm64_preempt_schedule_irq // irq en/disable is done inside 6401: 641#endif 642 643#ifdef CONFIG_ARM64_PSEUDO_NMI 644 /* 645 * When using IRQ priority masking, we can get spurious interrupts while 646 * PMR is set to GIC_PRIO_IRQOFF. An NMI might also have occurred in a 647 * section with interrupts disabled. Skip tracing in those cases. 648 */ 649 test_irqs_unmasked res=x0, pmr=x20 650 cbz x0, 1f 651 bl asm_nmi_exit 6521: 653#endif 654 655#ifdef CONFIG_TRACE_IRQFLAGS 656#ifdef CONFIG_ARM64_PSEUDO_NMI 657 test_irqs_unmasked res=x0, pmr=x20 658 cbnz x0, 1f 659#endif 660 bl trace_hardirqs_on 6611: 662#endif 663 664 kernel_exit 1 665SYM_CODE_END(el1_irq) 666 667/* 668 * EL0 mode handlers. 669 */ 670 .align 6 671SYM_CODE_START_LOCAL_NOALIGN(el0_sync) 672 kernel_entry 0 673 mov x0, sp 674 bl el0_sync_handler 675 b ret_to_user 676SYM_CODE_END(el0_sync) 677 678#ifdef CONFIG_COMPAT 679 .align 6 680SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat) 681 kernel_entry 0, 32 682 mov x0, sp 683 bl el0_sync_compat_handler 684 b ret_to_user 685SYM_CODE_END(el0_sync_compat) 686 687 .align 6 688SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat) 689 kernel_entry 0, 32 690 b el0_irq_naked 691SYM_CODE_END(el0_irq_compat) 692 693SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat) 694 kernel_entry 0, 32 695 b el0_error_naked 696SYM_CODE_END(el0_error_compat) 697#endif 698 699 .align 6 700SYM_CODE_START_LOCAL_NOALIGN(el0_irq) 701 kernel_entry 0 702el0_irq_naked: 703 gic_prio_irq_setup pmr=x20, tmp=x0 704 ct_user_exit_irqoff 705 enable_da_f 706 707#ifdef CONFIG_TRACE_IRQFLAGS 708 bl trace_hardirqs_off 709#endif 710 711#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR 712 tbz x22, #55, 1f 713 bl do_el0_irq_bp_hardening 7141: 715#endif 716 irq_handler 717 718#ifdef CONFIG_TRACE_IRQFLAGS 719 bl trace_hardirqs_on 720#endif 721 b ret_to_user 722SYM_CODE_END(el0_irq) 723 724SYM_CODE_START_LOCAL(el1_error) 725 kernel_entry 1 726 mrs x1, esr_el1 727 gic_prio_kentry_setup tmp=x2 728 enable_dbg 729 mov x0, sp 730 bl do_serror 731 kernel_exit 1 732SYM_CODE_END(el1_error) 733 734SYM_CODE_START_LOCAL(el0_error) 735 kernel_entry 0 736el0_error_naked: 737 mrs x25, esr_el1 738 gic_prio_kentry_setup tmp=x2 739 ct_user_exit_irqoff 740 enable_dbg 741 mov x0, sp 742 mov x1, x25 743 bl do_serror 744 enable_da_f 745 b ret_to_user 746SYM_CODE_END(el0_error) 747 748/* 749 * "slow" syscall return path. 750 */ 751SYM_CODE_START_LOCAL(ret_to_user) 752 disable_daif 753 gic_prio_kentry_setup tmp=x3 754 ldr x1, [tsk, #TSK_TI_FLAGS] 755 and x2, x1, #_TIF_WORK_MASK 756 cbnz x2, work_pending 757finish_ret_to_user: 758 enable_step_tsk x1, x2 759#ifdef CONFIG_GCC_PLUGIN_STACKLEAK 760 bl stackleak_erase 761#endif 762 kernel_exit 0 763 764/* 765 * Ok, we need to do extra processing, enter the slow path. 766 */ 767work_pending: 768 mov x0, sp // 'regs' 769 bl do_notify_resume 770#ifdef CONFIG_TRACE_IRQFLAGS 771 bl trace_hardirqs_on // enabled while in userspace 772#endif 773 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step 774 b finish_ret_to_user 775SYM_CODE_END(ret_to_user) 776 777 .popsection // .entry.text 778 779#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 780/* 781 * Exception vectors trampoline. 782 */ 783 .pushsection ".entry.tramp.text", "ax" 784 785 .macro tramp_map_kernel, tmp 786 mrs \tmp, ttbr1_el1 787 add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 788 bic \tmp, \tmp, #USER_ASID_FLAG 789 msr ttbr1_el1, \tmp 790#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 791alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 792 /* ASID already in \tmp[63:48] */ 793 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 794 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 795 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 796 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 797 isb 798 tlbi vae1, \tmp 799 dsb nsh 800alternative_else_nop_endif 801#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 802 .endm 803 804 .macro tramp_unmap_kernel, tmp 805 mrs \tmp, ttbr1_el1 806 sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) 807 orr \tmp, \tmp, #USER_ASID_FLAG 808 msr ttbr1_el1, \tmp 809 /* 810 * We avoid running the post_ttbr_update_workaround here because 811 * it's only needed by Cavium ThunderX, which requires KPTI to be 812 * disabled. 813 */ 814 .endm 815 816 .macro tramp_ventry, regsize = 64 817 .align 7 8181: 819 .if \regsize == 64 820 msr tpidrro_el0, x30 // Restored in kernel_ventry 821 .endif 822 /* 823 * Defend against branch aliasing attacks by pushing a dummy 824 * entry onto the return stack and using a RET instruction to 825 * enter the full-fat kernel vectors. 826 */ 827 bl 2f 828 b . 8292: 830 tramp_map_kernel x30 831#ifdef CONFIG_RANDOMIZE_BASE 832 adr x30, tramp_vectors + PAGE_SIZE 833alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 834 ldr x30, [x30] 835#else 836 ldr x30, =vectors 837#endif 838alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 839 prfm plil1strm, [x30, #(1b - tramp_vectors)] 840alternative_else_nop_endif 841 msr vbar_el1, x30 842 add x30, x30, #(1b - tramp_vectors) 843 isb 844 ret 845 .endm 846 847 .macro tramp_exit, regsize = 64 848 adr x30, tramp_vectors 849 msr vbar_el1, x30 850 tramp_unmap_kernel x30 851 .if \regsize == 64 852 mrs x30, far_el1 853 .endif 854 eret 855 sb 856 .endm 857 858 .align 11 859SYM_CODE_START_NOALIGN(tramp_vectors) 860 .space 0x400 861 862 tramp_ventry 863 tramp_ventry 864 tramp_ventry 865 tramp_ventry 866 867 tramp_ventry 32 868 tramp_ventry 32 869 tramp_ventry 32 870 tramp_ventry 32 871SYM_CODE_END(tramp_vectors) 872 873SYM_CODE_START(tramp_exit_native) 874 tramp_exit 875SYM_CODE_END(tramp_exit_native) 876 877SYM_CODE_START(tramp_exit_compat) 878 tramp_exit 32 879SYM_CODE_END(tramp_exit_compat) 880 881 .ltorg 882 .popsection // .entry.tramp.text 883#ifdef CONFIG_RANDOMIZE_BASE 884 .pushsection ".rodata", "a" 885 .align PAGE_SHIFT 886SYM_DATA_START(__entry_tramp_data_start) 887 .quad vectors 888SYM_DATA_END(__entry_tramp_data_start) 889 .popsection // .rodata 890#endif /* CONFIG_RANDOMIZE_BASE */ 891#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 892 893/* 894 * Register switch for AArch64. The callee-saved registers need to be saved 895 * and restored. On entry: 896 * x0 = previous task_struct (must be preserved across the switch) 897 * x1 = next task_struct 898 * Previous and next are guaranteed not to be the same. 899 * 900 */ 901SYM_FUNC_START(cpu_switch_to) 902 mov x10, #THREAD_CPU_CONTEXT 903 add x8, x0, x10 904 mov x9, sp 905 stp x19, x20, [x8], #16 // store callee-saved registers 906 stp x21, x22, [x8], #16 907 stp x23, x24, [x8], #16 908 stp x25, x26, [x8], #16 909 stp x27, x28, [x8], #16 910 stp x29, x9, [x8], #16 911 str lr, [x8] 912 add x8, x1, x10 913 ldp x19, x20, [x8], #16 // restore callee-saved registers 914 ldp x21, x22, [x8], #16 915 ldp x23, x24, [x8], #16 916 ldp x25, x26, [x8], #16 917 ldp x27, x28, [x8], #16 918 ldp x29, x9, [x8], #16 919 ldr lr, [x8] 920 mov sp, x9 921 msr sp_el0, x1 922 ptrauth_keys_install_kernel x1, x8, x9, x10 923 scs_save x0, x8 924 scs_load x1, x8 925 ret 926SYM_FUNC_END(cpu_switch_to) 927NOKPROBE(cpu_switch_to) 928 929/* 930 * This is how we return from a fork. 931 */ 932SYM_CODE_START(ret_from_fork) 933 bl schedule_tail 934 cbz x19, 1f // not a kernel thread 935 mov x0, x20 936 blr x19 9371: get_current_task tsk 938 b ret_to_user 939SYM_CODE_END(ret_from_fork) 940NOKPROBE(ret_from_fork) 941 942#ifdef CONFIG_ARM_SDE_INTERFACE 943 944#include <asm/sdei.h> 945#include <uapi/linux/arm_sdei.h> 946 947.macro sdei_handler_exit exit_mode 948 /* On success, this call never returns... */ 949 cmp \exit_mode, #SDEI_EXIT_SMC 950 b.ne 99f 951 smc #0 952 b . 95399: hvc #0 954 b . 955.endm 956 957#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 958/* 959 * The regular SDEI entry point may have been unmapped along with the rest of 960 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 961 * argument accessible. 962 * 963 * This clobbers x4, __sdei_handler() will restore this from firmware's 964 * copy. 965 */ 966.ltorg 967.pushsection ".entry.tramp.text", "ax" 968SYM_CODE_START(__sdei_asm_entry_trampoline) 969 mrs x4, ttbr1_el1 970 tbz x4, #USER_ASID_BIT, 1f 971 972 tramp_map_kernel tmp=x4 973 isb 974 mov x4, xzr 975 976 /* 977 * Use reg->interrupted_regs.addr_limit to remember whether to unmap 978 * the kernel on exit. 979 */ 9801: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 981 982#ifdef CONFIG_RANDOMIZE_BASE 983 adr x4, tramp_vectors + PAGE_SIZE 984 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler 985 ldr x4, [x4] 986#else 987 ldr x4, =__sdei_asm_handler 988#endif 989 br x4 990SYM_CODE_END(__sdei_asm_entry_trampoline) 991NOKPROBE(__sdei_asm_entry_trampoline) 992 993/* 994 * Make the exit call and restore the original ttbr1_el1 995 * 996 * x0 & x1: setup for the exit API call 997 * x2: exit_mode 998 * x4: struct sdei_registered_event argument from registration time. 999 */ 1000SYM_CODE_START(__sdei_asm_exit_trampoline) 1001 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] 1002 cbnz x4, 1f 1003 1004 tramp_unmap_kernel tmp=x4 1005 10061: sdei_handler_exit exit_mode=x2 1007SYM_CODE_END(__sdei_asm_exit_trampoline) 1008NOKPROBE(__sdei_asm_exit_trampoline) 1009 .ltorg 1010.popsection // .entry.tramp.text 1011#ifdef CONFIG_RANDOMIZE_BASE 1012.pushsection ".rodata", "a" 1013SYM_DATA_START(__sdei_asm_trampoline_next_handler) 1014 .quad __sdei_asm_handler 1015SYM_DATA_END(__sdei_asm_trampoline_next_handler) 1016.popsection // .rodata 1017#endif /* CONFIG_RANDOMIZE_BASE */ 1018#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1019 1020/* 1021 * Software Delegated Exception entry point. 1022 * 1023 * x0: Event number 1024 * x1: struct sdei_registered_event argument from registration time. 1025 * x2: interrupted PC 1026 * x3: interrupted PSTATE 1027 * x4: maybe clobbered by the trampoline 1028 * 1029 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 1030 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 1031 * want them. 1032 */ 1033SYM_CODE_START(__sdei_asm_handler) 1034 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 1035 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 1036 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 1037 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 1038 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 1039 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 1040 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 1041 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 1042 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 1043 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 1044 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 1045 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 1046 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 1047 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 1048 mov x4, sp 1049 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 1050 1051 mov x19, x1 1052 1053#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK) 1054 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1055#endif 1056 1057#ifdef CONFIG_VMAP_STACK 1058 /* 1059 * entry.S may have been using sp as a scratch register, find whether 1060 * this is a normal or critical event and switch to the appropriate 1061 * stack for this CPU. 1062 */ 1063 cbnz w4, 1f 1064 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1065 b 2f 10661: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10672: mov x6, #SDEI_STACK_SIZE 1068 add x5, x5, x6 1069 mov sp, x5 1070#endif 1071 1072#ifdef CONFIG_SHADOW_CALL_STACK 1073 /* Use a separate shadow call stack for normal and critical events */ 1074 cbnz w4, 3f 1075 adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal, tmp=x6 1076 b 4f 10773: adr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical, tmp=x6 10784: 1079#endif 1080 1081 /* 1082 * We may have interrupted userspace, or a guest, or exit-from or 1083 * return-to either of these. We can't trust sp_el0, restore it. 1084 */ 1085 mrs x28, sp_el0 1086 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1087 msr sp_el0, x0 1088 1089 /* If we interrupted the kernel point to the previous stack/frame. */ 1090 and x0, x3, #0xc 1091 mrs x1, CurrentEL 1092 cmp x0, x1 1093 csel x29, x29, xzr, eq // fp, or zero 1094 csel x4, x2, xzr, eq // elr, or zero 1095 1096 stp x29, x4, [sp, #-16]! 1097 mov x29, sp 1098 1099 add x0, x19, #SDEI_EVENT_INTREGS 1100 mov x1, x19 1101 bl __sdei_handler 1102 1103 msr sp_el0, x28 1104 /* restore regs >x17 that we clobbered */ 1105 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1106 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1107 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1108 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1109 mov sp, x1 1110 1111 mov x1, x0 // address to complete_and_resume 1112 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */ 1113 cmp x0, #1 1114 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1115 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1116 csel x0, x2, x3, ls 1117 1118 ldr_l x2, sdei_exit_mode 1119 1120alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1121 sdei_handler_exit exit_mode=x2 1122alternative_else_nop_endif 1123 1124#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1125 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1126 br x5 1127#endif 1128SYM_CODE_END(__sdei_asm_handler) 1129NOKPROBE(__sdei_asm_handler) 1130#endif /* CONFIG_ARM_SDE_INTERFACE */ 1131