1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VIPT: 40 return "VIPT"; 41 case CTR_EL0_L1Ip_PIPT: 42 return "PIPT"; 43 default: 44 return "RESERVED/UNKNOWN"; 45 } 46 } 47 48 unsigned long __icache_flags; 49 50 static const char *const hwcap_str[] = { 51 [KERNEL_HWCAP_FP] = "fp", 52 [KERNEL_HWCAP_ASIMD] = "asimd", 53 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 54 [KERNEL_HWCAP_AES] = "aes", 55 [KERNEL_HWCAP_PMULL] = "pmull", 56 [KERNEL_HWCAP_SHA1] = "sha1", 57 [KERNEL_HWCAP_SHA2] = "sha2", 58 [KERNEL_HWCAP_CRC32] = "crc32", 59 [KERNEL_HWCAP_ATOMICS] = "atomics", 60 [KERNEL_HWCAP_FPHP] = "fphp", 61 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 62 [KERNEL_HWCAP_CPUID] = "cpuid", 63 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 64 [KERNEL_HWCAP_JSCVT] = "jscvt", 65 [KERNEL_HWCAP_FCMA] = "fcma", 66 [KERNEL_HWCAP_LRCPC] = "lrcpc", 67 [KERNEL_HWCAP_DCPOP] = "dcpop", 68 [KERNEL_HWCAP_SHA3] = "sha3", 69 [KERNEL_HWCAP_SM3] = "sm3", 70 [KERNEL_HWCAP_SM4] = "sm4", 71 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 72 [KERNEL_HWCAP_SHA512] = "sha512", 73 [KERNEL_HWCAP_SVE] = "sve", 74 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 75 [KERNEL_HWCAP_DIT] = "dit", 76 [KERNEL_HWCAP_USCAT] = "uscat", 77 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 78 [KERNEL_HWCAP_FLAGM] = "flagm", 79 [KERNEL_HWCAP_SSBS] = "ssbs", 80 [KERNEL_HWCAP_SB] = "sb", 81 [KERNEL_HWCAP_PACA] = "paca", 82 [KERNEL_HWCAP_PACG] = "pacg", 83 [KERNEL_HWCAP_GCS] = "gcs", 84 [KERNEL_HWCAP_LS64] = "ls64", 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 86 [KERNEL_HWCAP_SVE2] = "sve2", 87 [KERNEL_HWCAP_SVEAES] = "sveaes", 88 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 90 [KERNEL_HWCAP_SVESHA3] = "svesha3", 91 [KERNEL_HWCAP_SVESM4] = "svesm4", 92 [KERNEL_HWCAP_FLAGM2] = "flagm2", 93 [KERNEL_HWCAP_FRINT] = "frint", 94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 97 [KERNEL_HWCAP_SVEBF16] = "svebf16", 98 [KERNEL_HWCAP_I8MM] = "i8mm", 99 [KERNEL_HWCAP_BF16] = "bf16", 100 [KERNEL_HWCAP_DGH] = "dgh", 101 [KERNEL_HWCAP_RNG] = "rng", 102 [KERNEL_HWCAP_BTI] = "bti", 103 [KERNEL_HWCAP_MTE] = "mte", 104 [KERNEL_HWCAP_ECV] = "ecv", 105 [KERNEL_HWCAP_AFP] = "afp", 106 [KERNEL_HWCAP_RPRES] = "rpres", 107 [KERNEL_HWCAP_MTE3] = "mte3", 108 [KERNEL_HWCAP_SME] = "sme", 109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 115 [KERNEL_HWCAP_SME_FA64] = "smefa64", 116 [KERNEL_HWCAP_WFXT] = "wfxt", 117 [KERNEL_HWCAP_EBF16] = "ebf16", 118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 119 [KERNEL_HWCAP_CSSC] = "cssc", 120 [KERNEL_HWCAP_RPRFM] = "rprfm", 121 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 122 [KERNEL_HWCAP_SME2] = "sme2", 123 [KERNEL_HWCAP_SME2P1] = "sme2p1", 124 [KERNEL_HWCAP_SME_I16I32] = "smei16i32", 125 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", 126 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", 127 [KERNEL_HWCAP_SME_F16F16] = "smef16f16", 128 [KERNEL_HWCAP_MOPS] = "mops", 129 [KERNEL_HWCAP_HBC] = "hbc", 130 [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", 131 [KERNEL_HWCAP_LRCPC3] = "lrcpc3", 132 [KERNEL_HWCAP_LSE128] = "lse128", 133 [KERNEL_HWCAP_FPMR] = "fpmr", 134 [KERNEL_HWCAP_LUT] = "lut", 135 [KERNEL_HWCAP_FAMINMAX] = "faminmax", 136 [KERNEL_HWCAP_F8CVT] = "f8cvt", 137 [KERNEL_HWCAP_F8FMA] = "f8fma", 138 [KERNEL_HWCAP_F8DP4] = "f8dp4", 139 [KERNEL_HWCAP_F8DP2] = "f8dp2", 140 [KERNEL_HWCAP_F8E4M3] = "f8e4m3", 141 [KERNEL_HWCAP_F8E5M2] = "f8e5m2", 142 [KERNEL_HWCAP_SME_LUTV2] = "smelutv2", 143 [KERNEL_HWCAP_SME_F8F16] = "smef8f16", 144 [KERNEL_HWCAP_SME_F8F32] = "smef8f32", 145 [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", 146 [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", 147 [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", 148 [KERNEL_HWCAP_POE] = "poe", 149 [KERNEL_HWCAP_CMPBR] = "cmpbr", 150 [KERNEL_HWCAP_FPRCVT] = "fprcvt", 151 [KERNEL_HWCAP_F8MM8] = "f8mm8", 152 [KERNEL_HWCAP_F8MM4] = "f8mm4", 153 [KERNEL_HWCAP_SVE_F16MM] = "svef16mm", 154 [KERNEL_HWCAP_SVE_ELTPERM] = "sveeltperm", 155 [KERNEL_HWCAP_SVE_AES2] = "sveaes2", 156 [KERNEL_HWCAP_SVE_BFSCALE] = "svebfscale", 157 [KERNEL_HWCAP_SVE2P2] = "sve2p2", 158 [KERNEL_HWCAP_SME2P2] = "sme2p2", 159 [KERNEL_HWCAP_SME_SBITPERM] = "smesbitperm", 160 [KERNEL_HWCAP_SME_AES] = "smeaes", 161 [KERNEL_HWCAP_SME_SFEXPA] = "smesfexpa", 162 [KERNEL_HWCAP_SME_STMOP] = "smestmop", 163 [KERNEL_HWCAP_SME_SMOP4] = "smesmop4", 164 [KERNEL_HWCAP_MTE_FAR] = "mtefar", 165 [KERNEL_HWCAP_MTE_STORE_ONLY] = "mtestoreonly", 166 [KERNEL_HWCAP_LSFE] = "lsfe", 167 [KERNEL_HWCAP_SVE_B16MM] = "sveb16mm", 168 [KERNEL_HWCAP_SVE2P3] = "sve2p3", 169 [KERNEL_HWCAP_SME_LUT6] = "smelut6", 170 [KERNEL_HWCAP_SME2P3] = "sme2p3", 171 [KERNEL_HWCAP_F16MM] = "f16mm", 172 [KERNEL_HWCAP_F16F32DOT] = "f16f32dot", 173 [KERNEL_HWCAP_F16F32MM] = "f16f32mm", 174 [KERNEL_HWCAP_SVE_LUT6] = "svelut6", 175 }; 176 177 #ifdef CONFIG_COMPAT 178 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 179 static const char *const compat_hwcap_str[] = { 180 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 181 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 182 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 183 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 184 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 185 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 186 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 187 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 188 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 189 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 190 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 191 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 192 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 193 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 194 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 195 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 196 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 197 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 198 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 199 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 200 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 201 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 202 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", 203 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", 204 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp", 205 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm", 206 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16", 207 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm", 208 }; 209 210 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 211 static const char *const compat_hwcap2_str[] = { 212 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 213 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 214 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 215 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 216 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 217 [COMPAT_KERNEL_HWCAP2(SB)] = "sb", 218 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", 219 }; 220 #endif /* CONFIG_COMPAT */ 221 222 static int c_show(struct seq_file *m, void *v) 223 { 224 int j; 225 int cpu = m->index; 226 bool compat = personality(current->personality) == PER_LINUX32; 227 struct cpuinfo_arm64 *cpuinfo = v; 228 u32 midr = cpuinfo->reg_midr; 229 230 /* 231 * glibc reads /proc/cpuinfo to determine the number of 232 * online processors, looking for lines beginning with 233 * "processor". Give glibc what it expects. 234 */ 235 seq_printf(m, "processor\t: %d\n", cpu); 236 if (compat) 237 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 238 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 239 240 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 241 loops_per_jiffy / (500000UL/HZ), 242 loops_per_jiffy / (5000UL/HZ) % 100); 243 244 /* 245 * Dump out the common processor features in a single line. 246 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 247 * rather than attempting to parse this, but there's a body of 248 * software which does already (at least for 32-bit). 249 */ 250 seq_puts(m, "Features\t:"); 251 if (compat) { 252 #ifdef CONFIG_COMPAT 253 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 254 if (compat_elf_hwcap & (1 << j)) { 255 /* 256 * Warn once if any feature should not 257 * have been present on arm64 platform. 258 */ 259 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 260 continue; 261 262 seq_printf(m, " %s", compat_hwcap_str[j]); 263 } 264 } 265 266 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 267 if (compat_elf_hwcap2 & (1 << j)) 268 seq_printf(m, " %s", compat_hwcap2_str[j]); 269 #endif /* CONFIG_COMPAT */ 270 } else { 271 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 272 if (cpu_have_feature(j)) 273 seq_printf(m, " %s", hwcap_str[j]); 274 } 275 seq_puts(m, "\n"); 276 277 seq_printf(m, "CPU implementer\t: 0x%02x\n", 278 MIDR_IMPLEMENTOR(midr)); 279 seq_puts(m, "CPU architecture: 8\n"); 280 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 281 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 282 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 283 284 return 0; 285 } 286 287 static void *c_start(struct seq_file *m, loff_t *pos) 288 { 289 *pos = cpumask_next(*pos - 1, cpu_online_mask); 290 return *pos < nr_cpu_ids ? &per_cpu(cpu_data, *pos) : NULL; 291 } 292 293 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 294 { 295 ++*pos; 296 return c_start(m, pos); 297 } 298 299 static void c_stop(struct seq_file *m, void *v) 300 { 301 } 302 303 const struct seq_operations cpuinfo_op = { 304 .start = c_start, 305 .next = c_next, 306 .stop = c_stop, 307 .show = c_show 308 }; 309 310 311 static const struct kobj_type cpuregs_kobj_type = { 312 .sysfs_ops = &kobj_sysfs_ops, 313 }; 314 315 /* 316 * The ARM ARM uses the phrase "32-bit register" to describe a register 317 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 318 * no statement is made as to whether the upper 32 bits will or will not 319 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 320 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 321 * 322 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 323 * registers, we expose them both as 64 bit values to cater for possible 324 * future expansion without an ABI break. 325 */ 326 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 327 #define CPUREGS_ATTR_RO(_name, _field) \ 328 static ssize_t _name##_show(struct kobject *kobj, \ 329 struct kobj_attribute *attr, char *buf) \ 330 { \ 331 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 332 \ 333 if (info->reg_midr) \ 334 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 335 else \ 336 return 0; \ 337 } \ 338 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 339 340 CPUREGS_ATTR_RO(midr_el1, midr); 341 CPUREGS_ATTR_RO(revidr_el1, revidr); 342 CPUREGS_ATTR_RO(aidr_el1, aidr); 343 CPUREGS_ATTR_RO(smidr_el1, smidr); 344 345 static struct attribute *cpuregs_id_attrs[] = { 346 &cpuregs_attr_midr_el1.attr, 347 &cpuregs_attr_revidr_el1.attr, 348 &cpuregs_attr_aidr_el1.attr, 349 NULL 350 }; 351 352 static const struct attribute_group cpuregs_attr_group = { 353 .attrs = cpuregs_id_attrs, 354 .name = "identification" 355 }; 356 357 static struct attribute *sme_cpuregs_id_attrs[] = { 358 &cpuregs_attr_smidr_el1.attr, 359 NULL 360 }; 361 362 static const struct attribute_group sme_cpuregs_attr_group = { 363 .attrs = sme_cpuregs_id_attrs, 364 .name = "identification" 365 }; 366 367 static int cpuid_cpu_online(unsigned int cpu) 368 { 369 int rc; 370 struct device *dev; 371 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 372 373 dev = get_cpu_device(cpu); 374 if (!dev) { 375 rc = -ENODEV; 376 goto out; 377 } 378 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 379 if (rc) 380 goto out; 381 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 382 if (rc) 383 kobject_del(&info->kobj); 384 if (system_supports_sme()) 385 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 386 out: 387 return rc; 388 } 389 390 static int cpuid_cpu_offline(unsigned int cpu) 391 { 392 struct device *dev; 393 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 394 395 dev = get_cpu_device(cpu); 396 if (!dev) 397 return -ENODEV; 398 if (info->kobj.parent) { 399 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 400 kobject_del(&info->kobj); 401 } 402 403 return 0; 404 } 405 406 static int __init cpuinfo_regs_init(void) 407 { 408 int cpu, ret; 409 410 for_each_possible_cpu(cpu) { 411 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 412 413 kobject_init(&info->kobj, &cpuregs_kobj_type); 414 } 415 416 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 417 cpuid_cpu_online, cpuid_cpu_offline); 418 if (ret < 0) { 419 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 420 return ret; 421 } 422 return 0; 423 } 424 device_initcall(cpuinfo_regs_init); 425 426 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 427 { 428 unsigned int cpu = smp_processor_id(); 429 u32 l1ip = CTR_L1IP(info->reg_ctr); 430 431 switch (l1ip) { 432 case CTR_EL0_L1Ip_PIPT: 433 break; 434 case CTR_EL0_L1Ip_VIPT: 435 default: 436 /* Assume aliasing */ 437 set_bit(ICACHEF_ALIASING, &__icache_flags); 438 break; 439 } 440 441 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 442 } 443 444 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 445 { 446 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 447 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 448 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 449 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 450 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 451 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 452 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 453 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 454 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 455 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 456 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 457 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 458 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 459 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 460 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 461 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 462 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 463 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 464 465 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 466 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 467 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 468 } 469 470 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 471 { 472 info->reg_cntfrq = arch_timer_get_cntfrq(); 473 /* 474 * Use the effective value of the CTR_EL0 than the raw value 475 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 476 * with the CLIDR_EL1 fields to avoid triggering false warnings 477 * when there is a mismatch across the CPUs. Keep track of the 478 * effective value of the CTR_EL0 in our internal records for 479 * accurate sanity check and feature enablement. 480 */ 481 info->reg_ctr = read_cpuid_effective_cachetype(); 482 info->reg_dczid = read_cpuid(DCZID_EL0); 483 info->reg_midr = read_cpuid_id(); 484 info->reg_revidr = read_cpuid(REVIDR_EL1); 485 info->reg_aidr = read_cpuid(AIDR_EL1); 486 487 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 488 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 489 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 490 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 491 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 492 info->reg_id_aa64isar3 = read_cpuid(ID_AA64ISAR3_EL1); 493 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 494 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 495 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 496 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); 497 info->reg_id_aa64mmfr4 = read_cpuid(ID_AA64MMFR4_EL1); 498 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 499 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 500 info->reg_id_aa64pfr2 = read_cpuid(ID_AA64PFR2_EL1); 501 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 502 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 503 info->reg_id_aa64fpfr0 = read_cpuid(ID_AA64FPFR0_EL1); 504 505 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 506 info->reg_gmid = read_cpuid(GMID_EL1); 507 508 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 509 __cpuinfo_store_cpu_32bit(&info->aarch32); 510 511 /* 512 * info->reg_mpamidr deferred to {init,update}_cpu_features because we 513 * don't want to read it (and trigger a trap on buggy firmware) if 514 * using an aa64pfr0_el1 override to unconditionally disable MPAM. 515 */ 516 517 if (IS_ENABLED(CONFIG_ARM64_SME) && 518 id_aa64pfr1_sme(info->reg_id_aa64pfr1)) { 519 /* 520 * We mask out SMPS since even if the hardware 521 * supports priorities the kernel does not at present 522 * and we block access to them. 523 */ 524 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 525 } 526 527 cpuinfo_detect_icache_policy(info); 528 } 529 530 void cpuinfo_store_cpu(void) 531 { 532 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 533 __cpuinfo_store_cpu(info); 534 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 535 } 536 537 void __init cpuinfo_store_boot_cpu(void) 538 { 539 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 540 __cpuinfo_store_cpu(info); 541 542 boot_cpu_data = *info; 543 init_cpu_features(&boot_cpu_data); 544 } 545