1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VPIPT: 40 return "VPIPT"; 41 case CTR_EL0_L1Ip_VIPT: 42 return "VIPT"; 43 case CTR_EL0_L1Ip_PIPT: 44 return "PIPT"; 45 default: 46 return "RESERVED/UNKNOWN"; 47 } 48 } 49 50 unsigned long __icache_flags; 51 52 static const char *const hwcap_str[] = { 53 [KERNEL_HWCAP_FP] = "fp", 54 [KERNEL_HWCAP_ASIMD] = "asimd", 55 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 56 [KERNEL_HWCAP_AES] = "aes", 57 [KERNEL_HWCAP_PMULL] = "pmull", 58 [KERNEL_HWCAP_SHA1] = "sha1", 59 [KERNEL_HWCAP_SHA2] = "sha2", 60 [KERNEL_HWCAP_CRC32] = "crc32", 61 [KERNEL_HWCAP_ATOMICS] = "atomics", 62 [KERNEL_HWCAP_FPHP] = "fphp", 63 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 64 [KERNEL_HWCAP_CPUID] = "cpuid", 65 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 66 [KERNEL_HWCAP_JSCVT] = "jscvt", 67 [KERNEL_HWCAP_FCMA] = "fcma", 68 [KERNEL_HWCAP_LRCPC] = "lrcpc", 69 [KERNEL_HWCAP_DCPOP] = "dcpop", 70 [KERNEL_HWCAP_SHA3] = "sha3", 71 [KERNEL_HWCAP_SM3] = "sm3", 72 [KERNEL_HWCAP_SM4] = "sm4", 73 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 74 [KERNEL_HWCAP_SHA512] = "sha512", 75 [KERNEL_HWCAP_SVE] = "sve", 76 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 77 [KERNEL_HWCAP_DIT] = "dit", 78 [KERNEL_HWCAP_USCAT] = "uscat", 79 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 80 [KERNEL_HWCAP_FLAGM] = "flagm", 81 [KERNEL_HWCAP_SSBS] = "ssbs", 82 [KERNEL_HWCAP_SB] = "sb", 83 [KERNEL_HWCAP_PACA] = "paca", 84 [KERNEL_HWCAP_PACG] = "pacg", 85 [KERNEL_HWCAP_DCPODP] = "dcpodp", 86 [KERNEL_HWCAP_SVE2] = "sve2", 87 [KERNEL_HWCAP_SVEAES] = "sveaes", 88 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 89 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 90 [KERNEL_HWCAP_SVESHA3] = "svesha3", 91 [KERNEL_HWCAP_SVESM4] = "svesm4", 92 [KERNEL_HWCAP_FLAGM2] = "flagm2", 93 [KERNEL_HWCAP_FRINT] = "frint", 94 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 95 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 96 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 97 [KERNEL_HWCAP_SVEBF16] = "svebf16", 98 [KERNEL_HWCAP_I8MM] = "i8mm", 99 [KERNEL_HWCAP_BF16] = "bf16", 100 [KERNEL_HWCAP_DGH] = "dgh", 101 [KERNEL_HWCAP_RNG] = "rng", 102 [KERNEL_HWCAP_BTI] = "bti", 103 [KERNEL_HWCAP_MTE] = "mte", 104 [KERNEL_HWCAP_ECV] = "ecv", 105 [KERNEL_HWCAP_AFP] = "afp", 106 [KERNEL_HWCAP_RPRES] = "rpres", 107 [KERNEL_HWCAP_MTE3] = "mte3", 108 [KERNEL_HWCAP_SME] = "sme", 109 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 110 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 111 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 112 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 113 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 114 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 115 [KERNEL_HWCAP_SME_FA64] = "smefa64", 116 [KERNEL_HWCAP_WFXT] = "wfxt", 117 [KERNEL_HWCAP_EBF16] = "ebf16", 118 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 119 [KERNEL_HWCAP_CSSC] = "cssc", 120 [KERNEL_HWCAP_RPRFM] = "rprfm", 121 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 122 [KERNEL_HWCAP_SME2] = "sme2", 123 [KERNEL_HWCAP_SME2P1] = "sme2p1", 124 [KERNEL_HWCAP_SME_I16I32] = "smei16i32", 125 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", 126 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", 127 [KERNEL_HWCAP_SME_F16F16] = "smef16f16", 128 [KERNEL_HWCAP_MOPS] = "mops", 129 [KERNEL_HWCAP_HBC] = "hbc", 130 }; 131 132 #ifdef CONFIG_COMPAT 133 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 134 static const char *const compat_hwcap_str[] = { 135 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 136 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 137 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 138 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 139 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 140 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 141 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 142 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 143 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 144 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 145 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 146 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 147 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 148 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 149 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 150 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 151 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 152 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 153 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 154 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 155 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 156 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 157 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", 158 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", 159 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp", 160 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm", 161 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16", 162 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm", 163 }; 164 165 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 166 static const char *const compat_hwcap2_str[] = { 167 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 168 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 169 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 170 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 171 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 172 [COMPAT_KERNEL_HWCAP2(SB)] = "sb", 173 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", 174 }; 175 #endif /* CONFIG_COMPAT */ 176 177 static int c_show(struct seq_file *m, void *v) 178 { 179 int i, j; 180 bool compat = personality(current->personality) == PER_LINUX32; 181 182 for_each_online_cpu(i) { 183 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 184 u32 midr = cpuinfo->reg_midr; 185 186 /* 187 * glibc reads /proc/cpuinfo to determine the number of 188 * online processors, looking for lines beginning with 189 * "processor". Give glibc what it expects. 190 */ 191 seq_printf(m, "processor\t: %d\n", i); 192 if (compat) 193 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 194 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 195 196 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 197 loops_per_jiffy / (500000UL/HZ), 198 loops_per_jiffy / (5000UL/HZ) % 100); 199 200 /* 201 * Dump out the common processor features in a single line. 202 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 203 * rather than attempting to parse this, but there's a body of 204 * software which does already (at least for 32-bit). 205 */ 206 seq_puts(m, "Features\t:"); 207 if (compat) { 208 #ifdef CONFIG_COMPAT 209 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 210 if (compat_elf_hwcap & (1 << j)) { 211 /* 212 * Warn once if any feature should not 213 * have been present on arm64 platform. 214 */ 215 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 216 continue; 217 218 seq_printf(m, " %s", compat_hwcap_str[j]); 219 } 220 } 221 222 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 223 if (compat_elf_hwcap2 & (1 << j)) 224 seq_printf(m, " %s", compat_hwcap2_str[j]); 225 #endif /* CONFIG_COMPAT */ 226 } else { 227 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 228 if (cpu_have_feature(j)) 229 seq_printf(m, " %s", hwcap_str[j]); 230 } 231 seq_puts(m, "\n"); 232 233 seq_printf(m, "CPU implementer\t: 0x%02x\n", 234 MIDR_IMPLEMENTOR(midr)); 235 seq_printf(m, "CPU architecture: 8\n"); 236 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 237 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 238 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 239 } 240 241 return 0; 242 } 243 244 static void *c_start(struct seq_file *m, loff_t *pos) 245 { 246 return *pos < 1 ? (void *)1 : NULL; 247 } 248 249 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 250 { 251 ++*pos; 252 return NULL; 253 } 254 255 static void c_stop(struct seq_file *m, void *v) 256 { 257 } 258 259 const struct seq_operations cpuinfo_op = { 260 .start = c_start, 261 .next = c_next, 262 .stop = c_stop, 263 .show = c_show 264 }; 265 266 267 static struct kobj_type cpuregs_kobj_type = { 268 .sysfs_ops = &kobj_sysfs_ops, 269 }; 270 271 /* 272 * The ARM ARM uses the phrase "32-bit register" to describe a register 273 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 274 * no statement is made as to whether the upper 32 bits will or will not 275 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 276 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 277 * 278 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 279 * registers, we expose them both as 64 bit values to cater for possible 280 * future expansion without an ABI break. 281 */ 282 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 283 #define CPUREGS_ATTR_RO(_name, _field) \ 284 static ssize_t _name##_show(struct kobject *kobj, \ 285 struct kobj_attribute *attr, char *buf) \ 286 { \ 287 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 288 \ 289 if (info->reg_midr) \ 290 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 291 else \ 292 return 0; \ 293 } \ 294 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 295 296 CPUREGS_ATTR_RO(midr_el1, midr); 297 CPUREGS_ATTR_RO(revidr_el1, revidr); 298 CPUREGS_ATTR_RO(smidr_el1, smidr); 299 300 static struct attribute *cpuregs_id_attrs[] = { 301 &cpuregs_attr_midr_el1.attr, 302 &cpuregs_attr_revidr_el1.attr, 303 NULL 304 }; 305 306 static const struct attribute_group cpuregs_attr_group = { 307 .attrs = cpuregs_id_attrs, 308 .name = "identification" 309 }; 310 311 static struct attribute *sme_cpuregs_id_attrs[] = { 312 &cpuregs_attr_smidr_el1.attr, 313 NULL 314 }; 315 316 static const struct attribute_group sme_cpuregs_attr_group = { 317 .attrs = sme_cpuregs_id_attrs, 318 .name = "identification" 319 }; 320 321 static int cpuid_cpu_online(unsigned int cpu) 322 { 323 int rc; 324 struct device *dev; 325 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 326 327 dev = get_cpu_device(cpu); 328 if (!dev) { 329 rc = -ENODEV; 330 goto out; 331 } 332 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 333 if (rc) 334 goto out; 335 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 336 if (rc) 337 kobject_del(&info->kobj); 338 if (system_supports_sme()) 339 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 340 out: 341 return rc; 342 } 343 344 static int cpuid_cpu_offline(unsigned int cpu) 345 { 346 struct device *dev; 347 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 348 349 dev = get_cpu_device(cpu); 350 if (!dev) 351 return -ENODEV; 352 if (info->kobj.parent) { 353 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 354 kobject_del(&info->kobj); 355 } 356 357 return 0; 358 } 359 360 static int __init cpuinfo_regs_init(void) 361 { 362 int cpu, ret; 363 364 for_each_possible_cpu(cpu) { 365 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 366 367 kobject_init(&info->kobj, &cpuregs_kobj_type); 368 } 369 370 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 371 cpuid_cpu_online, cpuid_cpu_offline); 372 if (ret < 0) { 373 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 374 return ret; 375 } 376 return 0; 377 } 378 device_initcall(cpuinfo_regs_init); 379 380 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 381 { 382 unsigned int cpu = smp_processor_id(); 383 u32 l1ip = CTR_L1IP(info->reg_ctr); 384 385 switch (l1ip) { 386 case CTR_EL0_L1Ip_PIPT: 387 break; 388 case CTR_EL0_L1Ip_VPIPT: 389 set_bit(ICACHEF_VPIPT, &__icache_flags); 390 break; 391 case CTR_EL0_L1Ip_VIPT: 392 default: 393 /* Assume aliasing */ 394 set_bit(ICACHEF_ALIASING, &__icache_flags); 395 break; 396 } 397 398 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 399 } 400 401 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 402 { 403 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 404 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 405 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 406 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 407 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 408 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 409 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 410 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 411 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 412 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 413 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 414 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 415 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 416 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 417 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 418 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 419 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 420 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 421 422 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 423 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 424 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 425 } 426 427 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 428 { 429 info->reg_cntfrq = arch_timer_get_cntfrq(); 430 /* 431 * Use the effective value of the CTR_EL0 than the raw value 432 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 433 * with the CLIDR_EL1 fields to avoid triggering false warnings 434 * when there is a mismatch across the CPUs. Keep track of the 435 * effective value of the CTR_EL0 in our internal records for 436 * accurate sanity check and feature enablement. 437 */ 438 info->reg_ctr = read_cpuid_effective_cachetype(); 439 info->reg_dczid = read_cpuid(DCZID_EL0); 440 info->reg_midr = read_cpuid_id(); 441 info->reg_revidr = read_cpuid(REVIDR_EL1); 442 443 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 444 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 445 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 446 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 447 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 448 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 449 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 450 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 451 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); 452 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 453 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 454 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 455 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 456 457 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 458 info->reg_gmid = read_cpuid(GMID_EL1); 459 460 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 461 __cpuinfo_store_cpu_32bit(&info->aarch32); 462 463 cpuinfo_detect_icache_policy(info); 464 } 465 466 void cpuinfo_store_cpu(void) 467 { 468 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 469 __cpuinfo_store_cpu(info); 470 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 471 } 472 473 void __init cpuinfo_store_boot_cpu(void) 474 { 475 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 476 __cpuinfo_store_cpu(info); 477 478 boot_cpu_data = *info; 479 init_cpu_features(&boot_cpu_data); 480 } 481