xref: /linux/arch/arm64/kernel/cpuinfo.c (revision 1c07425e902cd3137961c3d45b4271bf8a9b8eb9)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Record and handle CPU attributes.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  */
7 #include <asm/arch_timer.h>
8 #include <asm/cache.h>
9 #include <asm/cpu.h>
10 #include <asm/cputype.h>
11 #include <asm/cpufeature.h>
12 #include <asm/fpsimd.h>
13 
14 #include <linux/bitops.h>
15 #include <linux/bug.h>
16 #include <linux/compat.h>
17 #include <linux/elf.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/personality.h>
21 #include <linux/preempt.h>
22 #include <linux/printk.h>
23 #include <linux/seq_file.h>
24 #include <linux/sched.h>
25 #include <linux/smp.h>
26 #include <linux/delay.h>
27 
28 /*
29  * In case the boot CPU is hotpluggable, we record its initial state and
30  * current state separately. Certain system registers may contain different
31  * values depending on configuration at or after reset.
32  */
33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
34 static struct cpuinfo_arm64 boot_cpu_data;
35 
36 static inline const char *icache_policy_str(int l1ip)
37 {
38 	switch (l1ip) {
39 	case CTR_EL0_L1Ip_VPIPT:
40 		return "VPIPT";
41 	case CTR_EL0_L1Ip_VIPT:
42 		return "VIPT";
43 	case CTR_EL0_L1Ip_PIPT:
44 		return "PIPT";
45 	default:
46 		return "RESERVED/UNKNOWN";
47 	}
48 }
49 
50 unsigned long __icache_flags;
51 
52 static const char *const hwcap_str[] = {
53 	[KERNEL_HWCAP_FP]		= "fp",
54 	[KERNEL_HWCAP_ASIMD]		= "asimd",
55 	[KERNEL_HWCAP_EVTSTRM]		= "evtstrm",
56 	[KERNEL_HWCAP_AES]		= "aes",
57 	[KERNEL_HWCAP_PMULL]		= "pmull",
58 	[KERNEL_HWCAP_SHA1]		= "sha1",
59 	[KERNEL_HWCAP_SHA2]		= "sha2",
60 	[KERNEL_HWCAP_CRC32]		= "crc32",
61 	[KERNEL_HWCAP_ATOMICS]		= "atomics",
62 	[KERNEL_HWCAP_FPHP]		= "fphp",
63 	[KERNEL_HWCAP_ASIMDHP]		= "asimdhp",
64 	[KERNEL_HWCAP_CPUID]		= "cpuid",
65 	[KERNEL_HWCAP_ASIMDRDM]		= "asimdrdm",
66 	[KERNEL_HWCAP_JSCVT]		= "jscvt",
67 	[KERNEL_HWCAP_FCMA]		= "fcma",
68 	[KERNEL_HWCAP_LRCPC]		= "lrcpc",
69 	[KERNEL_HWCAP_DCPOP]		= "dcpop",
70 	[KERNEL_HWCAP_SHA3]		= "sha3",
71 	[KERNEL_HWCAP_SM3]		= "sm3",
72 	[KERNEL_HWCAP_SM4]		= "sm4",
73 	[KERNEL_HWCAP_ASIMDDP]		= "asimddp",
74 	[KERNEL_HWCAP_SHA512]		= "sha512",
75 	[KERNEL_HWCAP_SVE]		= "sve",
76 	[KERNEL_HWCAP_ASIMDFHM]		= "asimdfhm",
77 	[KERNEL_HWCAP_DIT]		= "dit",
78 	[KERNEL_HWCAP_USCAT]		= "uscat",
79 	[KERNEL_HWCAP_ILRCPC]		= "ilrcpc",
80 	[KERNEL_HWCAP_FLAGM]		= "flagm",
81 	[KERNEL_HWCAP_SSBS]		= "ssbs",
82 	[KERNEL_HWCAP_SB]		= "sb",
83 	[KERNEL_HWCAP_PACA]		= "paca",
84 	[KERNEL_HWCAP_PACG]		= "pacg",
85 	[KERNEL_HWCAP_DCPODP]		= "dcpodp",
86 	[KERNEL_HWCAP_SVE2]		= "sve2",
87 	[KERNEL_HWCAP_SVEAES]		= "sveaes",
88 	[KERNEL_HWCAP_SVEPMULL]		= "svepmull",
89 	[KERNEL_HWCAP_SVEBITPERM]	= "svebitperm",
90 	[KERNEL_HWCAP_SVESHA3]		= "svesha3",
91 	[KERNEL_HWCAP_SVESM4]		= "svesm4",
92 	[KERNEL_HWCAP_FLAGM2]		= "flagm2",
93 	[KERNEL_HWCAP_FRINT]		= "frint",
94 	[KERNEL_HWCAP_SVEI8MM]		= "svei8mm",
95 	[KERNEL_HWCAP_SVEF32MM]		= "svef32mm",
96 	[KERNEL_HWCAP_SVEF64MM]		= "svef64mm",
97 	[KERNEL_HWCAP_SVEBF16]		= "svebf16",
98 	[KERNEL_HWCAP_I8MM]		= "i8mm",
99 	[KERNEL_HWCAP_BF16]		= "bf16",
100 	[KERNEL_HWCAP_DGH]		= "dgh",
101 	[KERNEL_HWCAP_RNG]		= "rng",
102 	[KERNEL_HWCAP_BTI]		= "bti",
103 	[KERNEL_HWCAP_MTE]		= "mte",
104 	[KERNEL_HWCAP_ECV]		= "ecv",
105 	[KERNEL_HWCAP_AFP]		= "afp",
106 	[KERNEL_HWCAP_RPRES]		= "rpres",
107 	[KERNEL_HWCAP_MTE3]		= "mte3",
108 	[KERNEL_HWCAP_SME]		= "sme",
109 	[KERNEL_HWCAP_SME_I16I64]	= "smei16i64",
110 	[KERNEL_HWCAP_SME_F64F64]	= "smef64f64",
111 	[KERNEL_HWCAP_SME_I8I32]	= "smei8i32",
112 	[KERNEL_HWCAP_SME_F16F32]	= "smef16f32",
113 	[KERNEL_HWCAP_SME_B16F32]	= "smeb16f32",
114 	[KERNEL_HWCAP_SME_F32F32]	= "smef32f32",
115 	[KERNEL_HWCAP_SME_FA64]		= "smefa64",
116 	[KERNEL_HWCAP_WFXT]		= "wfxt",
117 	[KERNEL_HWCAP_EBF16]		= "ebf16",
118 	[KERNEL_HWCAP_SVE_EBF16]	= "sveebf16",
119 	[KERNEL_HWCAP_CSSC]		= "cssc",
120 	[KERNEL_HWCAP_RPRFM]		= "rprfm",
121 	[KERNEL_HWCAP_SVE2P1]		= "sve2p1",
122 	[KERNEL_HWCAP_SME2]		= "sme2",
123 	[KERNEL_HWCAP_SME2P1]		= "sme2p1",
124 	[KERNEL_HWCAP_SME_I16I32]	= "smei16i32",
125 	[KERNEL_HWCAP_SME_BI32I32]	= "smebi32i32",
126 	[KERNEL_HWCAP_SME_B16B16]	= "smeb16b16",
127 	[KERNEL_HWCAP_SME_F16F16]	= "smef16f16",
128 };
129 
130 #ifdef CONFIG_COMPAT
131 #define COMPAT_KERNEL_HWCAP(x)	const_ilog2(COMPAT_HWCAP_ ## x)
132 static const char *const compat_hwcap_str[] = {
133 	[COMPAT_KERNEL_HWCAP(SWP)]	= "swp",
134 	[COMPAT_KERNEL_HWCAP(HALF)]	= "half",
135 	[COMPAT_KERNEL_HWCAP(THUMB)]	= "thumb",
136 	[COMPAT_KERNEL_HWCAP(26BIT)]	= NULL,	/* Not possible on arm64 */
137 	[COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult",
138 	[COMPAT_KERNEL_HWCAP(FPA)]	= NULL,	/* Not possible on arm64 */
139 	[COMPAT_KERNEL_HWCAP(VFP)]	= "vfp",
140 	[COMPAT_KERNEL_HWCAP(EDSP)]	= "edsp",
141 	[COMPAT_KERNEL_HWCAP(JAVA)]	= NULL,	/* Not possible on arm64 */
142 	[COMPAT_KERNEL_HWCAP(IWMMXT)]	= NULL,	/* Not possible on arm64 */
143 	[COMPAT_KERNEL_HWCAP(CRUNCH)]	= NULL,	/* Not possible on arm64 */
144 	[COMPAT_KERNEL_HWCAP(THUMBEE)]	= NULL,	/* Not possible on arm64 */
145 	[COMPAT_KERNEL_HWCAP(NEON)]	= "neon",
146 	[COMPAT_KERNEL_HWCAP(VFPv3)]	= "vfpv3",
147 	[COMPAT_KERNEL_HWCAP(VFPV3D16)]	= NULL,	/* Not possible on arm64 */
148 	[COMPAT_KERNEL_HWCAP(TLS)]	= "tls",
149 	[COMPAT_KERNEL_HWCAP(VFPv4)]	= "vfpv4",
150 	[COMPAT_KERNEL_HWCAP(IDIVA)]	= "idiva",
151 	[COMPAT_KERNEL_HWCAP(IDIVT)]	= "idivt",
152 	[COMPAT_KERNEL_HWCAP(VFPD32)]	= NULL,	/* Not possible on arm64 */
153 	[COMPAT_KERNEL_HWCAP(LPAE)]	= "lpae",
154 	[COMPAT_KERNEL_HWCAP(EVTSTRM)]	= "evtstrm",
155 };
156 
157 #define COMPAT_KERNEL_HWCAP2(x)	const_ilog2(COMPAT_HWCAP2_ ## x)
158 static const char *const compat_hwcap2_str[] = {
159 	[COMPAT_KERNEL_HWCAP2(AES)]	= "aes",
160 	[COMPAT_KERNEL_HWCAP2(PMULL)]	= "pmull",
161 	[COMPAT_KERNEL_HWCAP2(SHA1)]	= "sha1",
162 	[COMPAT_KERNEL_HWCAP2(SHA2)]	= "sha2",
163 	[COMPAT_KERNEL_HWCAP2(CRC32)]	= "crc32",
164 };
165 #endif /* CONFIG_COMPAT */
166 
167 static int c_show(struct seq_file *m, void *v)
168 {
169 	int i, j;
170 	bool compat = personality(current->personality) == PER_LINUX32;
171 
172 	for_each_online_cpu(i) {
173 		struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
174 		u32 midr = cpuinfo->reg_midr;
175 
176 		/*
177 		 * glibc reads /proc/cpuinfo to determine the number of
178 		 * online processors, looking for lines beginning with
179 		 * "processor".  Give glibc what it expects.
180 		 */
181 		seq_printf(m, "processor\t: %d\n", i);
182 		if (compat)
183 			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
184 				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
185 
186 		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
187 			   loops_per_jiffy / (500000UL/HZ),
188 			   loops_per_jiffy / (5000UL/HZ) % 100);
189 
190 		/*
191 		 * Dump out the common processor features in a single line.
192 		 * Userspace should read the hwcaps with getauxval(AT_HWCAP)
193 		 * rather than attempting to parse this, but there's a body of
194 		 * software which does already (at least for 32-bit).
195 		 */
196 		seq_puts(m, "Features\t:");
197 		if (compat) {
198 #ifdef CONFIG_COMPAT
199 			for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) {
200 				if (compat_elf_hwcap & (1 << j)) {
201 					/*
202 					 * Warn once if any feature should not
203 					 * have been present on arm64 platform.
204 					 */
205 					if (WARN_ON_ONCE(!compat_hwcap_str[j]))
206 						continue;
207 
208 					seq_printf(m, " %s", compat_hwcap_str[j]);
209 				}
210 			}
211 
212 			for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++)
213 				if (compat_elf_hwcap2 & (1 << j))
214 					seq_printf(m, " %s", compat_hwcap2_str[j]);
215 #endif /* CONFIG_COMPAT */
216 		} else {
217 			for (j = 0; j < ARRAY_SIZE(hwcap_str); j++)
218 				if (cpu_have_feature(j))
219 					seq_printf(m, " %s", hwcap_str[j]);
220 		}
221 		seq_puts(m, "\n");
222 
223 		seq_printf(m, "CPU implementer\t: 0x%02x\n",
224 			   MIDR_IMPLEMENTOR(midr));
225 		seq_printf(m, "CPU architecture: 8\n");
226 		seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
227 		seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
228 		seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
229 	}
230 
231 	return 0;
232 }
233 
234 static void *c_start(struct seq_file *m, loff_t *pos)
235 {
236 	return *pos < 1 ? (void *)1 : NULL;
237 }
238 
239 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
240 {
241 	++*pos;
242 	return NULL;
243 }
244 
245 static void c_stop(struct seq_file *m, void *v)
246 {
247 }
248 
249 const struct seq_operations cpuinfo_op = {
250 	.start	= c_start,
251 	.next	= c_next,
252 	.stop	= c_stop,
253 	.show	= c_show
254 };
255 
256 
257 static struct kobj_type cpuregs_kobj_type = {
258 	.sysfs_ops = &kobj_sysfs_ops,
259 };
260 
261 /*
262  * The ARM ARM uses the phrase "32-bit register" to describe a register
263  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
264  * no statement is made as to whether the upper 32 bits will or will not
265  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
266  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
267  *
268  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
269  * registers, we expose them both as 64 bit values to cater for possible
270  * future expansion without an ABI break.
271  */
272 #define kobj_to_cpuinfo(kobj)	container_of(kobj, struct cpuinfo_arm64, kobj)
273 #define CPUREGS_ATTR_RO(_name, _field)						\
274 	static ssize_t _name##_show(struct kobject *kobj,			\
275 			struct kobj_attribute *attr, char *buf)			\
276 	{									\
277 		struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);		\
278 										\
279 		if (info->reg_midr)						\
280 			return sprintf(buf, "0x%016llx\n", info->reg_##_field);	\
281 		else								\
282 			return 0;						\
283 	}									\
284 	static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
285 
286 CPUREGS_ATTR_RO(midr_el1, midr);
287 CPUREGS_ATTR_RO(revidr_el1, revidr);
288 CPUREGS_ATTR_RO(smidr_el1, smidr);
289 
290 static struct attribute *cpuregs_id_attrs[] = {
291 	&cpuregs_attr_midr_el1.attr,
292 	&cpuregs_attr_revidr_el1.attr,
293 	NULL
294 };
295 
296 static const struct attribute_group cpuregs_attr_group = {
297 	.attrs = cpuregs_id_attrs,
298 	.name = "identification"
299 };
300 
301 static struct attribute *sme_cpuregs_id_attrs[] = {
302 	&cpuregs_attr_smidr_el1.attr,
303 	NULL
304 };
305 
306 static const struct attribute_group sme_cpuregs_attr_group = {
307 	.attrs = sme_cpuregs_id_attrs,
308 	.name = "identification"
309 };
310 
311 static int cpuid_cpu_online(unsigned int cpu)
312 {
313 	int rc;
314 	struct device *dev;
315 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
316 
317 	dev = get_cpu_device(cpu);
318 	if (!dev) {
319 		rc = -ENODEV;
320 		goto out;
321 	}
322 	rc = kobject_add(&info->kobj, &dev->kobj, "regs");
323 	if (rc)
324 		goto out;
325 	rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
326 	if (rc)
327 		kobject_del(&info->kobj);
328 	if (system_supports_sme())
329 		rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group);
330 out:
331 	return rc;
332 }
333 
334 static int cpuid_cpu_offline(unsigned int cpu)
335 {
336 	struct device *dev;
337 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
338 
339 	dev = get_cpu_device(cpu);
340 	if (!dev)
341 		return -ENODEV;
342 	if (info->kobj.parent) {
343 		sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
344 		kobject_del(&info->kobj);
345 	}
346 
347 	return 0;
348 }
349 
350 static int __init cpuinfo_regs_init(void)
351 {
352 	int cpu, ret;
353 
354 	for_each_possible_cpu(cpu) {
355 		struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
356 
357 		kobject_init(&info->kobj, &cpuregs_kobj_type);
358 	}
359 
360 	ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
361 				cpuid_cpu_online, cpuid_cpu_offline);
362 	if (ret < 0) {
363 		pr_err("cpuinfo: failed to register hotplug callbacks.\n");
364 		return ret;
365 	}
366 	return 0;
367 }
368 device_initcall(cpuinfo_regs_init);
369 
370 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
371 {
372 	unsigned int cpu = smp_processor_id();
373 	u32 l1ip = CTR_L1IP(info->reg_ctr);
374 
375 	switch (l1ip) {
376 	case CTR_EL0_L1Ip_PIPT:
377 		break;
378 	case CTR_EL0_L1Ip_VPIPT:
379 		set_bit(ICACHEF_VPIPT, &__icache_flags);
380 		break;
381 	case CTR_EL0_L1Ip_VIPT:
382 	default:
383 		/* Assume aliasing */
384 		set_bit(ICACHEF_ALIASING, &__icache_flags);
385 		break;
386 	}
387 
388 	pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu);
389 }
390 
391 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info)
392 {
393 	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
394 	info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
395 	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
396 	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
397 	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
398 	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
399 	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
400 	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
401 	info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1);
402 	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
403 	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
404 	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
405 	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
406 	info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1);
407 	info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1);
408 	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
409 	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
410 	info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1);
411 
412 	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
413 	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
414 	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
415 }
416 
417 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
418 {
419 	info->reg_cntfrq = arch_timer_get_cntfrq();
420 	/*
421 	 * Use the effective value of the CTR_EL0 than the raw value
422 	 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted
423 	 * with the CLIDR_EL1 fields to avoid triggering false warnings
424 	 * when there is a mismatch across the CPUs. Keep track of the
425 	 * effective value of the CTR_EL0 in our internal records for
426 	 * accurate sanity check and feature enablement.
427 	 */
428 	info->reg_ctr = read_cpuid_effective_cachetype();
429 	info->reg_dczid = read_cpuid(DCZID_EL0);
430 	info->reg_midr = read_cpuid_id();
431 	info->reg_revidr = read_cpuid(REVIDR_EL1);
432 
433 	info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
434 	info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
435 	info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
436 	info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
437 	info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
438 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
439 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
440 	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
441 	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
442 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
443 	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
444 	info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1);
445 
446 	if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
447 		info->reg_gmid = read_cpuid(GMID_EL1);
448 
449 	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
450 		__cpuinfo_store_cpu_32bit(&info->aarch32);
451 
452 	cpuinfo_detect_icache_policy(info);
453 }
454 
455 void cpuinfo_store_cpu(void)
456 {
457 	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
458 	__cpuinfo_store_cpu(info);
459 	update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
460 }
461 
462 void __init cpuinfo_store_boot_cpu(void)
463 {
464 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
465 	__cpuinfo_store_cpu(info);
466 
467 	boot_cpu_data = *info;
468 	init_cpu_features(&boot_cpu_data);
469 }
470