1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 unsigned long __icache_flags; 35 36 static const char *const hwcap_str[] = { 37 [KERNEL_HWCAP_FP] = "fp", 38 [KERNEL_HWCAP_ASIMD] = "asimd", 39 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 40 [KERNEL_HWCAP_AES] = "aes", 41 [KERNEL_HWCAP_PMULL] = "pmull", 42 [KERNEL_HWCAP_SHA1] = "sha1", 43 [KERNEL_HWCAP_SHA2] = "sha2", 44 [KERNEL_HWCAP_CRC32] = "crc32", 45 [KERNEL_HWCAP_ATOMICS] = "atomics", 46 [KERNEL_HWCAP_FPHP] = "fphp", 47 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 48 [KERNEL_HWCAP_CPUID] = "cpuid", 49 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 50 [KERNEL_HWCAP_JSCVT] = "jscvt", 51 [KERNEL_HWCAP_FCMA] = "fcma", 52 [KERNEL_HWCAP_LRCPC] = "lrcpc", 53 [KERNEL_HWCAP_DCPOP] = "dcpop", 54 [KERNEL_HWCAP_SHA3] = "sha3", 55 [KERNEL_HWCAP_SM3] = "sm3", 56 [KERNEL_HWCAP_SM4] = "sm4", 57 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 58 [KERNEL_HWCAP_SHA512] = "sha512", 59 [KERNEL_HWCAP_SVE] = "sve", 60 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 61 [KERNEL_HWCAP_DIT] = "dit", 62 [KERNEL_HWCAP_USCAT] = "uscat", 63 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 64 [KERNEL_HWCAP_FLAGM] = "flagm", 65 [KERNEL_HWCAP_SSBS] = "ssbs", 66 [KERNEL_HWCAP_SB] = "sb", 67 [KERNEL_HWCAP_PACA] = "paca", 68 [KERNEL_HWCAP_PACG] = "pacg", 69 [KERNEL_HWCAP_GCS] = "gcs", 70 [KERNEL_HWCAP_LS64] = "ls64", 71 [KERNEL_HWCAP_DCPODP] = "dcpodp", 72 [KERNEL_HWCAP_SVE2] = "sve2", 73 [KERNEL_HWCAP_SVEAES] = "sveaes", 74 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 75 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 76 [KERNEL_HWCAP_SVESHA3] = "svesha3", 77 [KERNEL_HWCAP_SVESM4] = "svesm4", 78 [KERNEL_HWCAP_FLAGM2] = "flagm2", 79 [KERNEL_HWCAP_FRINT] = "frint", 80 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 81 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 82 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 83 [KERNEL_HWCAP_SVEBF16] = "svebf16", 84 [KERNEL_HWCAP_I8MM] = "i8mm", 85 [KERNEL_HWCAP_BF16] = "bf16", 86 [KERNEL_HWCAP_DGH] = "dgh", 87 [KERNEL_HWCAP_RNG] = "rng", 88 [KERNEL_HWCAP_BTI] = "bti", 89 [KERNEL_HWCAP_MTE] = "mte", 90 [KERNEL_HWCAP_ECV] = "ecv", 91 [KERNEL_HWCAP_AFP] = "afp", 92 [KERNEL_HWCAP_RPRES] = "rpres", 93 [KERNEL_HWCAP_MTE3] = "mte3", 94 [KERNEL_HWCAP_SME] = "sme", 95 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 96 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 97 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 98 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 99 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 100 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 101 [KERNEL_HWCAP_SME_FA64] = "smefa64", 102 [KERNEL_HWCAP_WFXT] = "wfxt", 103 [KERNEL_HWCAP_EBF16] = "ebf16", 104 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 105 [KERNEL_HWCAP_CSSC] = "cssc", 106 [KERNEL_HWCAP_RPRFM] = "rprfm", 107 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 108 [KERNEL_HWCAP_SME2] = "sme2", 109 [KERNEL_HWCAP_SME2P1] = "sme2p1", 110 [KERNEL_HWCAP_SME_I16I32] = "smei16i32", 111 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", 112 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", 113 [KERNEL_HWCAP_SME_F16F16] = "smef16f16", 114 [KERNEL_HWCAP_MOPS] = "mops", 115 [KERNEL_HWCAP_HBC] = "hbc", 116 [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", 117 [KERNEL_HWCAP_LRCPC3] = "lrcpc3", 118 [KERNEL_HWCAP_LSE128] = "lse128", 119 [KERNEL_HWCAP_FPMR] = "fpmr", 120 [KERNEL_HWCAP_LUT] = "lut", 121 [KERNEL_HWCAP_FAMINMAX] = "faminmax", 122 [KERNEL_HWCAP_F8CVT] = "f8cvt", 123 [KERNEL_HWCAP_F8FMA] = "f8fma", 124 [KERNEL_HWCAP_F8DP4] = "f8dp4", 125 [KERNEL_HWCAP_F8DP2] = "f8dp2", 126 [KERNEL_HWCAP_F8E4M3] = "f8e4m3", 127 [KERNEL_HWCAP_F8E5M2] = "f8e5m2", 128 [KERNEL_HWCAP_SME_LUTV2] = "smelutv2", 129 [KERNEL_HWCAP_SME_F8F16] = "smef8f16", 130 [KERNEL_HWCAP_SME_F8F32] = "smef8f32", 131 [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", 132 [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", 133 [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", 134 [KERNEL_HWCAP_POE] = "poe", 135 [KERNEL_HWCAP_CMPBR] = "cmpbr", 136 [KERNEL_HWCAP_FPRCVT] = "fprcvt", 137 [KERNEL_HWCAP_F8MM8] = "f8mm8", 138 [KERNEL_HWCAP_F8MM4] = "f8mm4", 139 [KERNEL_HWCAP_SVE_F16MM] = "svef16mm", 140 [KERNEL_HWCAP_SVE_ELTPERM] = "sveeltperm", 141 [KERNEL_HWCAP_SVE_AES2] = "sveaes2", 142 [KERNEL_HWCAP_SVE_BFSCALE] = "svebfscale", 143 [KERNEL_HWCAP_SVE2P2] = "sve2p2", 144 [KERNEL_HWCAP_SME2P2] = "sme2p2", 145 [KERNEL_HWCAP_SME_SBITPERM] = "smesbitperm", 146 [KERNEL_HWCAP_SME_AES] = "smeaes", 147 [KERNEL_HWCAP_SME_SFEXPA] = "smesfexpa", 148 [KERNEL_HWCAP_SME_STMOP] = "smestmop", 149 [KERNEL_HWCAP_SME_SMOP4] = "smesmop4", 150 [KERNEL_HWCAP_MTE_FAR] = "mtefar", 151 [KERNEL_HWCAP_MTE_STORE_ONLY] = "mtestoreonly", 152 [KERNEL_HWCAP_LSFE] = "lsfe", 153 [KERNEL_HWCAP_SVE_B16MM] = "sveb16mm", 154 [KERNEL_HWCAP_SVE2P3] = "sve2p3", 155 [KERNEL_HWCAP_SME_LUT6] = "smelut6", 156 [KERNEL_HWCAP_SME2P3] = "sme2p3", 157 [KERNEL_HWCAP_F16MM] = "f16mm", 158 [KERNEL_HWCAP_F16F32DOT] = "f16f32dot", 159 [KERNEL_HWCAP_F16F32MM] = "f16f32mm", 160 [KERNEL_HWCAP_SVE_LUT6] = "svelut6", 161 }; 162 163 #ifdef CONFIG_COMPAT 164 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 165 static const char *const compat_hwcap_str[] = { 166 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 167 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 168 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 169 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 170 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 171 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 172 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 173 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 174 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 175 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 176 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 177 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 178 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 179 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 180 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 181 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 182 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 183 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 184 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 185 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 186 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 187 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 188 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", 189 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", 190 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp", 191 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm", 192 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16", 193 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm", 194 }; 195 196 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 197 static const char *const compat_hwcap2_str[] = { 198 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 199 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 200 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 201 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 202 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 203 [COMPAT_KERNEL_HWCAP2(SB)] = "sb", 204 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", 205 }; 206 #endif /* CONFIG_COMPAT */ 207 208 static int c_show(struct seq_file *m, void *v) 209 { 210 int j; 211 int cpu = m->index; 212 bool compat = personality(current->personality) == PER_LINUX32; 213 struct cpuinfo_arm64 *cpuinfo = v; 214 u32 midr = cpuinfo->reg_midr; 215 216 /* 217 * glibc reads /proc/cpuinfo to determine the number of 218 * online processors, looking for lines beginning with 219 * "processor". Give glibc what it expects. 220 */ 221 seq_printf(m, "processor\t: %d\n", cpu); 222 if (compat) 223 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 224 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 225 226 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 227 loops_per_jiffy / (500000UL/HZ), 228 loops_per_jiffy / (5000UL/HZ) % 100); 229 230 /* 231 * Dump out the common processor features in a single line. 232 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 233 * rather than attempting to parse this, but there's a body of 234 * software which does already (at least for 32-bit). 235 */ 236 seq_puts(m, "Features\t:"); 237 if (compat) { 238 #ifdef CONFIG_COMPAT 239 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 240 if (compat_elf_hwcap & (1 << j)) { 241 /* 242 * Warn once if any feature should not 243 * have been present on arm64 platform. 244 */ 245 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 246 continue; 247 248 seq_printf(m, " %s", compat_hwcap_str[j]); 249 } 250 } 251 252 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 253 if (compat_elf_hwcap2 & (1 << j)) 254 seq_printf(m, " %s", compat_hwcap2_str[j]); 255 #endif /* CONFIG_COMPAT */ 256 } else { 257 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 258 if (cpu_have_feature(j)) 259 seq_printf(m, " %s", hwcap_str[j]); 260 } 261 seq_puts(m, "\n"); 262 263 seq_printf(m, "CPU implementer\t: 0x%02x\n", 264 MIDR_IMPLEMENTOR(midr)); 265 seq_puts(m, "CPU architecture: 8\n"); 266 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 267 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 268 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 269 270 return 0; 271 } 272 273 static void *c_start(struct seq_file *m, loff_t *pos) 274 { 275 *pos = cpumask_next(*pos - 1, cpu_online_mask); 276 return *pos < nr_cpu_ids ? &per_cpu(cpu_data, *pos) : NULL; 277 } 278 279 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 280 { 281 ++*pos; 282 return c_start(m, pos); 283 } 284 285 static void c_stop(struct seq_file *m, void *v) 286 { 287 } 288 289 const struct seq_operations cpuinfo_op = { 290 .start = c_start, 291 .next = c_next, 292 .stop = c_stop, 293 .show = c_show 294 }; 295 296 297 static const struct kobj_type cpuregs_kobj_type = { 298 .sysfs_ops = &kobj_sysfs_ops, 299 }; 300 301 /* 302 * The ARM ARM uses the phrase "32-bit register" to describe a register 303 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 304 * no statement is made as to whether the upper 32 bits will or will not 305 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 306 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 307 * 308 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 309 * registers, we expose them both as 64 bit values to cater for possible 310 * future expansion without an ABI break. 311 */ 312 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 313 #define CPUREGS_ATTR_RO(_name, _field) \ 314 static ssize_t _name##_show(struct kobject *kobj, \ 315 struct kobj_attribute *attr, char *buf) \ 316 { \ 317 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 318 \ 319 if (info->reg_midr) \ 320 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 321 else \ 322 return 0; \ 323 } \ 324 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 325 326 CPUREGS_ATTR_RO(midr_el1, midr); 327 CPUREGS_ATTR_RO(revidr_el1, revidr); 328 CPUREGS_ATTR_RO(aidr_el1, aidr); 329 CPUREGS_ATTR_RO(smidr_el1, smidr); 330 331 static struct attribute *cpuregs_id_attrs[] = { 332 &cpuregs_attr_midr_el1.attr, 333 &cpuregs_attr_revidr_el1.attr, 334 &cpuregs_attr_aidr_el1.attr, 335 NULL 336 }; 337 338 static const struct attribute_group cpuregs_attr_group = { 339 .attrs = cpuregs_id_attrs, 340 .name = "identification" 341 }; 342 343 static struct attribute *sme_cpuregs_id_attrs[] = { 344 &cpuregs_attr_smidr_el1.attr, 345 NULL 346 }; 347 348 static const struct attribute_group sme_cpuregs_attr_group = { 349 .attrs = sme_cpuregs_id_attrs, 350 .name = "identification" 351 }; 352 353 static int cpuid_cpu_online(unsigned int cpu) 354 { 355 int rc; 356 struct device *dev; 357 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 358 359 dev = get_cpu_device(cpu); 360 if (!dev) { 361 rc = -ENODEV; 362 goto out; 363 } 364 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 365 if (rc) 366 goto out; 367 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 368 if (rc) 369 kobject_del(&info->kobj); 370 if (system_supports_sme()) 371 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 372 out: 373 return rc; 374 } 375 376 static int cpuid_cpu_offline(unsigned int cpu) 377 { 378 struct device *dev; 379 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 380 381 dev = get_cpu_device(cpu); 382 if (!dev) 383 return -ENODEV; 384 if (info->kobj.parent) { 385 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 386 kobject_del(&info->kobj); 387 } 388 389 return 0; 390 } 391 392 static int __init cpuinfo_regs_init(void) 393 { 394 int cpu, ret; 395 396 for_each_possible_cpu(cpu) { 397 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 398 399 kobject_init(&info->kobj, &cpuregs_kobj_type); 400 } 401 402 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 403 cpuid_cpu_online, cpuid_cpu_offline); 404 if (ret < 0) { 405 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 406 return ret; 407 } 408 return 0; 409 } 410 device_initcall(cpuinfo_regs_init); 411 412 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 413 { 414 u32 l1ip = CTR_L1IP(info->reg_ctr); 415 416 switch (l1ip) { 417 case CTR_EL0_L1Ip_PIPT: 418 break; 419 case CTR_EL0_L1Ip_VIPT: 420 default: 421 /* Assume aliasing */ 422 set_bit(ICACHEF_ALIASING, &__icache_flags); 423 break; 424 } 425 } 426 427 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 428 { 429 info->reg_id_dfr0 = read_cpuid_with_overrides(ID_DFR0_EL1); 430 info->reg_id_dfr1 = read_cpuid_with_overrides(ID_DFR1_EL1); 431 info->reg_id_isar0 = read_cpuid_with_overrides(ID_ISAR0_EL1); 432 info->reg_id_isar1 = read_cpuid_with_overrides(ID_ISAR1_EL1); 433 info->reg_id_isar2 = read_cpuid_with_overrides(ID_ISAR2_EL1); 434 info->reg_id_isar3 = read_cpuid_with_overrides(ID_ISAR3_EL1); 435 info->reg_id_isar4 = read_cpuid_with_overrides(ID_ISAR4_EL1); 436 info->reg_id_isar5 = read_cpuid_with_overrides(ID_ISAR5_EL1); 437 info->reg_id_isar6 = read_cpuid_with_overrides(ID_ISAR6_EL1); 438 info->reg_id_mmfr0 = read_cpuid_with_overrides(ID_MMFR0_EL1); 439 info->reg_id_mmfr1 = read_cpuid_with_overrides(ID_MMFR1_EL1); 440 info->reg_id_mmfr2 = read_cpuid_with_overrides(ID_MMFR2_EL1); 441 info->reg_id_mmfr3 = read_cpuid_with_overrides(ID_MMFR3_EL1); 442 info->reg_id_mmfr4 = read_cpuid_with_overrides(ID_MMFR4_EL1); 443 info->reg_id_mmfr5 = read_cpuid_with_overrides(ID_MMFR5_EL1); 444 info->reg_id_pfr0 = read_cpuid_with_overrides(ID_PFR0_EL1); 445 info->reg_id_pfr1 = read_cpuid_with_overrides(ID_PFR1_EL1); 446 info->reg_id_pfr2 = read_cpuid_with_overrides(ID_PFR2_EL1); 447 448 info->reg_mvfr0 = read_cpuid_with_overrides(MVFR0_EL1); 449 info->reg_mvfr1 = read_cpuid_with_overrides(MVFR1_EL1); 450 info->reg_mvfr2 = read_cpuid_with_overrides(MVFR2_EL1); 451 } 452 453 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 454 { 455 info->reg_cntfrq = arm64_ftr_reg_override(SYS_CNTFRQ_EL0, arch_timer_get_cntfrq()); 456 /* 457 * Use the effective value of the CTR_EL0 than the raw value 458 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 459 * with the CLIDR_EL1 fields to avoid triggering false warnings 460 * when there is a mismatch across the CPUs. Keep track of the 461 * effective value of the CTR_EL0 in our internal records for 462 * accurate sanity check and feature enablement. 463 */ 464 info->reg_ctr = arm64_ftr_reg_override(SYS_CTR_EL0, read_cpuid_effective_cachetype()); 465 info->reg_dczid = read_cpuid_with_overrides(DCZID_EL0); 466 info->reg_midr = read_cpuid_id(); 467 info->reg_revidr = read_cpuid(REVIDR_EL1); 468 info->reg_aidr = read_cpuid(AIDR_EL1); 469 470 info->reg_id_aa64dfr0 = read_cpuid_with_overrides(ID_AA64DFR0_EL1); 471 info->reg_id_aa64dfr1 = read_cpuid_with_overrides(ID_AA64DFR1_EL1); 472 info->reg_id_aa64isar0 = read_cpuid_with_overrides(ID_AA64ISAR0_EL1); 473 info->reg_id_aa64isar1 = read_cpuid_with_overrides(ID_AA64ISAR1_EL1); 474 info->reg_id_aa64isar2 = read_cpuid_with_overrides(ID_AA64ISAR2_EL1); 475 info->reg_id_aa64isar3 = read_cpuid_with_overrides(ID_AA64ISAR3_EL1); 476 info->reg_id_aa64mmfr0 = read_cpuid_with_overrides(ID_AA64MMFR0_EL1); 477 info->reg_id_aa64mmfr1 = read_cpuid_with_overrides(ID_AA64MMFR1_EL1); 478 info->reg_id_aa64mmfr2 = read_cpuid_with_overrides(ID_AA64MMFR2_EL1); 479 info->reg_id_aa64mmfr3 = read_cpuid_with_overrides(ID_AA64MMFR3_EL1); 480 info->reg_id_aa64mmfr4 = read_cpuid_with_overrides(ID_AA64MMFR4_EL1); 481 info->reg_id_aa64pfr0 = read_cpuid_with_overrides(ID_AA64PFR0_EL1); 482 info->reg_id_aa64pfr1 = read_cpuid_with_overrides(ID_AA64PFR1_EL1); 483 info->reg_id_aa64pfr2 = read_cpuid_with_overrides(ID_AA64PFR2_EL1); 484 info->reg_id_aa64zfr0 = read_cpuid_with_overrides(ID_AA64ZFR0_EL1); 485 info->reg_id_aa64smfr0 = read_cpuid_with_overrides(ID_AA64SMFR0_EL1); 486 info->reg_id_aa64fpfr0 = read_cpuid_with_overrides(ID_AA64FPFR0_EL1); 487 488 if (IS_ENABLED(CONFIG_ARM64_MTE) && id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 489 info->reg_gmid = read_cpuid_with_overrides(GMID_EL1); 490 491 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0) || id_aa64pfr1_mpamfrac(info->reg_id_aa64pfr1)) 492 info->reg_mpamidr = read_cpuid_with_overrides(MPAMIDR_EL1); 493 494 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 495 __cpuinfo_store_cpu_32bit(&info->aarch32); 496 497 if (IS_ENABLED(CONFIG_ARM64_SME) && 498 id_aa64pfr1_sme(info->reg_id_aa64pfr1)) { 499 /* 500 * We mask out SMPS since even if the hardware 501 * supports priorities the kernel does not at present 502 * and we block access to them. 503 */ 504 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 505 } 506 507 cpuinfo_detect_icache_policy(info); 508 } 509 510 void cpuinfo_store_cpu(void) 511 { 512 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 513 __cpuinfo_store_cpu(info); 514 } 515