1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 #include <asm/arch_timer.h> 8 #include <asm/cache.h> 9 #include <asm/cpu.h> 10 #include <asm/cputype.h> 11 #include <asm/cpufeature.h> 12 #include <asm/fpsimd.h> 13 14 #include <linux/bitops.h> 15 #include <linux/bug.h> 16 #include <linux/compat.h> 17 #include <linux/elf.h> 18 #include <linux/init.h> 19 #include <linux/kernel.h> 20 #include <linux/personality.h> 21 #include <linux/preempt.h> 22 #include <linux/printk.h> 23 #include <linux/seq_file.h> 24 #include <linux/sched.h> 25 #include <linux/smp.h> 26 #include <linux/delay.h> 27 28 /* 29 * In case the boot CPU is hotpluggable, we record its initial state and 30 * current state separately. Certain system registers may contain different 31 * values depending on configuration at or after reset. 32 */ 33 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 34 static struct cpuinfo_arm64 boot_cpu_data; 35 36 static inline const char *icache_policy_str(int l1ip) 37 { 38 switch (l1ip) { 39 case CTR_EL0_L1Ip_VIPT: 40 return "VIPT"; 41 case CTR_EL0_L1Ip_PIPT: 42 return "PIPT"; 43 default: 44 return "RESERVED/UNKNOWN"; 45 } 46 } 47 48 unsigned long __icache_flags; 49 50 static const char *const hwcap_str[] = { 51 [KERNEL_HWCAP_FP] = "fp", 52 [KERNEL_HWCAP_ASIMD] = "asimd", 53 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 54 [KERNEL_HWCAP_AES] = "aes", 55 [KERNEL_HWCAP_PMULL] = "pmull", 56 [KERNEL_HWCAP_SHA1] = "sha1", 57 [KERNEL_HWCAP_SHA2] = "sha2", 58 [KERNEL_HWCAP_CRC32] = "crc32", 59 [KERNEL_HWCAP_ATOMICS] = "atomics", 60 [KERNEL_HWCAP_FPHP] = "fphp", 61 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 62 [KERNEL_HWCAP_CPUID] = "cpuid", 63 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 64 [KERNEL_HWCAP_JSCVT] = "jscvt", 65 [KERNEL_HWCAP_FCMA] = "fcma", 66 [KERNEL_HWCAP_LRCPC] = "lrcpc", 67 [KERNEL_HWCAP_DCPOP] = "dcpop", 68 [KERNEL_HWCAP_SHA3] = "sha3", 69 [KERNEL_HWCAP_SM3] = "sm3", 70 [KERNEL_HWCAP_SM4] = "sm4", 71 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 72 [KERNEL_HWCAP_SHA512] = "sha512", 73 [KERNEL_HWCAP_SVE] = "sve", 74 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 75 [KERNEL_HWCAP_DIT] = "dit", 76 [KERNEL_HWCAP_USCAT] = "uscat", 77 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 78 [KERNEL_HWCAP_FLAGM] = "flagm", 79 [KERNEL_HWCAP_SSBS] = "ssbs", 80 [KERNEL_HWCAP_SB] = "sb", 81 [KERNEL_HWCAP_PACA] = "paca", 82 [KERNEL_HWCAP_PACG] = "pacg", 83 [KERNEL_HWCAP_DCPODP] = "dcpodp", 84 [KERNEL_HWCAP_SVE2] = "sve2", 85 [KERNEL_HWCAP_SVEAES] = "sveaes", 86 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 87 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 88 [KERNEL_HWCAP_SVESHA3] = "svesha3", 89 [KERNEL_HWCAP_SVESM4] = "svesm4", 90 [KERNEL_HWCAP_FLAGM2] = "flagm2", 91 [KERNEL_HWCAP_FRINT] = "frint", 92 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 93 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 94 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 95 [KERNEL_HWCAP_SVEBF16] = "svebf16", 96 [KERNEL_HWCAP_I8MM] = "i8mm", 97 [KERNEL_HWCAP_BF16] = "bf16", 98 [KERNEL_HWCAP_DGH] = "dgh", 99 [KERNEL_HWCAP_RNG] = "rng", 100 [KERNEL_HWCAP_BTI] = "bti", 101 [KERNEL_HWCAP_MTE] = "mte", 102 [KERNEL_HWCAP_ECV] = "ecv", 103 [KERNEL_HWCAP_AFP] = "afp", 104 [KERNEL_HWCAP_RPRES] = "rpres", 105 [KERNEL_HWCAP_MTE3] = "mte3", 106 [KERNEL_HWCAP_SME] = "sme", 107 [KERNEL_HWCAP_SME_I16I64] = "smei16i64", 108 [KERNEL_HWCAP_SME_F64F64] = "smef64f64", 109 [KERNEL_HWCAP_SME_I8I32] = "smei8i32", 110 [KERNEL_HWCAP_SME_F16F32] = "smef16f32", 111 [KERNEL_HWCAP_SME_B16F32] = "smeb16f32", 112 [KERNEL_HWCAP_SME_F32F32] = "smef32f32", 113 [KERNEL_HWCAP_SME_FA64] = "smefa64", 114 [KERNEL_HWCAP_WFXT] = "wfxt", 115 [KERNEL_HWCAP_EBF16] = "ebf16", 116 [KERNEL_HWCAP_SVE_EBF16] = "sveebf16", 117 [KERNEL_HWCAP_CSSC] = "cssc", 118 [KERNEL_HWCAP_RPRFM] = "rprfm", 119 [KERNEL_HWCAP_SVE2P1] = "sve2p1", 120 [KERNEL_HWCAP_SME2] = "sme2", 121 [KERNEL_HWCAP_SME2P1] = "sme2p1", 122 [KERNEL_HWCAP_SME_I16I32] = "smei16i32", 123 [KERNEL_HWCAP_SME_BI32I32] = "smebi32i32", 124 [KERNEL_HWCAP_SME_B16B16] = "smeb16b16", 125 [KERNEL_HWCAP_SME_F16F16] = "smef16f16", 126 [KERNEL_HWCAP_MOPS] = "mops", 127 [KERNEL_HWCAP_HBC] = "hbc", 128 [KERNEL_HWCAP_SVE_B16B16] = "sveb16b16", 129 [KERNEL_HWCAP_LRCPC3] = "lrcpc3", 130 [KERNEL_HWCAP_LSE128] = "lse128", 131 }; 132 133 #ifdef CONFIG_COMPAT 134 #define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_ ## x) 135 static const char *const compat_hwcap_str[] = { 136 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 137 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 138 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 139 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 140 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 141 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 142 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 143 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 144 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 145 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 146 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 147 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 148 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 149 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 150 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 151 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 152 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 153 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 154 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 155 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 156 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 157 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 158 [COMPAT_KERNEL_HWCAP(FPHP)] = "fphp", 159 [COMPAT_KERNEL_HWCAP(ASIMDHP)] = "asimdhp", 160 [COMPAT_KERNEL_HWCAP(ASIMDDP)] = "asimddp", 161 [COMPAT_KERNEL_HWCAP(ASIMDFHM)] = "asimdfhm", 162 [COMPAT_KERNEL_HWCAP(ASIMDBF16)] = "asimdbf16", 163 [COMPAT_KERNEL_HWCAP(I8MM)] = "i8mm", 164 }; 165 166 #define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_ ## x) 167 static const char *const compat_hwcap2_str[] = { 168 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", 169 [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 170 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", 171 [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 172 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 173 [COMPAT_KERNEL_HWCAP2(SB)] = "sb", 174 [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", 175 }; 176 #endif /* CONFIG_COMPAT */ 177 178 static int c_show(struct seq_file *m, void *v) 179 { 180 int i, j; 181 bool compat = personality(current->personality) == PER_LINUX32; 182 183 for_each_online_cpu(i) { 184 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 185 u32 midr = cpuinfo->reg_midr; 186 187 /* 188 * glibc reads /proc/cpuinfo to determine the number of 189 * online processors, looking for lines beginning with 190 * "processor". Give glibc what it expects. 191 */ 192 seq_printf(m, "processor\t: %d\n", i); 193 if (compat) 194 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", 195 MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 196 197 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", 198 loops_per_jiffy / (500000UL/HZ), 199 loops_per_jiffy / (5000UL/HZ) % 100); 200 201 /* 202 * Dump out the common processor features in a single line. 203 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 204 * rather than attempting to parse this, but there's a body of 205 * software which does already (at least for 32-bit). 206 */ 207 seq_puts(m, "Features\t:"); 208 if (compat) { 209 #ifdef CONFIG_COMPAT 210 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 211 if (compat_elf_hwcap & (1 << j)) { 212 /* 213 * Warn once if any feature should not 214 * have been present on arm64 platform. 215 */ 216 if (WARN_ON_ONCE(!compat_hwcap_str[j])) 217 continue; 218 219 seq_printf(m, " %s", compat_hwcap_str[j]); 220 } 221 } 222 223 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) 224 if (compat_elf_hwcap2 & (1 << j)) 225 seq_printf(m, " %s", compat_hwcap2_str[j]); 226 #endif /* CONFIG_COMPAT */ 227 } else { 228 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) 229 if (cpu_have_feature(j)) 230 seq_printf(m, " %s", hwcap_str[j]); 231 } 232 seq_puts(m, "\n"); 233 234 seq_printf(m, "CPU implementer\t: 0x%02x\n", 235 MIDR_IMPLEMENTOR(midr)); 236 seq_printf(m, "CPU architecture: 8\n"); 237 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 238 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 239 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 240 } 241 242 return 0; 243 } 244 245 static void *c_start(struct seq_file *m, loff_t *pos) 246 { 247 return *pos < 1 ? (void *)1 : NULL; 248 } 249 250 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 251 { 252 ++*pos; 253 return NULL; 254 } 255 256 static void c_stop(struct seq_file *m, void *v) 257 { 258 } 259 260 const struct seq_operations cpuinfo_op = { 261 .start = c_start, 262 .next = c_next, 263 .stop = c_stop, 264 .show = c_show 265 }; 266 267 268 static struct kobj_type cpuregs_kobj_type = { 269 .sysfs_ops = &kobj_sysfs_ops, 270 }; 271 272 /* 273 * The ARM ARM uses the phrase "32-bit register" to describe a register 274 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 275 * no statement is made as to whether the upper 32 bits will or will not 276 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 277 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 278 * 279 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 280 * registers, we expose them both as 64 bit values to cater for possible 281 * future expansion without an ABI break. 282 */ 283 #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 284 #define CPUREGS_ATTR_RO(_name, _field) \ 285 static ssize_t _name##_show(struct kobject *kobj, \ 286 struct kobj_attribute *attr, char *buf) \ 287 { \ 288 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 289 \ 290 if (info->reg_midr) \ 291 return sprintf(buf, "0x%016llx\n", info->reg_##_field); \ 292 else \ 293 return 0; \ 294 } \ 295 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 296 297 CPUREGS_ATTR_RO(midr_el1, midr); 298 CPUREGS_ATTR_RO(revidr_el1, revidr); 299 CPUREGS_ATTR_RO(smidr_el1, smidr); 300 301 static struct attribute *cpuregs_id_attrs[] = { 302 &cpuregs_attr_midr_el1.attr, 303 &cpuregs_attr_revidr_el1.attr, 304 NULL 305 }; 306 307 static const struct attribute_group cpuregs_attr_group = { 308 .attrs = cpuregs_id_attrs, 309 .name = "identification" 310 }; 311 312 static struct attribute *sme_cpuregs_id_attrs[] = { 313 &cpuregs_attr_smidr_el1.attr, 314 NULL 315 }; 316 317 static const struct attribute_group sme_cpuregs_attr_group = { 318 .attrs = sme_cpuregs_id_attrs, 319 .name = "identification" 320 }; 321 322 static int cpuid_cpu_online(unsigned int cpu) 323 { 324 int rc; 325 struct device *dev; 326 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 327 328 dev = get_cpu_device(cpu); 329 if (!dev) { 330 rc = -ENODEV; 331 goto out; 332 } 333 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 334 if (rc) 335 goto out; 336 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 337 if (rc) 338 kobject_del(&info->kobj); 339 if (system_supports_sme()) 340 rc = sysfs_merge_group(&info->kobj, &sme_cpuregs_attr_group); 341 out: 342 return rc; 343 } 344 345 static int cpuid_cpu_offline(unsigned int cpu) 346 { 347 struct device *dev; 348 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 349 350 dev = get_cpu_device(cpu); 351 if (!dev) 352 return -ENODEV; 353 if (info->kobj.parent) { 354 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 355 kobject_del(&info->kobj); 356 } 357 358 return 0; 359 } 360 361 static int __init cpuinfo_regs_init(void) 362 { 363 int cpu, ret; 364 365 for_each_possible_cpu(cpu) { 366 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 367 368 kobject_init(&info->kobj, &cpuregs_kobj_type); 369 } 370 371 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", 372 cpuid_cpu_online, cpuid_cpu_offline); 373 if (ret < 0) { 374 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 375 return ret; 376 } 377 return 0; 378 } 379 device_initcall(cpuinfo_regs_init); 380 381 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 382 { 383 unsigned int cpu = smp_processor_id(); 384 u32 l1ip = CTR_L1IP(info->reg_ctr); 385 386 switch (l1ip) { 387 case CTR_EL0_L1Ip_PIPT: 388 break; 389 case CTR_EL0_L1Ip_VIPT: 390 default: 391 /* Assume aliasing */ 392 set_bit(ICACHEF_ALIASING, &__icache_flags); 393 break; 394 } 395 396 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str(l1ip), cpu); 397 } 398 399 static void __cpuinfo_store_cpu_32bit(struct cpuinfo_32bit *info) 400 { 401 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 402 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 403 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 404 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 405 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 406 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 407 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 408 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 409 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 410 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 411 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 412 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 413 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 414 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 415 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 416 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 417 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 418 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 419 420 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 421 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 422 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 423 } 424 425 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 426 { 427 info->reg_cntfrq = arch_timer_get_cntfrq(); 428 /* 429 * Use the effective value of the CTR_EL0 than the raw value 430 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 431 * with the CLIDR_EL1 fields to avoid triggering false warnings 432 * when there is a mismatch across the CPUs. Keep track of the 433 * effective value of the CTR_EL0 in our internal records for 434 * accurate sanity check and feature enablement. 435 */ 436 info->reg_ctr = read_cpuid_effective_cachetype(); 437 info->reg_dczid = read_cpuid(DCZID_EL0); 438 info->reg_midr = read_cpuid_id(); 439 info->reg_revidr = read_cpuid(REVIDR_EL1); 440 441 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 442 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 443 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 444 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 445 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 446 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 447 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 448 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 449 info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); 450 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 451 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 452 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 453 info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); 454 455 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 456 info->reg_gmid = read_cpuid(GMID_EL1); 457 458 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 459 __cpuinfo_store_cpu_32bit(&info->aarch32); 460 461 cpuinfo_detect_icache_policy(info); 462 } 463 464 void cpuinfo_store_cpu(void) 465 { 466 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 467 __cpuinfo_store_cpu(info); 468 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 469 } 470 471 void __init cpuinfo_store_boot_cpu(void) 472 { 473 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 474 __cpuinfo_store_cpu(info); 475 476 boot_cpu_data = *info; 477 init_cpu_features(&boot_cpu_data); 478 } 479