1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 144 .sys_reg = SYS_##reg, \ 145 .field_pos = reg##_##field##_SHIFT, \ 146 .field_width = reg##_##field##_WIDTH, \ 147 .sign = reg##_##field##_SIGNED, \ 148 .min_field_value = reg##_##field##_##min_value, 149 150 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 { \ 152 .sign = SIGNED, \ 153 .visible = VISIBLE, \ 154 .strict = STRICT, \ 155 .type = TYPE, \ 156 .shift = SHIFT, \ 157 .width = WIDTH, \ 158 .safe_val = SAFE_VAL, \ 159 } 160 161 /* Define a feature with unsigned values */ 162 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 163 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 164 165 /* Define a feature with a signed value */ 166 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 167 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 168 169 #define ARM64_FTR_END \ 170 { \ 171 .width = 0, \ 172 } 173 174 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 175 176 static bool __system_matches_cap(unsigned int n); 177 178 /* 179 * NOTE: Any changes to the visibility of features should be kept in 180 * sync with the documentation of the CPU feature register ABI. 181 */ 182 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 183 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 197 ARM64_FTR_END, 198 }; 199 200 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 207 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 208 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 210 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 215 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 217 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 219 ARM64_FTR_END, 220 }; 221 222 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 230 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 232 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 235 ARM64_FTR_END, 236 }; 237 238 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 240 ARM64_FTR_END, 241 }; 242 243 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 254 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 255 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_ELx_64BIT_ONLY), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 269 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 273 ARM64_FTR_END, 274 }; 275 276 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 277 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 278 ARM64_FTR_END, 279 }; 280 281 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 285 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 287 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 289 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 291 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 295 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 297 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 301 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 307 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 308 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 309 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 311 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 313 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 315 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 317 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 319 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 321 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 323 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 325 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 327 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 329 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 331 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 333 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 335 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 337 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 339 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 342 ARM64_FTR_END, 343 }; 344 345 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 346 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 352 ARM64_FTR_END, 353 }; 354 355 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 356 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 359 /* 360 * Page size not being supported at Stage-2 is not fatal. You 361 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 362 * your favourite nesting hypervisor. 363 * 364 * There is a small corner case where the hypervisor explicitly 365 * advertises a given granule size at Stage-2 (value 2) on some 366 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 367 * vCPUs. Although this is not forbidden by the architecture, it 368 * indicates that the hypervisor is being silly (or buggy). 369 * 370 * We make no effort to cope with this and pretend that if these 371 * fields are inconsistent across vCPUs, then it isn't worth 372 * trying to bring KVM up. 373 */ 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 377 /* 378 * We already refuse to boot CPUs that don't support our configured 379 * page size, so we can only detect mismatches for a page size other 380 * than the one we're currently using. Unfortunately, SoCs like this 381 * exist in the wild so, even though we don't like it, we'll have to go 382 * along with it and treat them as non-strict. 383 */ 384 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 387 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 389 /* Linux shouldn't care about secure memory */ 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 393 /* 394 * Differing PARange is fine as long as all peripherals and memory are mapped 395 * within the minimum PARange of all CPUs 396 */ 397 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 398 ARM64_FTR_END, 399 }; 400 401 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 434 ARM64_FTR_END, 435 }; 436 437 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 440 ARM64_FTR_END, 441 }; 442 443 static const struct arm64_ftr_bits ftr_ctr[] = { 444 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 445 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 446 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 447 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 450 /* 451 * Linux can handle differing I-cache policies. Userspace JITs will 452 * make use of *minLine. 453 * If we have differing I-cache policies, report it as the weakest - VIPT. 454 */ 455 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 457 ARM64_FTR_END, 458 }; 459 460 static struct arm64_ftr_override __ro_after_init no_override = { }; 461 462 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 463 .name = "SYS_CTR_EL0", 464 .ftr_bits = ftr_ctr, 465 .override = &no_override, 466 }; 467 468 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 469 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 474 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 481 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 486 /* 487 * We can instantiate multiple PMU instances with different levels 488 * of support. 489 */ 490 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_mvfr0[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 504 ARM64_FTR_END, 505 }; 506 507 static const struct arm64_ftr_bits ftr_mvfr1[] = { 508 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static const struct arm64_ftr_bits ftr_mvfr2[] = { 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_dczid[] = { 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 527 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static const struct arm64_ftr_bits ftr_gmid[] = { 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 533 ARM64_FTR_END, 534 }; 535 536 static const struct arm64_ftr_bits ftr_id_isar0[] = { 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 544 ARM64_FTR_END, 545 }; 546 547 static const struct arm64_ftr_bits ftr_id_isar5[] = { 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 554 ARM64_FTR_END, 555 }; 556 557 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 565 566 /* 567 * SpecSEI = 1 indicates that the PE might generate an SError on an 568 * external abort on speculative read. It is safe to assume that an 569 * SError might be generated than it will not be. Hence it has been 570 * classified as FTR_HIGHER_SAFE. 571 */ 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 573 ARM64_FTR_END, 574 }; 575 576 static const struct arm64_ftr_bits ftr_id_isar4[] = { 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 585 ARM64_FTR_END, 586 }; 587 588 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_id_isar6[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 601 ARM64_FTR_END, 602 }; 603 604 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 611 ARM64_FTR_END, 612 }; 613 614 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 623 ARM64_FTR_END, 624 }; 625 626 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 627 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 629 ARM64_FTR_END, 630 }; 631 632 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 633 /* [31:28] TraceFilt */ 634 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 641 ARM64_FTR_END, 642 }; 643 644 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 645 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 646 ARM64_FTR_END, 647 }; 648 649 /* 650 * Common ftr bits for a 32bit register with all hidden, strict 651 * attributes, with 4bit feature fields and a default safe value of 652 * 0. Covers the following 32bit registers: 653 * id_isar[1-3], id_mmfr[1-3] 654 */ 655 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 664 ARM64_FTR_END, 665 }; 666 667 /* Table for a single 32bit feature value */ 668 static const struct arm64_ftr_bits ftr_single32[] = { 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 670 ARM64_FTR_END, 671 }; 672 673 static const struct arm64_ftr_bits ftr_raz[] = { 674 ARM64_FTR_END, 675 }; 676 677 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 678 .sys_id = id, \ 679 .reg = &(struct arm64_ftr_reg){ \ 680 .name = id_str, \ 681 .override = (ovr), \ 682 .ftr_bits = &((table)[0]), \ 683 }} 684 685 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 686 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 687 688 #define ARM64_FTR_REG(id, table) \ 689 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 690 691 struct arm64_ftr_override id_aa64mmfr0_override; 692 struct arm64_ftr_override id_aa64mmfr1_override; 693 struct arm64_ftr_override id_aa64mmfr2_override; 694 struct arm64_ftr_override id_aa64pfr0_override; 695 struct arm64_ftr_override id_aa64pfr1_override; 696 struct arm64_ftr_override id_aa64zfr0_override; 697 struct arm64_ftr_override id_aa64smfr0_override; 698 struct arm64_ftr_override id_aa64isar1_override; 699 struct arm64_ftr_override id_aa64isar2_override; 700 701 struct arm64_ftr_override arm64_sw_feature_override; 702 703 static const struct __ftr_reg_entry { 704 u32 sys_id; 705 struct arm64_ftr_reg *reg; 706 } arm64_ftr_regs[] = { 707 708 /* Op1 = 0, CRn = 0, CRm = 1 */ 709 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 710 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 711 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 712 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 713 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 714 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 715 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 716 717 /* Op1 = 0, CRn = 0, CRm = 2 */ 718 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 719 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 720 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 721 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 722 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 723 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 724 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 725 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 726 727 /* Op1 = 0, CRn = 0, CRm = 3 */ 728 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 729 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 730 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 731 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 732 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 733 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 734 735 /* Op1 = 0, CRn = 0, CRm = 4 */ 736 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 737 &id_aa64pfr0_override), 738 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 739 &id_aa64pfr1_override), 740 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 741 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 742 &id_aa64zfr0_override), 743 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 744 &id_aa64smfr0_override), 745 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 746 747 /* Op1 = 0, CRn = 0, CRm = 5 */ 748 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 749 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 750 751 /* Op1 = 0, CRn = 0, CRm = 6 */ 752 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 753 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 754 &id_aa64isar1_override), 755 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 756 &id_aa64isar2_override), 757 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 758 759 /* Op1 = 0, CRn = 0, CRm = 7 */ 760 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 761 &id_aa64mmfr0_override), 762 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 763 &id_aa64mmfr1_override), 764 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 765 &id_aa64mmfr2_override), 766 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 767 768 /* Op1 = 1, CRn = 0, CRm = 0 */ 769 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 770 771 /* Op1 = 3, CRn = 0, CRm = 0 */ 772 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 773 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 774 775 /* Op1 = 3, CRn = 14, CRm = 0 */ 776 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 777 }; 778 779 static int search_cmp_ftr_reg(const void *id, const void *regp) 780 { 781 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 782 } 783 784 /* 785 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 786 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 787 * ascending order of sys_id, we use binary search to find a matching 788 * entry. 789 * 790 * returns - Upon success, matching ftr_reg entry for id. 791 * - NULL on failure. It is upto the caller to decide 792 * the impact of a failure. 793 */ 794 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 795 { 796 const struct __ftr_reg_entry *ret; 797 798 ret = bsearch((const void *)(unsigned long)sys_id, 799 arm64_ftr_regs, 800 ARRAY_SIZE(arm64_ftr_regs), 801 sizeof(arm64_ftr_regs[0]), 802 search_cmp_ftr_reg); 803 if (ret) 804 return ret->reg; 805 return NULL; 806 } 807 808 /* 809 * get_arm64_ftr_reg - Looks up a feature register entry using 810 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 811 * 812 * returns - Upon success, matching ftr_reg entry for id. 813 * - NULL on failure but with an WARN_ON(). 814 */ 815 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 816 { 817 struct arm64_ftr_reg *reg; 818 819 reg = get_arm64_ftr_reg_nowarn(sys_id); 820 821 /* 822 * Requesting a non-existent register search is an error. Warn 823 * and let the caller handle it. 824 */ 825 WARN_ON(!reg); 826 return reg; 827 } 828 829 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 830 s64 ftr_val) 831 { 832 u64 mask = arm64_ftr_mask(ftrp); 833 834 reg &= ~mask; 835 reg |= (ftr_val << ftrp->shift) & mask; 836 return reg; 837 } 838 839 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 840 s64 cur) 841 { 842 s64 ret = 0; 843 844 switch (ftrp->type) { 845 case FTR_EXACT: 846 ret = ftrp->safe_val; 847 break; 848 case FTR_LOWER_SAFE: 849 ret = min(new, cur); 850 break; 851 case FTR_HIGHER_OR_ZERO_SAFE: 852 if (!cur || !new) 853 break; 854 fallthrough; 855 case FTR_HIGHER_SAFE: 856 ret = max(new, cur); 857 break; 858 default: 859 BUG(); 860 } 861 862 return ret; 863 } 864 865 static void __init sort_ftr_regs(void) 866 { 867 unsigned int i; 868 869 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 870 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 871 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 872 unsigned int j = 0; 873 874 /* 875 * Features here must be sorted in descending order with respect 876 * to their shift values and should not overlap with each other. 877 */ 878 for (; ftr_bits->width != 0; ftr_bits++, j++) { 879 unsigned int width = ftr_reg->ftr_bits[j].width; 880 unsigned int shift = ftr_reg->ftr_bits[j].shift; 881 unsigned int prev_shift; 882 883 WARN((shift + width) > 64, 884 "%s has invalid feature at shift %d\n", 885 ftr_reg->name, shift); 886 887 /* 888 * Skip the first feature. There is nothing to 889 * compare against for now. 890 */ 891 if (j == 0) 892 continue; 893 894 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 895 WARN((shift + width) > prev_shift, 896 "%s has feature overlap at shift %d\n", 897 ftr_reg->name, shift); 898 } 899 900 /* 901 * Skip the first register. There is nothing to 902 * compare against for now. 903 */ 904 if (i == 0) 905 continue; 906 /* 907 * Registers here must be sorted in ascending order with respect 908 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 909 * to work correctly. 910 */ 911 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 912 } 913 } 914 915 /* 916 * Initialise the CPU feature register from Boot CPU values. 917 * Also initiliases the strict_mask for the register. 918 * Any bits that are not covered by an arm64_ftr_bits entry are considered 919 * RES0 for the system-wide value, and must strictly match. 920 */ 921 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 922 { 923 u64 val = 0; 924 u64 strict_mask = ~0x0ULL; 925 u64 user_mask = 0; 926 u64 valid_mask = 0; 927 928 const struct arm64_ftr_bits *ftrp; 929 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 930 931 if (!reg) 932 return; 933 934 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 935 u64 ftr_mask = arm64_ftr_mask(ftrp); 936 s64 ftr_new = arm64_ftr_value(ftrp, new); 937 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 938 939 if ((ftr_mask & reg->override->mask) == ftr_mask) { 940 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 941 char *str = NULL; 942 943 if (ftr_ovr != tmp) { 944 /* Unsafe, remove the override */ 945 reg->override->mask &= ~ftr_mask; 946 reg->override->val &= ~ftr_mask; 947 tmp = ftr_ovr; 948 str = "ignoring override"; 949 } else if (ftr_new != tmp) { 950 /* Override was valid */ 951 ftr_new = tmp; 952 str = "forced"; 953 } else if (ftr_ovr == tmp) { 954 /* Override was the safe value */ 955 str = "already set"; 956 } 957 958 if (str) 959 pr_warn("%s[%d:%d]: %s to %llx\n", 960 reg->name, 961 ftrp->shift + ftrp->width - 1, 962 ftrp->shift, str, tmp); 963 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 964 reg->override->val &= ~ftr_mask; 965 pr_warn("%s[%d:%d]: impossible override, ignored\n", 966 reg->name, 967 ftrp->shift + ftrp->width - 1, 968 ftrp->shift); 969 } 970 971 val = arm64_ftr_set_value(ftrp, val, ftr_new); 972 973 valid_mask |= ftr_mask; 974 if (!ftrp->strict) 975 strict_mask &= ~ftr_mask; 976 if (ftrp->visible) 977 user_mask |= ftr_mask; 978 else 979 reg->user_val = arm64_ftr_set_value(ftrp, 980 reg->user_val, 981 ftrp->safe_val); 982 } 983 984 val &= valid_mask; 985 986 reg->sys_val = val; 987 reg->strict_mask = strict_mask; 988 reg->user_mask = user_mask; 989 } 990 991 extern const struct arm64_cpu_capabilities arm64_errata[]; 992 static const struct arm64_cpu_capabilities arm64_features[]; 993 994 static void __init 995 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 996 { 997 for (; caps->matches; caps++) { 998 if (WARN(caps->capability >= ARM64_NCAPS, 999 "Invalid capability %d\n", caps->capability)) 1000 continue; 1001 if (WARN(cpucap_ptrs[caps->capability], 1002 "Duplicate entry for capability %d\n", 1003 caps->capability)) 1004 continue; 1005 cpucap_ptrs[caps->capability] = caps; 1006 } 1007 } 1008 1009 static void __init init_cpucap_indirect_list(void) 1010 { 1011 init_cpucap_indirect_list_from_array(arm64_features); 1012 init_cpucap_indirect_list_from_array(arm64_errata); 1013 } 1014 1015 static void __init setup_boot_cpu_capabilities(void); 1016 1017 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1018 { 1019 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1020 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1021 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1022 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1023 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1024 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1025 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1026 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1027 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1028 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1029 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1030 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1031 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1032 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1033 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1034 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1035 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1036 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1037 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1038 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1039 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1040 } 1041 1042 #ifdef CONFIG_ARM64_PSEUDO_NMI 1043 static bool enable_pseudo_nmi; 1044 1045 static int __init early_enable_pseudo_nmi(char *p) 1046 { 1047 return kstrtobool(p, &enable_pseudo_nmi); 1048 } 1049 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1050 1051 static __init void detect_system_supports_pseudo_nmi(void) 1052 { 1053 struct device_node *np; 1054 1055 if (!enable_pseudo_nmi) 1056 return; 1057 1058 /* 1059 * Detect broken MediaTek firmware that doesn't properly save and 1060 * restore GIC priorities. 1061 */ 1062 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1063 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1064 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1065 enable_pseudo_nmi = false; 1066 } 1067 of_node_put(np); 1068 } 1069 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1070 static inline void detect_system_supports_pseudo_nmi(void) { } 1071 #endif 1072 1073 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1074 { 1075 /* Before we start using the tables, make sure it is sorted */ 1076 sort_ftr_regs(); 1077 1078 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1079 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1080 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1081 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1082 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1083 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1084 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1085 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1086 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1087 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1088 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1089 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1090 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1091 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1092 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1093 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1094 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1095 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1096 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1097 1098 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1099 init_32bit_cpu_features(&info->aarch32); 1100 1101 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1102 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1103 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1104 1105 vec_init_vq_map(ARM64_VEC_SVE); 1106 1107 cpacr_restore(cpacr); 1108 } 1109 1110 if (IS_ENABLED(CONFIG_ARM64_SME) && 1111 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1112 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1113 1114 /* 1115 * We mask out SMPS since even if the hardware 1116 * supports priorities the kernel does not at present 1117 * and we block access to them. 1118 */ 1119 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1120 vec_init_vq_map(ARM64_VEC_SME); 1121 1122 cpacr_restore(cpacr); 1123 } 1124 1125 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1126 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1127 } 1128 1129 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1130 { 1131 const struct arm64_ftr_bits *ftrp; 1132 1133 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1134 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1135 s64 ftr_new = arm64_ftr_value(ftrp, new); 1136 1137 if (ftr_cur == ftr_new) 1138 continue; 1139 /* Find a safe value */ 1140 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1141 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1142 } 1143 1144 } 1145 1146 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1147 { 1148 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1149 1150 if (!regp) 1151 return 0; 1152 1153 update_cpu_ftr_reg(regp, val); 1154 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1155 return 0; 1156 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1157 regp->name, boot, cpu, val); 1158 return 1; 1159 } 1160 1161 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1162 { 1163 const struct arm64_ftr_bits *ftrp; 1164 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1165 1166 if (!regp) 1167 return; 1168 1169 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1170 if (ftrp->shift == field) { 1171 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1172 break; 1173 } 1174 } 1175 1176 /* Bogus field? */ 1177 WARN_ON(!ftrp->width); 1178 } 1179 1180 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1181 struct cpuinfo_arm64 *boot) 1182 { 1183 static bool boot_cpu_32bit_regs_overridden = false; 1184 1185 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1186 return; 1187 1188 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1189 return; 1190 1191 boot->aarch32 = info->aarch32; 1192 init_32bit_cpu_features(&boot->aarch32); 1193 boot_cpu_32bit_regs_overridden = true; 1194 } 1195 1196 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1197 struct cpuinfo_32bit *boot) 1198 { 1199 int taint = 0; 1200 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1201 1202 /* 1203 * If we don't have AArch32 at EL1, then relax the strictness of 1204 * EL1-dependent register fields to avoid spurious sanity check fails. 1205 */ 1206 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1207 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1208 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1209 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1210 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1211 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1212 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1213 } 1214 1215 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1216 info->reg_id_dfr0, boot->reg_id_dfr0); 1217 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1218 info->reg_id_dfr1, boot->reg_id_dfr1); 1219 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1220 info->reg_id_isar0, boot->reg_id_isar0); 1221 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1222 info->reg_id_isar1, boot->reg_id_isar1); 1223 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1224 info->reg_id_isar2, boot->reg_id_isar2); 1225 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1226 info->reg_id_isar3, boot->reg_id_isar3); 1227 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1228 info->reg_id_isar4, boot->reg_id_isar4); 1229 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1230 info->reg_id_isar5, boot->reg_id_isar5); 1231 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1232 info->reg_id_isar6, boot->reg_id_isar6); 1233 1234 /* 1235 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1236 * ACTLR formats could differ across CPUs and therefore would have to 1237 * be trapped for virtualization anyway. 1238 */ 1239 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1240 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1241 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1242 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1243 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1244 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1245 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1246 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1247 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1248 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1249 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1250 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1251 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1252 info->reg_id_pfr0, boot->reg_id_pfr0); 1253 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1254 info->reg_id_pfr1, boot->reg_id_pfr1); 1255 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1256 info->reg_id_pfr2, boot->reg_id_pfr2); 1257 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1258 info->reg_mvfr0, boot->reg_mvfr0); 1259 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1260 info->reg_mvfr1, boot->reg_mvfr1); 1261 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1262 info->reg_mvfr2, boot->reg_mvfr2); 1263 1264 return taint; 1265 } 1266 1267 /* 1268 * Update system wide CPU feature registers with the values from a 1269 * non-boot CPU. Also performs SANITY checks to make sure that there 1270 * aren't any insane variations from that of the boot CPU. 1271 */ 1272 void update_cpu_features(int cpu, 1273 struct cpuinfo_arm64 *info, 1274 struct cpuinfo_arm64 *boot) 1275 { 1276 int taint = 0; 1277 1278 /* 1279 * The kernel can handle differing I-cache policies, but otherwise 1280 * caches should look identical. Userspace JITs will make use of 1281 * *minLine. 1282 */ 1283 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1284 info->reg_ctr, boot->reg_ctr); 1285 1286 /* 1287 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1288 * could result in too much or too little memory being zeroed if a 1289 * process is preempted and migrated between CPUs. 1290 */ 1291 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1292 info->reg_dczid, boot->reg_dczid); 1293 1294 /* If different, timekeeping will be broken (especially with KVM) */ 1295 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1296 info->reg_cntfrq, boot->reg_cntfrq); 1297 1298 /* 1299 * The kernel uses self-hosted debug features and expects CPUs to 1300 * support identical debug features. We presently need CTX_CMPs, WRPs, 1301 * and BRPs to be identical. 1302 * ID_AA64DFR1 is currently RES0. 1303 */ 1304 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1305 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1306 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1307 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1308 /* 1309 * Even in big.LITTLE, processors should be identical instruction-set 1310 * wise. 1311 */ 1312 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1313 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1314 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1315 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1316 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1317 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1318 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1319 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1320 1321 /* 1322 * Differing PARange support is fine as long as all peripherals and 1323 * memory are mapped within the minimum PARange of all CPUs. 1324 * Linux should not care about secure memory. 1325 */ 1326 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1327 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1328 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1329 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1330 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1331 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1332 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1333 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1334 1335 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1336 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1337 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1338 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1339 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1340 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1341 1342 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1343 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1344 1345 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1346 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1347 1348 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1349 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1350 1351 /* Probe vector lengths */ 1352 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1353 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1354 if (!system_capabilities_finalized()) { 1355 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1356 1357 vec_update_vq_map(ARM64_VEC_SVE); 1358 1359 cpacr_restore(cpacr); 1360 } 1361 } 1362 1363 if (IS_ENABLED(CONFIG_ARM64_SME) && 1364 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1365 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1366 1367 /* 1368 * We mask out SMPS since even if the hardware 1369 * supports priorities the kernel does not at present 1370 * and we block access to them. 1371 */ 1372 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1373 1374 /* Probe vector lengths */ 1375 if (!system_capabilities_finalized()) 1376 vec_update_vq_map(ARM64_VEC_SME); 1377 1378 cpacr_restore(cpacr); 1379 } 1380 1381 /* 1382 * The kernel uses the LDGM/STGM instructions and the number of tags 1383 * they read/write depends on the GMID_EL1.BS field. Check that the 1384 * value is the same on all CPUs. 1385 */ 1386 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1387 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1388 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1389 info->reg_gmid, boot->reg_gmid); 1390 } 1391 1392 /* 1393 * If we don't have AArch32 at all then skip the checks entirely 1394 * as the register values may be UNKNOWN and we're not going to be 1395 * using them for anything. 1396 * 1397 * This relies on a sanitised view of the AArch64 ID registers 1398 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1399 */ 1400 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1401 lazy_init_32bit_cpu_features(info, boot); 1402 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1403 &boot->aarch32); 1404 } 1405 1406 /* 1407 * Mismatched CPU features are a recipe for disaster. Don't even 1408 * pretend to support them. 1409 */ 1410 if (taint) { 1411 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1412 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1413 } 1414 } 1415 1416 u64 read_sanitised_ftr_reg(u32 id) 1417 { 1418 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1419 1420 if (!regp) 1421 return 0; 1422 return regp->sys_val; 1423 } 1424 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1425 1426 #define read_sysreg_case(r) \ 1427 case r: val = read_sysreg_s(r); break; 1428 1429 /* 1430 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1431 * Read the system register on the current CPU 1432 */ 1433 u64 __read_sysreg_by_encoding(u32 sys_id) 1434 { 1435 struct arm64_ftr_reg *regp; 1436 u64 val; 1437 1438 switch (sys_id) { 1439 read_sysreg_case(SYS_ID_PFR0_EL1); 1440 read_sysreg_case(SYS_ID_PFR1_EL1); 1441 read_sysreg_case(SYS_ID_PFR2_EL1); 1442 read_sysreg_case(SYS_ID_DFR0_EL1); 1443 read_sysreg_case(SYS_ID_DFR1_EL1); 1444 read_sysreg_case(SYS_ID_MMFR0_EL1); 1445 read_sysreg_case(SYS_ID_MMFR1_EL1); 1446 read_sysreg_case(SYS_ID_MMFR2_EL1); 1447 read_sysreg_case(SYS_ID_MMFR3_EL1); 1448 read_sysreg_case(SYS_ID_MMFR4_EL1); 1449 read_sysreg_case(SYS_ID_MMFR5_EL1); 1450 read_sysreg_case(SYS_ID_ISAR0_EL1); 1451 read_sysreg_case(SYS_ID_ISAR1_EL1); 1452 read_sysreg_case(SYS_ID_ISAR2_EL1); 1453 read_sysreg_case(SYS_ID_ISAR3_EL1); 1454 read_sysreg_case(SYS_ID_ISAR4_EL1); 1455 read_sysreg_case(SYS_ID_ISAR5_EL1); 1456 read_sysreg_case(SYS_ID_ISAR6_EL1); 1457 read_sysreg_case(SYS_MVFR0_EL1); 1458 read_sysreg_case(SYS_MVFR1_EL1); 1459 read_sysreg_case(SYS_MVFR2_EL1); 1460 1461 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1462 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1463 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1464 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1465 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1466 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1467 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1468 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1469 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1470 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1471 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1472 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1473 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1474 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1475 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1476 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1477 1478 read_sysreg_case(SYS_CNTFRQ_EL0); 1479 read_sysreg_case(SYS_CTR_EL0); 1480 read_sysreg_case(SYS_DCZID_EL0); 1481 1482 default: 1483 BUG(); 1484 return 0; 1485 } 1486 1487 regp = get_arm64_ftr_reg(sys_id); 1488 if (regp) { 1489 val &= ~regp->override->mask; 1490 val |= (regp->override->val & regp->override->mask); 1491 } 1492 1493 return val; 1494 } 1495 1496 #include <linux/irqchip/arm-gic-v3.h> 1497 1498 static bool 1499 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1500 { 1501 return true; 1502 } 1503 1504 static bool 1505 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1506 { 1507 int val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1508 entry->field_width, 1509 entry->sign); 1510 1511 return val >= entry->min_field_value; 1512 } 1513 1514 static u64 1515 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1516 { 1517 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1518 if (scope == SCOPE_SYSTEM) 1519 return read_sanitised_ftr_reg(entry->sys_reg); 1520 else 1521 return __read_sysreg_by_encoding(entry->sys_reg); 1522 } 1523 1524 static bool 1525 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1526 { 1527 int mask; 1528 struct arm64_ftr_reg *regp; 1529 u64 val = read_scoped_sysreg(entry, scope); 1530 1531 regp = get_arm64_ftr_reg(entry->sys_reg); 1532 if (!regp) 1533 return false; 1534 1535 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1536 entry->field_pos, 1537 entry->field_width); 1538 if (!mask) 1539 return false; 1540 1541 return feature_matches(val, entry); 1542 } 1543 1544 static bool 1545 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1546 { 1547 u64 val = read_scoped_sysreg(entry, scope); 1548 return feature_matches(val, entry); 1549 } 1550 1551 const struct cpumask *system_32bit_el0_cpumask(void) 1552 { 1553 if (!system_supports_32bit_el0()) 1554 return cpu_none_mask; 1555 1556 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1557 return cpu_32bit_el0_mask; 1558 1559 return cpu_possible_mask; 1560 } 1561 1562 static int __init parse_32bit_el0_param(char *str) 1563 { 1564 allow_mismatched_32bit_el0 = true; 1565 return 0; 1566 } 1567 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1568 1569 static ssize_t aarch32_el0_show(struct device *dev, 1570 struct device_attribute *attr, char *buf) 1571 { 1572 const struct cpumask *mask = system_32bit_el0_cpumask(); 1573 1574 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1575 } 1576 static const DEVICE_ATTR_RO(aarch32_el0); 1577 1578 static int __init aarch32_el0_sysfs_init(void) 1579 { 1580 struct device *dev_root; 1581 int ret = 0; 1582 1583 if (!allow_mismatched_32bit_el0) 1584 return 0; 1585 1586 dev_root = bus_get_dev_root(&cpu_subsys); 1587 if (dev_root) { 1588 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1589 put_device(dev_root); 1590 } 1591 return ret; 1592 } 1593 device_initcall(aarch32_el0_sysfs_init); 1594 1595 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1596 { 1597 if (!has_cpuid_feature(entry, scope)) 1598 return allow_mismatched_32bit_el0; 1599 1600 if (scope == SCOPE_SYSTEM) 1601 pr_info("detected: 32-bit EL0 Support\n"); 1602 1603 return true; 1604 } 1605 1606 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1607 { 1608 bool has_sre; 1609 1610 if (!has_cpuid_feature(entry, scope)) 1611 return false; 1612 1613 has_sre = gic_enable_sre(); 1614 if (!has_sre) 1615 pr_warn_once("%s present but disabled by higher exception level\n", 1616 entry->desc); 1617 1618 return has_sre; 1619 } 1620 1621 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1622 int scope) 1623 { 1624 u64 ctr; 1625 1626 if (scope == SCOPE_SYSTEM) 1627 ctr = arm64_ftr_reg_ctrel0.sys_val; 1628 else 1629 ctr = read_cpuid_effective_cachetype(); 1630 1631 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1632 } 1633 1634 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1635 { 1636 /* 1637 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1638 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1639 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1640 * value. 1641 */ 1642 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1643 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1644 } 1645 1646 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1647 int scope) 1648 { 1649 u64 ctr; 1650 1651 if (scope == SCOPE_SYSTEM) 1652 ctr = arm64_ftr_reg_ctrel0.sys_val; 1653 else 1654 ctr = read_cpuid_cachetype(); 1655 1656 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1657 } 1658 1659 static bool __maybe_unused 1660 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1661 { 1662 /* 1663 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1664 * may share TLB entries with a CPU stuck in the crashed 1665 * kernel. 1666 */ 1667 if (is_kdump_kernel()) 1668 return false; 1669 1670 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1671 return false; 1672 1673 return has_cpuid_feature(entry, scope); 1674 } 1675 1676 static bool __meltdown_safe = true; 1677 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1678 1679 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1680 int scope) 1681 { 1682 /* List of CPUs that are not vulnerable and don't need KPTI */ 1683 static const struct midr_range kpti_safe_list[] = { 1684 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1685 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1686 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1687 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1688 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1689 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1690 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1691 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1692 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1693 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1694 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1695 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1696 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1697 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1698 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1699 { /* sentinel */ } 1700 }; 1701 char const *str = "kpti command line option"; 1702 bool meltdown_safe; 1703 1704 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1705 1706 /* Defer to CPU feature registers */ 1707 if (has_cpuid_feature(entry, scope)) 1708 meltdown_safe = true; 1709 1710 if (!meltdown_safe) 1711 __meltdown_safe = false; 1712 1713 /* 1714 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1715 * ThunderX leads to apparent I-cache corruption of kernel text, which 1716 * ends as well as you might imagine. Don't even try. We cannot rely 1717 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1718 * because cpucap detection order may change. However, since we know 1719 * affected CPUs are always in a homogeneous configuration, it is 1720 * safe to rely on this_cpu_has_cap() here. 1721 */ 1722 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1723 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1724 __kpti_forced = -1; 1725 } 1726 1727 /* Useful for KASLR robustness */ 1728 if (kaslr_enabled() && kaslr_requires_kpti()) { 1729 if (!__kpti_forced) { 1730 str = "KASLR"; 1731 __kpti_forced = 1; 1732 } 1733 } 1734 1735 if (cpu_mitigations_off() && !__kpti_forced) { 1736 str = "mitigations=off"; 1737 __kpti_forced = -1; 1738 } 1739 1740 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1741 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1742 return false; 1743 } 1744 1745 /* Forced? */ 1746 if (__kpti_forced) { 1747 pr_info_once("kernel page table isolation forced %s by %s\n", 1748 __kpti_forced > 0 ? "ON" : "OFF", str); 1749 return __kpti_forced > 0; 1750 } 1751 1752 return !meltdown_safe; 1753 } 1754 1755 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1756 static bool has_lpa2_at_stage1(u64 mmfr0) 1757 { 1758 unsigned int tgran; 1759 1760 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1761 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1762 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1763 } 1764 1765 static bool has_lpa2_at_stage2(u64 mmfr0) 1766 { 1767 unsigned int tgran; 1768 1769 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1770 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1771 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1772 } 1773 1774 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1775 { 1776 u64 mmfr0; 1777 1778 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1779 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1780 } 1781 #else 1782 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1783 { 1784 return false; 1785 } 1786 #endif 1787 1788 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1789 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1790 1791 extern 1792 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1793 phys_addr_t size, pgprot_t prot, 1794 phys_addr_t (*pgtable_alloc)(int), int flags); 1795 1796 static phys_addr_t __initdata kpti_ng_temp_alloc; 1797 1798 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1799 { 1800 kpti_ng_temp_alloc -= PAGE_SIZE; 1801 return kpti_ng_temp_alloc; 1802 } 1803 1804 static int __init __kpti_install_ng_mappings(void *__unused) 1805 { 1806 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1807 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1808 kpti_remap_fn *remap_fn; 1809 1810 int cpu = smp_processor_id(); 1811 int levels = CONFIG_PGTABLE_LEVELS; 1812 int order = order_base_2(levels); 1813 u64 kpti_ng_temp_pgd_pa = 0; 1814 pgd_t *kpti_ng_temp_pgd; 1815 u64 alloc = 0; 1816 1817 if (levels == 5 && !pgtable_l5_enabled()) 1818 levels = 4; 1819 else if (levels == 4 && !pgtable_l4_enabled()) 1820 levels = 3; 1821 1822 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1823 1824 if (!cpu) { 1825 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1826 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1827 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1828 1829 // 1830 // Create a minimal page table hierarchy that permits us to map 1831 // the swapper page tables temporarily as we traverse them. 1832 // 1833 // The physical pages are laid out as follows: 1834 // 1835 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1836 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1837 // +--------+-\-------+-\------ +-\------ +-///--------+ 1838 // ^ 1839 // The first page is mapped into this hierarchy at a PMD_SHIFT 1840 // aligned virtual address, so that we can manipulate the PTE 1841 // level entries while the mapping is active. The first entry 1842 // covers the PTE[] page itself, the remaining entries are free 1843 // to be used as a ad-hoc fixmap. 1844 // 1845 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1846 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1847 kpti_ng_pgd_alloc, 0); 1848 } 1849 1850 cpu_install_idmap(); 1851 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1852 cpu_uninstall_idmap(); 1853 1854 if (!cpu) { 1855 free_pages(alloc, order); 1856 arm64_use_ng_mappings = true; 1857 } 1858 1859 return 0; 1860 } 1861 1862 static void __init kpti_install_ng_mappings(void) 1863 { 1864 /* Check whether KPTI is going to be used */ 1865 if (!arm64_kernel_unmapped_at_el0()) 1866 return; 1867 1868 /* 1869 * We don't need to rewrite the page-tables if either we've done 1870 * it already or we have KASLR enabled and therefore have not 1871 * created any global mappings at all. 1872 */ 1873 if (arm64_use_ng_mappings) 1874 return; 1875 1876 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1877 } 1878 1879 #else 1880 static inline void kpti_install_ng_mappings(void) 1881 { 1882 } 1883 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1884 1885 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1886 { 1887 if (__this_cpu_read(this_cpu_vector) == vectors) { 1888 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1889 1890 __this_cpu_write(this_cpu_vector, v); 1891 } 1892 1893 } 1894 1895 static int __init parse_kpti(char *str) 1896 { 1897 bool enabled; 1898 int ret = kstrtobool(str, &enabled); 1899 1900 if (ret) 1901 return ret; 1902 1903 __kpti_forced = enabled ? 1 : -1; 1904 return 0; 1905 } 1906 early_param("kpti", parse_kpti); 1907 1908 #ifdef CONFIG_ARM64_HW_AFDBM 1909 static struct cpumask dbm_cpus __read_mostly; 1910 1911 static inline void __cpu_enable_hw_dbm(void) 1912 { 1913 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1914 1915 write_sysreg(tcr, tcr_el1); 1916 isb(); 1917 local_flush_tlb_all(); 1918 } 1919 1920 static bool cpu_has_broken_dbm(void) 1921 { 1922 /* List of CPUs which have broken DBM support. */ 1923 static const struct midr_range cpus[] = { 1924 #ifdef CONFIG_ARM64_ERRATUM_1024718 1925 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1926 /* Kryo4xx Silver (rdpe => r1p0) */ 1927 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1928 #endif 1929 #ifdef CONFIG_ARM64_ERRATUM_2051678 1930 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1931 #endif 1932 {}, 1933 }; 1934 1935 return is_midr_in_range_list(read_cpuid_id(), cpus); 1936 } 1937 1938 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1939 { 1940 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1941 !cpu_has_broken_dbm(); 1942 } 1943 1944 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1945 { 1946 if (cpu_can_use_dbm(cap)) { 1947 __cpu_enable_hw_dbm(); 1948 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 1949 } 1950 } 1951 1952 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1953 int __unused) 1954 { 1955 /* 1956 * DBM is a non-conflicting feature. i.e, the kernel can safely 1957 * run a mix of CPUs with and without the feature. So, we 1958 * unconditionally enable the capability to allow any late CPU 1959 * to use the feature. We only enable the control bits on the 1960 * CPU, if it is supported. 1961 */ 1962 1963 return true; 1964 } 1965 1966 #endif 1967 1968 #ifdef CONFIG_ARM64_AMU_EXTN 1969 1970 /* 1971 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1972 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1973 * information regarding all the events that it supports. When a CPU bit is 1974 * set in the cpumask, the user of this feature can only rely on the presence 1975 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1976 * counters are enabled or access to these counters is enabled by code 1977 * executed at higher exception levels (firmware). 1978 */ 1979 static struct cpumask amu_cpus __read_mostly; 1980 1981 bool cpu_has_amu_feat(int cpu) 1982 { 1983 return cpumask_test_cpu(cpu, &amu_cpus); 1984 } 1985 1986 int get_cpu_with_amu_feat(void) 1987 { 1988 return cpumask_any(&amu_cpus); 1989 } 1990 1991 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1992 { 1993 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1994 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1995 1996 /* 0 reference values signal broken/disabled counters */ 1997 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 1998 update_freq_counters_refs(); 1999 } 2000 } 2001 2002 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2003 int __unused) 2004 { 2005 /* 2006 * The AMU extension is a non-conflicting feature: the kernel can 2007 * safely run a mix of CPUs with and without support for the 2008 * activity monitors extension. Therefore, unconditionally enable 2009 * the capability to allow any late CPU to use the feature. 2010 * 2011 * With this feature unconditionally enabled, the cpu_enable 2012 * function will be called for all CPUs that match the criteria, 2013 * including secondary and hotplugged, marking this feature as 2014 * present on that respective CPU. The enable function will also 2015 * print a detection message. 2016 */ 2017 2018 return true; 2019 } 2020 #else 2021 int get_cpu_with_amu_feat(void) 2022 { 2023 return nr_cpu_ids; 2024 } 2025 #endif 2026 2027 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2028 { 2029 return is_kernel_in_hyp_mode(); 2030 } 2031 2032 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2033 { 2034 /* 2035 * Copy register values that aren't redirected by hardware. 2036 * 2037 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2038 * this value to tpidr_el2 before we patch the code. Once we've done 2039 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2040 * do anything here. 2041 */ 2042 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2043 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2044 } 2045 2046 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2047 int scope) 2048 { 2049 if (kvm_get_mode() != KVM_MODE_NV) 2050 return false; 2051 2052 if (!has_cpuid_feature(cap, scope)) { 2053 pr_warn("unavailable: %s\n", cap->desc); 2054 return false; 2055 } 2056 2057 return true; 2058 } 2059 2060 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2061 int __unused) 2062 { 2063 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2064 } 2065 2066 #ifdef CONFIG_ARM64_PAN 2067 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2068 { 2069 /* 2070 * We modify PSTATE. This won't work from irq context as the PSTATE 2071 * is discarded once we return from the exception. 2072 */ 2073 WARN_ON_ONCE(in_interrupt()); 2074 2075 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2076 set_pstate_pan(1); 2077 } 2078 #endif /* CONFIG_ARM64_PAN */ 2079 2080 #ifdef CONFIG_ARM64_RAS_EXTN 2081 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2082 { 2083 /* Firmware may have left a deferred SError in this register. */ 2084 write_sysreg_s(0, SYS_DISR_EL1); 2085 } 2086 #endif /* CONFIG_ARM64_RAS_EXTN */ 2087 2088 #ifdef CONFIG_ARM64_PTR_AUTH 2089 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2090 { 2091 int boot_val, sec_val; 2092 2093 /* We don't expect to be called with SCOPE_SYSTEM */ 2094 WARN_ON(scope == SCOPE_SYSTEM); 2095 /* 2096 * The ptr-auth feature levels are not intercompatible with lower 2097 * levels. Hence we must match ptr-auth feature level of the secondary 2098 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2099 * from the sanitised register whereas direct register read is done for 2100 * the secondary CPUs. 2101 * The sanitised feature state is guaranteed to match that of the 2102 * boot CPU as a mismatched secondary CPU is parked before it gets 2103 * a chance to update the state, with the capability. 2104 */ 2105 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2106 entry->field_pos, entry->sign); 2107 if (scope & SCOPE_BOOT_CPU) 2108 return boot_val >= entry->min_field_value; 2109 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2110 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2111 entry->field_pos, entry->sign); 2112 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2113 } 2114 2115 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2116 int scope) 2117 { 2118 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2119 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2120 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2121 2122 return apa || apa3 || api; 2123 } 2124 2125 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2126 int __unused) 2127 { 2128 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2129 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2130 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2131 2132 return gpa || gpa3 || gpi; 2133 } 2134 #endif /* CONFIG_ARM64_PTR_AUTH */ 2135 2136 #ifdef CONFIG_ARM64_E0PD 2137 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2138 { 2139 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2140 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2141 } 2142 #endif /* CONFIG_ARM64_E0PD */ 2143 2144 #ifdef CONFIG_ARM64_PSEUDO_NMI 2145 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2146 int scope) 2147 { 2148 /* 2149 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2150 * feature, so will be detected earlier. 2151 */ 2152 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2153 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2154 return false; 2155 2156 return enable_pseudo_nmi; 2157 } 2158 2159 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2160 int scope) 2161 { 2162 /* 2163 * If we're not using priority masking then we won't be poking PMR_EL1, 2164 * and there's no need to relax synchronization of writes to it, and 2165 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2166 * that. 2167 * 2168 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2169 * feature, so will be detected earlier. 2170 */ 2171 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2172 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2173 return false; 2174 2175 /* 2176 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2177 * hint for interrupt distribution, a DSB is not necessary when 2178 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2179 * 2180 * Linux itself doesn't use 1:N distribution, so has no need to 2181 * set PMHE. The only reason to have it set is if EL3 requires it 2182 * (and we can't change it). 2183 */ 2184 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2185 } 2186 #endif 2187 2188 #ifdef CONFIG_ARM64_BTI 2189 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2190 { 2191 /* 2192 * Use of X16/X17 for tail-calls and trampolines that jump to 2193 * function entry points using BR is a requirement for 2194 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2195 * So, be strict and forbid other BRs using other registers to 2196 * jump onto a PACIxSP instruction: 2197 */ 2198 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2199 isb(); 2200 } 2201 #endif /* CONFIG_ARM64_BTI */ 2202 2203 #ifdef CONFIG_ARM64_MTE 2204 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2205 { 2206 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2207 2208 mte_cpu_setup(); 2209 2210 /* 2211 * Clear the tags in the zero page. This needs to be done via the 2212 * linear map which has the Tagged attribute. 2213 */ 2214 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2215 mte_clear_page_tags(lm_alias(empty_zero_page)); 2216 set_page_mte_tagged(ZERO_PAGE(0)); 2217 } 2218 2219 kasan_init_hw_tags_cpu(); 2220 } 2221 #endif /* CONFIG_ARM64_MTE */ 2222 2223 static void user_feature_fixup(void) 2224 { 2225 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2226 struct arm64_ftr_reg *regp; 2227 2228 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2229 if (regp) 2230 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2231 } 2232 } 2233 2234 static void elf_hwcap_fixup(void) 2235 { 2236 #ifdef CONFIG_COMPAT 2237 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2238 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2239 #endif /* CONFIG_COMPAT */ 2240 } 2241 2242 #ifdef CONFIG_KVM 2243 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2244 { 2245 return kvm_get_mode() == KVM_MODE_PROTECTED; 2246 } 2247 #endif /* CONFIG_KVM */ 2248 2249 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2250 { 2251 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2252 } 2253 2254 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2255 { 2256 set_pstate_dit(1); 2257 } 2258 2259 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2260 { 2261 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2262 } 2263 2264 /* Internal helper functions to match cpu capability type */ 2265 static bool 2266 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2267 { 2268 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2269 } 2270 2271 static bool 2272 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2273 { 2274 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2275 } 2276 2277 static bool 2278 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2279 { 2280 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2281 } 2282 2283 static const struct arm64_cpu_capabilities arm64_features[] = { 2284 { 2285 .capability = ARM64_ALWAYS_BOOT, 2286 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2287 .matches = has_always, 2288 }, 2289 { 2290 .capability = ARM64_ALWAYS_SYSTEM, 2291 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2292 .matches = has_always, 2293 }, 2294 { 2295 .desc = "GIC system register CPU interface", 2296 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2297 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2298 .matches = has_useable_gicv3_cpuif, 2299 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2300 }, 2301 { 2302 .desc = "Enhanced Counter Virtualization", 2303 .capability = ARM64_HAS_ECV, 2304 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2305 .matches = has_cpuid_feature, 2306 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2307 }, 2308 { 2309 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2310 .capability = ARM64_HAS_ECV_CNTPOFF, 2311 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2312 .matches = has_cpuid_feature, 2313 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2314 }, 2315 #ifdef CONFIG_ARM64_PAN 2316 { 2317 .desc = "Privileged Access Never", 2318 .capability = ARM64_HAS_PAN, 2319 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2320 .matches = has_cpuid_feature, 2321 .cpu_enable = cpu_enable_pan, 2322 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2323 }, 2324 #endif /* CONFIG_ARM64_PAN */ 2325 #ifdef CONFIG_ARM64_EPAN 2326 { 2327 .desc = "Enhanced Privileged Access Never", 2328 .capability = ARM64_HAS_EPAN, 2329 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2330 .matches = has_cpuid_feature, 2331 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2332 }, 2333 #endif /* CONFIG_ARM64_EPAN */ 2334 #ifdef CONFIG_ARM64_LSE_ATOMICS 2335 { 2336 .desc = "LSE atomic instructions", 2337 .capability = ARM64_HAS_LSE_ATOMICS, 2338 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2339 .matches = has_cpuid_feature, 2340 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2341 }, 2342 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2343 { 2344 .desc = "Virtualization Host Extensions", 2345 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2346 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2347 .matches = runs_at_el2, 2348 .cpu_enable = cpu_copy_el2regs, 2349 }, 2350 { 2351 .desc = "Nested Virtualization Support", 2352 .capability = ARM64_HAS_NESTED_VIRT, 2353 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2354 .matches = has_nested_virt_support, 2355 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2356 }, 2357 { 2358 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2359 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2360 .matches = has_32bit_el0, 2361 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2362 }, 2363 #ifdef CONFIG_KVM 2364 { 2365 .desc = "32-bit EL1 Support", 2366 .capability = ARM64_HAS_32BIT_EL1, 2367 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2368 .matches = has_cpuid_feature, 2369 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2370 }, 2371 { 2372 .desc = "Protected KVM", 2373 .capability = ARM64_KVM_PROTECTED_MODE, 2374 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2375 .matches = is_kvm_protected_mode, 2376 }, 2377 { 2378 .desc = "HCRX_EL2 register", 2379 .capability = ARM64_HAS_HCX, 2380 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2381 .matches = has_cpuid_feature, 2382 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2383 }, 2384 #endif 2385 { 2386 .desc = "Kernel page table isolation (KPTI)", 2387 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2388 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2389 .cpu_enable = cpu_enable_kpti, 2390 .matches = unmap_kernel_at_el0, 2391 /* 2392 * The ID feature fields below are used to indicate that 2393 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2394 * more details. 2395 */ 2396 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2397 }, 2398 { 2399 .capability = ARM64_HAS_FPSIMD, 2400 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2401 .matches = has_cpuid_feature, 2402 .cpu_enable = cpu_enable_fpsimd, 2403 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2404 }, 2405 #ifdef CONFIG_ARM64_PMEM 2406 { 2407 .desc = "Data cache clean to Point of Persistence", 2408 .capability = ARM64_HAS_DCPOP, 2409 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2410 .matches = has_cpuid_feature, 2411 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2412 }, 2413 { 2414 .desc = "Data cache clean to Point of Deep Persistence", 2415 .capability = ARM64_HAS_DCPODP, 2416 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2417 .matches = has_cpuid_feature, 2418 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2419 }, 2420 #endif 2421 #ifdef CONFIG_ARM64_SVE 2422 { 2423 .desc = "Scalable Vector Extension", 2424 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2425 .capability = ARM64_SVE, 2426 .cpu_enable = cpu_enable_sve, 2427 .matches = has_cpuid_feature, 2428 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2429 }, 2430 #endif /* CONFIG_ARM64_SVE */ 2431 #ifdef CONFIG_ARM64_RAS_EXTN 2432 { 2433 .desc = "RAS Extension Support", 2434 .capability = ARM64_HAS_RAS_EXTN, 2435 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2436 .matches = has_cpuid_feature, 2437 .cpu_enable = cpu_clear_disr, 2438 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2439 }, 2440 #endif /* CONFIG_ARM64_RAS_EXTN */ 2441 #ifdef CONFIG_ARM64_AMU_EXTN 2442 { 2443 .desc = "Activity Monitors Unit (AMU)", 2444 .capability = ARM64_HAS_AMU_EXTN, 2445 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2446 .matches = has_amu, 2447 .cpu_enable = cpu_amu_enable, 2448 .cpus = &amu_cpus, 2449 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2450 }, 2451 #endif /* CONFIG_ARM64_AMU_EXTN */ 2452 { 2453 .desc = "Data cache clean to the PoU not required for I/D coherence", 2454 .capability = ARM64_HAS_CACHE_IDC, 2455 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2456 .matches = has_cache_idc, 2457 .cpu_enable = cpu_emulate_effective_ctr, 2458 }, 2459 { 2460 .desc = "Instruction cache invalidation not required for I/D coherence", 2461 .capability = ARM64_HAS_CACHE_DIC, 2462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2463 .matches = has_cache_dic, 2464 }, 2465 { 2466 .desc = "Stage-2 Force Write-Back", 2467 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2468 .capability = ARM64_HAS_STAGE2_FWB, 2469 .matches = has_cpuid_feature, 2470 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2471 }, 2472 { 2473 .desc = "ARMv8.4 Translation Table Level", 2474 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2475 .capability = ARM64_HAS_ARMv8_4_TTL, 2476 .matches = has_cpuid_feature, 2477 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2478 }, 2479 { 2480 .desc = "TLB range maintenance instructions", 2481 .capability = ARM64_HAS_TLB_RANGE, 2482 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2483 .matches = has_cpuid_feature, 2484 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2485 }, 2486 #ifdef CONFIG_ARM64_HW_AFDBM 2487 { 2488 .desc = "Hardware dirty bit management", 2489 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2490 .capability = ARM64_HW_DBM, 2491 .matches = has_hw_dbm, 2492 .cpu_enable = cpu_enable_hw_dbm, 2493 .cpus = &dbm_cpus, 2494 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2495 }, 2496 #endif 2497 { 2498 .desc = "CRC32 instructions", 2499 .capability = ARM64_HAS_CRC32, 2500 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2501 .matches = has_cpuid_feature, 2502 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2503 }, 2504 { 2505 .desc = "Speculative Store Bypassing Safe (SSBS)", 2506 .capability = ARM64_SSBS, 2507 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2508 .matches = has_cpuid_feature, 2509 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2510 }, 2511 #ifdef CONFIG_ARM64_CNP 2512 { 2513 .desc = "Common not Private translations", 2514 .capability = ARM64_HAS_CNP, 2515 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2516 .matches = has_useable_cnp, 2517 .cpu_enable = cpu_enable_cnp, 2518 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2519 }, 2520 #endif 2521 { 2522 .desc = "Speculation barrier (SB)", 2523 .capability = ARM64_HAS_SB, 2524 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2525 .matches = has_cpuid_feature, 2526 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2527 }, 2528 #ifdef CONFIG_ARM64_PTR_AUTH 2529 { 2530 .desc = "Address authentication (architected QARMA5 algorithm)", 2531 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2532 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2533 .matches = has_address_auth_cpucap, 2534 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2535 }, 2536 { 2537 .desc = "Address authentication (architected QARMA3 algorithm)", 2538 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2539 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2540 .matches = has_address_auth_cpucap, 2541 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2542 }, 2543 { 2544 .desc = "Address authentication (IMP DEF algorithm)", 2545 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2546 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2547 .matches = has_address_auth_cpucap, 2548 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2549 }, 2550 { 2551 .capability = ARM64_HAS_ADDRESS_AUTH, 2552 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2553 .matches = has_address_auth_metacap, 2554 }, 2555 { 2556 .desc = "Generic authentication (architected QARMA5 algorithm)", 2557 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2558 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2559 .matches = has_cpuid_feature, 2560 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2561 }, 2562 { 2563 .desc = "Generic authentication (architected QARMA3 algorithm)", 2564 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2565 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2566 .matches = has_cpuid_feature, 2567 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2568 }, 2569 { 2570 .desc = "Generic authentication (IMP DEF algorithm)", 2571 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2572 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2573 .matches = has_cpuid_feature, 2574 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2575 }, 2576 { 2577 .capability = ARM64_HAS_GENERIC_AUTH, 2578 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2579 .matches = has_generic_auth, 2580 }, 2581 #endif /* CONFIG_ARM64_PTR_AUTH */ 2582 #ifdef CONFIG_ARM64_PSEUDO_NMI 2583 { 2584 /* 2585 * Depends on having GICv3 2586 */ 2587 .desc = "IRQ priority masking", 2588 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2589 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2590 .matches = can_use_gic_priorities, 2591 }, 2592 { 2593 /* 2594 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2595 */ 2596 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2597 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2598 .matches = has_gic_prio_relaxed_sync, 2599 }, 2600 #endif 2601 #ifdef CONFIG_ARM64_E0PD 2602 { 2603 .desc = "E0PD", 2604 .capability = ARM64_HAS_E0PD, 2605 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2606 .cpu_enable = cpu_enable_e0pd, 2607 .matches = has_cpuid_feature, 2608 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2609 }, 2610 #endif 2611 { 2612 .desc = "Random Number Generator", 2613 .capability = ARM64_HAS_RNG, 2614 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2615 .matches = has_cpuid_feature, 2616 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2617 }, 2618 #ifdef CONFIG_ARM64_BTI 2619 { 2620 .desc = "Branch Target Identification", 2621 .capability = ARM64_BTI, 2622 #ifdef CONFIG_ARM64_BTI_KERNEL 2623 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2624 #else 2625 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2626 #endif 2627 .matches = has_cpuid_feature, 2628 .cpu_enable = bti_enable, 2629 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2630 }, 2631 #endif 2632 #ifdef CONFIG_ARM64_MTE 2633 { 2634 .desc = "Memory Tagging Extension", 2635 .capability = ARM64_MTE, 2636 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2637 .matches = has_cpuid_feature, 2638 .cpu_enable = cpu_enable_mte, 2639 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2640 }, 2641 { 2642 .desc = "Asymmetric MTE Tag Check Fault", 2643 .capability = ARM64_MTE_ASYMM, 2644 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2645 .matches = has_cpuid_feature, 2646 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2647 }, 2648 #endif /* CONFIG_ARM64_MTE */ 2649 { 2650 .desc = "RCpc load-acquire (LDAPR)", 2651 .capability = ARM64_HAS_LDAPR, 2652 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2653 .matches = has_cpuid_feature, 2654 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2655 }, 2656 { 2657 .desc = "Fine Grained Traps", 2658 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2659 .capability = ARM64_HAS_FGT, 2660 .matches = has_cpuid_feature, 2661 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2662 }, 2663 #ifdef CONFIG_ARM64_SME 2664 { 2665 .desc = "Scalable Matrix Extension", 2666 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2667 .capability = ARM64_SME, 2668 .matches = has_cpuid_feature, 2669 .cpu_enable = cpu_enable_sme, 2670 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2671 }, 2672 /* FA64 should be sorted after the base SME capability */ 2673 { 2674 .desc = "FA64", 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .capability = ARM64_SME_FA64, 2677 .matches = has_cpuid_feature, 2678 .cpu_enable = cpu_enable_fa64, 2679 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2680 }, 2681 { 2682 .desc = "SME2", 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .capability = ARM64_SME2, 2685 .matches = has_cpuid_feature, 2686 .cpu_enable = cpu_enable_sme2, 2687 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2688 }, 2689 #endif /* CONFIG_ARM64_SME */ 2690 { 2691 .desc = "WFx with timeout", 2692 .capability = ARM64_HAS_WFXT, 2693 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2694 .matches = has_cpuid_feature, 2695 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2696 }, 2697 { 2698 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2699 .capability = ARM64_HAS_TIDCP1, 2700 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2701 .matches = has_cpuid_feature, 2702 .cpu_enable = cpu_trap_el0_impdef, 2703 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2704 }, 2705 { 2706 .desc = "Data independent timing control (DIT)", 2707 .capability = ARM64_HAS_DIT, 2708 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2709 .matches = has_cpuid_feature, 2710 .cpu_enable = cpu_enable_dit, 2711 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2712 }, 2713 { 2714 .desc = "Memory Copy and Memory Set instructions", 2715 .capability = ARM64_HAS_MOPS, 2716 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2717 .matches = has_cpuid_feature, 2718 .cpu_enable = cpu_enable_mops, 2719 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2720 }, 2721 { 2722 .capability = ARM64_HAS_TCR2, 2723 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2724 .matches = has_cpuid_feature, 2725 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2726 }, 2727 { 2728 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2729 .capability = ARM64_HAS_S1PIE, 2730 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2731 .matches = has_cpuid_feature, 2732 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2733 }, 2734 { 2735 .desc = "VHE for hypervisor only", 2736 .capability = ARM64_KVM_HVHE, 2737 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2738 .matches = hvhe_possible, 2739 }, 2740 { 2741 .desc = "Enhanced Virtualization Traps", 2742 .capability = ARM64_HAS_EVT, 2743 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2744 .matches = has_cpuid_feature, 2745 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2746 }, 2747 { 2748 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2749 .capability = ARM64_HAS_LPA2, 2750 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2751 .matches = has_lpa2, 2752 }, 2753 { 2754 .desc = "FPMR", 2755 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2756 .capability = ARM64_HAS_FPMR, 2757 .matches = has_cpuid_feature, 2758 .cpu_enable = cpu_enable_fpmr, 2759 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2760 }, 2761 #ifdef CONFIG_ARM64_VA_BITS_52 2762 { 2763 .capability = ARM64_HAS_VA52, 2764 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2765 .matches = has_cpuid_feature, 2766 #ifdef CONFIG_ARM64_64K_PAGES 2767 .desc = "52-bit Virtual Addressing (LVA)", 2768 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2769 #else 2770 .desc = "52-bit Virtual Addressing (LPA2)", 2771 #ifdef CONFIG_ARM64_4K_PAGES 2772 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2773 #else 2774 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2775 #endif 2776 #endif 2777 }, 2778 #endif 2779 {}, 2780 }; 2781 2782 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2783 .matches = has_user_cpuid_feature, \ 2784 ARM64_CPUID_FIELDS(reg, field, min_value) 2785 2786 #define __HWCAP_CAP(name, cap_type, cap) \ 2787 .desc = name, \ 2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2789 .hwcap_type = cap_type, \ 2790 .hwcap = cap, \ 2791 2792 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2793 { \ 2794 __HWCAP_CAP(#cap, cap_type, cap) \ 2795 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2796 } 2797 2798 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2799 { \ 2800 __HWCAP_CAP(#cap, cap_type, cap) \ 2801 .matches = cpucap_multi_entry_cap_matches, \ 2802 .match_list = list, \ 2803 } 2804 2805 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2806 { \ 2807 __HWCAP_CAP(#cap, cap_type, cap) \ 2808 .matches = match, \ 2809 } 2810 2811 #ifdef CONFIG_ARM64_PTR_AUTH 2812 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2813 { 2814 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2815 }, 2816 { 2817 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2818 }, 2819 { 2820 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2821 }, 2822 {}, 2823 }; 2824 2825 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2826 { 2827 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2828 }, 2829 { 2830 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2831 }, 2832 { 2833 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2834 }, 2835 {}, 2836 }; 2837 #endif 2838 2839 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2840 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2841 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2842 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2843 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2844 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2845 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2846 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2847 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2848 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2849 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2850 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2851 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2852 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2853 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2854 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2855 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2856 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2857 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2858 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2859 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2860 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2861 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2862 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 2863 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2864 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2865 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2866 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2867 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2868 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2869 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 2870 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2871 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2872 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2873 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2874 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2875 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2876 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 2877 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 2878 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2879 #ifdef CONFIG_ARM64_SVE 2880 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2881 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2882 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2883 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2884 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2885 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2886 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 2887 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2888 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 2889 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2890 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2891 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2892 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2893 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2894 #endif 2895 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2896 #ifdef CONFIG_ARM64_BTI 2897 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 2898 #endif 2899 #ifdef CONFIG_ARM64_PTR_AUTH 2900 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2901 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2902 #endif 2903 #ifdef CONFIG_ARM64_MTE 2904 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 2905 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 2906 #endif /* CONFIG_ARM64_MTE */ 2907 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 2908 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 2909 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 2910 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 2911 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 2912 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 2913 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 2914 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 2915 #ifdef CONFIG_ARM64_SME 2916 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 2917 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 2918 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 2919 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 2920 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 2921 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 2922 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 2923 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 2924 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 2925 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 2926 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 2927 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 2928 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 2929 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 2930 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 2931 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 2932 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 2933 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 2934 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 2935 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 2936 #endif /* CONFIG_ARM64_SME */ 2937 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 2938 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 2939 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 2940 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 2941 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 2942 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 2943 {}, 2944 }; 2945 2946 #ifdef CONFIG_COMPAT 2947 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2948 { 2949 /* 2950 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2951 * in line with that of arm32 as in vfp_init(). We make sure that the 2952 * check is future proof, by making sure value is non-zero. 2953 */ 2954 u32 mvfr1; 2955 2956 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2957 if (scope == SCOPE_SYSTEM) 2958 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2959 else 2960 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2961 2962 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 2963 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 2964 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 2965 } 2966 #endif 2967 2968 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2969 #ifdef CONFIG_COMPAT 2970 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2971 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2972 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2973 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2974 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2975 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 2976 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 2977 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2978 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2979 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2980 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2981 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2982 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 2983 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 2984 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 2985 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 2986 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 2987 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 2988 #endif 2989 {}, 2990 }; 2991 2992 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2993 { 2994 switch (cap->hwcap_type) { 2995 case CAP_HWCAP: 2996 cpu_set_feature(cap->hwcap); 2997 break; 2998 #ifdef CONFIG_COMPAT 2999 case CAP_COMPAT_HWCAP: 3000 compat_elf_hwcap |= (u32)cap->hwcap; 3001 break; 3002 case CAP_COMPAT_HWCAP2: 3003 compat_elf_hwcap2 |= (u32)cap->hwcap; 3004 break; 3005 #endif 3006 default: 3007 WARN_ON(1); 3008 break; 3009 } 3010 } 3011 3012 /* Check if we have a particular HWCAP enabled */ 3013 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3014 { 3015 bool rc; 3016 3017 switch (cap->hwcap_type) { 3018 case CAP_HWCAP: 3019 rc = cpu_have_feature(cap->hwcap); 3020 break; 3021 #ifdef CONFIG_COMPAT 3022 case CAP_COMPAT_HWCAP: 3023 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3024 break; 3025 case CAP_COMPAT_HWCAP2: 3026 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3027 break; 3028 #endif 3029 default: 3030 WARN_ON(1); 3031 rc = false; 3032 } 3033 3034 return rc; 3035 } 3036 3037 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3038 { 3039 /* We support emulation of accesses to CPU ID feature registers */ 3040 cpu_set_named_feature(CPUID); 3041 for (; hwcaps->matches; hwcaps++) 3042 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3043 cap_set_elf_hwcap(hwcaps); 3044 } 3045 3046 static void update_cpu_capabilities(u16 scope_mask) 3047 { 3048 int i; 3049 const struct arm64_cpu_capabilities *caps; 3050 3051 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3052 for (i = 0; i < ARM64_NCAPS; i++) { 3053 caps = cpucap_ptrs[i]; 3054 if (!caps || !(caps->type & scope_mask) || 3055 cpus_have_cap(caps->capability) || 3056 !caps->matches(caps, cpucap_default_scope(caps))) 3057 continue; 3058 3059 if (caps->desc && !caps->cpus) 3060 pr_info("detected: %s\n", caps->desc); 3061 3062 __set_bit(caps->capability, system_cpucaps); 3063 3064 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3065 set_bit(caps->capability, boot_cpucaps); 3066 } 3067 } 3068 3069 /* 3070 * Enable all the available capabilities on this CPU. The capabilities 3071 * with BOOT_CPU scope are handled separately and hence skipped here. 3072 */ 3073 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3074 { 3075 int i; 3076 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3077 3078 for_each_available_cap(i) { 3079 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3080 3081 if (WARN_ON(!cap)) 3082 continue; 3083 3084 if (!(cap->type & non_boot_scope)) 3085 continue; 3086 3087 if (cap->cpu_enable) 3088 cap->cpu_enable(cap); 3089 } 3090 return 0; 3091 } 3092 3093 /* 3094 * Run through the enabled capabilities and enable() it on all active 3095 * CPUs 3096 */ 3097 static void __init enable_cpu_capabilities(u16 scope_mask) 3098 { 3099 int i; 3100 const struct arm64_cpu_capabilities *caps; 3101 bool boot_scope; 3102 3103 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3104 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3105 3106 for (i = 0; i < ARM64_NCAPS; i++) { 3107 caps = cpucap_ptrs[i]; 3108 if (!caps || !(caps->type & scope_mask) || 3109 !cpus_have_cap(caps->capability)) 3110 continue; 3111 3112 if (boot_scope && caps->cpu_enable) 3113 /* 3114 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3115 * before any secondary CPU boots. Thus, each secondary 3116 * will enable the capability as appropriate via 3117 * check_local_cpu_capabilities(). The only exception is 3118 * the boot CPU, for which the capability must be 3119 * enabled here. This approach avoids costly 3120 * stop_machine() calls for this case. 3121 */ 3122 caps->cpu_enable(caps); 3123 } 3124 3125 /* 3126 * For all non-boot scope capabilities, use stop_machine() 3127 * as it schedules the work allowing us to modify PSTATE, 3128 * instead of on_each_cpu() which uses an IPI, giving us a 3129 * PSTATE that disappears when we return. 3130 */ 3131 if (!boot_scope) 3132 stop_machine(cpu_enable_non_boot_scope_capabilities, 3133 NULL, cpu_online_mask); 3134 } 3135 3136 /* 3137 * Run through the list of capabilities to check for conflicts. 3138 * If the system has already detected a capability, take necessary 3139 * action on this CPU. 3140 */ 3141 static void verify_local_cpu_caps(u16 scope_mask) 3142 { 3143 int i; 3144 bool cpu_has_cap, system_has_cap; 3145 const struct arm64_cpu_capabilities *caps; 3146 3147 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3148 3149 for (i = 0; i < ARM64_NCAPS; i++) { 3150 caps = cpucap_ptrs[i]; 3151 if (!caps || !(caps->type & scope_mask)) 3152 continue; 3153 3154 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3155 system_has_cap = cpus_have_cap(caps->capability); 3156 3157 if (system_has_cap) { 3158 /* 3159 * Check if the new CPU misses an advertised feature, 3160 * which is not safe to miss. 3161 */ 3162 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3163 break; 3164 /* 3165 * We have to issue cpu_enable() irrespective of 3166 * whether the CPU has it or not, as it is enabeld 3167 * system wide. It is upto the call back to take 3168 * appropriate action on this CPU. 3169 */ 3170 if (caps->cpu_enable) 3171 caps->cpu_enable(caps); 3172 } else { 3173 /* 3174 * Check if the CPU has this capability if it isn't 3175 * safe to have when the system doesn't. 3176 */ 3177 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3178 break; 3179 } 3180 } 3181 3182 if (i < ARM64_NCAPS) { 3183 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3184 smp_processor_id(), caps->capability, 3185 caps->desc, system_has_cap, cpu_has_cap); 3186 3187 if (cpucap_panic_on_conflict(caps)) 3188 cpu_panic_kernel(); 3189 else 3190 cpu_die_early(); 3191 } 3192 } 3193 3194 /* 3195 * Check for CPU features that are used in early boot 3196 * based on the Boot CPU value. 3197 */ 3198 static void check_early_cpu_features(void) 3199 { 3200 verify_cpu_asid_bits(); 3201 3202 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3203 } 3204 3205 static void 3206 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3207 { 3208 3209 for (; caps->matches; caps++) 3210 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3211 pr_crit("CPU%d: missing HWCAP: %s\n", 3212 smp_processor_id(), caps->desc); 3213 cpu_die_early(); 3214 } 3215 } 3216 3217 static void verify_local_elf_hwcaps(void) 3218 { 3219 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3220 3221 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3222 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3223 } 3224 3225 static void verify_sve_features(void) 3226 { 3227 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3228 3229 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3230 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3231 smp_processor_id()); 3232 cpu_die_early(); 3233 } 3234 3235 cpacr_restore(cpacr); 3236 } 3237 3238 static void verify_sme_features(void) 3239 { 3240 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3241 3242 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3243 pr_crit("CPU%d: SME: vector length support mismatch\n", 3244 smp_processor_id()); 3245 cpu_die_early(); 3246 } 3247 3248 cpacr_restore(cpacr); 3249 } 3250 3251 static void verify_hyp_capabilities(void) 3252 { 3253 u64 safe_mmfr1, mmfr0, mmfr1; 3254 int parange, ipa_max; 3255 unsigned int safe_vmid_bits, vmid_bits; 3256 3257 if (!IS_ENABLED(CONFIG_KVM)) 3258 return; 3259 3260 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3261 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3262 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3263 3264 /* Verify VMID bits */ 3265 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3266 vmid_bits = get_vmid_bits(mmfr1); 3267 if (vmid_bits < safe_vmid_bits) { 3268 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3269 cpu_die_early(); 3270 } 3271 3272 /* Verify IPA range */ 3273 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3274 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3275 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3276 if (ipa_max < get_kvm_ipa_limit()) { 3277 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3278 cpu_die_early(); 3279 } 3280 } 3281 3282 /* 3283 * Run through the enabled system capabilities and enable() it on this CPU. 3284 * The capabilities were decided based on the available CPUs at the boot time. 3285 * Any new CPU should match the system wide status of the capability. If the 3286 * new CPU doesn't have a capability which the system now has enabled, we 3287 * cannot do anything to fix it up and could cause unexpected failures. So 3288 * we park the CPU. 3289 */ 3290 static void verify_local_cpu_capabilities(void) 3291 { 3292 /* 3293 * The capabilities with SCOPE_BOOT_CPU are checked from 3294 * check_early_cpu_features(), as they need to be verified 3295 * on all secondary CPUs. 3296 */ 3297 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3298 verify_local_elf_hwcaps(); 3299 3300 if (system_supports_sve()) 3301 verify_sve_features(); 3302 3303 if (system_supports_sme()) 3304 verify_sme_features(); 3305 3306 if (is_hyp_mode_available()) 3307 verify_hyp_capabilities(); 3308 } 3309 3310 void check_local_cpu_capabilities(void) 3311 { 3312 /* 3313 * All secondary CPUs should conform to the early CPU features 3314 * in use by the kernel based on boot CPU. 3315 */ 3316 check_early_cpu_features(); 3317 3318 /* 3319 * If we haven't finalised the system capabilities, this CPU gets 3320 * a chance to update the errata work arounds and local features. 3321 * Otherwise, this CPU should verify that it has all the system 3322 * advertised capabilities. 3323 */ 3324 if (!system_capabilities_finalized()) 3325 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3326 else 3327 verify_local_cpu_capabilities(); 3328 } 3329 3330 bool this_cpu_has_cap(unsigned int n) 3331 { 3332 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3333 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3334 3335 if (cap) 3336 return cap->matches(cap, SCOPE_LOCAL_CPU); 3337 } 3338 3339 return false; 3340 } 3341 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3342 3343 /* 3344 * This helper function is used in a narrow window when, 3345 * - The system wide safe registers are set with all the SMP CPUs and, 3346 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3347 */ 3348 static bool __maybe_unused __system_matches_cap(unsigned int n) 3349 { 3350 if (n < ARM64_NCAPS) { 3351 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3352 3353 if (cap) 3354 return cap->matches(cap, SCOPE_SYSTEM); 3355 } 3356 return false; 3357 } 3358 3359 void cpu_set_feature(unsigned int num) 3360 { 3361 set_bit(num, elf_hwcap); 3362 } 3363 3364 bool cpu_have_feature(unsigned int num) 3365 { 3366 return test_bit(num, elf_hwcap); 3367 } 3368 EXPORT_SYMBOL_GPL(cpu_have_feature); 3369 3370 unsigned long cpu_get_elf_hwcap(void) 3371 { 3372 /* 3373 * We currently only populate the first 32 bits of AT_HWCAP. Please 3374 * note that for userspace compatibility we guarantee that bits 62 3375 * and 63 will always be returned as 0. 3376 */ 3377 return elf_hwcap[0]; 3378 } 3379 3380 unsigned long cpu_get_elf_hwcap2(void) 3381 { 3382 return elf_hwcap[1]; 3383 } 3384 3385 static void __init setup_boot_cpu_capabilities(void) 3386 { 3387 /* 3388 * The boot CPU's feature register values have been recorded. Detect 3389 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3390 * patch alternatives for the available boot cpucaps. 3391 */ 3392 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3393 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3394 apply_boot_alternatives(); 3395 } 3396 3397 void __init setup_boot_cpu_features(void) 3398 { 3399 /* 3400 * Initialize the indirect array of CPU capabilities pointers before we 3401 * handle the boot CPU. 3402 */ 3403 init_cpucap_indirect_list(); 3404 3405 /* 3406 * Detect broken pseudo-NMI. Must be called _before_ the call to 3407 * setup_boot_cpu_capabilities() since it interacts with 3408 * can_use_gic_priorities(). 3409 */ 3410 detect_system_supports_pseudo_nmi(); 3411 3412 setup_boot_cpu_capabilities(); 3413 } 3414 3415 static void __init setup_system_capabilities(void) 3416 { 3417 /* 3418 * The system-wide safe feature register values have been finalized. 3419 * Detect, enable, and patch alternatives for the available system 3420 * cpucaps. 3421 */ 3422 update_cpu_capabilities(SCOPE_SYSTEM); 3423 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3424 apply_alternatives_all(); 3425 3426 /* 3427 * Log any cpucaps with a cpumask as these aren't logged by 3428 * update_cpu_capabilities(). 3429 */ 3430 for (int i = 0; i < ARM64_NCAPS; i++) { 3431 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3432 3433 if (caps && caps->cpus && caps->desc && 3434 cpumask_any(caps->cpus) < nr_cpu_ids) 3435 pr_info("detected: %s on CPU%*pbl\n", 3436 caps->desc, cpumask_pr_args(caps->cpus)); 3437 } 3438 3439 /* 3440 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3441 */ 3442 if (system_uses_ttbr0_pan()) 3443 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3444 } 3445 3446 void __init setup_system_features(void) 3447 { 3448 setup_system_capabilities(); 3449 3450 kpti_install_ng_mappings(); 3451 3452 sve_setup(); 3453 sme_setup(); 3454 3455 /* 3456 * Check for sane CTR_EL0.CWG value. 3457 */ 3458 if (!cache_type_cwg()) 3459 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3460 ARCH_DMA_MINALIGN); 3461 } 3462 3463 void __init setup_user_features(void) 3464 { 3465 user_feature_fixup(); 3466 3467 setup_elf_hwcaps(arm64_elf_hwcaps); 3468 3469 if (system_supports_32bit_el0()) { 3470 setup_elf_hwcaps(compat_elf_hwcaps); 3471 elf_hwcap_fixup(); 3472 } 3473 3474 minsigstksz_setup(); 3475 } 3476 3477 static int enable_mismatched_32bit_el0(unsigned int cpu) 3478 { 3479 /* 3480 * The first 32-bit-capable CPU we detected and so can no longer 3481 * be offlined by userspace. -1 indicates we haven't yet onlined 3482 * a 32-bit-capable CPU. 3483 */ 3484 static int lucky_winner = -1; 3485 3486 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3487 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3488 3489 if (cpu_32bit) { 3490 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3491 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3492 } 3493 3494 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3495 return 0; 3496 3497 if (lucky_winner >= 0) 3498 return 0; 3499 3500 /* 3501 * We've detected a mismatch. We need to keep one of our CPUs with 3502 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3503 * every CPU in the system for a 32-bit task. 3504 */ 3505 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3506 cpu_active_mask); 3507 get_cpu_device(lucky_winner)->offline_disabled = true; 3508 setup_elf_hwcaps(compat_elf_hwcaps); 3509 elf_hwcap_fixup(); 3510 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3511 cpu, lucky_winner); 3512 return 0; 3513 } 3514 3515 static int __init init_32bit_el0_mask(void) 3516 { 3517 if (!allow_mismatched_32bit_el0) 3518 return 0; 3519 3520 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3521 return -ENOMEM; 3522 3523 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3524 "arm64/mismatched_32bit_el0:online", 3525 enable_mismatched_32bit_el0, NULL); 3526 } 3527 subsys_initcall_sync(init_32bit_el0_mask); 3528 3529 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3530 { 3531 cpu_enable_swapper_cnp(); 3532 } 3533 3534 /* 3535 * We emulate only the following system register space. 3536 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3537 * See Table C5-6 System instruction encodings for System register accesses, 3538 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3539 */ 3540 static inline bool __attribute_const__ is_emulated(u32 id) 3541 { 3542 return (sys_reg_Op0(id) == 0x3 && 3543 sys_reg_CRn(id) == 0x0 && 3544 sys_reg_Op1(id) == 0x0 && 3545 (sys_reg_CRm(id) == 0 || 3546 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3547 } 3548 3549 /* 3550 * With CRm == 0, reg should be one of : 3551 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3552 */ 3553 static inline int emulate_id_reg(u32 id, u64 *valp) 3554 { 3555 switch (id) { 3556 case SYS_MIDR_EL1: 3557 *valp = read_cpuid_id(); 3558 break; 3559 case SYS_MPIDR_EL1: 3560 *valp = SYS_MPIDR_SAFE_VAL; 3561 break; 3562 case SYS_REVIDR_EL1: 3563 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3564 *valp = 0; 3565 break; 3566 default: 3567 return -EINVAL; 3568 } 3569 3570 return 0; 3571 } 3572 3573 static int emulate_sys_reg(u32 id, u64 *valp) 3574 { 3575 struct arm64_ftr_reg *regp; 3576 3577 if (!is_emulated(id)) 3578 return -EINVAL; 3579 3580 if (sys_reg_CRm(id) == 0) 3581 return emulate_id_reg(id, valp); 3582 3583 regp = get_arm64_ftr_reg_nowarn(id); 3584 if (regp) 3585 *valp = arm64_ftr_reg_user_value(regp); 3586 else 3587 /* 3588 * The untracked registers are either IMPLEMENTATION DEFINED 3589 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3590 */ 3591 *valp = 0; 3592 return 0; 3593 } 3594 3595 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3596 { 3597 int rc; 3598 u64 val; 3599 3600 rc = emulate_sys_reg(sys_reg, &val); 3601 if (!rc) { 3602 pt_regs_write_reg(regs, rt, val); 3603 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3604 } 3605 return rc; 3606 } 3607 3608 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3609 { 3610 u32 sys_reg, rt; 3611 3612 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3613 return false; 3614 3615 /* 3616 * sys_reg values are defined as used in mrs/msr instruction. 3617 * shift the imm value to get the encoding. 3618 */ 3619 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3620 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3621 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3622 } 3623 3624 enum mitigation_state arm64_get_meltdown_state(void) 3625 { 3626 if (__meltdown_safe) 3627 return SPECTRE_UNAFFECTED; 3628 3629 if (arm64_kernel_unmapped_at_el0()) 3630 return SPECTRE_MITIGATED; 3631 3632 return SPECTRE_VULNERABLE; 3633 } 3634 3635 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3636 char *buf) 3637 { 3638 switch (arm64_get_meltdown_state()) { 3639 case SPECTRE_UNAFFECTED: 3640 return sprintf(buf, "Not affected\n"); 3641 3642 case SPECTRE_MITIGATED: 3643 return sprintf(buf, "Mitigation: PTI\n"); 3644 3645 default: 3646 return sprintf(buf, "Vulnerable\n"); 3647 } 3648 } 3649