1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/processor.h> 90 #include <asm/smp.h> 91 #include <asm/sysreg.h> 92 #include <asm/traps.h> 93 #include <asm/vectors.h> 94 #include <asm/virt.h> 95 96 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 97 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 98 99 #ifdef CONFIG_COMPAT 100 #define COMPAT_ELF_HWCAP_DEFAULT \ 101 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 102 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 103 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 104 COMPAT_HWCAP_LPAE) 105 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 106 unsigned int compat_elf_hwcap2 __read_mostly; 107 unsigned int compat_elf_hwcap3 __read_mostly; 108 #endif 109 110 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 111 EXPORT_SYMBOL(system_cpucaps); 112 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 113 114 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 115 116 bool arm64_use_ng_mappings = false; 117 EXPORT_SYMBOL(arm64_use_ng_mappings); 118 119 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 120 121 /* 122 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 123 * support it? 124 */ 125 static bool __read_mostly allow_mismatched_32bit_el0; 126 127 /* 128 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 129 * seen at least one CPU capable of 32-bit EL0. 130 */ 131 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 132 133 /* 134 * Mask of CPUs supporting 32-bit EL0. 135 * Only valid if arm64_mismatched_32bit_el0 is enabled. 136 */ 137 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 138 139 void dump_cpu_features(void) 140 { 141 /* file-wide pr_fmt adds "CPU features: " prefix */ 142 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 143 } 144 145 #define __ARM64_MAX_POSITIVE(reg, field) \ 146 ((reg##_##field##_SIGNED ? \ 147 BIT(reg##_##field##_WIDTH - 1) : \ 148 BIT(reg##_##field##_WIDTH)) - 1) 149 150 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 151 152 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 153 .sys_reg = SYS_##reg, \ 154 .field_pos = reg##_##field##_SHIFT, \ 155 .field_width = reg##_##field##_WIDTH, \ 156 .sign = reg##_##field##_SIGNED, \ 157 .min_field_value = min_value, \ 158 .max_field_value = max_value, 159 160 /* 161 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 162 * an implicit maximum that depends on the sign-ess of the field. 163 * 164 * An unsigned field will be capped at all ones, while a signed field 165 * will be limited to the positive half only. 166 */ 167 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 168 __ARM64_CPUID_FIELDS(reg, field, \ 169 SYS_FIELD_VALUE(reg, field, min_value), \ 170 __ARM64_MAX_POSITIVE(reg, field)) 171 172 /* 173 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 174 * implicit minimal value to max_value. This should be used when 175 * matching a non-implemented property. 176 */ 177 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 178 __ARM64_CPUID_FIELDS(reg, field, \ 179 __ARM64_MIN_NEGATIVE(reg, field), \ 180 SYS_FIELD_VALUE(reg, field, max_value)) 181 182 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 183 { \ 184 .sign = SIGNED, \ 185 .visible = VISIBLE, \ 186 .strict = STRICT, \ 187 .type = TYPE, \ 188 .shift = SHIFT, \ 189 .width = WIDTH, \ 190 .safe_val = SAFE_VAL, \ 191 } 192 193 /* Define a feature with unsigned values */ 194 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 196 197 /* Define a feature with a signed value */ 198 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 199 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 200 201 #define ARM64_FTR_END \ 202 { \ 203 .width = 0, \ 204 } 205 206 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 207 208 static bool __system_matches_cap(unsigned int n); 209 210 /* 211 * NOTE: Any changes to the visibility of features should be kept in 212 * sync with the documentation of the CPU feature register ABI. 213 */ 214 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 229 ARM64_FTR_END, 230 }; 231 232 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 248 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 250 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 252 ARM64_FTR_END, 253 }; 254 255 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 265 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 268 ARM64_FTR_END, 269 }; 270 271 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 274 ARM64_FTR_END, 275 }; 276 277 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 285 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 288 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 289 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 294 ARM64_FTR_END, 295 }; 296 297 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 301 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 304 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 305 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 306 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 308 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 309 ARM64_FTR_END, 310 }; 311 312 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 313 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 314 ARM64_FTR_END, 315 }; 316 317 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 342 ARM64_FTR_END, 343 }; 344 345 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 392 ARM64_FTR_END, 393 }; 394 395 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 396 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 404 ARM64_FTR_END, 405 }; 406 407 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 411 /* 412 * Page size not being supported at Stage-2 is not fatal. You 413 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 414 * your favourite nesting hypervisor. 415 * 416 * There is a small corner case where the hypervisor explicitly 417 * advertises a given granule size at Stage-2 (value 2) on some 418 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 419 * vCPUs. Although this is not forbidden by the architecture, it 420 * indicates that the hypervisor is being silly (or buggy). 421 * 422 * We make no effort to cope with this and pretend that if these 423 * fields are inconsistent across vCPUs, then it isn't worth 424 * trying to bring KVM up. 425 */ 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 429 /* 430 * We already refuse to boot CPUs that don't support our configured 431 * page size, so we can only detect mismatches for a page size other 432 * than the one we're currently using. Unfortunately, SoCs like this 433 * exist in the wild so, even though we don't like it, we'll have to go 434 * along with it and treat them as non-strict. 435 */ 436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 437 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 439 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 441 /* Linux shouldn't care about secure memory */ 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 445 /* 446 * Differing PARange is fine as long as all peripherals and memory are mapped 447 * within the minimum PARange of all CPUs 448 */ 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 450 ARM64_FTR_END, 451 }; 452 453 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 468 ARM64_FTR_END, 469 }; 470 471 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 487 ARM64_FTR_END, 488 }; 489 490 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 491 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 492 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 499 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 500 ARM64_FTR_END, 501 }; 502 503 static const struct arm64_ftr_bits ftr_ctr[] = { 504 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 505 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 506 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 507 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 510 /* 511 * Linux can handle differing I-cache policies. Userspace JITs will 512 * make use of *minLine. 513 * If we have differing I-cache policies, report it as the weakest - VIPT. 514 */ 515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 517 ARM64_FTR_END, 518 }; 519 520 static struct arm64_ftr_override __ro_after_init no_override = { }; 521 522 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 523 .name = "SYS_CTR_EL0", 524 .ftr_bits = ftr_ctr, 525 .override = &no_override, 526 }; 527 528 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 529 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 534 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 537 ARM64_FTR_END, 538 }; 539 540 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 541 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 546 /* 547 * We can instantiate multiple PMU instances with different levels 548 * of support. 549 */ 550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 552 ARM64_FTR_END, 553 }; 554 555 static const struct arm64_ftr_bits ftr_mvfr0[] = { 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_mvfr1[] = { 568 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 576 ARM64_FTR_END, 577 }; 578 579 static const struct arm64_ftr_bits ftr_mvfr2[] = { 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 582 ARM64_FTR_END, 583 }; 584 585 static const struct arm64_ftr_bits ftr_dczid[] = { 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 588 ARM64_FTR_END, 589 }; 590 591 static const struct arm64_ftr_bits ftr_gmid[] = { 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 593 ARM64_FTR_END, 594 }; 595 596 static const struct arm64_ftr_bits ftr_id_isar0[] = { 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 604 ARM64_FTR_END, 605 }; 606 607 static const struct arm64_ftr_bits ftr_id_isar5[] = { 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 625 626 /* 627 * SpecSEI = 1 indicates that the PE might generate an SError on an 628 * external abort on speculative read. It is safe to assume that an 629 * SError might be generated than it will not be. Hence it has been 630 * classified as FTR_HIGHER_SAFE. 631 */ 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 633 ARM64_FTR_END, 634 }; 635 636 static const struct arm64_ftr_bits ftr_id_isar4[] = { 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 645 ARM64_FTR_END, 646 }; 647 648 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 650 ARM64_FTR_END, 651 }; 652 653 static const struct arm64_ftr_bits ftr_id_isar6[] = { 654 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 661 ARM64_FTR_END, 662 }; 663 664 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 687 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 689 ARM64_FTR_END, 690 }; 691 692 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 693 /* [31:28] TraceFilt */ 694 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 701 ARM64_FTR_END, 702 }; 703 704 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 705 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 706 ARM64_FTR_END, 707 }; 708 709 static const struct arm64_ftr_bits ftr_mpamidr[] = { 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 714 ARM64_FTR_END, 715 }; 716 717 /* 718 * Common ftr bits for a 32bit register with all hidden, strict 719 * attributes, with 4bit feature fields and a default safe value of 720 * 0. Covers the following 32bit registers: 721 * id_isar[1-3], id_mmfr[1-3] 722 */ 723 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 731 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 732 ARM64_FTR_END, 733 }; 734 735 /* Table for a single 32bit feature value */ 736 static const struct arm64_ftr_bits ftr_single32[] = { 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 738 ARM64_FTR_END, 739 }; 740 741 static const struct arm64_ftr_bits ftr_raz[] = { 742 ARM64_FTR_END, 743 }; 744 745 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 746 .sys_id = id, \ 747 .reg = &(struct arm64_ftr_reg){ \ 748 .name = id_str, \ 749 .override = (ovr), \ 750 .ftr_bits = &((table)[0]), \ 751 }} 752 753 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 754 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 755 756 #define ARM64_FTR_REG(id, table) \ 757 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 758 759 struct arm64_ftr_override id_aa64mmfr0_override; 760 struct arm64_ftr_override id_aa64mmfr1_override; 761 struct arm64_ftr_override id_aa64mmfr2_override; 762 struct arm64_ftr_override id_aa64pfr0_override; 763 struct arm64_ftr_override id_aa64pfr1_override; 764 struct arm64_ftr_override id_aa64zfr0_override; 765 struct arm64_ftr_override id_aa64smfr0_override; 766 struct arm64_ftr_override id_aa64isar1_override; 767 struct arm64_ftr_override id_aa64isar2_override; 768 769 struct arm64_ftr_override arm64_sw_feature_override; 770 771 static const struct __ftr_reg_entry { 772 u32 sys_id; 773 struct arm64_ftr_reg *reg; 774 } arm64_ftr_regs[] = { 775 776 /* Op1 = 0, CRn = 0, CRm = 1 */ 777 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 778 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 779 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 780 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 781 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 782 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 783 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 784 785 /* Op1 = 0, CRn = 0, CRm = 2 */ 786 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 787 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 788 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 789 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 790 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 791 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 792 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 793 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 794 795 /* Op1 = 0, CRn = 0, CRm = 3 */ 796 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 797 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 798 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 799 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 800 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 801 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 802 803 /* Op1 = 0, CRn = 0, CRm = 4 */ 804 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 805 &id_aa64pfr0_override), 806 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 807 &id_aa64pfr1_override), 808 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 809 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 810 &id_aa64zfr0_override), 811 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 812 &id_aa64smfr0_override), 813 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 814 815 /* Op1 = 0, CRn = 0, CRm = 5 */ 816 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 817 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 818 819 /* Op1 = 0, CRn = 0, CRm = 6 */ 820 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 821 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 822 &id_aa64isar1_override), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 824 &id_aa64isar2_override), 825 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 826 827 /* Op1 = 0, CRn = 0, CRm = 7 */ 828 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 829 &id_aa64mmfr0_override), 830 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 831 &id_aa64mmfr1_override), 832 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 833 &id_aa64mmfr2_override), 834 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 835 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 836 837 /* Op1 = 0, CRn = 10, CRm = 4 */ 838 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 839 840 /* Op1 = 1, CRn = 0, CRm = 0 */ 841 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 842 843 /* Op1 = 3, CRn = 0, CRm = 0 */ 844 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 845 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 846 847 /* Op1 = 3, CRn = 14, CRm = 0 */ 848 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 849 }; 850 851 static int search_cmp_ftr_reg(const void *id, const void *regp) 852 { 853 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 854 } 855 856 /* 857 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 858 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 859 * ascending order of sys_id, we use binary search to find a matching 860 * entry. 861 * 862 * returns - Upon success, matching ftr_reg entry for id. 863 * - NULL on failure. It is upto the caller to decide 864 * the impact of a failure. 865 */ 866 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 867 { 868 const struct __ftr_reg_entry *ret; 869 870 ret = bsearch((const void *)(unsigned long)sys_id, 871 arm64_ftr_regs, 872 ARRAY_SIZE(arm64_ftr_regs), 873 sizeof(arm64_ftr_regs[0]), 874 search_cmp_ftr_reg); 875 if (ret) 876 return ret->reg; 877 return NULL; 878 } 879 880 /* 881 * get_arm64_ftr_reg - Looks up a feature register entry using 882 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 883 * 884 * returns - Upon success, matching ftr_reg entry for id. 885 * - NULL on failure but with an WARN_ON(). 886 */ 887 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 888 { 889 struct arm64_ftr_reg *reg; 890 891 reg = get_arm64_ftr_reg_nowarn(sys_id); 892 893 /* 894 * Requesting a non-existent register search is an error. Warn 895 * and let the caller handle it. 896 */ 897 WARN_ON(!reg); 898 return reg; 899 } 900 901 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 902 s64 ftr_val) 903 { 904 u64 mask = arm64_ftr_mask(ftrp); 905 906 reg &= ~mask; 907 reg |= (ftr_val << ftrp->shift) & mask; 908 return reg; 909 } 910 911 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 912 s64 cur) 913 { 914 s64 ret = 0; 915 916 switch (ftrp->type) { 917 case FTR_EXACT: 918 ret = ftrp->safe_val; 919 break; 920 case FTR_LOWER_SAFE: 921 ret = min(new, cur); 922 break; 923 case FTR_HIGHER_OR_ZERO_SAFE: 924 if (!cur || !new) 925 break; 926 fallthrough; 927 case FTR_HIGHER_SAFE: 928 ret = max(new, cur); 929 break; 930 default: 931 BUG(); 932 } 933 934 return ret; 935 } 936 937 static void __init sort_ftr_regs(void) 938 { 939 unsigned int i; 940 941 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 942 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 943 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 944 unsigned int j = 0; 945 946 /* 947 * Features here must be sorted in descending order with respect 948 * to their shift values and should not overlap with each other. 949 */ 950 for (; ftr_bits->width != 0; ftr_bits++, j++) { 951 unsigned int width = ftr_reg->ftr_bits[j].width; 952 unsigned int shift = ftr_reg->ftr_bits[j].shift; 953 unsigned int prev_shift; 954 955 WARN((shift + width) > 64, 956 "%s has invalid feature at shift %d\n", 957 ftr_reg->name, shift); 958 959 /* 960 * Skip the first feature. There is nothing to 961 * compare against for now. 962 */ 963 if (j == 0) 964 continue; 965 966 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 967 WARN((shift + width) > prev_shift, 968 "%s has feature overlap at shift %d\n", 969 ftr_reg->name, shift); 970 } 971 972 /* 973 * Skip the first register. There is nothing to 974 * compare against for now. 975 */ 976 if (i == 0) 977 continue; 978 /* 979 * Registers here must be sorted in ascending order with respect 980 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 981 * to work correctly. 982 */ 983 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 984 } 985 } 986 987 /* 988 * Initialise the CPU feature register from Boot CPU values. 989 * Also initiliases the strict_mask for the register. 990 * Any bits that are not covered by an arm64_ftr_bits entry are considered 991 * RES0 for the system-wide value, and must strictly match. 992 */ 993 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 994 { 995 u64 val = 0; 996 u64 strict_mask = ~0x0ULL; 997 u64 user_mask = 0; 998 u64 valid_mask = 0; 999 1000 const struct arm64_ftr_bits *ftrp; 1001 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1002 1003 if (!reg) 1004 return; 1005 1006 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1007 u64 ftr_mask = arm64_ftr_mask(ftrp); 1008 s64 ftr_new = arm64_ftr_value(ftrp, new); 1009 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1010 1011 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1012 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1013 char *str = NULL; 1014 1015 if (ftr_ovr != tmp) { 1016 /* Unsafe, remove the override */ 1017 reg->override->mask &= ~ftr_mask; 1018 reg->override->val &= ~ftr_mask; 1019 tmp = ftr_ovr; 1020 str = "ignoring override"; 1021 } else if (ftr_new != tmp) { 1022 /* Override was valid */ 1023 ftr_new = tmp; 1024 str = "forced"; 1025 } else { 1026 /* Override was the safe value */ 1027 str = "already set"; 1028 } 1029 1030 pr_warn("%s[%d:%d]: %s to %llx\n", 1031 reg->name, 1032 ftrp->shift + ftrp->width - 1, 1033 ftrp->shift, str, 1034 tmp & (BIT(ftrp->width) - 1)); 1035 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1036 reg->override->val &= ~ftr_mask; 1037 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1038 reg->name, 1039 ftrp->shift + ftrp->width - 1, 1040 ftrp->shift); 1041 } 1042 1043 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1044 1045 valid_mask |= ftr_mask; 1046 if (!ftrp->strict) 1047 strict_mask &= ~ftr_mask; 1048 if (ftrp->visible) 1049 user_mask |= ftr_mask; 1050 else 1051 reg->user_val = arm64_ftr_set_value(ftrp, 1052 reg->user_val, 1053 ftrp->safe_val); 1054 } 1055 1056 val &= valid_mask; 1057 1058 reg->sys_val = val; 1059 reg->strict_mask = strict_mask; 1060 reg->user_mask = user_mask; 1061 } 1062 1063 extern const struct arm64_cpu_capabilities arm64_errata[]; 1064 static const struct arm64_cpu_capabilities arm64_features[]; 1065 1066 static void __init 1067 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1068 { 1069 for (; caps->matches; caps++) { 1070 if (WARN(caps->capability >= ARM64_NCAPS, 1071 "Invalid capability %d\n", caps->capability)) 1072 continue; 1073 if (WARN(cpucap_ptrs[caps->capability], 1074 "Duplicate entry for capability %d\n", 1075 caps->capability)) 1076 continue; 1077 cpucap_ptrs[caps->capability] = caps; 1078 } 1079 } 1080 1081 static void __init init_cpucap_indirect_list(void) 1082 { 1083 init_cpucap_indirect_list_from_array(arm64_features); 1084 init_cpucap_indirect_list_from_array(arm64_errata); 1085 } 1086 1087 static void __init setup_boot_cpu_capabilities(void); 1088 1089 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1090 { 1091 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1092 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1093 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1094 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1095 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1096 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1097 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1098 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1099 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1100 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1101 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1102 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1103 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1104 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1105 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1106 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1107 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1108 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1109 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1110 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1111 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1112 } 1113 1114 #ifdef CONFIG_ARM64_PSEUDO_NMI 1115 static bool enable_pseudo_nmi; 1116 1117 static int __init early_enable_pseudo_nmi(char *p) 1118 { 1119 return kstrtobool(p, &enable_pseudo_nmi); 1120 } 1121 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1122 1123 static __init void detect_system_supports_pseudo_nmi(void) 1124 { 1125 struct device_node *np; 1126 1127 if (!enable_pseudo_nmi) 1128 return; 1129 1130 /* 1131 * Detect broken MediaTek firmware that doesn't properly save and 1132 * restore GIC priorities. 1133 */ 1134 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1135 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1136 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1137 enable_pseudo_nmi = false; 1138 } 1139 of_node_put(np); 1140 } 1141 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1142 static inline void detect_system_supports_pseudo_nmi(void) { } 1143 #endif 1144 1145 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1146 { 1147 /* Before we start using the tables, make sure it is sorted */ 1148 sort_ftr_regs(); 1149 1150 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1151 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1152 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1153 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1154 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1155 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1156 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1157 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1158 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1159 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1160 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1161 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1162 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1163 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1164 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1165 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1166 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1167 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1168 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1169 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1170 1171 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1172 init_32bit_cpu_features(&info->aarch32); 1173 1174 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1175 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1176 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1177 1178 vec_init_vq_map(ARM64_VEC_SVE); 1179 1180 cpacr_restore(cpacr); 1181 } 1182 1183 if (IS_ENABLED(CONFIG_ARM64_SME) && 1184 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1185 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1186 1187 vec_init_vq_map(ARM64_VEC_SME); 1188 1189 cpacr_restore(cpacr); 1190 } 1191 1192 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1193 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1194 1195 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1196 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1197 } 1198 1199 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1200 { 1201 const struct arm64_ftr_bits *ftrp; 1202 1203 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1204 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1205 s64 ftr_new = arm64_ftr_value(ftrp, new); 1206 1207 if (ftr_cur == ftr_new) 1208 continue; 1209 /* Find a safe value */ 1210 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1211 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1212 } 1213 1214 } 1215 1216 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1217 { 1218 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1219 1220 if (!regp) 1221 return 0; 1222 1223 update_cpu_ftr_reg(regp, val); 1224 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1225 return 0; 1226 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1227 regp->name, boot, cpu, val); 1228 return 1; 1229 } 1230 1231 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1232 { 1233 const struct arm64_ftr_bits *ftrp; 1234 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1235 1236 if (!regp) 1237 return; 1238 1239 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1240 if (ftrp->shift == field) { 1241 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1242 break; 1243 } 1244 } 1245 1246 /* Bogus field? */ 1247 WARN_ON(!ftrp->width); 1248 } 1249 1250 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1251 struct cpuinfo_arm64 *boot) 1252 { 1253 static bool boot_cpu_32bit_regs_overridden = false; 1254 1255 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1256 return; 1257 1258 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1259 return; 1260 1261 boot->aarch32 = info->aarch32; 1262 init_32bit_cpu_features(&boot->aarch32); 1263 boot_cpu_32bit_regs_overridden = true; 1264 } 1265 1266 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1267 struct cpuinfo_32bit *boot) 1268 { 1269 int taint = 0; 1270 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1271 1272 /* 1273 * If we don't have AArch32 at EL1, then relax the strictness of 1274 * EL1-dependent register fields to avoid spurious sanity check fails. 1275 */ 1276 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1277 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1278 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1279 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1280 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1281 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1282 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1283 } 1284 1285 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1286 info->reg_id_dfr0, boot->reg_id_dfr0); 1287 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1288 info->reg_id_dfr1, boot->reg_id_dfr1); 1289 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1290 info->reg_id_isar0, boot->reg_id_isar0); 1291 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1292 info->reg_id_isar1, boot->reg_id_isar1); 1293 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1294 info->reg_id_isar2, boot->reg_id_isar2); 1295 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1296 info->reg_id_isar3, boot->reg_id_isar3); 1297 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1298 info->reg_id_isar4, boot->reg_id_isar4); 1299 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1300 info->reg_id_isar5, boot->reg_id_isar5); 1301 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1302 info->reg_id_isar6, boot->reg_id_isar6); 1303 1304 /* 1305 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1306 * ACTLR formats could differ across CPUs and therefore would have to 1307 * be trapped for virtualization anyway. 1308 */ 1309 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1310 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1311 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1312 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1313 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1314 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1315 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1316 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1317 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1318 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1319 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1320 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1321 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1322 info->reg_id_pfr0, boot->reg_id_pfr0); 1323 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1324 info->reg_id_pfr1, boot->reg_id_pfr1); 1325 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1326 info->reg_id_pfr2, boot->reg_id_pfr2); 1327 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1328 info->reg_mvfr0, boot->reg_mvfr0); 1329 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1330 info->reg_mvfr1, boot->reg_mvfr1); 1331 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1332 info->reg_mvfr2, boot->reg_mvfr2); 1333 1334 return taint; 1335 } 1336 1337 /* 1338 * Update system wide CPU feature registers with the values from a 1339 * non-boot CPU. Also performs SANITY checks to make sure that there 1340 * aren't any insane variations from that of the boot CPU. 1341 */ 1342 void update_cpu_features(int cpu, 1343 struct cpuinfo_arm64 *info, 1344 struct cpuinfo_arm64 *boot) 1345 { 1346 int taint = 0; 1347 1348 /* 1349 * The kernel can handle differing I-cache policies, but otherwise 1350 * caches should look identical. Userspace JITs will make use of 1351 * *minLine. 1352 */ 1353 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1354 info->reg_ctr, boot->reg_ctr); 1355 1356 /* 1357 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1358 * could result in too much or too little memory being zeroed if a 1359 * process is preempted and migrated between CPUs. 1360 */ 1361 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1362 info->reg_dczid, boot->reg_dczid); 1363 1364 /* If different, timekeeping will be broken (especially with KVM) */ 1365 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1366 info->reg_cntfrq, boot->reg_cntfrq); 1367 1368 /* 1369 * The kernel uses self-hosted debug features and expects CPUs to 1370 * support identical debug features. We presently need CTX_CMPs, WRPs, 1371 * and BRPs to be identical. 1372 * ID_AA64DFR1 is currently RES0. 1373 */ 1374 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1375 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1376 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1377 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1378 /* 1379 * Even in big.LITTLE, processors should be identical instruction-set 1380 * wise. 1381 */ 1382 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1383 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1384 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1385 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1386 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1387 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1388 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1389 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1390 1391 /* 1392 * Differing PARange support is fine as long as all peripherals and 1393 * memory are mapped within the minimum PARange of all CPUs. 1394 * Linux should not care about secure memory. 1395 */ 1396 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1397 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1398 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1399 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1400 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1401 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1402 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1403 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1404 1405 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1406 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1407 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1408 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1409 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1410 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1411 1412 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1413 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1414 1415 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1416 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1417 1418 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1419 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1420 1421 /* Probe vector lengths */ 1422 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1423 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1424 if (!system_capabilities_finalized()) { 1425 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1426 1427 vec_update_vq_map(ARM64_VEC_SVE); 1428 1429 cpacr_restore(cpacr); 1430 } 1431 } 1432 1433 if (IS_ENABLED(CONFIG_ARM64_SME) && 1434 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1435 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1436 1437 /* Probe vector lengths */ 1438 if (!system_capabilities_finalized()) 1439 vec_update_vq_map(ARM64_VEC_SME); 1440 1441 cpacr_restore(cpacr); 1442 } 1443 1444 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1445 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1446 info->reg_mpamidr, boot->reg_mpamidr); 1447 } 1448 1449 /* 1450 * The kernel uses the LDGM/STGM instructions and the number of tags 1451 * they read/write depends on the GMID_EL1.BS field. Check that the 1452 * value is the same on all CPUs. 1453 */ 1454 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1455 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1456 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1457 info->reg_gmid, boot->reg_gmid); 1458 } 1459 1460 /* 1461 * If we don't have AArch32 at all then skip the checks entirely 1462 * as the register values may be UNKNOWN and we're not going to be 1463 * using them for anything. 1464 * 1465 * This relies on a sanitised view of the AArch64 ID registers 1466 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1467 */ 1468 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1469 lazy_init_32bit_cpu_features(info, boot); 1470 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1471 &boot->aarch32); 1472 } 1473 1474 /* 1475 * Mismatched CPU features are a recipe for disaster. Don't even 1476 * pretend to support them. 1477 */ 1478 if (taint) { 1479 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1480 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1481 } 1482 } 1483 1484 u64 read_sanitised_ftr_reg(u32 id) 1485 { 1486 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1487 1488 if (!regp) 1489 return 0; 1490 return regp->sys_val; 1491 } 1492 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1493 1494 #define read_sysreg_case(r) \ 1495 case r: val = read_sysreg_s(r); break; 1496 1497 /* 1498 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1499 * Read the system register on the current CPU 1500 */ 1501 u64 __read_sysreg_by_encoding(u32 sys_id) 1502 { 1503 struct arm64_ftr_reg *regp; 1504 u64 val; 1505 1506 switch (sys_id) { 1507 read_sysreg_case(SYS_ID_PFR0_EL1); 1508 read_sysreg_case(SYS_ID_PFR1_EL1); 1509 read_sysreg_case(SYS_ID_PFR2_EL1); 1510 read_sysreg_case(SYS_ID_DFR0_EL1); 1511 read_sysreg_case(SYS_ID_DFR1_EL1); 1512 read_sysreg_case(SYS_ID_MMFR0_EL1); 1513 read_sysreg_case(SYS_ID_MMFR1_EL1); 1514 read_sysreg_case(SYS_ID_MMFR2_EL1); 1515 read_sysreg_case(SYS_ID_MMFR3_EL1); 1516 read_sysreg_case(SYS_ID_MMFR4_EL1); 1517 read_sysreg_case(SYS_ID_MMFR5_EL1); 1518 read_sysreg_case(SYS_ID_ISAR0_EL1); 1519 read_sysreg_case(SYS_ID_ISAR1_EL1); 1520 read_sysreg_case(SYS_ID_ISAR2_EL1); 1521 read_sysreg_case(SYS_ID_ISAR3_EL1); 1522 read_sysreg_case(SYS_ID_ISAR4_EL1); 1523 read_sysreg_case(SYS_ID_ISAR5_EL1); 1524 read_sysreg_case(SYS_ID_ISAR6_EL1); 1525 read_sysreg_case(SYS_MVFR0_EL1); 1526 read_sysreg_case(SYS_MVFR1_EL1); 1527 read_sysreg_case(SYS_MVFR2_EL1); 1528 1529 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1530 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1531 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1532 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1533 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1534 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1535 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1536 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1537 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1538 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1539 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1540 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1541 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1542 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1543 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1544 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1545 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1546 1547 read_sysreg_case(SYS_CNTFRQ_EL0); 1548 read_sysreg_case(SYS_CTR_EL0); 1549 read_sysreg_case(SYS_DCZID_EL0); 1550 1551 default: 1552 BUG(); 1553 return 0; 1554 } 1555 1556 regp = get_arm64_ftr_reg(sys_id); 1557 if (regp) { 1558 val &= ~regp->override->mask; 1559 val |= (regp->override->val & regp->override->mask); 1560 } 1561 1562 return val; 1563 } 1564 1565 #include <linux/irqchip/arm-gic-v3.h> 1566 1567 static bool 1568 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1569 { 1570 return true; 1571 } 1572 1573 static bool 1574 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1575 { 1576 int val, min, max; 1577 u64 tmp; 1578 1579 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1580 entry->field_width, 1581 entry->sign); 1582 1583 tmp = entry->min_field_value; 1584 tmp <<= entry->field_pos; 1585 1586 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1587 entry->field_width, 1588 entry->sign); 1589 1590 tmp = entry->max_field_value; 1591 tmp <<= entry->field_pos; 1592 1593 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1594 entry->field_width, 1595 entry->sign); 1596 1597 return val >= min && val <= max; 1598 } 1599 1600 static u64 1601 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1602 { 1603 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1604 if (scope == SCOPE_SYSTEM) 1605 return read_sanitised_ftr_reg(entry->sys_reg); 1606 else 1607 return __read_sysreg_by_encoding(entry->sys_reg); 1608 } 1609 1610 static bool 1611 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1612 { 1613 int mask; 1614 struct arm64_ftr_reg *regp; 1615 u64 val = read_scoped_sysreg(entry, scope); 1616 1617 regp = get_arm64_ftr_reg(entry->sys_reg); 1618 if (!regp) 1619 return false; 1620 1621 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1622 entry->field_pos, 1623 entry->field_width); 1624 if (!mask) 1625 return false; 1626 1627 return feature_matches(val, entry); 1628 } 1629 1630 static bool 1631 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1632 { 1633 u64 val = read_scoped_sysreg(entry, scope); 1634 return feature_matches(val, entry); 1635 } 1636 1637 const struct cpumask *system_32bit_el0_cpumask(void) 1638 { 1639 if (!system_supports_32bit_el0()) 1640 return cpu_none_mask; 1641 1642 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1643 return cpu_32bit_el0_mask; 1644 1645 return cpu_possible_mask; 1646 } 1647 1648 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1649 { 1650 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1651 } 1652 1653 static int __init parse_32bit_el0_param(char *str) 1654 { 1655 allow_mismatched_32bit_el0 = true; 1656 return 0; 1657 } 1658 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1659 1660 static ssize_t aarch32_el0_show(struct device *dev, 1661 struct device_attribute *attr, char *buf) 1662 { 1663 const struct cpumask *mask = system_32bit_el0_cpumask(); 1664 1665 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1666 } 1667 static const DEVICE_ATTR_RO(aarch32_el0); 1668 1669 static int __init aarch32_el0_sysfs_init(void) 1670 { 1671 struct device *dev_root; 1672 int ret = 0; 1673 1674 if (!allow_mismatched_32bit_el0) 1675 return 0; 1676 1677 dev_root = bus_get_dev_root(&cpu_subsys); 1678 if (dev_root) { 1679 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1680 put_device(dev_root); 1681 } 1682 return ret; 1683 } 1684 device_initcall(aarch32_el0_sysfs_init); 1685 1686 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1687 { 1688 if (!has_cpuid_feature(entry, scope)) 1689 return allow_mismatched_32bit_el0; 1690 1691 if (scope == SCOPE_SYSTEM) 1692 pr_info("detected: 32-bit EL0 Support\n"); 1693 1694 return true; 1695 } 1696 1697 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1698 { 1699 bool has_sre; 1700 1701 if (!has_cpuid_feature(entry, scope)) 1702 return false; 1703 1704 has_sre = gic_enable_sre(); 1705 if (!has_sre) 1706 pr_warn_once("%s present but disabled by higher exception level\n", 1707 entry->desc); 1708 1709 return has_sre; 1710 } 1711 1712 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1713 int scope) 1714 { 1715 u64 ctr; 1716 1717 if (scope == SCOPE_SYSTEM) 1718 ctr = arm64_ftr_reg_ctrel0.sys_val; 1719 else 1720 ctr = read_cpuid_effective_cachetype(); 1721 1722 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1723 } 1724 1725 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1726 { 1727 /* 1728 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1729 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1730 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1731 * value. 1732 */ 1733 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1734 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1735 } 1736 1737 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1738 int scope) 1739 { 1740 u64 ctr; 1741 1742 if (scope == SCOPE_SYSTEM) 1743 ctr = arm64_ftr_reg_ctrel0.sys_val; 1744 else 1745 ctr = read_cpuid_cachetype(); 1746 1747 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1748 } 1749 1750 static bool __maybe_unused 1751 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1752 { 1753 /* 1754 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1755 * may share TLB entries with a CPU stuck in the crashed 1756 * kernel. 1757 */ 1758 if (is_kdump_kernel()) 1759 return false; 1760 1761 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1762 return false; 1763 1764 return has_cpuid_feature(entry, scope); 1765 } 1766 1767 static bool __meltdown_safe = true; 1768 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1769 1770 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1771 int scope) 1772 { 1773 /* List of CPUs that are not vulnerable and don't need KPTI */ 1774 static const struct midr_range kpti_safe_list[] = { 1775 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1776 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1777 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1778 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1779 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1780 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1781 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1782 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1783 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1784 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1785 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1786 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1787 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1788 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1789 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1790 { /* sentinel */ } 1791 }; 1792 char const *str = "kpti command line option"; 1793 bool meltdown_safe; 1794 1795 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1796 1797 /* Defer to CPU feature registers */ 1798 if (has_cpuid_feature(entry, scope)) 1799 meltdown_safe = true; 1800 1801 if (!meltdown_safe) 1802 __meltdown_safe = false; 1803 1804 /* 1805 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1806 * ThunderX leads to apparent I-cache corruption of kernel text, which 1807 * ends as well as you might imagine. Don't even try. We cannot rely 1808 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1809 * because cpucap detection order may change. However, since we know 1810 * affected CPUs are always in a homogeneous configuration, it is 1811 * safe to rely on this_cpu_has_cap() here. 1812 */ 1813 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1814 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1815 __kpti_forced = -1; 1816 } 1817 1818 /* Useful for KASLR robustness */ 1819 if (kaslr_enabled() && kaslr_requires_kpti()) { 1820 if (!__kpti_forced) { 1821 str = "KASLR"; 1822 __kpti_forced = 1; 1823 } 1824 } 1825 1826 if (cpu_mitigations_off() && !__kpti_forced) { 1827 str = "mitigations=off"; 1828 __kpti_forced = -1; 1829 } 1830 1831 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1832 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1833 return false; 1834 } 1835 1836 /* Forced? */ 1837 if (__kpti_forced) { 1838 pr_info_once("kernel page table isolation forced %s by %s\n", 1839 __kpti_forced > 0 ? "ON" : "OFF", str); 1840 return __kpti_forced > 0; 1841 } 1842 1843 return !meltdown_safe; 1844 } 1845 1846 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1847 { 1848 /* 1849 * Although the Apple M2 family appears to support NV1, the 1850 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1851 * that it doesn't support NV1 at all. 1852 */ 1853 static const struct midr_range nv1_ni_list[] = { 1854 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1855 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1856 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1857 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1858 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1859 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1860 {} 1861 }; 1862 1863 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1864 !(has_cpuid_feature(entry, scope) || 1865 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1866 } 1867 1868 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1869 static bool has_lpa2_at_stage1(u64 mmfr0) 1870 { 1871 unsigned int tgran; 1872 1873 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1874 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1875 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1876 } 1877 1878 static bool has_lpa2_at_stage2(u64 mmfr0) 1879 { 1880 unsigned int tgran; 1881 1882 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1883 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1884 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1885 } 1886 1887 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1888 { 1889 u64 mmfr0; 1890 1891 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1892 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1893 } 1894 #else 1895 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1896 { 1897 return false; 1898 } 1899 #endif 1900 1901 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1902 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1903 1904 extern 1905 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1906 phys_addr_t size, pgprot_t prot, 1907 phys_addr_t (*pgtable_alloc)(int), int flags); 1908 1909 static phys_addr_t __initdata kpti_ng_temp_alloc; 1910 1911 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1912 { 1913 kpti_ng_temp_alloc -= PAGE_SIZE; 1914 return kpti_ng_temp_alloc; 1915 } 1916 1917 static int __init __kpti_install_ng_mappings(void *__unused) 1918 { 1919 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1920 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1921 kpti_remap_fn *remap_fn; 1922 1923 int cpu = smp_processor_id(); 1924 int levels = CONFIG_PGTABLE_LEVELS; 1925 int order = order_base_2(levels); 1926 u64 kpti_ng_temp_pgd_pa = 0; 1927 pgd_t *kpti_ng_temp_pgd; 1928 u64 alloc = 0; 1929 1930 if (levels == 5 && !pgtable_l5_enabled()) 1931 levels = 4; 1932 else if (levels == 4 && !pgtable_l4_enabled()) 1933 levels = 3; 1934 1935 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1936 1937 if (!cpu) { 1938 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1939 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1940 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1941 1942 // 1943 // Create a minimal page table hierarchy that permits us to map 1944 // the swapper page tables temporarily as we traverse them. 1945 // 1946 // The physical pages are laid out as follows: 1947 // 1948 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1949 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1950 // +--------+-\-------+-\------ +-\------ +-///--------+ 1951 // ^ 1952 // The first page is mapped into this hierarchy at a PMD_SHIFT 1953 // aligned virtual address, so that we can manipulate the PTE 1954 // level entries while the mapping is active. The first entry 1955 // covers the PTE[] page itself, the remaining entries are free 1956 // to be used as a ad-hoc fixmap. 1957 // 1958 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1959 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1960 kpti_ng_pgd_alloc, 0); 1961 } 1962 1963 cpu_install_idmap(); 1964 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1965 cpu_uninstall_idmap(); 1966 1967 if (!cpu) { 1968 free_pages(alloc, order); 1969 arm64_use_ng_mappings = true; 1970 } 1971 1972 return 0; 1973 } 1974 1975 static void __init kpti_install_ng_mappings(void) 1976 { 1977 /* Check whether KPTI is going to be used */ 1978 if (!arm64_kernel_unmapped_at_el0()) 1979 return; 1980 1981 /* 1982 * We don't need to rewrite the page-tables if either we've done 1983 * it already or we have KASLR enabled and therefore have not 1984 * created any global mappings at all. 1985 */ 1986 if (arm64_use_ng_mappings) 1987 return; 1988 1989 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1990 } 1991 1992 #else 1993 static inline void kpti_install_ng_mappings(void) 1994 { 1995 } 1996 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1997 1998 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1999 { 2000 if (__this_cpu_read(this_cpu_vector) == vectors) { 2001 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2002 2003 __this_cpu_write(this_cpu_vector, v); 2004 } 2005 2006 } 2007 2008 static int __init parse_kpti(char *str) 2009 { 2010 bool enabled; 2011 int ret = kstrtobool(str, &enabled); 2012 2013 if (ret) 2014 return ret; 2015 2016 __kpti_forced = enabled ? 1 : -1; 2017 return 0; 2018 } 2019 early_param("kpti", parse_kpti); 2020 2021 #ifdef CONFIG_ARM64_HW_AFDBM 2022 static struct cpumask dbm_cpus __read_mostly; 2023 2024 static inline void __cpu_enable_hw_dbm(void) 2025 { 2026 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2027 2028 write_sysreg(tcr, tcr_el1); 2029 isb(); 2030 local_flush_tlb_all(); 2031 } 2032 2033 static bool cpu_has_broken_dbm(void) 2034 { 2035 /* List of CPUs which have broken DBM support. */ 2036 static const struct midr_range cpus[] = { 2037 #ifdef CONFIG_ARM64_ERRATUM_1024718 2038 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2039 /* Kryo4xx Silver (rdpe => r1p0) */ 2040 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2041 #endif 2042 #ifdef CONFIG_ARM64_ERRATUM_2051678 2043 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2044 #endif 2045 {}, 2046 }; 2047 2048 return is_midr_in_range_list(read_cpuid_id(), cpus); 2049 } 2050 2051 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2052 { 2053 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2054 !cpu_has_broken_dbm(); 2055 } 2056 2057 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2058 { 2059 if (cpu_can_use_dbm(cap)) { 2060 __cpu_enable_hw_dbm(); 2061 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2062 } 2063 } 2064 2065 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2066 int __unused) 2067 { 2068 /* 2069 * DBM is a non-conflicting feature. i.e, the kernel can safely 2070 * run a mix of CPUs with and without the feature. So, we 2071 * unconditionally enable the capability to allow any late CPU 2072 * to use the feature. We only enable the control bits on the 2073 * CPU, if it is supported. 2074 */ 2075 2076 return true; 2077 } 2078 2079 #endif 2080 2081 #ifdef CONFIG_ARM64_AMU_EXTN 2082 2083 /* 2084 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2085 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2086 * information regarding all the events that it supports. When a CPU bit is 2087 * set in the cpumask, the user of this feature can only rely on the presence 2088 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2089 * counters are enabled or access to these counters is enabled by code 2090 * executed at higher exception levels (firmware). 2091 */ 2092 static struct cpumask amu_cpus __read_mostly; 2093 2094 bool cpu_has_amu_feat(int cpu) 2095 { 2096 return cpumask_test_cpu(cpu, &amu_cpus); 2097 } 2098 2099 int get_cpu_with_amu_feat(void) 2100 { 2101 return cpumask_any(&amu_cpus); 2102 } 2103 2104 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2105 { 2106 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2107 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2108 2109 /* 0 reference values signal broken/disabled counters */ 2110 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2111 update_freq_counters_refs(); 2112 } 2113 } 2114 2115 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2116 int __unused) 2117 { 2118 /* 2119 * The AMU extension is a non-conflicting feature: the kernel can 2120 * safely run a mix of CPUs with and without support for the 2121 * activity monitors extension. Therefore, unconditionally enable 2122 * the capability to allow any late CPU to use the feature. 2123 * 2124 * With this feature unconditionally enabled, the cpu_enable 2125 * function will be called for all CPUs that match the criteria, 2126 * including secondary and hotplugged, marking this feature as 2127 * present on that respective CPU. The enable function will also 2128 * print a detection message. 2129 */ 2130 2131 return true; 2132 } 2133 #else 2134 int get_cpu_with_amu_feat(void) 2135 { 2136 return nr_cpu_ids; 2137 } 2138 #endif 2139 2140 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2141 { 2142 return is_kernel_in_hyp_mode(); 2143 } 2144 2145 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2146 { 2147 /* 2148 * Copy register values that aren't redirected by hardware. 2149 * 2150 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2151 * this value to tpidr_el2 before we patch the code. Once we've done 2152 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2153 * do anything here. 2154 */ 2155 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2156 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2157 } 2158 2159 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2160 int scope) 2161 { 2162 if (kvm_get_mode() != KVM_MODE_NV) 2163 return false; 2164 2165 if (!has_cpuid_feature(cap, scope)) { 2166 pr_warn("unavailable: %s\n", cap->desc); 2167 return false; 2168 } 2169 2170 return true; 2171 } 2172 2173 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2174 int __unused) 2175 { 2176 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2177 } 2178 2179 #ifdef CONFIG_ARM64_PAN 2180 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2181 { 2182 /* 2183 * We modify PSTATE. This won't work from irq context as the PSTATE 2184 * is discarded once we return from the exception. 2185 */ 2186 WARN_ON_ONCE(in_interrupt()); 2187 2188 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2189 set_pstate_pan(1); 2190 } 2191 #endif /* CONFIG_ARM64_PAN */ 2192 2193 #ifdef CONFIG_ARM64_RAS_EXTN 2194 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2195 { 2196 /* Firmware may have left a deferred SError in this register. */ 2197 write_sysreg_s(0, SYS_DISR_EL1); 2198 } 2199 #endif /* CONFIG_ARM64_RAS_EXTN */ 2200 2201 #ifdef CONFIG_ARM64_PTR_AUTH 2202 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2203 { 2204 int boot_val, sec_val; 2205 2206 /* We don't expect to be called with SCOPE_SYSTEM */ 2207 WARN_ON(scope == SCOPE_SYSTEM); 2208 /* 2209 * The ptr-auth feature levels are not intercompatible with lower 2210 * levels. Hence we must match ptr-auth feature level of the secondary 2211 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2212 * from the sanitised register whereas direct register read is done for 2213 * the secondary CPUs. 2214 * The sanitised feature state is guaranteed to match that of the 2215 * boot CPU as a mismatched secondary CPU is parked before it gets 2216 * a chance to update the state, with the capability. 2217 */ 2218 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2219 entry->field_pos, entry->sign); 2220 if (scope & SCOPE_BOOT_CPU) 2221 return boot_val >= entry->min_field_value; 2222 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2223 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2224 entry->field_pos, entry->sign); 2225 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2226 } 2227 2228 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2229 int scope) 2230 { 2231 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2232 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2233 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2234 2235 return apa || apa3 || api; 2236 } 2237 2238 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2239 int __unused) 2240 { 2241 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2242 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2243 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2244 2245 return gpa || gpa3 || gpi; 2246 } 2247 #endif /* CONFIG_ARM64_PTR_AUTH */ 2248 2249 #ifdef CONFIG_ARM64_E0PD 2250 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2251 { 2252 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2253 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2254 } 2255 #endif /* CONFIG_ARM64_E0PD */ 2256 2257 #ifdef CONFIG_ARM64_PSEUDO_NMI 2258 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2259 int scope) 2260 { 2261 /* 2262 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2263 * feature, so will be detected earlier. 2264 */ 2265 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2266 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2267 return false; 2268 2269 return enable_pseudo_nmi; 2270 } 2271 2272 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2273 int scope) 2274 { 2275 /* 2276 * If we're not using priority masking then we won't be poking PMR_EL1, 2277 * and there's no need to relax synchronization of writes to it, and 2278 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2279 * that. 2280 * 2281 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2282 * feature, so will be detected earlier. 2283 */ 2284 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2285 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2286 return false; 2287 2288 /* 2289 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2290 * hint for interrupt distribution, a DSB is not necessary when 2291 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2292 * 2293 * Linux itself doesn't use 1:N distribution, so has no need to 2294 * set PMHE. The only reason to have it set is if EL3 requires it 2295 * (and we can't change it). 2296 */ 2297 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2298 } 2299 #endif 2300 2301 #ifdef CONFIG_ARM64_BTI 2302 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2303 { 2304 /* 2305 * Use of X16/X17 for tail-calls and trampolines that jump to 2306 * function entry points using BR is a requirement for 2307 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2308 * So, be strict and forbid other BRs using other registers to 2309 * jump onto a PACIxSP instruction: 2310 */ 2311 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2312 isb(); 2313 } 2314 #endif /* CONFIG_ARM64_BTI */ 2315 2316 #ifdef CONFIG_ARM64_MTE 2317 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2318 { 2319 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2320 2321 mte_cpu_setup(); 2322 2323 /* 2324 * Clear the tags in the zero page. This needs to be done via the 2325 * linear map which has the Tagged attribute. 2326 */ 2327 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2328 mte_clear_page_tags(lm_alias(empty_zero_page)); 2329 set_page_mte_tagged(ZERO_PAGE(0)); 2330 } 2331 2332 kasan_init_hw_tags_cpu(); 2333 } 2334 #endif /* CONFIG_ARM64_MTE */ 2335 2336 static void user_feature_fixup(void) 2337 { 2338 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2339 struct arm64_ftr_reg *regp; 2340 2341 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2342 if (regp) 2343 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2344 } 2345 2346 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2347 struct arm64_ftr_reg *regp; 2348 2349 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2350 if (regp) 2351 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2352 } 2353 } 2354 2355 static void elf_hwcap_fixup(void) 2356 { 2357 #ifdef CONFIG_COMPAT 2358 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2359 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2360 #endif /* CONFIG_COMPAT */ 2361 } 2362 2363 #ifdef CONFIG_KVM 2364 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2365 { 2366 return kvm_get_mode() == KVM_MODE_PROTECTED; 2367 } 2368 #endif /* CONFIG_KVM */ 2369 2370 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2371 { 2372 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2373 } 2374 2375 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2376 { 2377 set_pstate_dit(1); 2378 } 2379 2380 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2381 { 2382 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2383 } 2384 2385 #ifdef CONFIG_ARM64_POE 2386 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2387 { 2388 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2389 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2390 } 2391 #endif 2392 2393 #ifdef CONFIG_ARM64_GCS 2394 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2395 { 2396 /* GCSPR_EL0 is always readable */ 2397 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2398 } 2399 #endif 2400 2401 /* Internal helper functions to match cpu capability type */ 2402 static bool 2403 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2404 { 2405 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2406 } 2407 2408 static bool 2409 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2410 { 2411 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2412 } 2413 2414 static bool 2415 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2416 { 2417 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2418 } 2419 2420 static bool 2421 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2422 { 2423 if (!has_cpuid_feature(entry, scope)) 2424 return false; 2425 2426 /* Check firmware actually enabled MPAM on this cpu. */ 2427 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2428 } 2429 2430 static void 2431 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2432 { 2433 /* 2434 * Access by the kernel (at EL1) should use the reserved PARTID 2435 * which is configured unrestricted. This avoids priority-inversion 2436 * where latency sensitive tasks have to wait for a task that has 2437 * been throttled to release the lock. 2438 */ 2439 write_sysreg_s(0, SYS_MPAM1_EL1); 2440 } 2441 2442 static bool 2443 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2444 { 2445 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2446 2447 return idr & MPAMIDR_EL1_HAS_HCR; 2448 } 2449 2450 static const struct arm64_cpu_capabilities arm64_features[] = { 2451 { 2452 .capability = ARM64_ALWAYS_BOOT, 2453 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2454 .matches = has_always, 2455 }, 2456 { 2457 .capability = ARM64_ALWAYS_SYSTEM, 2458 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2459 .matches = has_always, 2460 }, 2461 { 2462 .desc = "GIC system register CPU interface", 2463 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2464 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2465 .matches = has_useable_gicv3_cpuif, 2466 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2467 }, 2468 { 2469 .desc = "Enhanced Counter Virtualization", 2470 .capability = ARM64_HAS_ECV, 2471 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2472 .matches = has_cpuid_feature, 2473 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2474 }, 2475 { 2476 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2477 .capability = ARM64_HAS_ECV_CNTPOFF, 2478 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2479 .matches = has_cpuid_feature, 2480 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2481 }, 2482 #ifdef CONFIG_ARM64_PAN 2483 { 2484 .desc = "Privileged Access Never", 2485 .capability = ARM64_HAS_PAN, 2486 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2487 .matches = has_cpuid_feature, 2488 .cpu_enable = cpu_enable_pan, 2489 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2490 }, 2491 #endif /* CONFIG_ARM64_PAN */ 2492 #ifdef CONFIG_ARM64_EPAN 2493 { 2494 .desc = "Enhanced Privileged Access Never", 2495 .capability = ARM64_HAS_EPAN, 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .matches = has_cpuid_feature, 2498 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2499 }, 2500 #endif /* CONFIG_ARM64_EPAN */ 2501 #ifdef CONFIG_ARM64_LSE_ATOMICS 2502 { 2503 .desc = "LSE atomic instructions", 2504 .capability = ARM64_HAS_LSE_ATOMICS, 2505 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2506 .matches = has_cpuid_feature, 2507 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2508 }, 2509 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2510 { 2511 .desc = "Virtualization Host Extensions", 2512 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2513 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2514 .matches = runs_at_el2, 2515 .cpu_enable = cpu_copy_el2regs, 2516 }, 2517 { 2518 .desc = "Nested Virtualization Support", 2519 .capability = ARM64_HAS_NESTED_VIRT, 2520 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2521 .matches = has_nested_virt_support, 2522 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2523 }, 2524 { 2525 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2526 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2527 .matches = has_32bit_el0, 2528 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2529 }, 2530 #ifdef CONFIG_KVM 2531 { 2532 .desc = "32-bit EL1 Support", 2533 .capability = ARM64_HAS_32BIT_EL1, 2534 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2535 .matches = has_cpuid_feature, 2536 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2537 }, 2538 { 2539 .desc = "Protected KVM", 2540 .capability = ARM64_KVM_PROTECTED_MODE, 2541 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2542 .matches = is_kvm_protected_mode, 2543 }, 2544 { 2545 .desc = "HCRX_EL2 register", 2546 .capability = ARM64_HAS_HCX, 2547 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2548 .matches = has_cpuid_feature, 2549 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2550 }, 2551 #endif 2552 { 2553 .desc = "Kernel page table isolation (KPTI)", 2554 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2555 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2556 .cpu_enable = cpu_enable_kpti, 2557 .matches = unmap_kernel_at_el0, 2558 /* 2559 * The ID feature fields below are used to indicate that 2560 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2561 * more details. 2562 */ 2563 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2564 }, 2565 { 2566 .capability = ARM64_HAS_FPSIMD, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_cpuid_feature, 2569 .cpu_enable = cpu_enable_fpsimd, 2570 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2571 }, 2572 #ifdef CONFIG_ARM64_PMEM 2573 { 2574 .desc = "Data cache clean to Point of Persistence", 2575 .capability = ARM64_HAS_DCPOP, 2576 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2577 .matches = has_cpuid_feature, 2578 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2579 }, 2580 { 2581 .desc = "Data cache clean to Point of Deep Persistence", 2582 .capability = ARM64_HAS_DCPODP, 2583 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2584 .matches = has_cpuid_feature, 2585 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2586 }, 2587 #endif 2588 #ifdef CONFIG_ARM64_SVE 2589 { 2590 .desc = "Scalable Vector Extension", 2591 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2592 .capability = ARM64_SVE, 2593 .cpu_enable = cpu_enable_sve, 2594 .matches = has_cpuid_feature, 2595 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2596 }, 2597 #endif /* CONFIG_ARM64_SVE */ 2598 #ifdef CONFIG_ARM64_RAS_EXTN 2599 { 2600 .desc = "RAS Extension Support", 2601 .capability = ARM64_HAS_RAS_EXTN, 2602 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2603 .matches = has_cpuid_feature, 2604 .cpu_enable = cpu_clear_disr, 2605 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2606 }, 2607 #endif /* CONFIG_ARM64_RAS_EXTN */ 2608 #ifdef CONFIG_ARM64_AMU_EXTN 2609 { 2610 .desc = "Activity Monitors Unit (AMU)", 2611 .capability = ARM64_HAS_AMU_EXTN, 2612 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2613 .matches = has_amu, 2614 .cpu_enable = cpu_amu_enable, 2615 .cpus = &amu_cpus, 2616 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2617 }, 2618 #endif /* CONFIG_ARM64_AMU_EXTN */ 2619 { 2620 .desc = "Data cache clean to the PoU not required for I/D coherence", 2621 .capability = ARM64_HAS_CACHE_IDC, 2622 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2623 .matches = has_cache_idc, 2624 .cpu_enable = cpu_emulate_effective_ctr, 2625 }, 2626 { 2627 .desc = "Instruction cache invalidation not required for I/D coherence", 2628 .capability = ARM64_HAS_CACHE_DIC, 2629 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2630 .matches = has_cache_dic, 2631 }, 2632 { 2633 .desc = "Stage-2 Force Write-Back", 2634 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2635 .capability = ARM64_HAS_STAGE2_FWB, 2636 .matches = has_cpuid_feature, 2637 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2638 }, 2639 { 2640 .desc = "ARMv8.4 Translation Table Level", 2641 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2642 .capability = ARM64_HAS_ARMv8_4_TTL, 2643 .matches = has_cpuid_feature, 2644 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2645 }, 2646 { 2647 .desc = "TLB range maintenance instructions", 2648 .capability = ARM64_HAS_TLB_RANGE, 2649 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2650 .matches = has_cpuid_feature, 2651 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2652 }, 2653 #ifdef CONFIG_ARM64_HW_AFDBM 2654 { 2655 .desc = "Hardware dirty bit management", 2656 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2657 .capability = ARM64_HW_DBM, 2658 .matches = has_hw_dbm, 2659 .cpu_enable = cpu_enable_hw_dbm, 2660 .cpus = &dbm_cpus, 2661 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2662 }, 2663 #endif 2664 #ifdef CONFIG_ARM64_HAFT 2665 { 2666 .desc = "Hardware managed Access Flag for Table Descriptors", 2667 /* 2668 * Contrary to the page/block access flag, the table access flag 2669 * cannot be emulated in software (no access fault will occur). 2670 * Therefore this should be used only if it's supported system 2671 * wide. 2672 */ 2673 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2674 .capability = ARM64_HAFT, 2675 .matches = has_cpuid_feature, 2676 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2677 }, 2678 #endif 2679 { 2680 .desc = "CRC32 instructions", 2681 .capability = ARM64_HAS_CRC32, 2682 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2683 .matches = has_cpuid_feature, 2684 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2685 }, 2686 { 2687 .desc = "Speculative Store Bypassing Safe (SSBS)", 2688 .capability = ARM64_SSBS, 2689 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2690 .matches = has_cpuid_feature, 2691 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2692 }, 2693 #ifdef CONFIG_ARM64_CNP 2694 { 2695 .desc = "Common not Private translations", 2696 .capability = ARM64_HAS_CNP, 2697 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2698 .matches = has_useable_cnp, 2699 .cpu_enable = cpu_enable_cnp, 2700 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2701 }, 2702 #endif 2703 { 2704 .desc = "Speculation barrier (SB)", 2705 .capability = ARM64_HAS_SB, 2706 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2707 .matches = has_cpuid_feature, 2708 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2709 }, 2710 #ifdef CONFIG_ARM64_PTR_AUTH 2711 { 2712 .desc = "Address authentication (architected QARMA5 algorithm)", 2713 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2714 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2715 .matches = has_address_auth_cpucap, 2716 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2717 }, 2718 { 2719 .desc = "Address authentication (architected QARMA3 algorithm)", 2720 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2721 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2722 .matches = has_address_auth_cpucap, 2723 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2724 }, 2725 { 2726 .desc = "Address authentication (IMP DEF algorithm)", 2727 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2728 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2729 .matches = has_address_auth_cpucap, 2730 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2731 }, 2732 { 2733 .capability = ARM64_HAS_ADDRESS_AUTH, 2734 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2735 .matches = has_address_auth_metacap, 2736 }, 2737 { 2738 .desc = "Generic authentication (architected QARMA5 algorithm)", 2739 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2740 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2741 .matches = has_cpuid_feature, 2742 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2743 }, 2744 { 2745 .desc = "Generic authentication (architected QARMA3 algorithm)", 2746 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2747 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2748 .matches = has_cpuid_feature, 2749 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2750 }, 2751 { 2752 .desc = "Generic authentication (IMP DEF algorithm)", 2753 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2754 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2755 .matches = has_cpuid_feature, 2756 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2757 }, 2758 { 2759 .capability = ARM64_HAS_GENERIC_AUTH, 2760 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2761 .matches = has_generic_auth, 2762 }, 2763 #endif /* CONFIG_ARM64_PTR_AUTH */ 2764 #ifdef CONFIG_ARM64_PSEUDO_NMI 2765 { 2766 /* 2767 * Depends on having GICv3 2768 */ 2769 .desc = "IRQ priority masking", 2770 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2771 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2772 .matches = can_use_gic_priorities, 2773 }, 2774 { 2775 /* 2776 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2777 */ 2778 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2779 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2780 .matches = has_gic_prio_relaxed_sync, 2781 }, 2782 #endif 2783 #ifdef CONFIG_ARM64_E0PD 2784 { 2785 .desc = "E0PD", 2786 .capability = ARM64_HAS_E0PD, 2787 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2788 .cpu_enable = cpu_enable_e0pd, 2789 .matches = has_cpuid_feature, 2790 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2791 }, 2792 #endif 2793 { 2794 .desc = "Random Number Generator", 2795 .capability = ARM64_HAS_RNG, 2796 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2797 .matches = has_cpuid_feature, 2798 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2799 }, 2800 #ifdef CONFIG_ARM64_BTI 2801 { 2802 .desc = "Branch Target Identification", 2803 .capability = ARM64_BTI, 2804 #ifdef CONFIG_ARM64_BTI_KERNEL 2805 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2806 #else 2807 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2808 #endif 2809 .matches = has_cpuid_feature, 2810 .cpu_enable = bti_enable, 2811 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2812 }, 2813 #endif 2814 #ifdef CONFIG_ARM64_MTE 2815 { 2816 .desc = "Memory Tagging Extension", 2817 .capability = ARM64_MTE, 2818 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2819 .matches = has_cpuid_feature, 2820 .cpu_enable = cpu_enable_mte, 2821 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2822 }, 2823 { 2824 .desc = "Asymmetric MTE Tag Check Fault", 2825 .capability = ARM64_MTE_ASYMM, 2826 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2827 .matches = has_cpuid_feature, 2828 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2829 }, 2830 #endif /* CONFIG_ARM64_MTE */ 2831 { 2832 .desc = "RCpc load-acquire (LDAPR)", 2833 .capability = ARM64_HAS_LDAPR, 2834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2835 .matches = has_cpuid_feature, 2836 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2837 }, 2838 { 2839 .desc = "Fine Grained Traps", 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .capability = ARM64_HAS_FGT, 2842 .matches = has_cpuid_feature, 2843 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2844 }, 2845 #ifdef CONFIG_ARM64_SME 2846 { 2847 .desc = "Scalable Matrix Extension", 2848 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2849 .capability = ARM64_SME, 2850 .matches = has_cpuid_feature, 2851 .cpu_enable = cpu_enable_sme, 2852 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2853 }, 2854 /* FA64 should be sorted after the base SME capability */ 2855 { 2856 .desc = "FA64", 2857 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2858 .capability = ARM64_SME_FA64, 2859 .matches = has_cpuid_feature, 2860 .cpu_enable = cpu_enable_fa64, 2861 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2862 }, 2863 { 2864 .desc = "SME2", 2865 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2866 .capability = ARM64_SME2, 2867 .matches = has_cpuid_feature, 2868 .cpu_enable = cpu_enable_sme2, 2869 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2870 }, 2871 #endif /* CONFIG_ARM64_SME */ 2872 { 2873 .desc = "WFx with timeout", 2874 .capability = ARM64_HAS_WFXT, 2875 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2876 .matches = has_cpuid_feature, 2877 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2878 }, 2879 { 2880 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2881 .capability = ARM64_HAS_TIDCP1, 2882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2883 .matches = has_cpuid_feature, 2884 .cpu_enable = cpu_trap_el0_impdef, 2885 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2886 }, 2887 { 2888 .desc = "Data independent timing control (DIT)", 2889 .capability = ARM64_HAS_DIT, 2890 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2891 .matches = has_cpuid_feature, 2892 .cpu_enable = cpu_enable_dit, 2893 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2894 }, 2895 { 2896 .desc = "Memory Copy and Memory Set instructions", 2897 .capability = ARM64_HAS_MOPS, 2898 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2899 .matches = has_cpuid_feature, 2900 .cpu_enable = cpu_enable_mops, 2901 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2902 }, 2903 { 2904 .capability = ARM64_HAS_TCR2, 2905 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2906 .matches = has_cpuid_feature, 2907 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2908 }, 2909 { 2910 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2911 .capability = ARM64_HAS_S1PIE, 2912 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2913 .matches = has_cpuid_feature, 2914 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2915 }, 2916 { 2917 .desc = "VHE for hypervisor only", 2918 .capability = ARM64_KVM_HVHE, 2919 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2920 .matches = hvhe_possible, 2921 }, 2922 { 2923 .desc = "Enhanced Virtualization Traps", 2924 .capability = ARM64_HAS_EVT, 2925 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2926 .matches = has_cpuid_feature, 2927 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2928 }, 2929 { 2930 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2931 .capability = ARM64_HAS_LPA2, 2932 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2933 .matches = has_lpa2, 2934 }, 2935 { 2936 .desc = "FPMR", 2937 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2938 .capability = ARM64_HAS_FPMR, 2939 .matches = has_cpuid_feature, 2940 .cpu_enable = cpu_enable_fpmr, 2941 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2942 }, 2943 #ifdef CONFIG_ARM64_VA_BITS_52 2944 { 2945 .capability = ARM64_HAS_VA52, 2946 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2947 .matches = has_cpuid_feature, 2948 #ifdef CONFIG_ARM64_64K_PAGES 2949 .desc = "52-bit Virtual Addressing (LVA)", 2950 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2951 #else 2952 .desc = "52-bit Virtual Addressing (LPA2)", 2953 #ifdef CONFIG_ARM64_4K_PAGES 2954 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2955 #else 2956 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2957 #endif 2958 #endif 2959 }, 2960 #endif 2961 { 2962 .desc = "Memory Partitioning And Monitoring", 2963 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2964 .capability = ARM64_MPAM, 2965 .matches = test_has_mpam, 2966 .cpu_enable = cpu_enable_mpam, 2967 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 2968 }, 2969 { 2970 .desc = "Memory Partitioning And Monitoring Virtualisation", 2971 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2972 .capability = ARM64_MPAM_HCR, 2973 .matches = test_has_mpam_hcr, 2974 }, 2975 { 2976 .desc = "NV1", 2977 .capability = ARM64_HAS_HCR_NV1, 2978 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2979 .matches = has_nv1, 2980 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2981 }, 2982 #ifdef CONFIG_ARM64_POE 2983 { 2984 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2985 .capability = ARM64_HAS_S1POE, 2986 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2987 .matches = has_cpuid_feature, 2988 .cpu_enable = cpu_enable_poe, 2989 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2990 }, 2991 #endif 2992 #ifdef CONFIG_ARM64_GCS 2993 { 2994 .desc = "Guarded Control Stack (GCS)", 2995 .capability = ARM64_HAS_GCS, 2996 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2997 .cpu_enable = cpu_enable_gcs, 2998 .matches = has_cpuid_feature, 2999 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3000 }, 3001 #endif 3002 {}, 3003 }; 3004 3005 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3006 .matches = has_user_cpuid_feature, \ 3007 ARM64_CPUID_FIELDS(reg, field, min_value) 3008 3009 #define __HWCAP_CAP(name, cap_type, cap) \ 3010 .desc = name, \ 3011 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3012 .hwcap_type = cap_type, \ 3013 .hwcap = cap, \ 3014 3015 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3016 { \ 3017 __HWCAP_CAP(#cap, cap_type, cap) \ 3018 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3019 } 3020 3021 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3022 { \ 3023 __HWCAP_CAP(#cap, cap_type, cap) \ 3024 .matches = cpucap_multi_entry_cap_matches, \ 3025 .match_list = list, \ 3026 } 3027 3028 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3029 { \ 3030 __HWCAP_CAP(#cap, cap_type, cap) \ 3031 .matches = match, \ 3032 } 3033 3034 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3035 { \ 3036 __HWCAP_CAP(#cap, cap_type, cap) \ 3037 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3038 .matches = match, \ 3039 } 3040 3041 #ifdef CONFIG_ARM64_PTR_AUTH 3042 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3043 { 3044 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3045 }, 3046 { 3047 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3048 }, 3049 { 3050 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3051 }, 3052 {}, 3053 }; 3054 3055 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3056 { 3057 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3058 }, 3059 { 3060 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3061 }, 3062 { 3063 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3064 }, 3065 {}, 3066 }; 3067 #endif 3068 3069 #ifdef CONFIG_ARM64_SVE 3070 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3071 { 3072 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3073 } 3074 #endif 3075 3076 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3077 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3078 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3079 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3080 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3081 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3082 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3083 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3084 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3085 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3086 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3087 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3088 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3089 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3090 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3091 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3092 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3093 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3094 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3095 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3096 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3097 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3098 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3099 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3100 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3101 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3102 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3103 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3104 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3105 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3106 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3107 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3108 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3109 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3110 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3111 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3112 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3113 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3114 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3115 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3116 #ifdef CONFIG_ARM64_SVE 3117 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3118 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3119 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3120 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3121 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3122 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3123 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3124 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3125 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3126 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3127 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3128 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3129 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3130 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3131 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3132 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3133 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3134 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3135 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3136 #endif 3137 #ifdef CONFIG_ARM64_GCS 3138 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3139 #endif 3140 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3141 #ifdef CONFIG_ARM64_BTI 3142 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3143 #endif 3144 #ifdef CONFIG_ARM64_PTR_AUTH 3145 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3146 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3147 #endif 3148 #ifdef CONFIG_ARM64_MTE 3149 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3150 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3151 #endif /* CONFIG_ARM64_MTE */ 3152 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3153 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3154 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3155 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3156 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3157 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3158 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3159 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3160 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3161 #ifdef CONFIG_ARM64_SME 3162 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3163 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3164 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3165 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3166 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3167 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3168 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3169 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3170 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3171 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3172 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3173 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3174 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3175 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3176 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3177 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3178 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3179 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3180 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3181 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3182 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3183 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM8), 3184 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM4), 3185 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3186 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3187 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3188 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3189 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3190 #endif /* CONFIG_ARM64_SME */ 3191 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3192 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3193 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3194 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3195 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3196 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3197 #ifdef CONFIG_ARM64_POE 3198 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3199 #endif 3200 {}, 3201 }; 3202 3203 #ifdef CONFIG_COMPAT 3204 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3205 { 3206 /* 3207 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3208 * in line with that of arm32 as in vfp_init(). We make sure that the 3209 * check is future proof, by making sure value is non-zero. 3210 */ 3211 u32 mvfr1; 3212 3213 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3214 if (scope == SCOPE_SYSTEM) 3215 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3216 else 3217 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3218 3219 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3220 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3221 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3222 } 3223 #endif 3224 3225 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3226 #ifdef CONFIG_COMPAT 3227 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3228 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3229 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3230 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3231 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3232 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3233 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3234 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3235 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3236 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3237 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3238 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3239 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3240 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3241 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3242 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3243 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3244 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3245 #endif 3246 {}, 3247 }; 3248 3249 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3250 { 3251 switch (cap->hwcap_type) { 3252 case CAP_HWCAP: 3253 cpu_set_feature(cap->hwcap); 3254 break; 3255 #ifdef CONFIG_COMPAT 3256 case CAP_COMPAT_HWCAP: 3257 compat_elf_hwcap |= (u32)cap->hwcap; 3258 break; 3259 case CAP_COMPAT_HWCAP2: 3260 compat_elf_hwcap2 |= (u32)cap->hwcap; 3261 break; 3262 #endif 3263 default: 3264 WARN_ON(1); 3265 break; 3266 } 3267 } 3268 3269 /* Check if we have a particular HWCAP enabled */ 3270 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3271 { 3272 bool rc; 3273 3274 switch (cap->hwcap_type) { 3275 case CAP_HWCAP: 3276 rc = cpu_have_feature(cap->hwcap); 3277 break; 3278 #ifdef CONFIG_COMPAT 3279 case CAP_COMPAT_HWCAP: 3280 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3281 break; 3282 case CAP_COMPAT_HWCAP2: 3283 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3284 break; 3285 #endif 3286 default: 3287 WARN_ON(1); 3288 rc = false; 3289 } 3290 3291 return rc; 3292 } 3293 3294 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3295 { 3296 /* We support emulation of accesses to CPU ID feature registers */ 3297 cpu_set_named_feature(CPUID); 3298 for (; hwcaps->matches; hwcaps++) 3299 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3300 cap_set_elf_hwcap(hwcaps); 3301 } 3302 3303 static void update_cpu_capabilities(u16 scope_mask) 3304 { 3305 int i; 3306 const struct arm64_cpu_capabilities *caps; 3307 3308 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3309 for (i = 0; i < ARM64_NCAPS; i++) { 3310 caps = cpucap_ptrs[i]; 3311 if (!caps || !(caps->type & scope_mask) || 3312 cpus_have_cap(caps->capability) || 3313 !caps->matches(caps, cpucap_default_scope(caps))) 3314 continue; 3315 3316 if (caps->desc && !caps->cpus) 3317 pr_info("detected: %s\n", caps->desc); 3318 3319 __set_bit(caps->capability, system_cpucaps); 3320 3321 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3322 set_bit(caps->capability, boot_cpucaps); 3323 } 3324 } 3325 3326 /* 3327 * Enable all the available capabilities on this CPU. The capabilities 3328 * with BOOT_CPU scope are handled separately and hence skipped here. 3329 */ 3330 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3331 { 3332 int i; 3333 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3334 3335 for_each_available_cap(i) { 3336 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3337 3338 if (WARN_ON(!cap)) 3339 continue; 3340 3341 if (!(cap->type & non_boot_scope)) 3342 continue; 3343 3344 if (cap->cpu_enable) 3345 cap->cpu_enable(cap); 3346 } 3347 return 0; 3348 } 3349 3350 /* 3351 * Run through the enabled capabilities and enable() it on all active 3352 * CPUs 3353 */ 3354 static void __init enable_cpu_capabilities(u16 scope_mask) 3355 { 3356 int i; 3357 const struct arm64_cpu_capabilities *caps; 3358 bool boot_scope; 3359 3360 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3361 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3362 3363 for (i = 0; i < ARM64_NCAPS; i++) { 3364 caps = cpucap_ptrs[i]; 3365 if (!caps || !(caps->type & scope_mask) || 3366 !cpus_have_cap(caps->capability)) 3367 continue; 3368 3369 if (boot_scope && caps->cpu_enable) 3370 /* 3371 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3372 * before any secondary CPU boots. Thus, each secondary 3373 * will enable the capability as appropriate via 3374 * check_local_cpu_capabilities(). The only exception is 3375 * the boot CPU, for which the capability must be 3376 * enabled here. This approach avoids costly 3377 * stop_machine() calls for this case. 3378 */ 3379 caps->cpu_enable(caps); 3380 } 3381 3382 /* 3383 * For all non-boot scope capabilities, use stop_machine() 3384 * as it schedules the work allowing us to modify PSTATE, 3385 * instead of on_each_cpu() which uses an IPI, giving us a 3386 * PSTATE that disappears when we return. 3387 */ 3388 if (!boot_scope) 3389 stop_machine(cpu_enable_non_boot_scope_capabilities, 3390 NULL, cpu_online_mask); 3391 } 3392 3393 /* 3394 * Run through the list of capabilities to check for conflicts. 3395 * If the system has already detected a capability, take necessary 3396 * action on this CPU. 3397 */ 3398 static void verify_local_cpu_caps(u16 scope_mask) 3399 { 3400 int i; 3401 bool cpu_has_cap, system_has_cap; 3402 const struct arm64_cpu_capabilities *caps; 3403 3404 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3405 3406 for (i = 0; i < ARM64_NCAPS; i++) { 3407 caps = cpucap_ptrs[i]; 3408 if (!caps || !(caps->type & scope_mask)) 3409 continue; 3410 3411 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3412 system_has_cap = cpus_have_cap(caps->capability); 3413 3414 if (system_has_cap) { 3415 /* 3416 * Check if the new CPU misses an advertised feature, 3417 * which is not safe to miss. 3418 */ 3419 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3420 break; 3421 /* 3422 * We have to issue cpu_enable() irrespective of 3423 * whether the CPU has it or not, as it is enabeld 3424 * system wide. It is upto the call back to take 3425 * appropriate action on this CPU. 3426 */ 3427 if (caps->cpu_enable) 3428 caps->cpu_enable(caps); 3429 } else { 3430 /* 3431 * Check if the CPU has this capability if it isn't 3432 * safe to have when the system doesn't. 3433 */ 3434 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3435 break; 3436 } 3437 } 3438 3439 if (i < ARM64_NCAPS) { 3440 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3441 smp_processor_id(), caps->capability, 3442 caps->desc, system_has_cap, cpu_has_cap); 3443 3444 if (cpucap_panic_on_conflict(caps)) 3445 cpu_panic_kernel(); 3446 else 3447 cpu_die_early(); 3448 } 3449 } 3450 3451 /* 3452 * Check for CPU features that are used in early boot 3453 * based on the Boot CPU value. 3454 */ 3455 static void check_early_cpu_features(void) 3456 { 3457 verify_cpu_asid_bits(); 3458 3459 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3460 } 3461 3462 static void 3463 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3464 { 3465 3466 for (; caps->matches; caps++) 3467 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3468 pr_crit("CPU%d: missing HWCAP: %s\n", 3469 smp_processor_id(), caps->desc); 3470 cpu_die_early(); 3471 } 3472 } 3473 3474 static void verify_local_elf_hwcaps(void) 3475 { 3476 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3477 3478 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3479 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3480 } 3481 3482 static void verify_sve_features(void) 3483 { 3484 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3485 3486 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3487 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3488 smp_processor_id()); 3489 cpu_die_early(); 3490 } 3491 3492 cpacr_restore(cpacr); 3493 } 3494 3495 static void verify_sme_features(void) 3496 { 3497 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3498 3499 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3500 pr_crit("CPU%d: SME: vector length support mismatch\n", 3501 smp_processor_id()); 3502 cpu_die_early(); 3503 } 3504 3505 cpacr_restore(cpacr); 3506 } 3507 3508 static void verify_hyp_capabilities(void) 3509 { 3510 u64 safe_mmfr1, mmfr0, mmfr1; 3511 int parange, ipa_max; 3512 unsigned int safe_vmid_bits, vmid_bits; 3513 3514 if (!IS_ENABLED(CONFIG_KVM)) 3515 return; 3516 3517 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3518 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3519 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3520 3521 /* Verify VMID bits */ 3522 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3523 vmid_bits = get_vmid_bits(mmfr1); 3524 if (vmid_bits < safe_vmid_bits) { 3525 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3526 cpu_die_early(); 3527 } 3528 3529 /* Verify IPA range */ 3530 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3531 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3532 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3533 if (ipa_max < get_kvm_ipa_limit()) { 3534 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3535 cpu_die_early(); 3536 } 3537 } 3538 3539 static void verify_mpam_capabilities(void) 3540 { 3541 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3542 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3543 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3544 3545 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3546 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3547 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3548 cpu_die_early(); 3549 } 3550 3551 cpu_idr = read_cpuid(MPAMIDR_EL1); 3552 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3553 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3554 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3555 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3556 cpu_die_early(); 3557 } 3558 3559 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3560 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3561 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3562 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3563 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3564 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3565 cpu_die_early(); 3566 } 3567 } 3568 3569 /* 3570 * Run through the enabled system capabilities and enable() it on this CPU. 3571 * The capabilities were decided based on the available CPUs at the boot time. 3572 * Any new CPU should match the system wide status of the capability. If the 3573 * new CPU doesn't have a capability which the system now has enabled, we 3574 * cannot do anything to fix it up and could cause unexpected failures. So 3575 * we park the CPU. 3576 */ 3577 static void verify_local_cpu_capabilities(void) 3578 { 3579 /* 3580 * The capabilities with SCOPE_BOOT_CPU are checked from 3581 * check_early_cpu_features(), as they need to be verified 3582 * on all secondary CPUs. 3583 */ 3584 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3585 verify_local_elf_hwcaps(); 3586 3587 if (system_supports_sve()) 3588 verify_sve_features(); 3589 3590 if (system_supports_sme()) 3591 verify_sme_features(); 3592 3593 if (is_hyp_mode_available()) 3594 verify_hyp_capabilities(); 3595 3596 if (system_supports_mpam()) 3597 verify_mpam_capabilities(); 3598 } 3599 3600 void check_local_cpu_capabilities(void) 3601 { 3602 /* 3603 * All secondary CPUs should conform to the early CPU features 3604 * in use by the kernel based on boot CPU. 3605 */ 3606 check_early_cpu_features(); 3607 3608 /* 3609 * If we haven't finalised the system capabilities, this CPU gets 3610 * a chance to update the errata work arounds and local features. 3611 * Otherwise, this CPU should verify that it has all the system 3612 * advertised capabilities. 3613 */ 3614 if (!system_capabilities_finalized()) 3615 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3616 else 3617 verify_local_cpu_capabilities(); 3618 } 3619 3620 bool this_cpu_has_cap(unsigned int n) 3621 { 3622 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3623 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3624 3625 if (cap) 3626 return cap->matches(cap, SCOPE_LOCAL_CPU); 3627 } 3628 3629 return false; 3630 } 3631 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3632 3633 /* 3634 * This helper function is used in a narrow window when, 3635 * - The system wide safe registers are set with all the SMP CPUs and, 3636 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3637 */ 3638 static bool __maybe_unused __system_matches_cap(unsigned int n) 3639 { 3640 if (n < ARM64_NCAPS) { 3641 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3642 3643 if (cap) 3644 return cap->matches(cap, SCOPE_SYSTEM); 3645 } 3646 return false; 3647 } 3648 3649 void cpu_set_feature(unsigned int num) 3650 { 3651 set_bit(num, elf_hwcap); 3652 } 3653 3654 bool cpu_have_feature(unsigned int num) 3655 { 3656 return test_bit(num, elf_hwcap); 3657 } 3658 EXPORT_SYMBOL_GPL(cpu_have_feature); 3659 3660 unsigned long cpu_get_elf_hwcap(void) 3661 { 3662 /* 3663 * We currently only populate the first 32 bits of AT_HWCAP. Please 3664 * note that for userspace compatibility we guarantee that bits 62 3665 * and 63 will always be returned as 0. 3666 */ 3667 return elf_hwcap[0]; 3668 } 3669 3670 unsigned long cpu_get_elf_hwcap2(void) 3671 { 3672 return elf_hwcap[1]; 3673 } 3674 3675 unsigned long cpu_get_elf_hwcap3(void) 3676 { 3677 return elf_hwcap[2]; 3678 } 3679 3680 static void __init setup_boot_cpu_capabilities(void) 3681 { 3682 /* 3683 * The boot CPU's feature register values have been recorded. Detect 3684 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3685 * patch alternatives for the available boot cpucaps. 3686 */ 3687 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3688 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3689 apply_boot_alternatives(); 3690 } 3691 3692 void __init setup_boot_cpu_features(void) 3693 { 3694 /* 3695 * Initialize the indirect array of CPU capabilities pointers before we 3696 * handle the boot CPU. 3697 */ 3698 init_cpucap_indirect_list(); 3699 3700 /* 3701 * Detect broken pseudo-NMI. Must be called _before_ the call to 3702 * setup_boot_cpu_capabilities() since it interacts with 3703 * can_use_gic_priorities(). 3704 */ 3705 detect_system_supports_pseudo_nmi(); 3706 3707 setup_boot_cpu_capabilities(); 3708 } 3709 3710 static void __init setup_system_capabilities(void) 3711 { 3712 /* 3713 * The system-wide safe feature register values have been finalized. 3714 * Detect, enable, and patch alternatives for the available system 3715 * cpucaps. 3716 */ 3717 update_cpu_capabilities(SCOPE_SYSTEM); 3718 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3719 apply_alternatives_all(); 3720 3721 /* 3722 * Log any cpucaps with a cpumask as these aren't logged by 3723 * update_cpu_capabilities(). 3724 */ 3725 for (int i = 0; i < ARM64_NCAPS; i++) { 3726 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3727 3728 if (caps && caps->cpus && caps->desc && 3729 cpumask_any(caps->cpus) < nr_cpu_ids) 3730 pr_info("detected: %s on CPU%*pbl\n", 3731 caps->desc, cpumask_pr_args(caps->cpus)); 3732 } 3733 3734 /* 3735 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3736 */ 3737 if (system_uses_ttbr0_pan()) 3738 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3739 } 3740 3741 void __init setup_system_features(void) 3742 { 3743 setup_system_capabilities(); 3744 3745 kpti_install_ng_mappings(); 3746 3747 sve_setup(); 3748 sme_setup(); 3749 3750 /* 3751 * Check for sane CTR_EL0.CWG value. 3752 */ 3753 if (!cache_type_cwg()) 3754 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3755 ARCH_DMA_MINALIGN); 3756 } 3757 3758 void __init setup_user_features(void) 3759 { 3760 user_feature_fixup(); 3761 3762 setup_elf_hwcaps(arm64_elf_hwcaps); 3763 3764 if (system_supports_32bit_el0()) { 3765 setup_elf_hwcaps(compat_elf_hwcaps); 3766 elf_hwcap_fixup(); 3767 } 3768 3769 minsigstksz_setup(); 3770 } 3771 3772 static int enable_mismatched_32bit_el0(unsigned int cpu) 3773 { 3774 /* 3775 * The first 32-bit-capable CPU we detected and so can no longer 3776 * be offlined by userspace. -1 indicates we haven't yet onlined 3777 * a 32-bit-capable CPU. 3778 */ 3779 static int lucky_winner = -1; 3780 3781 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3782 bool cpu_32bit = false; 3783 3784 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3785 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3786 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3787 else 3788 cpu_32bit = true; 3789 } 3790 3791 if (cpu_32bit) { 3792 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3793 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3794 } 3795 3796 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3797 return 0; 3798 3799 if (lucky_winner >= 0) 3800 return 0; 3801 3802 /* 3803 * We've detected a mismatch. We need to keep one of our CPUs with 3804 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3805 * every CPU in the system for a 32-bit task. 3806 */ 3807 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3808 cpu_active_mask); 3809 get_cpu_device(lucky_winner)->offline_disabled = true; 3810 setup_elf_hwcaps(compat_elf_hwcaps); 3811 elf_hwcap_fixup(); 3812 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3813 cpu, lucky_winner); 3814 return 0; 3815 } 3816 3817 static int __init init_32bit_el0_mask(void) 3818 { 3819 if (!allow_mismatched_32bit_el0) 3820 return 0; 3821 3822 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3823 return -ENOMEM; 3824 3825 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3826 "arm64/mismatched_32bit_el0:online", 3827 enable_mismatched_32bit_el0, NULL); 3828 } 3829 subsys_initcall_sync(init_32bit_el0_mask); 3830 3831 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3832 { 3833 cpu_enable_swapper_cnp(); 3834 } 3835 3836 /* 3837 * We emulate only the following system register space. 3838 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3839 * See Table C5-6 System instruction encodings for System register accesses, 3840 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3841 */ 3842 static inline bool __attribute_const__ is_emulated(u32 id) 3843 { 3844 return (sys_reg_Op0(id) == 0x3 && 3845 sys_reg_CRn(id) == 0x0 && 3846 sys_reg_Op1(id) == 0x0 && 3847 (sys_reg_CRm(id) == 0 || 3848 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3849 } 3850 3851 /* 3852 * With CRm == 0, reg should be one of : 3853 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3854 */ 3855 static inline int emulate_id_reg(u32 id, u64 *valp) 3856 { 3857 switch (id) { 3858 case SYS_MIDR_EL1: 3859 *valp = read_cpuid_id(); 3860 break; 3861 case SYS_MPIDR_EL1: 3862 *valp = SYS_MPIDR_SAFE_VAL; 3863 break; 3864 case SYS_REVIDR_EL1: 3865 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3866 *valp = 0; 3867 break; 3868 default: 3869 return -EINVAL; 3870 } 3871 3872 return 0; 3873 } 3874 3875 static int emulate_sys_reg(u32 id, u64 *valp) 3876 { 3877 struct arm64_ftr_reg *regp; 3878 3879 if (!is_emulated(id)) 3880 return -EINVAL; 3881 3882 if (sys_reg_CRm(id) == 0) 3883 return emulate_id_reg(id, valp); 3884 3885 regp = get_arm64_ftr_reg_nowarn(id); 3886 if (regp) 3887 *valp = arm64_ftr_reg_user_value(regp); 3888 else 3889 /* 3890 * The untracked registers are either IMPLEMENTATION DEFINED 3891 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3892 */ 3893 *valp = 0; 3894 return 0; 3895 } 3896 3897 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3898 { 3899 int rc; 3900 u64 val; 3901 3902 rc = emulate_sys_reg(sys_reg, &val); 3903 if (!rc) { 3904 pt_regs_write_reg(regs, rt, val); 3905 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3906 } 3907 return rc; 3908 } 3909 3910 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3911 { 3912 u32 sys_reg, rt; 3913 3914 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3915 return false; 3916 3917 /* 3918 * sys_reg values are defined as used in mrs/msr instruction. 3919 * shift the imm value to get the encoding. 3920 */ 3921 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3922 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3923 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3924 } 3925 3926 enum mitigation_state arm64_get_meltdown_state(void) 3927 { 3928 if (__meltdown_safe) 3929 return SPECTRE_UNAFFECTED; 3930 3931 if (arm64_kernel_unmapped_at_el0()) 3932 return SPECTRE_MITIGATED; 3933 3934 return SPECTRE_VULNERABLE; 3935 } 3936 3937 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3938 char *buf) 3939 { 3940 switch (arm64_get_meltdown_state()) { 3941 case SPECTRE_UNAFFECTED: 3942 return sprintf(buf, "Not affected\n"); 3943 3944 case SPECTRE_MITIGATED: 3945 return sprintf(buf, "Mitigation: PTI\n"); 3946 3947 default: 3948 return sprintf(buf, "Vulnerable\n"); 3949 } 3950 } 3951