1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/hypervisor.h> 90 #include <asm/processor.h> 91 #include <asm/smp.h> 92 #include <asm/sysreg.h> 93 #include <asm/traps.h> 94 #include <asm/vectors.h> 95 #include <asm/virt.h> 96 97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 99 100 #ifdef CONFIG_COMPAT 101 #define COMPAT_ELF_HWCAP_DEFAULT \ 102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 105 COMPAT_HWCAP_LPAE) 106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 107 unsigned int compat_elf_hwcap2 __read_mostly; 108 unsigned int compat_elf_hwcap3 __read_mostly; 109 #endif 110 111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 112 EXPORT_SYMBOL(system_cpucaps); 113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 114 115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 116 117 bool arm64_use_ng_mappings = false; 118 EXPORT_SYMBOL(arm64_use_ng_mappings); 119 120 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 121 122 /* 123 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 124 * support it? 125 */ 126 static bool __read_mostly allow_mismatched_32bit_el0; 127 128 /* 129 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 130 * seen at least one CPU capable of 32-bit EL0. 131 */ 132 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 133 134 /* 135 * Mask of CPUs supporting 32-bit EL0. 136 * Only valid if arm64_mismatched_32bit_el0 is enabled. 137 */ 138 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 139 140 void dump_cpu_features(void) 141 { 142 /* file-wide pr_fmt adds "CPU features: " prefix */ 143 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 144 } 145 146 #define __ARM64_MAX_POSITIVE(reg, field) \ 147 ((reg##_##field##_SIGNED ? \ 148 BIT(reg##_##field##_WIDTH - 1) : \ 149 BIT(reg##_##field##_WIDTH)) - 1) 150 151 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 152 153 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 154 .sys_reg = SYS_##reg, \ 155 .field_pos = reg##_##field##_SHIFT, \ 156 .field_width = reg##_##field##_WIDTH, \ 157 .sign = reg##_##field##_SIGNED, \ 158 .min_field_value = min_value, \ 159 .max_field_value = max_value, 160 161 /* 162 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 163 * an implicit maximum that depends on the sign-ess of the field. 164 * 165 * An unsigned field will be capped at all ones, while a signed field 166 * will be limited to the positive half only. 167 */ 168 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 169 __ARM64_CPUID_FIELDS(reg, field, \ 170 SYS_FIELD_VALUE(reg, field, min_value), \ 171 __ARM64_MAX_POSITIVE(reg, field)) 172 173 /* 174 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 175 * implicit minimal value to max_value. This should be used when 176 * matching a non-implemented property. 177 */ 178 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 179 __ARM64_CPUID_FIELDS(reg, field, \ 180 __ARM64_MIN_NEGATIVE(reg, field), \ 181 SYS_FIELD_VALUE(reg, field, max_value)) 182 183 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 184 { \ 185 .sign = SIGNED, \ 186 .visible = VISIBLE, \ 187 .strict = STRICT, \ 188 .type = TYPE, \ 189 .shift = SHIFT, \ 190 .width = WIDTH, \ 191 .safe_val = SAFE_VAL, \ 192 } 193 194 /* Define a feature with unsigned values */ 195 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 196 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 197 198 /* Define a feature with a signed value */ 199 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 200 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 201 202 #define ARM64_FTR_END \ 203 { \ 204 .width = 0, \ 205 } 206 207 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 208 209 static bool __system_matches_cap(unsigned int n); 210 211 /* 212 * NOTE: Any changes to the visibility of features should be kept in 213 * sync with the documentation of the CPU feature register ABI. 214 */ 215 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 244 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 253 ARM64_FTR_END, 254 }; 255 256 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 269 ARM64_FTR_END, 270 }; 271 272 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 273 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 275 ARM64_FTR_END, 276 }; 277 278 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 289 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 290 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 295 ARM64_FTR_END, 296 }; 297 298 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 300 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 302 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 306 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 307 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 308 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 309 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 310 ARM64_FTR_END, 311 }; 312 313 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 314 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 315 ARM64_FTR_END, 316 }; 317 318 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 319 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 320 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 322 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 324 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 326 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 328 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 330 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 332 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 343 ARM64_FTR_END, 344 }; 345 346 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 348 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 350 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 352 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 354 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 356 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 358 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 360 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 393 ARM64_FTR_END, 394 }; 395 396 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 405 ARM64_FTR_END, 406 }; 407 408 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 412 /* 413 * Page size not being supported at Stage-2 is not fatal. You 414 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 415 * your favourite nesting hypervisor. 416 * 417 * There is a small corner case where the hypervisor explicitly 418 * advertises a given granule size at Stage-2 (value 2) on some 419 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 420 * vCPUs. Although this is not forbidden by the architecture, it 421 * indicates that the hypervisor is being silly (or buggy). 422 * 423 * We make no effort to cope with this and pretend that if these 424 * fields are inconsistent across vCPUs, then it isn't worth 425 * trying to bring KVM up. 426 */ 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 430 /* 431 * We already refuse to boot CPUs that don't support our configured 432 * page size, so we can only detect mismatches for a page size other 433 * than the one we're currently using. Unfortunately, SoCs like this 434 * exist in the wild so, even though we don't like it, we'll have to go 435 * along with it and treat them as non-strict. 436 */ 437 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 438 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 440 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 442 /* Linux shouldn't care about secure memory */ 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 446 /* 447 * Differing PARange is fine as long as all peripherals and memory are mapped 448 * within the minimum PARange of all CPUs 449 */ 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 451 ARM64_FTR_END, 452 }; 453 454 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 469 ARM64_FTR_END, 470 }; 471 472 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 488 ARM64_FTR_END, 489 }; 490 491 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 492 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 493 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 496 ARM64_FTR_END, 497 }; 498 499 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 500 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 502 ARM64_FTR_END, 503 }; 504 505 static const struct arm64_ftr_bits ftr_ctr[] = { 506 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 507 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 508 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 509 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 512 /* 513 * Linux can handle differing I-cache policies. Userspace JITs will 514 * make use of *minLine. 515 * If we have differing I-cache policies, report it as the weakest - VIPT. 516 */ 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static struct arm64_ftr_override __ro_after_init no_override = { }; 523 524 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 525 .name = "SYS_CTR_EL0", 526 .ftr_bits = ftr_ctr, 527 .override = &no_override, 528 }; 529 530 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 531 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 536 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 539 ARM64_FTR_END, 540 }; 541 542 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 543 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 548 /* 549 * We can instantiate multiple PMU instances with different levels 550 * of support. 551 */ 552 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 554 ARM64_FTR_END, 555 }; 556 557 static const struct arm64_ftr_bits ftr_mvfr0[] = { 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 566 ARM64_FTR_END, 567 }; 568 569 static const struct arm64_ftr_bits ftr_mvfr1[] = { 570 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_mvfr2[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 584 ARM64_FTR_END, 585 }; 586 587 static const struct arm64_ftr_bits ftr_dczid[] = { 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_gmid[] = { 594 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 595 ARM64_FTR_END, 596 }; 597 598 static const struct arm64_ftr_bits ftr_id_isar0[] = { 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 606 ARM64_FTR_END, 607 }; 608 609 static const struct arm64_ftr_bits ftr_id_isar5[] = { 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 614 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 616 ARM64_FTR_END, 617 }; 618 619 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 627 628 /* 629 * SpecSEI = 1 indicates that the PE might generate an SError on an 630 * external abort on speculative read. It is safe to assume that an 631 * SError might be generated than it will not be. Hence it has been 632 * classified as FTR_HIGHER_SAFE. 633 */ 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 635 ARM64_FTR_END, 636 }; 637 638 static const struct arm64_ftr_bits ftr_id_isar4[] = { 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 647 ARM64_FTR_END, 648 }; 649 650 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 652 ARM64_FTR_END, 653 }; 654 655 static const struct arm64_ftr_bits ftr_id_isar6[] = { 656 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 663 ARM64_FTR_END, 664 }; 665 666 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 673 ARM64_FTR_END, 674 }; 675 676 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 685 ARM64_FTR_END, 686 }; 687 688 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 689 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 691 ARM64_FTR_END, 692 }; 693 694 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 695 /* [31:28] TraceFilt */ 696 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 703 ARM64_FTR_END, 704 }; 705 706 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 707 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 708 ARM64_FTR_END, 709 }; 710 711 static const struct arm64_ftr_bits ftr_mpamidr[] = { 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 715 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 716 ARM64_FTR_END, 717 }; 718 719 /* 720 * Common ftr bits for a 32bit register with all hidden, strict 721 * attributes, with 4bit feature fields and a default safe value of 722 * 0. Covers the following 32bit registers: 723 * id_isar[1-3], id_mmfr[1-3] 724 */ 725 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 731 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 732 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 733 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 734 ARM64_FTR_END, 735 }; 736 737 /* Table for a single 32bit feature value */ 738 static const struct arm64_ftr_bits ftr_single32[] = { 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 740 ARM64_FTR_END, 741 }; 742 743 static const struct arm64_ftr_bits ftr_raz[] = { 744 ARM64_FTR_END, 745 }; 746 747 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 748 .sys_id = id, \ 749 .reg = &(struct arm64_ftr_reg){ \ 750 .name = id_str, \ 751 .override = (ovr), \ 752 .ftr_bits = &((table)[0]), \ 753 }} 754 755 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 756 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 757 758 #define ARM64_FTR_REG(id, table) \ 759 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 760 761 struct arm64_ftr_override id_aa64mmfr0_override; 762 struct arm64_ftr_override id_aa64mmfr1_override; 763 struct arm64_ftr_override id_aa64mmfr2_override; 764 struct arm64_ftr_override id_aa64pfr0_override; 765 struct arm64_ftr_override id_aa64pfr1_override; 766 struct arm64_ftr_override id_aa64zfr0_override; 767 struct arm64_ftr_override id_aa64smfr0_override; 768 struct arm64_ftr_override id_aa64isar1_override; 769 struct arm64_ftr_override id_aa64isar2_override; 770 771 struct arm64_ftr_override arm64_sw_feature_override; 772 773 static const struct __ftr_reg_entry { 774 u32 sys_id; 775 struct arm64_ftr_reg *reg; 776 } arm64_ftr_regs[] = { 777 778 /* Op1 = 0, CRn = 0, CRm = 1 */ 779 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 780 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 781 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 782 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 783 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 784 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 785 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 786 787 /* Op1 = 0, CRn = 0, CRm = 2 */ 788 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 789 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 790 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 791 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 792 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 793 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 794 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 795 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 796 797 /* Op1 = 0, CRn = 0, CRm = 3 */ 798 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 799 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 800 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 801 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 802 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 803 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 804 805 /* Op1 = 0, CRn = 0, CRm = 4 */ 806 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 807 &id_aa64pfr0_override), 808 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 809 &id_aa64pfr1_override), 810 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 811 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 812 &id_aa64zfr0_override), 813 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 814 &id_aa64smfr0_override), 815 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 816 817 /* Op1 = 0, CRn = 0, CRm = 5 */ 818 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 819 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 820 821 /* Op1 = 0, CRn = 0, CRm = 6 */ 822 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 824 &id_aa64isar1_override), 825 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 826 &id_aa64isar2_override), 827 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 828 829 /* Op1 = 0, CRn = 0, CRm = 7 */ 830 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 831 &id_aa64mmfr0_override), 832 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 833 &id_aa64mmfr1_override), 834 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 835 &id_aa64mmfr2_override), 836 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 837 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 838 839 /* Op1 = 0, CRn = 10, CRm = 4 */ 840 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 841 842 /* Op1 = 1, CRn = 0, CRm = 0 */ 843 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 844 845 /* Op1 = 3, CRn = 0, CRm = 0 */ 846 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 847 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 848 849 /* Op1 = 3, CRn = 14, CRm = 0 */ 850 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 851 }; 852 853 static int search_cmp_ftr_reg(const void *id, const void *regp) 854 { 855 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 856 } 857 858 /* 859 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 860 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 861 * ascending order of sys_id, we use binary search to find a matching 862 * entry. 863 * 864 * returns - Upon success, matching ftr_reg entry for id. 865 * - NULL on failure. It is upto the caller to decide 866 * the impact of a failure. 867 */ 868 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 869 { 870 const struct __ftr_reg_entry *ret; 871 872 ret = bsearch((const void *)(unsigned long)sys_id, 873 arm64_ftr_regs, 874 ARRAY_SIZE(arm64_ftr_regs), 875 sizeof(arm64_ftr_regs[0]), 876 search_cmp_ftr_reg); 877 if (ret) 878 return ret->reg; 879 return NULL; 880 } 881 882 /* 883 * get_arm64_ftr_reg - Looks up a feature register entry using 884 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 885 * 886 * returns - Upon success, matching ftr_reg entry for id. 887 * - NULL on failure but with an WARN_ON(). 888 */ 889 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 890 { 891 struct arm64_ftr_reg *reg; 892 893 reg = get_arm64_ftr_reg_nowarn(sys_id); 894 895 /* 896 * Requesting a non-existent register search is an error. Warn 897 * and let the caller handle it. 898 */ 899 WARN_ON(!reg); 900 return reg; 901 } 902 903 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 904 s64 ftr_val) 905 { 906 u64 mask = arm64_ftr_mask(ftrp); 907 908 reg &= ~mask; 909 reg |= (ftr_val << ftrp->shift) & mask; 910 return reg; 911 } 912 913 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 914 s64 cur) 915 { 916 s64 ret = 0; 917 918 switch (ftrp->type) { 919 case FTR_EXACT: 920 ret = ftrp->safe_val; 921 break; 922 case FTR_LOWER_SAFE: 923 ret = min(new, cur); 924 break; 925 case FTR_HIGHER_OR_ZERO_SAFE: 926 if (!cur || !new) 927 break; 928 fallthrough; 929 case FTR_HIGHER_SAFE: 930 ret = max(new, cur); 931 break; 932 default: 933 BUG(); 934 } 935 936 return ret; 937 } 938 939 static void __init sort_ftr_regs(void) 940 { 941 unsigned int i; 942 943 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 944 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 945 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 946 unsigned int j = 0; 947 948 /* 949 * Features here must be sorted in descending order with respect 950 * to their shift values and should not overlap with each other. 951 */ 952 for (; ftr_bits->width != 0; ftr_bits++, j++) { 953 unsigned int width = ftr_reg->ftr_bits[j].width; 954 unsigned int shift = ftr_reg->ftr_bits[j].shift; 955 unsigned int prev_shift; 956 957 WARN((shift + width) > 64, 958 "%s has invalid feature at shift %d\n", 959 ftr_reg->name, shift); 960 961 /* 962 * Skip the first feature. There is nothing to 963 * compare against for now. 964 */ 965 if (j == 0) 966 continue; 967 968 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 969 WARN((shift + width) > prev_shift, 970 "%s has feature overlap at shift %d\n", 971 ftr_reg->name, shift); 972 } 973 974 /* 975 * Skip the first register. There is nothing to 976 * compare against for now. 977 */ 978 if (i == 0) 979 continue; 980 /* 981 * Registers here must be sorted in ascending order with respect 982 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 983 * to work correctly. 984 */ 985 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 986 } 987 } 988 989 /* 990 * Initialise the CPU feature register from Boot CPU values. 991 * Also initiliases the strict_mask for the register. 992 * Any bits that are not covered by an arm64_ftr_bits entry are considered 993 * RES0 for the system-wide value, and must strictly match. 994 */ 995 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 996 { 997 u64 val = 0; 998 u64 strict_mask = ~0x0ULL; 999 u64 user_mask = 0; 1000 u64 valid_mask = 0; 1001 1002 const struct arm64_ftr_bits *ftrp; 1003 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1004 1005 if (!reg) 1006 return; 1007 1008 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1009 u64 ftr_mask = arm64_ftr_mask(ftrp); 1010 s64 ftr_new = arm64_ftr_value(ftrp, new); 1011 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1012 1013 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1014 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1015 char *str = NULL; 1016 1017 if (ftr_ovr != tmp) { 1018 /* Unsafe, remove the override */ 1019 reg->override->mask &= ~ftr_mask; 1020 reg->override->val &= ~ftr_mask; 1021 tmp = ftr_ovr; 1022 str = "ignoring override"; 1023 } else if (ftr_new != tmp) { 1024 /* Override was valid */ 1025 ftr_new = tmp; 1026 str = "forced"; 1027 } else { 1028 /* Override was the safe value */ 1029 str = "already set"; 1030 } 1031 1032 pr_warn("%s[%d:%d]: %s to %llx\n", 1033 reg->name, 1034 ftrp->shift + ftrp->width - 1, 1035 ftrp->shift, str, 1036 tmp & (BIT(ftrp->width) - 1)); 1037 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1038 reg->override->val &= ~ftr_mask; 1039 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1040 reg->name, 1041 ftrp->shift + ftrp->width - 1, 1042 ftrp->shift); 1043 } 1044 1045 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1046 1047 valid_mask |= ftr_mask; 1048 if (!ftrp->strict) 1049 strict_mask &= ~ftr_mask; 1050 if (ftrp->visible) 1051 user_mask |= ftr_mask; 1052 else 1053 reg->user_val = arm64_ftr_set_value(ftrp, 1054 reg->user_val, 1055 ftrp->safe_val); 1056 } 1057 1058 val &= valid_mask; 1059 1060 reg->sys_val = val; 1061 reg->strict_mask = strict_mask; 1062 reg->user_mask = user_mask; 1063 } 1064 1065 extern const struct arm64_cpu_capabilities arm64_errata[]; 1066 static const struct arm64_cpu_capabilities arm64_features[]; 1067 1068 static void __init 1069 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1070 { 1071 for (; caps->matches; caps++) { 1072 if (WARN(caps->capability >= ARM64_NCAPS, 1073 "Invalid capability %d\n", caps->capability)) 1074 continue; 1075 if (WARN(cpucap_ptrs[caps->capability], 1076 "Duplicate entry for capability %d\n", 1077 caps->capability)) 1078 continue; 1079 cpucap_ptrs[caps->capability] = caps; 1080 } 1081 } 1082 1083 static void __init init_cpucap_indirect_list(void) 1084 { 1085 init_cpucap_indirect_list_from_array(arm64_features); 1086 init_cpucap_indirect_list_from_array(arm64_errata); 1087 } 1088 1089 static void __init setup_boot_cpu_capabilities(void); 1090 1091 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1092 { 1093 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1094 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1095 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1096 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1097 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1098 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1099 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1100 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1101 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1102 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1103 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1104 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1105 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1106 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1107 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1108 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1109 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1110 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1111 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1112 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1113 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1114 } 1115 1116 #ifdef CONFIG_ARM64_PSEUDO_NMI 1117 static bool enable_pseudo_nmi; 1118 1119 static int __init early_enable_pseudo_nmi(char *p) 1120 { 1121 return kstrtobool(p, &enable_pseudo_nmi); 1122 } 1123 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1124 1125 static __init void detect_system_supports_pseudo_nmi(void) 1126 { 1127 struct device_node *np; 1128 1129 if (!enable_pseudo_nmi) 1130 return; 1131 1132 /* 1133 * Detect broken MediaTek firmware that doesn't properly save and 1134 * restore GIC priorities. 1135 */ 1136 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1137 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1138 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1139 enable_pseudo_nmi = false; 1140 } 1141 of_node_put(np); 1142 } 1143 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1144 static inline void detect_system_supports_pseudo_nmi(void) { } 1145 #endif 1146 1147 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1148 { 1149 /* Before we start using the tables, make sure it is sorted */ 1150 sort_ftr_regs(); 1151 1152 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1153 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1154 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1155 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1156 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1157 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1158 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1159 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1160 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1161 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1162 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1163 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1164 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1165 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1166 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1167 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1168 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1169 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1170 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1171 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1172 1173 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1174 init_32bit_cpu_features(&info->aarch32); 1175 1176 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1177 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1178 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1179 1180 vec_init_vq_map(ARM64_VEC_SVE); 1181 1182 cpacr_restore(cpacr); 1183 } 1184 1185 if (IS_ENABLED(CONFIG_ARM64_SME) && 1186 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1187 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1188 1189 vec_init_vq_map(ARM64_VEC_SME); 1190 1191 cpacr_restore(cpacr); 1192 } 1193 1194 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1195 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1196 1197 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1198 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1199 } 1200 1201 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1202 { 1203 const struct arm64_ftr_bits *ftrp; 1204 1205 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1206 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1207 s64 ftr_new = arm64_ftr_value(ftrp, new); 1208 1209 if (ftr_cur == ftr_new) 1210 continue; 1211 /* Find a safe value */ 1212 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1213 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1214 } 1215 1216 } 1217 1218 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1219 { 1220 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1221 1222 if (!regp) 1223 return 0; 1224 1225 update_cpu_ftr_reg(regp, val); 1226 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1227 return 0; 1228 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1229 regp->name, boot, cpu, val); 1230 return 1; 1231 } 1232 1233 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1234 { 1235 const struct arm64_ftr_bits *ftrp; 1236 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1237 1238 if (!regp) 1239 return; 1240 1241 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1242 if (ftrp->shift == field) { 1243 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1244 break; 1245 } 1246 } 1247 1248 /* Bogus field? */ 1249 WARN_ON(!ftrp->width); 1250 } 1251 1252 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1253 struct cpuinfo_arm64 *boot) 1254 { 1255 static bool boot_cpu_32bit_regs_overridden = false; 1256 1257 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1258 return; 1259 1260 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1261 return; 1262 1263 boot->aarch32 = info->aarch32; 1264 init_32bit_cpu_features(&boot->aarch32); 1265 boot_cpu_32bit_regs_overridden = true; 1266 } 1267 1268 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1269 struct cpuinfo_32bit *boot) 1270 { 1271 int taint = 0; 1272 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1273 1274 /* 1275 * If we don't have AArch32 at EL1, then relax the strictness of 1276 * EL1-dependent register fields to avoid spurious sanity check fails. 1277 */ 1278 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1279 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1280 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1281 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1282 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1283 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1284 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1285 } 1286 1287 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1288 info->reg_id_dfr0, boot->reg_id_dfr0); 1289 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1290 info->reg_id_dfr1, boot->reg_id_dfr1); 1291 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1292 info->reg_id_isar0, boot->reg_id_isar0); 1293 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1294 info->reg_id_isar1, boot->reg_id_isar1); 1295 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1296 info->reg_id_isar2, boot->reg_id_isar2); 1297 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1298 info->reg_id_isar3, boot->reg_id_isar3); 1299 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1300 info->reg_id_isar4, boot->reg_id_isar4); 1301 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1302 info->reg_id_isar5, boot->reg_id_isar5); 1303 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1304 info->reg_id_isar6, boot->reg_id_isar6); 1305 1306 /* 1307 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1308 * ACTLR formats could differ across CPUs and therefore would have to 1309 * be trapped for virtualization anyway. 1310 */ 1311 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1312 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1313 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1314 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1315 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1316 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1317 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1318 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1319 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1320 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1321 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1322 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1323 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1324 info->reg_id_pfr0, boot->reg_id_pfr0); 1325 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1326 info->reg_id_pfr1, boot->reg_id_pfr1); 1327 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1328 info->reg_id_pfr2, boot->reg_id_pfr2); 1329 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1330 info->reg_mvfr0, boot->reg_mvfr0); 1331 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1332 info->reg_mvfr1, boot->reg_mvfr1); 1333 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1334 info->reg_mvfr2, boot->reg_mvfr2); 1335 1336 return taint; 1337 } 1338 1339 /* 1340 * Update system wide CPU feature registers with the values from a 1341 * non-boot CPU. Also performs SANITY checks to make sure that there 1342 * aren't any insane variations from that of the boot CPU. 1343 */ 1344 void update_cpu_features(int cpu, 1345 struct cpuinfo_arm64 *info, 1346 struct cpuinfo_arm64 *boot) 1347 { 1348 int taint = 0; 1349 1350 /* 1351 * The kernel can handle differing I-cache policies, but otherwise 1352 * caches should look identical. Userspace JITs will make use of 1353 * *minLine. 1354 */ 1355 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1356 info->reg_ctr, boot->reg_ctr); 1357 1358 /* 1359 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1360 * could result in too much or too little memory being zeroed if a 1361 * process is preempted and migrated between CPUs. 1362 */ 1363 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1364 info->reg_dczid, boot->reg_dczid); 1365 1366 /* If different, timekeeping will be broken (especially with KVM) */ 1367 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1368 info->reg_cntfrq, boot->reg_cntfrq); 1369 1370 /* 1371 * The kernel uses self-hosted debug features and expects CPUs to 1372 * support identical debug features. We presently need CTX_CMPs, WRPs, 1373 * and BRPs to be identical. 1374 * ID_AA64DFR1 is currently RES0. 1375 */ 1376 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1377 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1378 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1379 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1380 /* 1381 * Even in big.LITTLE, processors should be identical instruction-set 1382 * wise. 1383 */ 1384 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1385 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1386 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1387 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1388 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1389 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1390 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1391 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1392 1393 /* 1394 * Differing PARange support is fine as long as all peripherals and 1395 * memory are mapped within the minimum PARange of all CPUs. 1396 * Linux should not care about secure memory. 1397 */ 1398 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1399 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1400 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1401 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1402 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1403 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1404 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1405 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1406 1407 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1408 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1409 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1410 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1411 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1412 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1413 1414 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1415 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1416 1417 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1418 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1419 1420 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1421 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1422 1423 /* Probe vector lengths */ 1424 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1425 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1426 if (!system_capabilities_finalized()) { 1427 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1428 1429 vec_update_vq_map(ARM64_VEC_SVE); 1430 1431 cpacr_restore(cpacr); 1432 } 1433 } 1434 1435 if (IS_ENABLED(CONFIG_ARM64_SME) && 1436 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1437 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1438 1439 /* Probe vector lengths */ 1440 if (!system_capabilities_finalized()) 1441 vec_update_vq_map(ARM64_VEC_SME); 1442 1443 cpacr_restore(cpacr); 1444 } 1445 1446 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1447 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1448 info->reg_mpamidr, boot->reg_mpamidr); 1449 } 1450 1451 /* 1452 * The kernel uses the LDGM/STGM instructions and the number of tags 1453 * they read/write depends on the GMID_EL1.BS field. Check that the 1454 * value is the same on all CPUs. 1455 */ 1456 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1457 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1458 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1459 info->reg_gmid, boot->reg_gmid); 1460 } 1461 1462 /* 1463 * If we don't have AArch32 at all then skip the checks entirely 1464 * as the register values may be UNKNOWN and we're not going to be 1465 * using them for anything. 1466 * 1467 * This relies on a sanitised view of the AArch64 ID registers 1468 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1469 */ 1470 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1471 lazy_init_32bit_cpu_features(info, boot); 1472 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1473 &boot->aarch32); 1474 } 1475 1476 /* 1477 * Mismatched CPU features are a recipe for disaster. Don't even 1478 * pretend to support them. 1479 */ 1480 if (taint) { 1481 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1482 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1483 } 1484 } 1485 1486 u64 read_sanitised_ftr_reg(u32 id) 1487 { 1488 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1489 1490 if (!regp) 1491 return 0; 1492 return regp->sys_val; 1493 } 1494 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1495 1496 #define read_sysreg_case(r) \ 1497 case r: val = read_sysreg_s(r); break; 1498 1499 /* 1500 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1501 * Read the system register on the current CPU 1502 */ 1503 u64 __read_sysreg_by_encoding(u32 sys_id) 1504 { 1505 struct arm64_ftr_reg *regp; 1506 u64 val; 1507 1508 switch (sys_id) { 1509 read_sysreg_case(SYS_ID_PFR0_EL1); 1510 read_sysreg_case(SYS_ID_PFR1_EL1); 1511 read_sysreg_case(SYS_ID_PFR2_EL1); 1512 read_sysreg_case(SYS_ID_DFR0_EL1); 1513 read_sysreg_case(SYS_ID_DFR1_EL1); 1514 read_sysreg_case(SYS_ID_MMFR0_EL1); 1515 read_sysreg_case(SYS_ID_MMFR1_EL1); 1516 read_sysreg_case(SYS_ID_MMFR2_EL1); 1517 read_sysreg_case(SYS_ID_MMFR3_EL1); 1518 read_sysreg_case(SYS_ID_MMFR4_EL1); 1519 read_sysreg_case(SYS_ID_MMFR5_EL1); 1520 read_sysreg_case(SYS_ID_ISAR0_EL1); 1521 read_sysreg_case(SYS_ID_ISAR1_EL1); 1522 read_sysreg_case(SYS_ID_ISAR2_EL1); 1523 read_sysreg_case(SYS_ID_ISAR3_EL1); 1524 read_sysreg_case(SYS_ID_ISAR4_EL1); 1525 read_sysreg_case(SYS_ID_ISAR5_EL1); 1526 read_sysreg_case(SYS_ID_ISAR6_EL1); 1527 read_sysreg_case(SYS_MVFR0_EL1); 1528 read_sysreg_case(SYS_MVFR1_EL1); 1529 read_sysreg_case(SYS_MVFR2_EL1); 1530 1531 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1532 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1533 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1534 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1535 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1536 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1537 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1538 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1539 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1540 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1541 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1542 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1543 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1544 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1545 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1546 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1547 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1548 1549 read_sysreg_case(SYS_CNTFRQ_EL0); 1550 read_sysreg_case(SYS_CTR_EL0); 1551 read_sysreg_case(SYS_DCZID_EL0); 1552 1553 default: 1554 BUG(); 1555 return 0; 1556 } 1557 1558 regp = get_arm64_ftr_reg(sys_id); 1559 if (regp) { 1560 val &= ~regp->override->mask; 1561 val |= (regp->override->val & regp->override->mask); 1562 } 1563 1564 return val; 1565 } 1566 1567 #include <linux/irqchip/arm-gic-v3.h> 1568 1569 static bool 1570 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1571 { 1572 return true; 1573 } 1574 1575 static bool 1576 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1577 { 1578 int val, min, max; 1579 u64 tmp; 1580 1581 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1582 entry->field_width, 1583 entry->sign); 1584 1585 tmp = entry->min_field_value; 1586 tmp <<= entry->field_pos; 1587 1588 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1589 entry->field_width, 1590 entry->sign); 1591 1592 tmp = entry->max_field_value; 1593 tmp <<= entry->field_pos; 1594 1595 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1596 entry->field_width, 1597 entry->sign); 1598 1599 return val >= min && val <= max; 1600 } 1601 1602 static u64 1603 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1604 { 1605 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1606 if (scope == SCOPE_SYSTEM) 1607 return read_sanitised_ftr_reg(entry->sys_reg); 1608 else 1609 return __read_sysreg_by_encoding(entry->sys_reg); 1610 } 1611 1612 static bool 1613 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1614 { 1615 int mask; 1616 struct arm64_ftr_reg *regp; 1617 u64 val = read_scoped_sysreg(entry, scope); 1618 1619 regp = get_arm64_ftr_reg(entry->sys_reg); 1620 if (!regp) 1621 return false; 1622 1623 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1624 entry->field_pos, 1625 entry->field_width); 1626 if (!mask) 1627 return false; 1628 1629 return feature_matches(val, entry); 1630 } 1631 1632 static bool 1633 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1634 { 1635 u64 val = read_scoped_sysreg(entry, scope); 1636 return feature_matches(val, entry); 1637 } 1638 1639 const struct cpumask *system_32bit_el0_cpumask(void) 1640 { 1641 if (!system_supports_32bit_el0()) 1642 return cpu_none_mask; 1643 1644 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1645 return cpu_32bit_el0_mask; 1646 1647 return cpu_possible_mask; 1648 } 1649 1650 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1651 { 1652 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1653 } 1654 1655 static int __init parse_32bit_el0_param(char *str) 1656 { 1657 allow_mismatched_32bit_el0 = true; 1658 return 0; 1659 } 1660 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1661 1662 static ssize_t aarch32_el0_show(struct device *dev, 1663 struct device_attribute *attr, char *buf) 1664 { 1665 const struct cpumask *mask = system_32bit_el0_cpumask(); 1666 1667 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1668 } 1669 static const DEVICE_ATTR_RO(aarch32_el0); 1670 1671 static int __init aarch32_el0_sysfs_init(void) 1672 { 1673 struct device *dev_root; 1674 int ret = 0; 1675 1676 if (!allow_mismatched_32bit_el0) 1677 return 0; 1678 1679 dev_root = bus_get_dev_root(&cpu_subsys); 1680 if (dev_root) { 1681 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1682 put_device(dev_root); 1683 } 1684 return ret; 1685 } 1686 device_initcall(aarch32_el0_sysfs_init); 1687 1688 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1689 { 1690 if (!has_cpuid_feature(entry, scope)) 1691 return allow_mismatched_32bit_el0; 1692 1693 if (scope == SCOPE_SYSTEM) 1694 pr_info("detected: 32-bit EL0 Support\n"); 1695 1696 return true; 1697 } 1698 1699 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1700 { 1701 bool has_sre; 1702 1703 if (!has_cpuid_feature(entry, scope)) 1704 return false; 1705 1706 has_sre = gic_enable_sre(); 1707 if (!has_sre) 1708 pr_warn_once("%s present but disabled by higher exception level\n", 1709 entry->desc); 1710 1711 return has_sre; 1712 } 1713 1714 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1715 int scope) 1716 { 1717 u64 ctr; 1718 1719 if (scope == SCOPE_SYSTEM) 1720 ctr = arm64_ftr_reg_ctrel0.sys_val; 1721 else 1722 ctr = read_cpuid_effective_cachetype(); 1723 1724 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1725 } 1726 1727 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1728 { 1729 /* 1730 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1731 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1732 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1733 * value. 1734 */ 1735 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1736 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1737 } 1738 1739 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1740 int scope) 1741 { 1742 u64 ctr; 1743 1744 if (scope == SCOPE_SYSTEM) 1745 ctr = arm64_ftr_reg_ctrel0.sys_val; 1746 else 1747 ctr = read_cpuid_cachetype(); 1748 1749 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1750 } 1751 1752 static bool __maybe_unused 1753 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1754 { 1755 /* 1756 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1757 * may share TLB entries with a CPU stuck in the crashed 1758 * kernel. 1759 */ 1760 if (is_kdump_kernel()) 1761 return false; 1762 1763 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1764 return false; 1765 1766 return has_cpuid_feature(entry, scope); 1767 } 1768 1769 static bool __meltdown_safe = true; 1770 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1771 1772 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1773 int scope) 1774 { 1775 /* List of CPUs that are not vulnerable and don't need KPTI */ 1776 static const struct midr_range kpti_safe_list[] = { 1777 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1778 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1779 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1780 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1781 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1782 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1783 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1784 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1785 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1786 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1787 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1788 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1789 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1790 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1791 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1792 { /* sentinel */ } 1793 }; 1794 char const *str = "kpti command line option"; 1795 bool meltdown_safe; 1796 1797 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1798 1799 /* Defer to CPU feature registers */ 1800 if (has_cpuid_feature(entry, scope)) 1801 meltdown_safe = true; 1802 1803 if (!meltdown_safe) 1804 __meltdown_safe = false; 1805 1806 /* 1807 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1808 * ThunderX leads to apparent I-cache corruption of kernel text, which 1809 * ends as well as you might imagine. Don't even try. We cannot rely 1810 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1811 * because cpucap detection order may change. However, since we know 1812 * affected CPUs are always in a homogeneous configuration, it is 1813 * safe to rely on this_cpu_has_cap() here. 1814 */ 1815 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1816 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1817 __kpti_forced = -1; 1818 } 1819 1820 /* Useful for KASLR robustness */ 1821 if (kaslr_enabled() && kaslr_requires_kpti()) { 1822 if (!__kpti_forced) { 1823 str = "KASLR"; 1824 __kpti_forced = 1; 1825 } 1826 } 1827 1828 if (cpu_mitigations_off() && !__kpti_forced) { 1829 str = "mitigations=off"; 1830 __kpti_forced = -1; 1831 } 1832 1833 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1834 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1835 return false; 1836 } 1837 1838 /* Forced? */ 1839 if (__kpti_forced) { 1840 pr_info_once("kernel page table isolation forced %s by %s\n", 1841 __kpti_forced > 0 ? "ON" : "OFF", str); 1842 return __kpti_forced > 0; 1843 } 1844 1845 return !meltdown_safe; 1846 } 1847 1848 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1849 { 1850 /* 1851 * Although the Apple M2 family appears to support NV1, the 1852 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1853 * that it doesn't support NV1 at all. 1854 */ 1855 static const struct midr_range nv1_ni_list[] = { 1856 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1857 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1858 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1859 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1860 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1861 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1862 {} 1863 }; 1864 1865 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1866 !(has_cpuid_feature(entry, scope) || 1867 is_midr_in_range_list(nv1_ni_list))); 1868 } 1869 1870 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1871 static bool has_lpa2_at_stage1(u64 mmfr0) 1872 { 1873 unsigned int tgran; 1874 1875 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1876 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1877 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1878 } 1879 1880 static bool has_lpa2_at_stage2(u64 mmfr0) 1881 { 1882 unsigned int tgran; 1883 1884 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1885 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1886 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1887 } 1888 1889 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1890 { 1891 u64 mmfr0; 1892 1893 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1894 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1895 } 1896 #else 1897 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1898 { 1899 return false; 1900 } 1901 #endif 1902 1903 #ifdef CONFIG_HW_PERF_EVENTS 1904 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1905 { 1906 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1907 unsigned int pmuver; 1908 1909 /* 1910 * PMUVer follows the standard ID scheme for an unsigned field with the 1911 * exception of 0xF (IMP_DEF) which is treated specially and implies 1912 * FEAT_PMUv3 is not implemented. 1913 * 1914 * See DDI0487L.a D24.1.3.2 for more details. 1915 */ 1916 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1917 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1918 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1919 return false; 1920 1921 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1922 } 1923 #endif 1924 1925 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1926 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1927 1928 extern 1929 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1930 phys_addr_t size, pgprot_t prot, 1931 phys_addr_t (*pgtable_alloc)(int), int flags); 1932 1933 static phys_addr_t __initdata kpti_ng_temp_alloc; 1934 1935 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1936 { 1937 kpti_ng_temp_alloc -= PAGE_SIZE; 1938 return kpti_ng_temp_alloc; 1939 } 1940 1941 static int __init __kpti_install_ng_mappings(void *__unused) 1942 { 1943 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1944 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1945 kpti_remap_fn *remap_fn; 1946 1947 int cpu = smp_processor_id(); 1948 int levels = CONFIG_PGTABLE_LEVELS; 1949 int order = order_base_2(levels); 1950 u64 kpti_ng_temp_pgd_pa = 0; 1951 pgd_t *kpti_ng_temp_pgd; 1952 u64 alloc = 0; 1953 1954 if (levels == 5 && !pgtable_l5_enabled()) 1955 levels = 4; 1956 else if (levels == 4 && !pgtable_l4_enabled()) 1957 levels = 3; 1958 1959 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1960 1961 if (!cpu) { 1962 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1963 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1964 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1965 1966 // 1967 // Create a minimal page table hierarchy that permits us to map 1968 // the swapper page tables temporarily as we traverse them. 1969 // 1970 // The physical pages are laid out as follows: 1971 // 1972 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1973 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1974 // +--------+-\-------+-\------ +-\------ +-///--------+ 1975 // ^ 1976 // The first page is mapped into this hierarchy at a PMD_SHIFT 1977 // aligned virtual address, so that we can manipulate the PTE 1978 // level entries while the mapping is active. The first entry 1979 // covers the PTE[] page itself, the remaining entries are free 1980 // to be used as a ad-hoc fixmap. 1981 // 1982 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1983 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1984 kpti_ng_pgd_alloc, 0); 1985 } 1986 1987 cpu_install_idmap(); 1988 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1989 cpu_uninstall_idmap(); 1990 1991 if (!cpu) { 1992 free_pages(alloc, order); 1993 arm64_use_ng_mappings = true; 1994 } 1995 1996 return 0; 1997 } 1998 1999 static void __init kpti_install_ng_mappings(void) 2000 { 2001 /* Check whether KPTI is going to be used */ 2002 if (!arm64_kernel_unmapped_at_el0()) 2003 return; 2004 2005 /* 2006 * We don't need to rewrite the page-tables if either we've done 2007 * it already or we have KASLR enabled and therefore have not 2008 * created any global mappings at all. 2009 */ 2010 if (arm64_use_ng_mappings) 2011 return; 2012 2013 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 2014 } 2015 2016 #else 2017 static inline void kpti_install_ng_mappings(void) 2018 { 2019 } 2020 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 2021 2022 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 2023 { 2024 if (__this_cpu_read(this_cpu_vector) == vectors) { 2025 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2026 2027 __this_cpu_write(this_cpu_vector, v); 2028 } 2029 2030 } 2031 2032 static int __init parse_kpti(char *str) 2033 { 2034 bool enabled; 2035 int ret = kstrtobool(str, &enabled); 2036 2037 if (ret) 2038 return ret; 2039 2040 __kpti_forced = enabled ? 1 : -1; 2041 return 0; 2042 } 2043 early_param("kpti", parse_kpti); 2044 2045 #ifdef CONFIG_ARM64_HW_AFDBM 2046 static struct cpumask dbm_cpus __read_mostly; 2047 2048 static inline void __cpu_enable_hw_dbm(void) 2049 { 2050 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2051 2052 write_sysreg(tcr, tcr_el1); 2053 isb(); 2054 local_flush_tlb_all(); 2055 } 2056 2057 static bool cpu_has_broken_dbm(void) 2058 { 2059 /* List of CPUs which have broken DBM support. */ 2060 static const struct midr_range cpus[] = { 2061 #ifdef CONFIG_ARM64_ERRATUM_1024718 2062 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2063 /* Kryo4xx Silver (rdpe => r1p0) */ 2064 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2065 #endif 2066 #ifdef CONFIG_ARM64_ERRATUM_2051678 2067 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2068 #endif 2069 {}, 2070 }; 2071 2072 return is_midr_in_range_list(cpus); 2073 } 2074 2075 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2076 { 2077 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2078 !cpu_has_broken_dbm(); 2079 } 2080 2081 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2082 { 2083 if (cpu_can_use_dbm(cap)) { 2084 __cpu_enable_hw_dbm(); 2085 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2086 } 2087 } 2088 2089 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2090 int __unused) 2091 { 2092 /* 2093 * DBM is a non-conflicting feature. i.e, the kernel can safely 2094 * run a mix of CPUs with and without the feature. So, we 2095 * unconditionally enable the capability to allow any late CPU 2096 * to use the feature. We only enable the control bits on the 2097 * CPU, if it is supported. 2098 */ 2099 2100 return true; 2101 } 2102 2103 #endif 2104 2105 #ifdef CONFIG_ARM64_AMU_EXTN 2106 2107 /* 2108 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2109 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2110 * information regarding all the events that it supports. When a CPU bit is 2111 * set in the cpumask, the user of this feature can only rely on the presence 2112 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2113 * counters are enabled or access to these counters is enabled by code 2114 * executed at higher exception levels (firmware). 2115 */ 2116 static struct cpumask amu_cpus __read_mostly; 2117 2118 bool cpu_has_amu_feat(int cpu) 2119 { 2120 return cpumask_test_cpu(cpu, &amu_cpus); 2121 } 2122 2123 int get_cpu_with_amu_feat(void) 2124 { 2125 return cpumask_any(&amu_cpus); 2126 } 2127 2128 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2129 { 2130 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2131 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2132 2133 /* 0 reference values signal broken/disabled counters */ 2134 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2135 update_freq_counters_refs(); 2136 } 2137 } 2138 2139 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2140 int __unused) 2141 { 2142 /* 2143 * The AMU extension is a non-conflicting feature: the kernel can 2144 * safely run a mix of CPUs with and without support for the 2145 * activity monitors extension. Therefore, unconditionally enable 2146 * the capability to allow any late CPU to use the feature. 2147 * 2148 * With this feature unconditionally enabled, the cpu_enable 2149 * function will be called for all CPUs that match the criteria, 2150 * including secondary and hotplugged, marking this feature as 2151 * present on that respective CPU. The enable function will also 2152 * print a detection message. 2153 */ 2154 2155 return true; 2156 } 2157 #else 2158 int get_cpu_with_amu_feat(void) 2159 { 2160 return nr_cpu_ids; 2161 } 2162 #endif 2163 2164 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2165 { 2166 return is_kernel_in_hyp_mode(); 2167 } 2168 2169 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2170 { 2171 /* 2172 * Copy register values that aren't redirected by hardware. 2173 * 2174 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2175 * this value to tpidr_el2 before we patch the code. Once we've done 2176 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2177 * do anything here. 2178 */ 2179 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2180 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2181 } 2182 2183 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2184 int scope) 2185 { 2186 if (kvm_get_mode() != KVM_MODE_NV) 2187 return false; 2188 2189 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2190 pr_warn("unavailable: %s\n", cap->desc); 2191 return false; 2192 } 2193 2194 return true; 2195 } 2196 2197 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2198 int __unused) 2199 { 2200 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2201 } 2202 2203 #ifdef CONFIG_ARM64_PAN 2204 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2205 { 2206 /* 2207 * We modify PSTATE. This won't work from irq context as the PSTATE 2208 * is discarded once we return from the exception. 2209 */ 2210 WARN_ON_ONCE(in_interrupt()); 2211 2212 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2213 set_pstate_pan(1); 2214 } 2215 #endif /* CONFIG_ARM64_PAN */ 2216 2217 #ifdef CONFIG_ARM64_RAS_EXTN 2218 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2219 { 2220 /* Firmware may have left a deferred SError in this register. */ 2221 write_sysreg_s(0, SYS_DISR_EL1); 2222 } 2223 #endif /* CONFIG_ARM64_RAS_EXTN */ 2224 2225 #ifdef CONFIG_ARM64_PTR_AUTH 2226 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2227 { 2228 int boot_val, sec_val; 2229 2230 /* We don't expect to be called with SCOPE_SYSTEM */ 2231 WARN_ON(scope == SCOPE_SYSTEM); 2232 /* 2233 * The ptr-auth feature levels are not intercompatible with lower 2234 * levels. Hence we must match ptr-auth feature level of the secondary 2235 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2236 * from the sanitised register whereas direct register read is done for 2237 * the secondary CPUs. 2238 * The sanitised feature state is guaranteed to match that of the 2239 * boot CPU as a mismatched secondary CPU is parked before it gets 2240 * a chance to update the state, with the capability. 2241 */ 2242 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2243 entry->field_pos, entry->sign); 2244 if (scope & SCOPE_BOOT_CPU) 2245 return boot_val >= entry->min_field_value; 2246 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2247 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2248 entry->field_pos, entry->sign); 2249 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2250 } 2251 2252 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2253 int scope) 2254 { 2255 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2256 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2257 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2258 2259 return apa || apa3 || api; 2260 } 2261 2262 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2263 int __unused) 2264 { 2265 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2266 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2267 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2268 2269 return gpa || gpa3 || gpi; 2270 } 2271 #endif /* CONFIG_ARM64_PTR_AUTH */ 2272 2273 #ifdef CONFIG_ARM64_E0PD 2274 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2275 { 2276 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2277 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2278 } 2279 #endif /* CONFIG_ARM64_E0PD */ 2280 2281 #ifdef CONFIG_ARM64_PSEUDO_NMI 2282 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2283 int scope) 2284 { 2285 /* 2286 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2287 * feature, so will be detected earlier. 2288 */ 2289 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2290 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2291 return false; 2292 2293 return enable_pseudo_nmi; 2294 } 2295 2296 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2297 int scope) 2298 { 2299 /* 2300 * If we're not using priority masking then we won't be poking PMR_EL1, 2301 * and there's no need to relax synchronization of writes to it, and 2302 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2303 * that. 2304 * 2305 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2306 * feature, so will be detected earlier. 2307 */ 2308 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2309 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2310 return false; 2311 2312 /* 2313 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2314 * hint for interrupt distribution, a DSB is not necessary when 2315 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2316 * 2317 * Linux itself doesn't use 1:N distribution, so has no need to 2318 * set PMHE. The only reason to have it set is if EL3 requires it 2319 * (and we can't change it). 2320 */ 2321 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2322 } 2323 #endif 2324 2325 #ifdef CONFIG_ARM64_BTI 2326 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2327 { 2328 /* 2329 * Use of X16/X17 for tail-calls and trampolines that jump to 2330 * function entry points using BR is a requirement for 2331 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2332 * So, be strict and forbid other BRs using other registers to 2333 * jump onto a PACIxSP instruction: 2334 */ 2335 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2336 isb(); 2337 } 2338 #endif /* CONFIG_ARM64_BTI */ 2339 2340 #ifdef CONFIG_ARM64_MTE 2341 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2342 { 2343 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2344 2345 mte_cpu_setup(); 2346 2347 /* 2348 * Clear the tags in the zero page. This needs to be done via the 2349 * linear map which has the Tagged attribute. 2350 */ 2351 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2352 mte_clear_page_tags(lm_alias(empty_zero_page)); 2353 set_page_mte_tagged(ZERO_PAGE(0)); 2354 } 2355 2356 kasan_init_hw_tags_cpu(); 2357 } 2358 #endif /* CONFIG_ARM64_MTE */ 2359 2360 static void user_feature_fixup(void) 2361 { 2362 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2363 struct arm64_ftr_reg *regp; 2364 2365 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2366 if (regp) 2367 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2368 } 2369 2370 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2371 struct arm64_ftr_reg *regp; 2372 2373 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2374 if (regp) 2375 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2376 } 2377 } 2378 2379 static void elf_hwcap_fixup(void) 2380 { 2381 #ifdef CONFIG_COMPAT 2382 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2383 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2384 #endif /* CONFIG_COMPAT */ 2385 } 2386 2387 #ifdef CONFIG_KVM 2388 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2389 { 2390 return kvm_get_mode() == KVM_MODE_PROTECTED; 2391 } 2392 #endif /* CONFIG_KVM */ 2393 2394 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2395 { 2396 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2397 } 2398 2399 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2400 { 2401 set_pstate_dit(1); 2402 } 2403 2404 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2405 { 2406 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2407 } 2408 2409 #ifdef CONFIG_ARM64_POE 2410 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2411 { 2412 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2413 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2414 } 2415 #endif 2416 2417 #ifdef CONFIG_ARM64_GCS 2418 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2419 { 2420 /* GCSPR_EL0 is always readable */ 2421 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2422 } 2423 #endif 2424 2425 /* Internal helper functions to match cpu capability type */ 2426 static bool 2427 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2428 { 2429 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2430 } 2431 2432 static bool 2433 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2434 { 2435 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2436 } 2437 2438 static bool 2439 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2440 { 2441 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2442 } 2443 2444 static bool 2445 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2446 { 2447 if (!has_cpuid_feature(entry, scope)) 2448 return false; 2449 2450 /* Check firmware actually enabled MPAM on this cpu. */ 2451 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2452 } 2453 2454 static void 2455 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2456 { 2457 /* 2458 * Access by the kernel (at EL1) should use the reserved PARTID 2459 * which is configured unrestricted. This avoids priority-inversion 2460 * where latency sensitive tasks have to wait for a task that has 2461 * been throttled to release the lock. 2462 */ 2463 write_sysreg_s(0, SYS_MPAM1_EL1); 2464 } 2465 2466 static bool 2467 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2468 { 2469 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2470 2471 return idr & MPAMIDR_EL1_HAS_HCR; 2472 } 2473 2474 static const struct arm64_cpu_capabilities arm64_features[] = { 2475 { 2476 .capability = ARM64_ALWAYS_BOOT, 2477 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2478 .matches = has_always, 2479 }, 2480 { 2481 .capability = ARM64_ALWAYS_SYSTEM, 2482 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2483 .matches = has_always, 2484 }, 2485 { 2486 .desc = "GIC system register CPU interface", 2487 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2488 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2489 .matches = has_useable_gicv3_cpuif, 2490 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2491 }, 2492 { 2493 .desc = "Enhanced Counter Virtualization", 2494 .capability = ARM64_HAS_ECV, 2495 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2496 .matches = has_cpuid_feature, 2497 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2498 }, 2499 { 2500 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2501 .capability = ARM64_HAS_ECV_CNTPOFF, 2502 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2503 .matches = has_cpuid_feature, 2504 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2505 }, 2506 #ifdef CONFIG_ARM64_PAN 2507 { 2508 .desc = "Privileged Access Never", 2509 .capability = ARM64_HAS_PAN, 2510 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2511 .matches = has_cpuid_feature, 2512 .cpu_enable = cpu_enable_pan, 2513 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2514 }, 2515 #endif /* CONFIG_ARM64_PAN */ 2516 #ifdef CONFIG_ARM64_EPAN 2517 { 2518 .desc = "Enhanced Privileged Access Never", 2519 .capability = ARM64_HAS_EPAN, 2520 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2521 .matches = has_cpuid_feature, 2522 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2523 }, 2524 #endif /* CONFIG_ARM64_EPAN */ 2525 #ifdef CONFIG_ARM64_LSE_ATOMICS 2526 { 2527 .desc = "LSE atomic instructions", 2528 .capability = ARM64_HAS_LSE_ATOMICS, 2529 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2530 .matches = has_cpuid_feature, 2531 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2532 }, 2533 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2534 { 2535 .desc = "Virtualization Host Extensions", 2536 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2537 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2538 .matches = runs_at_el2, 2539 .cpu_enable = cpu_copy_el2regs, 2540 }, 2541 { 2542 .desc = "Nested Virtualization Support", 2543 .capability = ARM64_HAS_NESTED_VIRT, 2544 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2545 .matches = has_nested_virt_support, 2546 .match_list = (const struct arm64_cpu_capabilities []){ 2547 { 2548 .matches = has_cpuid_feature, 2549 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2550 }, 2551 { 2552 .matches = has_cpuid_feature, 2553 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2554 }, 2555 { /* Sentinel */ } 2556 }, 2557 }, 2558 { 2559 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2560 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2561 .matches = has_32bit_el0, 2562 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2563 }, 2564 #ifdef CONFIG_KVM 2565 { 2566 .desc = "32-bit EL1 Support", 2567 .capability = ARM64_HAS_32BIT_EL1, 2568 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2569 .matches = has_cpuid_feature, 2570 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2571 }, 2572 { 2573 .desc = "Protected KVM", 2574 .capability = ARM64_KVM_PROTECTED_MODE, 2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2576 .matches = is_kvm_protected_mode, 2577 }, 2578 { 2579 .desc = "HCRX_EL2 register", 2580 .capability = ARM64_HAS_HCX, 2581 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2582 .matches = has_cpuid_feature, 2583 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2584 }, 2585 #endif 2586 { 2587 .desc = "Kernel page table isolation (KPTI)", 2588 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2589 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2590 .cpu_enable = cpu_enable_kpti, 2591 .matches = unmap_kernel_at_el0, 2592 /* 2593 * The ID feature fields below are used to indicate that 2594 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2595 * more details. 2596 */ 2597 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2598 }, 2599 { 2600 .capability = ARM64_HAS_FPSIMD, 2601 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2602 .matches = has_cpuid_feature, 2603 .cpu_enable = cpu_enable_fpsimd, 2604 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2605 }, 2606 #ifdef CONFIG_ARM64_PMEM 2607 { 2608 .desc = "Data cache clean to Point of Persistence", 2609 .capability = ARM64_HAS_DCPOP, 2610 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2611 .matches = has_cpuid_feature, 2612 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2613 }, 2614 { 2615 .desc = "Data cache clean to Point of Deep Persistence", 2616 .capability = ARM64_HAS_DCPODP, 2617 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2618 .matches = has_cpuid_feature, 2619 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2620 }, 2621 #endif 2622 #ifdef CONFIG_ARM64_SVE 2623 { 2624 .desc = "Scalable Vector Extension", 2625 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2626 .capability = ARM64_SVE, 2627 .cpu_enable = cpu_enable_sve, 2628 .matches = has_cpuid_feature, 2629 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2630 }, 2631 #endif /* CONFIG_ARM64_SVE */ 2632 #ifdef CONFIG_ARM64_RAS_EXTN 2633 { 2634 .desc = "RAS Extension Support", 2635 .capability = ARM64_HAS_RAS_EXTN, 2636 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2637 .matches = has_cpuid_feature, 2638 .cpu_enable = cpu_clear_disr, 2639 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2640 }, 2641 #endif /* CONFIG_ARM64_RAS_EXTN */ 2642 #ifdef CONFIG_ARM64_AMU_EXTN 2643 { 2644 .desc = "Activity Monitors Unit (AMU)", 2645 .capability = ARM64_HAS_AMU_EXTN, 2646 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2647 .matches = has_amu, 2648 .cpu_enable = cpu_amu_enable, 2649 .cpus = &amu_cpus, 2650 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2651 }, 2652 #endif /* CONFIG_ARM64_AMU_EXTN */ 2653 { 2654 .desc = "Data cache clean to the PoU not required for I/D coherence", 2655 .capability = ARM64_HAS_CACHE_IDC, 2656 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2657 .matches = has_cache_idc, 2658 .cpu_enable = cpu_emulate_effective_ctr, 2659 }, 2660 { 2661 .desc = "Instruction cache invalidation not required for I/D coherence", 2662 .capability = ARM64_HAS_CACHE_DIC, 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .matches = has_cache_dic, 2665 }, 2666 { 2667 .desc = "Stage-2 Force Write-Back", 2668 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2669 .capability = ARM64_HAS_STAGE2_FWB, 2670 .matches = has_cpuid_feature, 2671 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2672 }, 2673 { 2674 .desc = "ARMv8.4 Translation Table Level", 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .capability = ARM64_HAS_ARMv8_4_TTL, 2677 .matches = has_cpuid_feature, 2678 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2679 }, 2680 { 2681 .desc = "TLB range maintenance instructions", 2682 .capability = ARM64_HAS_TLB_RANGE, 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .matches = has_cpuid_feature, 2685 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2686 }, 2687 #ifdef CONFIG_ARM64_HW_AFDBM 2688 { 2689 .desc = "Hardware dirty bit management", 2690 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2691 .capability = ARM64_HW_DBM, 2692 .matches = has_hw_dbm, 2693 .cpu_enable = cpu_enable_hw_dbm, 2694 .cpus = &dbm_cpus, 2695 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2696 }, 2697 #endif 2698 #ifdef CONFIG_ARM64_HAFT 2699 { 2700 .desc = "Hardware managed Access Flag for Table Descriptors", 2701 /* 2702 * Contrary to the page/block access flag, the table access flag 2703 * cannot be emulated in software (no access fault will occur). 2704 * Therefore this should be used only if it's supported system 2705 * wide. 2706 */ 2707 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2708 .capability = ARM64_HAFT, 2709 .matches = has_cpuid_feature, 2710 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2711 }, 2712 #endif 2713 { 2714 .desc = "CRC32 instructions", 2715 .capability = ARM64_HAS_CRC32, 2716 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2717 .matches = has_cpuid_feature, 2718 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2719 }, 2720 { 2721 .desc = "Speculative Store Bypassing Safe (SSBS)", 2722 .capability = ARM64_SSBS, 2723 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2724 .matches = has_cpuid_feature, 2725 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2726 }, 2727 #ifdef CONFIG_ARM64_CNP 2728 { 2729 .desc = "Common not Private translations", 2730 .capability = ARM64_HAS_CNP, 2731 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2732 .matches = has_useable_cnp, 2733 .cpu_enable = cpu_enable_cnp, 2734 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2735 }, 2736 #endif 2737 { 2738 .desc = "Speculation barrier (SB)", 2739 .capability = ARM64_HAS_SB, 2740 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2741 .matches = has_cpuid_feature, 2742 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2743 }, 2744 #ifdef CONFIG_ARM64_PTR_AUTH 2745 { 2746 .desc = "Address authentication (architected QARMA5 algorithm)", 2747 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2748 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2749 .matches = has_address_auth_cpucap, 2750 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2751 }, 2752 { 2753 .desc = "Address authentication (architected QARMA3 algorithm)", 2754 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2755 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2756 .matches = has_address_auth_cpucap, 2757 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2758 }, 2759 { 2760 .desc = "Address authentication (IMP DEF algorithm)", 2761 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2762 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2763 .matches = has_address_auth_cpucap, 2764 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2765 }, 2766 { 2767 .capability = ARM64_HAS_ADDRESS_AUTH, 2768 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2769 .matches = has_address_auth_metacap, 2770 }, 2771 { 2772 .desc = "Generic authentication (architected QARMA5 algorithm)", 2773 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2774 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2775 .matches = has_cpuid_feature, 2776 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2777 }, 2778 { 2779 .desc = "Generic authentication (architected QARMA3 algorithm)", 2780 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2782 .matches = has_cpuid_feature, 2783 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2784 }, 2785 { 2786 .desc = "Generic authentication (IMP DEF algorithm)", 2787 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2789 .matches = has_cpuid_feature, 2790 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2791 }, 2792 { 2793 .capability = ARM64_HAS_GENERIC_AUTH, 2794 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2795 .matches = has_generic_auth, 2796 }, 2797 #endif /* CONFIG_ARM64_PTR_AUTH */ 2798 #ifdef CONFIG_ARM64_PSEUDO_NMI 2799 { 2800 /* 2801 * Depends on having GICv3 2802 */ 2803 .desc = "IRQ priority masking", 2804 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2805 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2806 .matches = can_use_gic_priorities, 2807 }, 2808 { 2809 /* 2810 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2811 */ 2812 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2813 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2814 .matches = has_gic_prio_relaxed_sync, 2815 }, 2816 #endif 2817 #ifdef CONFIG_ARM64_E0PD 2818 { 2819 .desc = "E0PD", 2820 .capability = ARM64_HAS_E0PD, 2821 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2822 .cpu_enable = cpu_enable_e0pd, 2823 .matches = has_cpuid_feature, 2824 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2825 }, 2826 #endif 2827 { 2828 .desc = "Random Number Generator", 2829 .capability = ARM64_HAS_RNG, 2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2831 .matches = has_cpuid_feature, 2832 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2833 }, 2834 #ifdef CONFIG_ARM64_BTI 2835 { 2836 .desc = "Branch Target Identification", 2837 .capability = ARM64_BTI, 2838 #ifdef CONFIG_ARM64_BTI_KERNEL 2839 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2840 #else 2841 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2842 #endif 2843 .matches = has_cpuid_feature, 2844 .cpu_enable = bti_enable, 2845 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2846 }, 2847 #endif 2848 #ifdef CONFIG_ARM64_MTE 2849 { 2850 .desc = "Memory Tagging Extension", 2851 .capability = ARM64_MTE, 2852 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2853 .matches = has_cpuid_feature, 2854 .cpu_enable = cpu_enable_mte, 2855 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2856 }, 2857 { 2858 .desc = "Asymmetric MTE Tag Check Fault", 2859 .capability = ARM64_MTE_ASYMM, 2860 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2861 .matches = has_cpuid_feature, 2862 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2863 }, 2864 #endif /* CONFIG_ARM64_MTE */ 2865 { 2866 .desc = "RCpc load-acquire (LDAPR)", 2867 .capability = ARM64_HAS_LDAPR, 2868 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2869 .matches = has_cpuid_feature, 2870 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2871 }, 2872 { 2873 .desc = "Fine Grained Traps", 2874 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2875 .capability = ARM64_HAS_FGT, 2876 .matches = has_cpuid_feature, 2877 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2878 }, 2879 #ifdef CONFIG_ARM64_SME 2880 { 2881 .desc = "Scalable Matrix Extension", 2882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2883 .capability = ARM64_SME, 2884 .matches = has_cpuid_feature, 2885 .cpu_enable = cpu_enable_sme, 2886 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2887 }, 2888 /* FA64 should be sorted after the base SME capability */ 2889 { 2890 .desc = "FA64", 2891 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2892 .capability = ARM64_SME_FA64, 2893 .matches = has_cpuid_feature, 2894 .cpu_enable = cpu_enable_fa64, 2895 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2896 }, 2897 { 2898 .desc = "SME2", 2899 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2900 .capability = ARM64_SME2, 2901 .matches = has_cpuid_feature, 2902 .cpu_enable = cpu_enable_sme2, 2903 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2904 }, 2905 #endif /* CONFIG_ARM64_SME */ 2906 { 2907 .desc = "WFx with timeout", 2908 .capability = ARM64_HAS_WFXT, 2909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2910 .matches = has_cpuid_feature, 2911 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2912 }, 2913 { 2914 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2915 .capability = ARM64_HAS_TIDCP1, 2916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2917 .matches = has_cpuid_feature, 2918 .cpu_enable = cpu_trap_el0_impdef, 2919 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2920 }, 2921 { 2922 .desc = "Data independent timing control (DIT)", 2923 .capability = ARM64_HAS_DIT, 2924 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2925 .matches = has_cpuid_feature, 2926 .cpu_enable = cpu_enable_dit, 2927 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2928 }, 2929 { 2930 .desc = "Memory Copy and Memory Set instructions", 2931 .capability = ARM64_HAS_MOPS, 2932 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2933 .matches = has_cpuid_feature, 2934 .cpu_enable = cpu_enable_mops, 2935 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2936 }, 2937 { 2938 .capability = ARM64_HAS_TCR2, 2939 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2940 .matches = has_cpuid_feature, 2941 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2942 }, 2943 { 2944 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2945 .capability = ARM64_HAS_S1PIE, 2946 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2947 .matches = has_cpuid_feature, 2948 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2949 }, 2950 { 2951 .desc = "VHE for hypervisor only", 2952 .capability = ARM64_KVM_HVHE, 2953 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2954 .matches = hvhe_possible, 2955 }, 2956 { 2957 .desc = "Enhanced Virtualization Traps", 2958 .capability = ARM64_HAS_EVT, 2959 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2960 .matches = has_cpuid_feature, 2961 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2962 }, 2963 { 2964 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2965 .capability = ARM64_HAS_LPA2, 2966 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2967 .matches = has_lpa2, 2968 }, 2969 { 2970 .desc = "FPMR", 2971 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2972 .capability = ARM64_HAS_FPMR, 2973 .matches = has_cpuid_feature, 2974 .cpu_enable = cpu_enable_fpmr, 2975 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2976 }, 2977 #ifdef CONFIG_ARM64_VA_BITS_52 2978 { 2979 .capability = ARM64_HAS_VA52, 2980 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2981 .matches = has_cpuid_feature, 2982 #ifdef CONFIG_ARM64_64K_PAGES 2983 .desc = "52-bit Virtual Addressing (LVA)", 2984 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2985 #else 2986 .desc = "52-bit Virtual Addressing (LPA2)", 2987 #ifdef CONFIG_ARM64_4K_PAGES 2988 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2989 #else 2990 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2991 #endif 2992 #endif 2993 }, 2994 #endif 2995 { 2996 .desc = "Memory Partitioning And Monitoring", 2997 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2998 .capability = ARM64_MPAM, 2999 .matches = test_has_mpam, 3000 .cpu_enable = cpu_enable_mpam, 3001 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3002 }, 3003 { 3004 .desc = "Memory Partitioning And Monitoring Virtualisation", 3005 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3006 .capability = ARM64_MPAM_HCR, 3007 .matches = test_has_mpam_hcr, 3008 }, 3009 { 3010 .desc = "NV1", 3011 .capability = ARM64_HAS_HCR_NV1, 3012 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3013 .matches = has_nv1, 3014 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3015 }, 3016 #ifdef CONFIG_ARM64_POE 3017 { 3018 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3019 .capability = ARM64_HAS_S1POE, 3020 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3021 .matches = has_cpuid_feature, 3022 .cpu_enable = cpu_enable_poe, 3023 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3024 }, 3025 #endif 3026 #ifdef CONFIG_ARM64_GCS 3027 { 3028 .desc = "Guarded Control Stack (GCS)", 3029 .capability = ARM64_HAS_GCS, 3030 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3031 .cpu_enable = cpu_enable_gcs, 3032 .matches = has_cpuid_feature, 3033 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3034 }, 3035 #endif 3036 #ifdef CONFIG_HW_PERF_EVENTS 3037 { 3038 .desc = "PMUv3", 3039 .capability = ARM64_HAS_PMUV3, 3040 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3041 .matches = has_pmuv3, 3042 }, 3043 #endif 3044 {}, 3045 }; 3046 3047 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3048 .matches = has_user_cpuid_feature, \ 3049 ARM64_CPUID_FIELDS(reg, field, min_value) 3050 3051 #define __HWCAP_CAP(name, cap_type, cap) \ 3052 .desc = name, \ 3053 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3054 .hwcap_type = cap_type, \ 3055 .hwcap = cap, \ 3056 3057 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3058 { \ 3059 __HWCAP_CAP(#cap, cap_type, cap) \ 3060 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3061 } 3062 3063 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3064 { \ 3065 __HWCAP_CAP(#cap, cap_type, cap) \ 3066 .matches = cpucap_multi_entry_cap_matches, \ 3067 .match_list = list, \ 3068 } 3069 3070 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3071 { \ 3072 __HWCAP_CAP(#cap, cap_type, cap) \ 3073 .matches = match, \ 3074 } 3075 3076 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3077 { \ 3078 __HWCAP_CAP(#cap, cap_type, cap) \ 3079 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3080 .matches = match, \ 3081 } 3082 3083 #ifdef CONFIG_ARM64_PTR_AUTH 3084 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3085 { 3086 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3087 }, 3088 { 3089 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3090 }, 3091 { 3092 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3093 }, 3094 {}, 3095 }; 3096 3097 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3098 { 3099 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3100 }, 3101 { 3102 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3103 }, 3104 { 3105 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3106 }, 3107 {}, 3108 }; 3109 #endif 3110 3111 #ifdef CONFIG_ARM64_SVE 3112 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3113 { 3114 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3115 } 3116 #endif 3117 3118 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3119 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3120 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3121 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3122 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3123 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3124 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3125 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3126 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3127 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3128 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3129 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3130 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3131 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3132 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3133 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3134 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3135 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3136 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3137 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3138 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3139 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3140 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3141 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3142 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3143 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3144 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3145 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3146 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3147 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3148 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3149 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3150 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3151 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3152 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3153 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3154 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3155 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3156 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3157 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3158 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3159 #ifdef CONFIG_ARM64_SVE 3160 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3161 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3162 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3163 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3164 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3165 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3166 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3167 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3168 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3169 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3170 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3171 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3172 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3173 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3174 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3175 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3176 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3177 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3178 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3179 #endif 3180 #ifdef CONFIG_ARM64_GCS 3181 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3182 #endif 3183 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3184 #ifdef CONFIG_ARM64_BTI 3185 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3186 #endif 3187 #ifdef CONFIG_ARM64_PTR_AUTH 3188 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3189 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3190 #endif 3191 #ifdef CONFIG_ARM64_MTE 3192 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3193 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3194 #endif /* CONFIG_ARM64_MTE */ 3195 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3196 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3197 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3198 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3199 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3200 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3201 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3202 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3203 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3204 #ifdef CONFIG_ARM64_SME 3205 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3206 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3207 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3208 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3209 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3210 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3211 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3212 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3213 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3214 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3215 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3216 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3217 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3218 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3219 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3220 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3221 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3222 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3223 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3224 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3225 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3226 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3227 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3228 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3229 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3230 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3231 #endif /* CONFIG_ARM64_SME */ 3232 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3233 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3234 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3235 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3236 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3237 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3238 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3239 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3240 #ifdef CONFIG_ARM64_POE 3241 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3242 #endif 3243 {}, 3244 }; 3245 3246 #ifdef CONFIG_COMPAT 3247 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3248 { 3249 /* 3250 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3251 * in line with that of arm32 as in vfp_init(). We make sure that the 3252 * check is future proof, by making sure value is non-zero. 3253 */ 3254 u32 mvfr1; 3255 3256 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3257 if (scope == SCOPE_SYSTEM) 3258 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3259 else 3260 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3261 3262 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3263 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3264 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3265 } 3266 #endif 3267 3268 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3269 #ifdef CONFIG_COMPAT 3270 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3271 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3272 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3273 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3274 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3275 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3276 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3277 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3278 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3279 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3280 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3281 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3282 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3283 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3284 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3285 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3286 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3287 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3288 #endif 3289 {}, 3290 }; 3291 3292 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3293 { 3294 switch (cap->hwcap_type) { 3295 case CAP_HWCAP: 3296 cpu_set_feature(cap->hwcap); 3297 break; 3298 #ifdef CONFIG_COMPAT 3299 case CAP_COMPAT_HWCAP: 3300 compat_elf_hwcap |= (u32)cap->hwcap; 3301 break; 3302 case CAP_COMPAT_HWCAP2: 3303 compat_elf_hwcap2 |= (u32)cap->hwcap; 3304 break; 3305 #endif 3306 default: 3307 WARN_ON(1); 3308 break; 3309 } 3310 } 3311 3312 /* Check if we have a particular HWCAP enabled */ 3313 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3314 { 3315 bool rc; 3316 3317 switch (cap->hwcap_type) { 3318 case CAP_HWCAP: 3319 rc = cpu_have_feature(cap->hwcap); 3320 break; 3321 #ifdef CONFIG_COMPAT 3322 case CAP_COMPAT_HWCAP: 3323 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3324 break; 3325 case CAP_COMPAT_HWCAP2: 3326 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3327 break; 3328 #endif 3329 default: 3330 WARN_ON(1); 3331 rc = false; 3332 } 3333 3334 return rc; 3335 } 3336 3337 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3338 { 3339 /* We support emulation of accesses to CPU ID feature registers */ 3340 cpu_set_named_feature(CPUID); 3341 for (; hwcaps->matches; hwcaps++) 3342 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3343 cap_set_elf_hwcap(hwcaps); 3344 } 3345 3346 static void update_cpu_capabilities(u16 scope_mask) 3347 { 3348 int i; 3349 const struct arm64_cpu_capabilities *caps; 3350 3351 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3352 for (i = 0; i < ARM64_NCAPS; i++) { 3353 caps = cpucap_ptrs[i]; 3354 if (!caps || !(caps->type & scope_mask) || 3355 cpus_have_cap(caps->capability) || 3356 !caps->matches(caps, cpucap_default_scope(caps))) 3357 continue; 3358 3359 if (caps->desc && !caps->cpus) 3360 pr_info("detected: %s\n", caps->desc); 3361 3362 __set_bit(caps->capability, system_cpucaps); 3363 3364 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3365 set_bit(caps->capability, boot_cpucaps); 3366 } 3367 } 3368 3369 /* 3370 * Enable all the available capabilities on this CPU. The capabilities 3371 * with BOOT_CPU scope are handled separately and hence skipped here. 3372 */ 3373 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3374 { 3375 int i; 3376 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3377 3378 for_each_available_cap(i) { 3379 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3380 3381 if (WARN_ON(!cap)) 3382 continue; 3383 3384 if (!(cap->type & non_boot_scope)) 3385 continue; 3386 3387 if (cap->cpu_enable) 3388 cap->cpu_enable(cap); 3389 } 3390 return 0; 3391 } 3392 3393 /* 3394 * Run through the enabled capabilities and enable() it on all active 3395 * CPUs 3396 */ 3397 static void __init enable_cpu_capabilities(u16 scope_mask) 3398 { 3399 int i; 3400 const struct arm64_cpu_capabilities *caps; 3401 bool boot_scope; 3402 3403 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3404 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3405 3406 for (i = 0; i < ARM64_NCAPS; i++) { 3407 caps = cpucap_ptrs[i]; 3408 if (!caps || !(caps->type & scope_mask) || 3409 !cpus_have_cap(caps->capability)) 3410 continue; 3411 3412 if (boot_scope && caps->cpu_enable) 3413 /* 3414 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3415 * before any secondary CPU boots. Thus, each secondary 3416 * will enable the capability as appropriate via 3417 * check_local_cpu_capabilities(). The only exception is 3418 * the boot CPU, for which the capability must be 3419 * enabled here. This approach avoids costly 3420 * stop_machine() calls for this case. 3421 */ 3422 caps->cpu_enable(caps); 3423 } 3424 3425 /* 3426 * For all non-boot scope capabilities, use stop_machine() 3427 * as it schedules the work allowing us to modify PSTATE, 3428 * instead of on_each_cpu() which uses an IPI, giving us a 3429 * PSTATE that disappears when we return. 3430 */ 3431 if (!boot_scope) 3432 stop_machine(cpu_enable_non_boot_scope_capabilities, 3433 NULL, cpu_online_mask); 3434 } 3435 3436 /* 3437 * Run through the list of capabilities to check for conflicts. 3438 * If the system has already detected a capability, take necessary 3439 * action on this CPU. 3440 */ 3441 static void verify_local_cpu_caps(u16 scope_mask) 3442 { 3443 int i; 3444 bool cpu_has_cap, system_has_cap; 3445 const struct arm64_cpu_capabilities *caps; 3446 3447 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3448 3449 for (i = 0; i < ARM64_NCAPS; i++) { 3450 caps = cpucap_ptrs[i]; 3451 if (!caps || !(caps->type & scope_mask)) 3452 continue; 3453 3454 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3455 system_has_cap = cpus_have_cap(caps->capability); 3456 3457 if (system_has_cap) { 3458 /* 3459 * Check if the new CPU misses an advertised feature, 3460 * which is not safe to miss. 3461 */ 3462 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3463 break; 3464 /* 3465 * We have to issue cpu_enable() irrespective of 3466 * whether the CPU has it or not, as it is enabeld 3467 * system wide. It is upto the call back to take 3468 * appropriate action on this CPU. 3469 */ 3470 if (caps->cpu_enable) 3471 caps->cpu_enable(caps); 3472 } else { 3473 /* 3474 * Check if the CPU has this capability if it isn't 3475 * safe to have when the system doesn't. 3476 */ 3477 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3478 break; 3479 } 3480 } 3481 3482 if (i < ARM64_NCAPS) { 3483 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3484 smp_processor_id(), caps->capability, 3485 caps->desc, system_has_cap, cpu_has_cap); 3486 3487 if (cpucap_panic_on_conflict(caps)) 3488 cpu_panic_kernel(); 3489 else 3490 cpu_die_early(); 3491 } 3492 } 3493 3494 /* 3495 * Check for CPU features that are used in early boot 3496 * based on the Boot CPU value. 3497 */ 3498 static void check_early_cpu_features(void) 3499 { 3500 verify_cpu_asid_bits(); 3501 3502 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3503 } 3504 3505 static void 3506 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3507 { 3508 3509 for (; caps->matches; caps++) 3510 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3511 pr_crit("CPU%d: missing HWCAP: %s\n", 3512 smp_processor_id(), caps->desc); 3513 cpu_die_early(); 3514 } 3515 } 3516 3517 static void verify_local_elf_hwcaps(void) 3518 { 3519 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3520 3521 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3522 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3523 } 3524 3525 static void verify_sve_features(void) 3526 { 3527 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3528 3529 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3530 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3531 smp_processor_id()); 3532 cpu_die_early(); 3533 } 3534 3535 cpacr_restore(cpacr); 3536 } 3537 3538 static void verify_sme_features(void) 3539 { 3540 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3541 3542 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3543 pr_crit("CPU%d: SME: vector length support mismatch\n", 3544 smp_processor_id()); 3545 cpu_die_early(); 3546 } 3547 3548 cpacr_restore(cpacr); 3549 } 3550 3551 static void verify_hyp_capabilities(void) 3552 { 3553 u64 safe_mmfr1, mmfr0, mmfr1; 3554 int parange, ipa_max; 3555 unsigned int safe_vmid_bits, vmid_bits; 3556 3557 if (!IS_ENABLED(CONFIG_KVM)) 3558 return; 3559 3560 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3561 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3562 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3563 3564 /* Verify VMID bits */ 3565 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3566 vmid_bits = get_vmid_bits(mmfr1); 3567 if (vmid_bits < safe_vmid_bits) { 3568 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3569 cpu_die_early(); 3570 } 3571 3572 /* Verify IPA range */ 3573 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3574 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3575 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3576 if (ipa_max < get_kvm_ipa_limit()) { 3577 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3578 cpu_die_early(); 3579 } 3580 } 3581 3582 static void verify_mpam_capabilities(void) 3583 { 3584 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3585 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3586 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3587 3588 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3589 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3590 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3591 cpu_die_early(); 3592 } 3593 3594 cpu_idr = read_cpuid(MPAMIDR_EL1); 3595 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3596 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3597 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3598 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3599 cpu_die_early(); 3600 } 3601 3602 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3603 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3604 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3605 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3606 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3607 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3608 cpu_die_early(); 3609 } 3610 } 3611 3612 /* 3613 * Run through the enabled system capabilities and enable() it on this CPU. 3614 * The capabilities were decided based on the available CPUs at the boot time. 3615 * Any new CPU should match the system wide status of the capability. If the 3616 * new CPU doesn't have a capability which the system now has enabled, we 3617 * cannot do anything to fix it up and could cause unexpected failures. So 3618 * we park the CPU. 3619 */ 3620 static void verify_local_cpu_capabilities(void) 3621 { 3622 /* 3623 * The capabilities with SCOPE_BOOT_CPU are checked from 3624 * check_early_cpu_features(), as they need to be verified 3625 * on all secondary CPUs. 3626 */ 3627 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3628 verify_local_elf_hwcaps(); 3629 3630 if (system_supports_sve()) 3631 verify_sve_features(); 3632 3633 if (system_supports_sme()) 3634 verify_sme_features(); 3635 3636 if (is_hyp_mode_available()) 3637 verify_hyp_capabilities(); 3638 3639 if (system_supports_mpam()) 3640 verify_mpam_capabilities(); 3641 } 3642 3643 void check_local_cpu_capabilities(void) 3644 { 3645 /* 3646 * All secondary CPUs should conform to the early CPU features 3647 * in use by the kernel based on boot CPU. 3648 */ 3649 check_early_cpu_features(); 3650 3651 /* 3652 * If we haven't finalised the system capabilities, this CPU gets 3653 * a chance to update the errata work arounds and local features. 3654 * Otherwise, this CPU should verify that it has all the system 3655 * advertised capabilities. 3656 */ 3657 if (!system_capabilities_finalized()) 3658 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3659 else 3660 verify_local_cpu_capabilities(); 3661 } 3662 3663 bool this_cpu_has_cap(unsigned int n) 3664 { 3665 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3666 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3667 3668 if (cap) 3669 return cap->matches(cap, SCOPE_LOCAL_CPU); 3670 } 3671 3672 return false; 3673 } 3674 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3675 3676 /* 3677 * This helper function is used in a narrow window when, 3678 * - The system wide safe registers are set with all the SMP CPUs and, 3679 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3680 */ 3681 static bool __maybe_unused __system_matches_cap(unsigned int n) 3682 { 3683 if (n < ARM64_NCAPS) { 3684 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3685 3686 if (cap) 3687 return cap->matches(cap, SCOPE_SYSTEM); 3688 } 3689 return false; 3690 } 3691 3692 void cpu_set_feature(unsigned int num) 3693 { 3694 set_bit(num, elf_hwcap); 3695 } 3696 3697 bool cpu_have_feature(unsigned int num) 3698 { 3699 return test_bit(num, elf_hwcap); 3700 } 3701 EXPORT_SYMBOL_GPL(cpu_have_feature); 3702 3703 unsigned long cpu_get_elf_hwcap(void) 3704 { 3705 /* 3706 * We currently only populate the first 32 bits of AT_HWCAP. Please 3707 * note that for userspace compatibility we guarantee that bits 62 3708 * and 63 will always be returned as 0. 3709 */ 3710 return elf_hwcap[0]; 3711 } 3712 3713 unsigned long cpu_get_elf_hwcap2(void) 3714 { 3715 return elf_hwcap[1]; 3716 } 3717 3718 unsigned long cpu_get_elf_hwcap3(void) 3719 { 3720 return elf_hwcap[2]; 3721 } 3722 3723 static void __init setup_boot_cpu_capabilities(void) 3724 { 3725 kvm_arm_target_impl_cpu_init(); 3726 /* 3727 * The boot CPU's feature register values have been recorded. Detect 3728 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3729 * patch alternatives for the available boot cpucaps. 3730 */ 3731 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3732 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3733 apply_boot_alternatives(); 3734 } 3735 3736 void __init setup_boot_cpu_features(void) 3737 { 3738 /* 3739 * Initialize the indirect array of CPU capabilities pointers before we 3740 * handle the boot CPU. 3741 */ 3742 init_cpucap_indirect_list(); 3743 3744 /* 3745 * Detect broken pseudo-NMI. Must be called _before_ the call to 3746 * setup_boot_cpu_capabilities() since it interacts with 3747 * can_use_gic_priorities(). 3748 */ 3749 detect_system_supports_pseudo_nmi(); 3750 3751 setup_boot_cpu_capabilities(); 3752 } 3753 3754 static void __init setup_system_capabilities(void) 3755 { 3756 /* 3757 * The system-wide safe feature register values have been finalized. 3758 * Detect, enable, and patch alternatives for the available system 3759 * cpucaps. 3760 */ 3761 update_cpu_capabilities(SCOPE_SYSTEM); 3762 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3763 apply_alternatives_all(); 3764 3765 /* 3766 * Log any cpucaps with a cpumask as these aren't logged by 3767 * update_cpu_capabilities(). 3768 */ 3769 for (int i = 0; i < ARM64_NCAPS; i++) { 3770 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3771 3772 if (caps && caps->cpus && caps->desc && 3773 cpumask_any(caps->cpus) < nr_cpu_ids) 3774 pr_info("detected: %s on CPU%*pbl\n", 3775 caps->desc, cpumask_pr_args(caps->cpus)); 3776 } 3777 3778 /* 3779 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3780 */ 3781 if (system_uses_ttbr0_pan()) 3782 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3783 } 3784 3785 void __init setup_system_features(void) 3786 { 3787 setup_system_capabilities(); 3788 3789 kpti_install_ng_mappings(); 3790 3791 sve_setup(); 3792 sme_setup(); 3793 3794 /* 3795 * Check for sane CTR_EL0.CWG value. 3796 */ 3797 if (!cache_type_cwg()) 3798 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3799 ARCH_DMA_MINALIGN); 3800 } 3801 3802 void __init setup_user_features(void) 3803 { 3804 user_feature_fixup(); 3805 3806 setup_elf_hwcaps(arm64_elf_hwcaps); 3807 3808 if (system_supports_32bit_el0()) { 3809 setup_elf_hwcaps(compat_elf_hwcaps); 3810 elf_hwcap_fixup(); 3811 } 3812 3813 minsigstksz_setup(); 3814 } 3815 3816 static int enable_mismatched_32bit_el0(unsigned int cpu) 3817 { 3818 /* 3819 * The first 32-bit-capable CPU we detected and so can no longer 3820 * be offlined by userspace. -1 indicates we haven't yet onlined 3821 * a 32-bit-capable CPU. 3822 */ 3823 static int lucky_winner = -1; 3824 3825 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3826 bool cpu_32bit = false; 3827 3828 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3829 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3830 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3831 else 3832 cpu_32bit = true; 3833 } 3834 3835 if (cpu_32bit) { 3836 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3837 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3838 } 3839 3840 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3841 return 0; 3842 3843 if (lucky_winner >= 0) 3844 return 0; 3845 3846 /* 3847 * We've detected a mismatch. We need to keep one of our CPUs with 3848 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3849 * every CPU in the system for a 32-bit task. 3850 */ 3851 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3852 cpu_active_mask); 3853 get_cpu_device(lucky_winner)->offline_disabled = true; 3854 setup_elf_hwcaps(compat_elf_hwcaps); 3855 elf_hwcap_fixup(); 3856 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3857 cpu, lucky_winner); 3858 return 0; 3859 } 3860 3861 static int __init init_32bit_el0_mask(void) 3862 { 3863 if (!allow_mismatched_32bit_el0) 3864 return 0; 3865 3866 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3867 return -ENOMEM; 3868 3869 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3870 "arm64/mismatched_32bit_el0:online", 3871 enable_mismatched_32bit_el0, NULL); 3872 } 3873 subsys_initcall_sync(init_32bit_el0_mask); 3874 3875 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3876 { 3877 cpu_enable_swapper_cnp(); 3878 } 3879 3880 /* 3881 * We emulate only the following system register space. 3882 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3883 * See Table C5-6 System instruction encodings for System register accesses, 3884 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3885 */ 3886 static inline bool __attribute_const__ is_emulated(u32 id) 3887 { 3888 return (sys_reg_Op0(id) == 0x3 && 3889 sys_reg_CRn(id) == 0x0 && 3890 sys_reg_Op1(id) == 0x0 && 3891 (sys_reg_CRm(id) == 0 || 3892 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3893 } 3894 3895 /* 3896 * With CRm == 0, reg should be one of : 3897 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3898 */ 3899 static inline int emulate_id_reg(u32 id, u64 *valp) 3900 { 3901 switch (id) { 3902 case SYS_MIDR_EL1: 3903 *valp = read_cpuid_id(); 3904 break; 3905 case SYS_MPIDR_EL1: 3906 *valp = SYS_MPIDR_SAFE_VAL; 3907 break; 3908 case SYS_REVIDR_EL1: 3909 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3910 *valp = 0; 3911 break; 3912 default: 3913 return -EINVAL; 3914 } 3915 3916 return 0; 3917 } 3918 3919 static int emulate_sys_reg(u32 id, u64 *valp) 3920 { 3921 struct arm64_ftr_reg *regp; 3922 3923 if (!is_emulated(id)) 3924 return -EINVAL; 3925 3926 if (sys_reg_CRm(id) == 0) 3927 return emulate_id_reg(id, valp); 3928 3929 regp = get_arm64_ftr_reg_nowarn(id); 3930 if (regp) 3931 *valp = arm64_ftr_reg_user_value(regp); 3932 else 3933 /* 3934 * The untracked registers are either IMPLEMENTATION DEFINED 3935 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3936 */ 3937 *valp = 0; 3938 return 0; 3939 } 3940 3941 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3942 { 3943 int rc; 3944 u64 val; 3945 3946 rc = emulate_sys_reg(sys_reg, &val); 3947 if (!rc) { 3948 pt_regs_write_reg(regs, rt, val); 3949 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3950 } 3951 return rc; 3952 } 3953 3954 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3955 { 3956 u32 sys_reg, rt; 3957 3958 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3959 return false; 3960 3961 /* 3962 * sys_reg values are defined as used in mrs/msr instruction. 3963 * shift the imm value to get the encoding. 3964 */ 3965 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3966 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3967 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3968 } 3969 3970 enum mitigation_state arm64_get_meltdown_state(void) 3971 { 3972 if (__meltdown_safe) 3973 return SPECTRE_UNAFFECTED; 3974 3975 if (arm64_kernel_unmapped_at_el0()) 3976 return SPECTRE_MITIGATED; 3977 3978 return SPECTRE_VULNERABLE; 3979 } 3980 3981 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3982 char *buf) 3983 { 3984 switch (arm64_get_meltdown_state()) { 3985 case SPECTRE_UNAFFECTED: 3986 return sprintf(buf, "Not affected\n"); 3987 3988 case SPECTRE_MITIGATED: 3989 return sprintf(buf, "Mitigation: PTI\n"); 3990 3991 default: 3992 return sprintf(buf, "Vulnerable\n"); 3993 } 3994 } 3995