1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 #endif 107 108 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 109 EXPORT_SYMBOL(system_cpucaps); 110 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 111 112 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 113 114 bool arm64_use_ng_mappings = false; 115 EXPORT_SYMBOL(arm64_use_ng_mappings); 116 117 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 118 119 /* 120 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 121 * support it? 122 */ 123 static bool __read_mostly allow_mismatched_32bit_el0; 124 125 /* 126 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 127 * seen at least one CPU capable of 32-bit EL0. 128 */ 129 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 130 131 /* 132 * Mask of CPUs supporting 32-bit EL0. 133 * Only valid if arm64_mismatched_32bit_el0 is enabled. 134 */ 135 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 136 137 void dump_cpu_features(void) 138 { 139 /* file-wide pr_fmt adds "CPU features: " prefix */ 140 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 141 } 142 143 #define __ARM64_MAX_POSITIVE(reg, field) \ 144 ((reg##_##field##_SIGNED ? \ 145 BIT(reg##_##field##_WIDTH - 1) : \ 146 BIT(reg##_##field##_WIDTH)) - 1) 147 148 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 149 150 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 151 .sys_reg = SYS_##reg, \ 152 .field_pos = reg##_##field##_SHIFT, \ 153 .field_width = reg##_##field##_WIDTH, \ 154 .sign = reg##_##field##_SIGNED, \ 155 .min_field_value = min_value, \ 156 .max_field_value = max_value, 157 158 /* 159 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 160 * an implicit maximum that depends on the sign-ess of the field. 161 * 162 * An unsigned field will be capped at all ones, while a signed field 163 * will be limited to the positive half only. 164 */ 165 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 166 __ARM64_CPUID_FIELDS(reg, field, \ 167 SYS_FIELD_VALUE(reg, field, min_value), \ 168 __ARM64_MAX_POSITIVE(reg, field)) 169 170 /* 171 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 172 * implicit minimal value to max_value. This should be used when 173 * matching a non-implemented property. 174 */ 175 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 176 __ARM64_CPUID_FIELDS(reg, field, \ 177 __ARM64_MIN_NEGATIVE(reg, field), \ 178 SYS_FIELD_VALUE(reg, field, max_value)) 179 180 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 181 { \ 182 .sign = SIGNED, \ 183 .visible = VISIBLE, \ 184 .strict = STRICT, \ 185 .type = TYPE, \ 186 .shift = SHIFT, \ 187 .width = WIDTH, \ 188 .safe_val = SAFE_VAL, \ 189 } 190 191 /* Define a feature with unsigned values */ 192 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 193 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 194 195 /* Define a feature with a signed value */ 196 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 197 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 198 199 #define ARM64_FTR_END \ 200 { \ 201 .width = 0, \ 202 } 203 204 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 205 206 static bool __system_matches_cap(unsigned int n); 207 208 /* 209 * NOTE: Any changes to the visibility of features should be kept in 210 * sync with the documentation of the CPU feature register ABI. 211 */ 212 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 227 ARM64_FTR_END, 228 }; 229 230 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 238 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 245 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 249 ARM64_FTR_END, 250 }; 251 252 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 260 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 270 ARM64_FTR_END, 271 }; 272 273 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 281 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 284 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 285 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 290 ARM64_FTR_END, 291 }; 292 293 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 295 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 300 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 301 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 302 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 303 ARM64_FTR_END, 304 }; 305 306 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 307 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 308 ARM64_FTR_END, 309 }; 310 311 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 313 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 332 ARM64_FTR_END, 333 }; 334 335 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 337 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 339 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 343 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 345 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 372 ARM64_FTR_END, 373 }; 374 375 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 376 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 382 ARM64_FTR_END, 383 }; 384 385 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 386 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 389 /* 390 * Page size not being supported at Stage-2 is not fatal. You 391 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 392 * your favourite nesting hypervisor. 393 * 394 * There is a small corner case where the hypervisor explicitly 395 * advertises a given granule size at Stage-2 (value 2) on some 396 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 397 * vCPUs. Although this is not forbidden by the architecture, it 398 * indicates that the hypervisor is being silly (or buggy). 399 * 400 * We make no effort to cope with this and pretend that if these 401 * fields are inconsistent across vCPUs, then it isn't worth 402 * trying to bring KVM up. 403 */ 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 407 /* 408 * We already refuse to boot CPUs that don't support our configured 409 * page size, so we can only detect mismatches for a page size other 410 * than the one we're currently using. Unfortunately, SoCs like this 411 * exist in the wild so, even though we don't like it, we'll have to go 412 * along with it and treat them as non-strict. 413 */ 414 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 415 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 417 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 419 /* Linux shouldn't care about secure memory */ 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 423 /* 424 * Differing PARange is fine as long as all peripherals and memory are mapped 425 * within the minimum PARange of all CPUs 426 */ 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 428 ARM64_FTR_END, 429 }; 430 431 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 446 ARM64_FTR_END, 447 }; 448 449 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 465 ARM64_FTR_END, 466 }; 467 468 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 469 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 470 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 473 ARM64_FTR_END, 474 }; 475 476 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 477 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_ctr[] = { 482 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 483 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 484 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 485 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 488 /* 489 * Linux can handle differing I-cache policies. Userspace JITs will 490 * make use of *minLine. 491 * If we have differing I-cache policies, report it as the weakest - VIPT. 492 */ 493 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 494 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 495 ARM64_FTR_END, 496 }; 497 498 static struct arm64_ftr_override __ro_after_init no_override = { }; 499 500 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 501 .name = "SYS_CTR_EL0", 502 .ftr_bits = ftr_ctr, 503 .override = &no_override, 504 }; 505 506 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 507 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 515 ARM64_FTR_END, 516 }; 517 518 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 519 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 524 /* 525 * We can instantiate multiple PMU instances with different levels 526 * of support. 527 */ 528 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 530 ARM64_FTR_END, 531 }; 532 533 static const struct arm64_ftr_bits ftr_mvfr0[] = { 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 542 ARM64_FTR_END, 543 }; 544 545 static const struct arm64_ftr_bits ftr_mvfr1[] = { 546 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 554 ARM64_FTR_END, 555 }; 556 557 static const struct arm64_ftr_bits ftr_mvfr2[] = { 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 560 ARM64_FTR_END, 561 }; 562 563 static const struct arm64_ftr_bits ftr_dczid[] = { 564 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 565 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 566 ARM64_FTR_END, 567 }; 568 569 static const struct arm64_ftr_bits ftr_gmid[] = { 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 571 ARM64_FTR_END, 572 }; 573 574 static const struct arm64_ftr_bits ftr_id_isar0[] = { 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 582 ARM64_FTR_END, 583 }; 584 585 static const struct arm64_ftr_bits ftr_id_isar5[] = { 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 592 ARM64_FTR_END, 593 }; 594 595 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 603 604 /* 605 * SpecSEI = 1 indicates that the PE might generate an SError on an 606 * external abort on speculative read. It is safe to assume that an 607 * SError might be generated than it will not be. Hence it has been 608 * classified as FTR_HIGHER_SAFE. 609 */ 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 611 ARM64_FTR_END, 612 }; 613 614 static const struct arm64_ftr_bits ftr_id_isar4[] = { 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 623 ARM64_FTR_END, 624 }; 625 626 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 628 ARM64_FTR_END, 629 }; 630 631 static const struct arm64_ftr_bits ftr_id_isar6[] = { 632 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 639 ARM64_FTR_END, 640 }; 641 642 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 649 ARM64_FTR_END, 650 }; 651 652 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 661 ARM64_FTR_END, 662 }; 663 664 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 665 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 667 ARM64_FTR_END, 668 }; 669 670 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 671 /* [31:28] TraceFilt */ 672 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 679 ARM64_FTR_END, 680 }; 681 682 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 683 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 684 ARM64_FTR_END, 685 }; 686 687 /* 688 * Common ftr bits for a 32bit register with all hidden, strict 689 * attributes, with 4bit feature fields and a default safe value of 690 * 0. Covers the following 32bit registers: 691 * id_isar[1-3], id_mmfr[1-3] 692 */ 693 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 702 ARM64_FTR_END, 703 }; 704 705 /* Table for a single 32bit feature value */ 706 static const struct arm64_ftr_bits ftr_single32[] = { 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 708 ARM64_FTR_END, 709 }; 710 711 static const struct arm64_ftr_bits ftr_raz[] = { 712 ARM64_FTR_END, 713 }; 714 715 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 716 .sys_id = id, \ 717 .reg = &(struct arm64_ftr_reg){ \ 718 .name = id_str, \ 719 .override = (ovr), \ 720 .ftr_bits = &((table)[0]), \ 721 }} 722 723 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 724 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 725 726 #define ARM64_FTR_REG(id, table) \ 727 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 728 729 struct arm64_ftr_override id_aa64mmfr0_override; 730 struct arm64_ftr_override id_aa64mmfr1_override; 731 struct arm64_ftr_override id_aa64mmfr2_override; 732 struct arm64_ftr_override id_aa64pfr0_override; 733 struct arm64_ftr_override id_aa64pfr1_override; 734 struct arm64_ftr_override id_aa64zfr0_override; 735 struct arm64_ftr_override id_aa64smfr0_override; 736 struct arm64_ftr_override id_aa64isar1_override; 737 struct arm64_ftr_override id_aa64isar2_override; 738 739 struct arm64_ftr_override arm64_sw_feature_override; 740 741 static const struct __ftr_reg_entry { 742 u32 sys_id; 743 struct arm64_ftr_reg *reg; 744 } arm64_ftr_regs[] = { 745 746 /* Op1 = 0, CRn = 0, CRm = 1 */ 747 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 748 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 749 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 750 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 751 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 752 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 753 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 754 755 /* Op1 = 0, CRn = 0, CRm = 2 */ 756 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 757 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 758 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 759 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 760 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 761 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 762 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 763 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 764 765 /* Op1 = 0, CRn = 0, CRm = 3 */ 766 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 767 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 768 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 769 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 770 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 771 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 772 773 /* Op1 = 0, CRn = 0, CRm = 4 */ 774 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 775 &id_aa64pfr0_override), 776 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 777 &id_aa64pfr1_override), 778 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 779 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 780 &id_aa64zfr0_override), 781 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 782 &id_aa64smfr0_override), 783 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 784 785 /* Op1 = 0, CRn = 0, CRm = 5 */ 786 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 787 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 788 789 /* Op1 = 0, CRn = 0, CRm = 6 */ 790 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 791 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 792 &id_aa64isar1_override), 793 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 794 &id_aa64isar2_override), 795 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 796 797 /* Op1 = 0, CRn = 0, CRm = 7 */ 798 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 799 &id_aa64mmfr0_override), 800 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 801 &id_aa64mmfr1_override), 802 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 803 &id_aa64mmfr2_override), 804 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 805 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 806 807 /* Op1 = 1, CRn = 0, CRm = 0 */ 808 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 809 810 /* Op1 = 3, CRn = 0, CRm = 0 */ 811 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 812 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 813 814 /* Op1 = 3, CRn = 14, CRm = 0 */ 815 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 816 }; 817 818 static int search_cmp_ftr_reg(const void *id, const void *regp) 819 { 820 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 821 } 822 823 /* 824 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 825 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 826 * ascending order of sys_id, we use binary search to find a matching 827 * entry. 828 * 829 * returns - Upon success, matching ftr_reg entry for id. 830 * - NULL on failure. It is upto the caller to decide 831 * the impact of a failure. 832 */ 833 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 834 { 835 const struct __ftr_reg_entry *ret; 836 837 ret = bsearch((const void *)(unsigned long)sys_id, 838 arm64_ftr_regs, 839 ARRAY_SIZE(arm64_ftr_regs), 840 sizeof(arm64_ftr_regs[0]), 841 search_cmp_ftr_reg); 842 if (ret) 843 return ret->reg; 844 return NULL; 845 } 846 847 /* 848 * get_arm64_ftr_reg - Looks up a feature register entry using 849 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 850 * 851 * returns - Upon success, matching ftr_reg entry for id. 852 * - NULL on failure but with an WARN_ON(). 853 */ 854 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 855 { 856 struct arm64_ftr_reg *reg; 857 858 reg = get_arm64_ftr_reg_nowarn(sys_id); 859 860 /* 861 * Requesting a non-existent register search is an error. Warn 862 * and let the caller handle it. 863 */ 864 WARN_ON(!reg); 865 return reg; 866 } 867 868 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 869 s64 ftr_val) 870 { 871 u64 mask = arm64_ftr_mask(ftrp); 872 873 reg &= ~mask; 874 reg |= (ftr_val << ftrp->shift) & mask; 875 return reg; 876 } 877 878 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 879 s64 cur) 880 { 881 s64 ret = 0; 882 883 switch (ftrp->type) { 884 case FTR_EXACT: 885 ret = ftrp->safe_val; 886 break; 887 case FTR_LOWER_SAFE: 888 ret = min(new, cur); 889 break; 890 case FTR_HIGHER_OR_ZERO_SAFE: 891 if (!cur || !new) 892 break; 893 fallthrough; 894 case FTR_HIGHER_SAFE: 895 ret = max(new, cur); 896 break; 897 default: 898 BUG(); 899 } 900 901 return ret; 902 } 903 904 static void __init sort_ftr_regs(void) 905 { 906 unsigned int i; 907 908 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 909 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 910 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 911 unsigned int j = 0; 912 913 /* 914 * Features here must be sorted in descending order with respect 915 * to their shift values and should not overlap with each other. 916 */ 917 for (; ftr_bits->width != 0; ftr_bits++, j++) { 918 unsigned int width = ftr_reg->ftr_bits[j].width; 919 unsigned int shift = ftr_reg->ftr_bits[j].shift; 920 unsigned int prev_shift; 921 922 WARN((shift + width) > 64, 923 "%s has invalid feature at shift %d\n", 924 ftr_reg->name, shift); 925 926 /* 927 * Skip the first feature. There is nothing to 928 * compare against for now. 929 */ 930 if (j == 0) 931 continue; 932 933 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 934 WARN((shift + width) > prev_shift, 935 "%s has feature overlap at shift %d\n", 936 ftr_reg->name, shift); 937 } 938 939 /* 940 * Skip the first register. There is nothing to 941 * compare against for now. 942 */ 943 if (i == 0) 944 continue; 945 /* 946 * Registers here must be sorted in ascending order with respect 947 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 948 * to work correctly. 949 */ 950 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 951 } 952 } 953 954 /* 955 * Initialise the CPU feature register from Boot CPU values. 956 * Also initiliases the strict_mask for the register. 957 * Any bits that are not covered by an arm64_ftr_bits entry are considered 958 * RES0 for the system-wide value, and must strictly match. 959 */ 960 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 961 { 962 u64 val = 0; 963 u64 strict_mask = ~0x0ULL; 964 u64 user_mask = 0; 965 u64 valid_mask = 0; 966 967 const struct arm64_ftr_bits *ftrp; 968 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 969 970 if (!reg) 971 return; 972 973 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 974 u64 ftr_mask = arm64_ftr_mask(ftrp); 975 s64 ftr_new = arm64_ftr_value(ftrp, new); 976 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 977 978 if ((ftr_mask & reg->override->mask) == ftr_mask) { 979 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 980 char *str = NULL; 981 982 if (ftr_ovr != tmp) { 983 /* Unsafe, remove the override */ 984 reg->override->mask &= ~ftr_mask; 985 reg->override->val &= ~ftr_mask; 986 tmp = ftr_ovr; 987 str = "ignoring override"; 988 } else if (ftr_new != tmp) { 989 /* Override was valid */ 990 ftr_new = tmp; 991 str = "forced"; 992 } else if (ftr_ovr == tmp) { 993 /* Override was the safe value */ 994 str = "already set"; 995 } 996 997 if (str) 998 pr_warn("%s[%d:%d]: %s to %llx\n", 999 reg->name, 1000 ftrp->shift + ftrp->width - 1, 1001 ftrp->shift, str, 1002 tmp & (BIT(ftrp->width) - 1)); 1003 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1004 reg->override->val &= ~ftr_mask; 1005 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1006 reg->name, 1007 ftrp->shift + ftrp->width - 1, 1008 ftrp->shift); 1009 } 1010 1011 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1012 1013 valid_mask |= ftr_mask; 1014 if (!ftrp->strict) 1015 strict_mask &= ~ftr_mask; 1016 if (ftrp->visible) 1017 user_mask |= ftr_mask; 1018 else 1019 reg->user_val = arm64_ftr_set_value(ftrp, 1020 reg->user_val, 1021 ftrp->safe_val); 1022 } 1023 1024 val &= valid_mask; 1025 1026 reg->sys_val = val; 1027 reg->strict_mask = strict_mask; 1028 reg->user_mask = user_mask; 1029 } 1030 1031 extern const struct arm64_cpu_capabilities arm64_errata[]; 1032 static const struct arm64_cpu_capabilities arm64_features[]; 1033 1034 static void __init 1035 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1036 { 1037 for (; caps->matches; caps++) { 1038 if (WARN(caps->capability >= ARM64_NCAPS, 1039 "Invalid capability %d\n", caps->capability)) 1040 continue; 1041 if (WARN(cpucap_ptrs[caps->capability], 1042 "Duplicate entry for capability %d\n", 1043 caps->capability)) 1044 continue; 1045 cpucap_ptrs[caps->capability] = caps; 1046 } 1047 } 1048 1049 static void __init init_cpucap_indirect_list(void) 1050 { 1051 init_cpucap_indirect_list_from_array(arm64_features); 1052 init_cpucap_indirect_list_from_array(arm64_errata); 1053 } 1054 1055 static void __init setup_boot_cpu_capabilities(void); 1056 1057 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1058 { 1059 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1060 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1061 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1062 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1063 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1064 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1065 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1066 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1067 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1068 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1069 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1070 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1071 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1072 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1073 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1074 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1075 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1076 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1077 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1078 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1079 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1080 } 1081 1082 #ifdef CONFIG_ARM64_PSEUDO_NMI 1083 static bool enable_pseudo_nmi; 1084 1085 static int __init early_enable_pseudo_nmi(char *p) 1086 { 1087 return kstrtobool(p, &enable_pseudo_nmi); 1088 } 1089 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1090 1091 static __init void detect_system_supports_pseudo_nmi(void) 1092 { 1093 struct device_node *np; 1094 1095 if (!enable_pseudo_nmi) 1096 return; 1097 1098 /* 1099 * Detect broken MediaTek firmware that doesn't properly save and 1100 * restore GIC priorities. 1101 */ 1102 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1103 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1104 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1105 enable_pseudo_nmi = false; 1106 } 1107 of_node_put(np); 1108 } 1109 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1110 static inline void detect_system_supports_pseudo_nmi(void) { } 1111 #endif 1112 1113 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1114 { 1115 /* Before we start using the tables, make sure it is sorted */ 1116 sort_ftr_regs(); 1117 1118 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1119 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1120 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1121 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1122 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1123 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1124 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1125 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1126 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1127 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1128 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1129 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1130 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1131 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1132 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1133 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1134 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1135 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1136 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1137 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1138 1139 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1140 init_32bit_cpu_features(&info->aarch32); 1141 1142 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1143 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1144 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1145 1146 vec_init_vq_map(ARM64_VEC_SVE); 1147 1148 cpacr_restore(cpacr); 1149 } 1150 1151 if (IS_ENABLED(CONFIG_ARM64_SME) && 1152 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1153 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1154 1155 /* 1156 * We mask out SMPS since even if the hardware 1157 * supports priorities the kernel does not at present 1158 * and we block access to them. 1159 */ 1160 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1161 vec_init_vq_map(ARM64_VEC_SME); 1162 1163 cpacr_restore(cpacr); 1164 } 1165 1166 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1167 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1168 } 1169 1170 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1171 { 1172 const struct arm64_ftr_bits *ftrp; 1173 1174 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1175 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1176 s64 ftr_new = arm64_ftr_value(ftrp, new); 1177 1178 if (ftr_cur == ftr_new) 1179 continue; 1180 /* Find a safe value */ 1181 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1182 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1183 } 1184 1185 } 1186 1187 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1188 { 1189 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1190 1191 if (!regp) 1192 return 0; 1193 1194 update_cpu_ftr_reg(regp, val); 1195 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1196 return 0; 1197 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1198 regp->name, boot, cpu, val); 1199 return 1; 1200 } 1201 1202 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1203 { 1204 const struct arm64_ftr_bits *ftrp; 1205 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1206 1207 if (!regp) 1208 return; 1209 1210 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1211 if (ftrp->shift == field) { 1212 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1213 break; 1214 } 1215 } 1216 1217 /* Bogus field? */ 1218 WARN_ON(!ftrp->width); 1219 } 1220 1221 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1222 struct cpuinfo_arm64 *boot) 1223 { 1224 static bool boot_cpu_32bit_regs_overridden = false; 1225 1226 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1227 return; 1228 1229 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1230 return; 1231 1232 boot->aarch32 = info->aarch32; 1233 init_32bit_cpu_features(&boot->aarch32); 1234 boot_cpu_32bit_regs_overridden = true; 1235 } 1236 1237 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1238 struct cpuinfo_32bit *boot) 1239 { 1240 int taint = 0; 1241 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1242 1243 /* 1244 * If we don't have AArch32 at EL1, then relax the strictness of 1245 * EL1-dependent register fields to avoid spurious sanity check fails. 1246 */ 1247 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1248 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1249 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1250 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1251 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1252 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1253 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1254 } 1255 1256 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1257 info->reg_id_dfr0, boot->reg_id_dfr0); 1258 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1259 info->reg_id_dfr1, boot->reg_id_dfr1); 1260 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1261 info->reg_id_isar0, boot->reg_id_isar0); 1262 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1263 info->reg_id_isar1, boot->reg_id_isar1); 1264 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1265 info->reg_id_isar2, boot->reg_id_isar2); 1266 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1267 info->reg_id_isar3, boot->reg_id_isar3); 1268 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1269 info->reg_id_isar4, boot->reg_id_isar4); 1270 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1271 info->reg_id_isar5, boot->reg_id_isar5); 1272 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1273 info->reg_id_isar6, boot->reg_id_isar6); 1274 1275 /* 1276 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1277 * ACTLR formats could differ across CPUs and therefore would have to 1278 * be trapped for virtualization anyway. 1279 */ 1280 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1281 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1282 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1283 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1284 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1285 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1286 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1287 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1288 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1289 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1290 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1291 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1292 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1293 info->reg_id_pfr0, boot->reg_id_pfr0); 1294 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1295 info->reg_id_pfr1, boot->reg_id_pfr1); 1296 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1297 info->reg_id_pfr2, boot->reg_id_pfr2); 1298 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1299 info->reg_mvfr0, boot->reg_mvfr0); 1300 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1301 info->reg_mvfr1, boot->reg_mvfr1); 1302 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1303 info->reg_mvfr2, boot->reg_mvfr2); 1304 1305 return taint; 1306 } 1307 1308 /* 1309 * Update system wide CPU feature registers with the values from a 1310 * non-boot CPU. Also performs SANITY checks to make sure that there 1311 * aren't any insane variations from that of the boot CPU. 1312 */ 1313 void update_cpu_features(int cpu, 1314 struct cpuinfo_arm64 *info, 1315 struct cpuinfo_arm64 *boot) 1316 { 1317 int taint = 0; 1318 1319 /* 1320 * The kernel can handle differing I-cache policies, but otherwise 1321 * caches should look identical. Userspace JITs will make use of 1322 * *minLine. 1323 */ 1324 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1325 info->reg_ctr, boot->reg_ctr); 1326 1327 /* 1328 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1329 * could result in too much or too little memory being zeroed if a 1330 * process is preempted and migrated between CPUs. 1331 */ 1332 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1333 info->reg_dczid, boot->reg_dczid); 1334 1335 /* If different, timekeeping will be broken (especially with KVM) */ 1336 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1337 info->reg_cntfrq, boot->reg_cntfrq); 1338 1339 /* 1340 * The kernel uses self-hosted debug features and expects CPUs to 1341 * support identical debug features. We presently need CTX_CMPs, WRPs, 1342 * and BRPs to be identical. 1343 * ID_AA64DFR1 is currently RES0. 1344 */ 1345 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1346 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1347 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1348 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1349 /* 1350 * Even in big.LITTLE, processors should be identical instruction-set 1351 * wise. 1352 */ 1353 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1354 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1355 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1356 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1357 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1358 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1359 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1360 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1361 1362 /* 1363 * Differing PARange support is fine as long as all peripherals and 1364 * memory are mapped within the minimum PARange of all CPUs. 1365 * Linux should not care about secure memory. 1366 */ 1367 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1368 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1369 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1370 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1371 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1372 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1373 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1374 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1375 1376 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1377 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1378 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1379 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1380 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1381 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1382 1383 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1384 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1385 1386 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1387 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1388 1389 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1390 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1391 1392 /* Probe vector lengths */ 1393 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1394 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1395 if (!system_capabilities_finalized()) { 1396 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1397 1398 vec_update_vq_map(ARM64_VEC_SVE); 1399 1400 cpacr_restore(cpacr); 1401 } 1402 } 1403 1404 if (IS_ENABLED(CONFIG_ARM64_SME) && 1405 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1406 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1407 1408 /* 1409 * We mask out SMPS since even if the hardware 1410 * supports priorities the kernel does not at present 1411 * and we block access to them. 1412 */ 1413 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1414 1415 /* Probe vector lengths */ 1416 if (!system_capabilities_finalized()) 1417 vec_update_vq_map(ARM64_VEC_SME); 1418 1419 cpacr_restore(cpacr); 1420 } 1421 1422 /* 1423 * The kernel uses the LDGM/STGM instructions and the number of tags 1424 * they read/write depends on the GMID_EL1.BS field. Check that the 1425 * value is the same on all CPUs. 1426 */ 1427 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1428 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1429 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1430 info->reg_gmid, boot->reg_gmid); 1431 } 1432 1433 /* 1434 * If we don't have AArch32 at all then skip the checks entirely 1435 * as the register values may be UNKNOWN and we're not going to be 1436 * using them for anything. 1437 * 1438 * This relies on a sanitised view of the AArch64 ID registers 1439 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1440 */ 1441 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1442 lazy_init_32bit_cpu_features(info, boot); 1443 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1444 &boot->aarch32); 1445 } 1446 1447 /* 1448 * Mismatched CPU features are a recipe for disaster. Don't even 1449 * pretend to support them. 1450 */ 1451 if (taint) { 1452 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1453 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1454 } 1455 } 1456 1457 u64 read_sanitised_ftr_reg(u32 id) 1458 { 1459 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1460 1461 if (!regp) 1462 return 0; 1463 return regp->sys_val; 1464 } 1465 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1466 1467 #define read_sysreg_case(r) \ 1468 case r: val = read_sysreg_s(r); break; 1469 1470 /* 1471 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1472 * Read the system register on the current CPU 1473 */ 1474 u64 __read_sysreg_by_encoding(u32 sys_id) 1475 { 1476 struct arm64_ftr_reg *regp; 1477 u64 val; 1478 1479 switch (sys_id) { 1480 read_sysreg_case(SYS_ID_PFR0_EL1); 1481 read_sysreg_case(SYS_ID_PFR1_EL1); 1482 read_sysreg_case(SYS_ID_PFR2_EL1); 1483 read_sysreg_case(SYS_ID_DFR0_EL1); 1484 read_sysreg_case(SYS_ID_DFR1_EL1); 1485 read_sysreg_case(SYS_ID_MMFR0_EL1); 1486 read_sysreg_case(SYS_ID_MMFR1_EL1); 1487 read_sysreg_case(SYS_ID_MMFR2_EL1); 1488 read_sysreg_case(SYS_ID_MMFR3_EL1); 1489 read_sysreg_case(SYS_ID_MMFR4_EL1); 1490 read_sysreg_case(SYS_ID_MMFR5_EL1); 1491 read_sysreg_case(SYS_ID_ISAR0_EL1); 1492 read_sysreg_case(SYS_ID_ISAR1_EL1); 1493 read_sysreg_case(SYS_ID_ISAR2_EL1); 1494 read_sysreg_case(SYS_ID_ISAR3_EL1); 1495 read_sysreg_case(SYS_ID_ISAR4_EL1); 1496 read_sysreg_case(SYS_ID_ISAR5_EL1); 1497 read_sysreg_case(SYS_ID_ISAR6_EL1); 1498 read_sysreg_case(SYS_MVFR0_EL1); 1499 read_sysreg_case(SYS_MVFR1_EL1); 1500 read_sysreg_case(SYS_MVFR2_EL1); 1501 1502 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1503 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1504 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1505 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1506 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1507 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1508 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1509 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1510 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1511 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1512 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1513 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1514 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1515 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1516 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1517 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1518 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1519 1520 read_sysreg_case(SYS_CNTFRQ_EL0); 1521 read_sysreg_case(SYS_CTR_EL0); 1522 read_sysreg_case(SYS_DCZID_EL0); 1523 1524 default: 1525 BUG(); 1526 return 0; 1527 } 1528 1529 regp = get_arm64_ftr_reg(sys_id); 1530 if (regp) { 1531 val &= ~regp->override->mask; 1532 val |= (regp->override->val & regp->override->mask); 1533 } 1534 1535 return val; 1536 } 1537 1538 #include <linux/irqchip/arm-gic-v3.h> 1539 1540 static bool 1541 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1542 { 1543 return true; 1544 } 1545 1546 static bool 1547 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1548 { 1549 int val, min, max; 1550 u64 tmp; 1551 1552 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1553 entry->field_width, 1554 entry->sign); 1555 1556 tmp = entry->min_field_value; 1557 tmp <<= entry->field_pos; 1558 1559 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1560 entry->field_width, 1561 entry->sign); 1562 1563 tmp = entry->max_field_value; 1564 tmp <<= entry->field_pos; 1565 1566 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1567 entry->field_width, 1568 entry->sign); 1569 1570 return val >= min && val <= max; 1571 } 1572 1573 static u64 1574 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1575 { 1576 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1577 if (scope == SCOPE_SYSTEM) 1578 return read_sanitised_ftr_reg(entry->sys_reg); 1579 else 1580 return __read_sysreg_by_encoding(entry->sys_reg); 1581 } 1582 1583 static bool 1584 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1585 { 1586 int mask; 1587 struct arm64_ftr_reg *regp; 1588 u64 val = read_scoped_sysreg(entry, scope); 1589 1590 regp = get_arm64_ftr_reg(entry->sys_reg); 1591 if (!regp) 1592 return false; 1593 1594 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1595 entry->field_pos, 1596 entry->field_width); 1597 if (!mask) 1598 return false; 1599 1600 return feature_matches(val, entry); 1601 } 1602 1603 static bool 1604 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1605 { 1606 u64 val = read_scoped_sysreg(entry, scope); 1607 return feature_matches(val, entry); 1608 } 1609 1610 const struct cpumask *system_32bit_el0_cpumask(void) 1611 { 1612 if (!system_supports_32bit_el0()) 1613 return cpu_none_mask; 1614 1615 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1616 return cpu_32bit_el0_mask; 1617 1618 return cpu_possible_mask; 1619 } 1620 1621 static int __init parse_32bit_el0_param(char *str) 1622 { 1623 allow_mismatched_32bit_el0 = true; 1624 return 0; 1625 } 1626 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1627 1628 static ssize_t aarch32_el0_show(struct device *dev, 1629 struct device_attribute *attr, char *buf) 1630 { 1631 const struct cpumask *mask = system_32bit_el0_cpumask(); 1632 1633 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1634 } 1635 static const DEVICE_ATTR_RO(aarch32_el0); 1636 1637 static int __init aarch32_el0_sysfs_init(void) 1638 { 1639 struct device *dev_root; 1640 int ret = 0; 1641 1642 if (!allow_mismatched_32bit_el0) 1643 return 0; 1644 1645 dev_root = bus_get_dev_root(&cpu_subsys); 1646 if (dev_root) { 1647 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1648 put_device(dev_root); 1649 } 1650 return ret; 1651 } 1652 device_initcall(aarch32_el0_sysfs_init); 1653 1654 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1655 { 1656 if (!has_cpuid_feature(entry, scope)) 1657 return allow_mismatched_32bit_el0; 1658 1659 if (scope == SCOPE_SYSTEM) 1660 pr_info("detected: 32-bit EL0 Support\n"); 1661 1662 return true; 1663 } 1664 1665 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1666 { 1667 bool has_sre; 1668 1669 if (!has_cpuid_feature(entry, scope)) 1670 return false; 1671 1672 has_sre = gic_enable_sre(); 1673 if (!has_sre) 1674 pr_warn_once("%s present but disabled by higher exception level\n", 1675 entry->desc); 1676 1677 return has_sre; 1678 } 1679 1680 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1681 int scope) 1682 { 1683 u64 ctr; 1684 1685 if (scope == SCOPE_SYSTEM) 1686 ctr = arm64_ftr_reg_ctrel0.sys_val; 1687 else 1688 ctr = read_cpuid_effective_cachetype(); 1689 1690 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1691 } 1692 1693 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1694 { 1695 /* 1696 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1697 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1698 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1699 * value. 1700 */ 1701 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1702 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1703 } 1704 1705 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1706 int scope) 1707 { 1708 u64 ctr; 1709 1710 if (scope == SCOPE_SYSTEM) 1711 ctr = arm64_ftr_reg_ctrel0.sys_val; 1712 else 1713 ctr = read_cpuid_cachetype(); 1714 1715 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1716 } 1717 1718 static bool __maybe_unused 1719 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1720 { 1721 /* 1722 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1723 * may share TLB entries with a CPU stuck in the crashed 1724 * kernel. 1725 */ 1726 if (is_kdump_kernel()) 1727 return false; 1728 1729 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1730 return false; 1731 1732 return has_cpuid_feature(entry, scope); 1733 } 1734 1735 static bool __meltdown_safe = true; 1736 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1737 1738 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1739 int scope) 1740 { 1741 /* List of CPUs that are not vulnerable and don't need KPTI */ 1742 static const struct midr_range kpti_safe_list[] = { 1743 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1744 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1745 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1746 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1747 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1748 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1749 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1750 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1751 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1752 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1753 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1754 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1755 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1756 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1757 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1758 { /* sentinel */ } 1759 }; 1760 char const *str = "kpti command line option"; 1761 bool meltdown_safe; 1762 1763 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1764 1765 /* Defer to CPU feature registers */ 1766 if (has_cpuid_feature(entry, scope)) 1767 meltdown_safe = true; 1768 1769 if (!meltdown_safe) 1770 __meltdown_safe = false; 1771 1772 /* 1773 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1774 * ThunderX leads to apparent I-cache corruption of kernel text, which 1775 * ends as well as you might imagine. Don't even try. We cannot rely 1776 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1777 * because cpucap detection order may change. However, since we know 1778 * affected CPUs are always in a homogeneous configuration, it is 1779 * safe to rely on this_cpu_has_cap() here. 1780 */ 1781 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1782 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1783 __kpti_forced = -1; 1784 } 1785 1786 /* Useful for KASLR robustness */ 1787 if (kaslr_enabled() && kaslr_requires_kpti()) { 1788 if (!__kpti_forced) { 1789 str = "KASLR"; 1790 __kpti_forced = 1; 1791 } 1792 } 1793 1794 if (cpu_mitigations_off() && !__kpti_forced) { 1795 str = "mitigations=off"; 1796 __kpti_forced = -1; 1797 } 1798 1799 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1800 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1801 return false; 1802 } 1803 1804 /* Forced? */ 1805 if (__kpti_forced) { 1806 pr_info_once("kernel page table isolation forced %s by %s\n", 1807 __kpti_forced > 0 ? "ON" : "OFF", str); 1808 return __kpti_forced > 0; 1809 } 1810 1811 return !meltdown_safe; 1812 } 1813 1814 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1815 { 1816 /* 1817 * Although the Apple M2 family appears to support NV1, the 1818 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1819 * that it doesn't support NV1 at all. 1820 */ 1821 static const struct midr_range nv1_ni_list[] = { 1822 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1823 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1824 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1825 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1826 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1827 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1828 {} 1829 }; 1830 1831 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1832 !(has_cpuid_feature(entry, scope) || 1833 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1834 } 1835 1836 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1837 static bool has_lpa2_at_stage1(u64 mmfr0) 1838 { 1839 unsigned int tgran; 1840 1841 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1842 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1843 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1844 } 1845 1846 static bool has_lpa2_at_stage2(u64 mmfr0) 1847 { 1848 unsigned int tgran; 1849 1850 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1851 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1852 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1853 } 1854 1855 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1856 { 1857 u64 mmfr0; 1858 1859 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1860 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1861 } 1862 #else 1863 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1864 { 1865 return false; 1866 } 1867 #endif 1868 1869 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1870 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1871 1872 extern 1873 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1874 phys_addr_t size, pgprot_t prot, 1875 phys_addr_t (*pgtable_alloc)(int), int flags); 1876 1877 static phys_addr_t __initdata kpti_ng_temp_alloc; 1878 1879 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1880 { 1881 kpti_ng_temp_alloc -= PAGE_SIZE; 1882 return kpti_ng_temp_alloc; 1883 } 1884 1885 static int __init __kpti_install_ng_mappings(void *__unused) 1886 { 1887 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1888 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1889 kpti_remap_fn *remap_fn; 1890 1891 int cpu = smp_processor_id(); 1892 int levels = CONFIG_PGTABLE_LEVELS; 1893 int order = order_base_2(levels); 1894 u64 kpti_ng_temp_pgd_pa = 0; 1895 pgd_t *kpti_ng_temp_pgd; 1896 u64 alloc = 0; 1897 1898 if (levels == 5 && !pgtable_l5_enabled()) 1899 levels = 4; 1900 else if (levels == 4 && !pgtable_l4_enabled()) 1901 levels = 3; 1902 1903 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1904 1905 if (!cpu) { 1906 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1907 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1908 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1909 1910 // 1911 // Create a minimal page table hierarchy that permits us to map 1912 // the swapper page tables temporarily as we traverse them. 1913 // 1914 // The physical pages are laid out as follows: 1915 // 1916 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1917 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1918 // +--------+-\-------+-\------ +-\------ +-///--------+ 1919 // ^ 1920 // The first page is mapped into this hierarchy at a PMD_SHIFT 1921 // aligned virtual address, so that we can manipulate the PTE 1922 // level entries while the mapping is active. The first entry 1923 // covers the PTE[] page itself, the remaining entries are free 1924 // to be used as a ad-hoc fixmap. 1925 // 1926 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1927 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1928 kpti_ng_pgd_alloc, 0); 1929 } 1930 1931 cpu_install_idmap(); 1932 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1933 cpu_uninstall_idmap(); 1934 1935 if (!cpu) { 1936 free_pages(alloc, order); 1937 arm64_use_ng_mappings = true; 1938 } 1939 1940 return 0; 1941 } 1942 1943 static void __init kpti_install_ng_mappings(void) 1944 { 1945 /* Check whether KPTI is going to be used */ 1946 if (!arm64_kernel_unmapped_at_el0()) 1947 return; 1948 1949 /* 1950 * We don't need to rewrite the page-tables if either we've done 1951 * it already or we have KASLR enabled and therefore have not 1952 * created any global mappings at all. 1953 */ 1954 if (arm64_use_ng_mappings) 1955 return; 1956 1957 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1958 } 1959 1960 #else 1961 static inline void kpti_install_ng_mappings(void) 1962 { 1963 } 1964 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1965 1966 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1967 { 1968 if (__this_cpu_read(this_cpu_vector) == vectors) { 1969 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1970 1971 __this_cpu_write(this_cpu_vector, v); 1972 } 1973 1974 } 1975 1976 static int __init parse_kpti(char *str) 1977 { 1978 bool enabled; 1979 int ret = kstrtobool(str, &enabled); 1980 1981 if (ret) 1982 return ret; 1983 1984 __kpti_forced = enabled ? 1 : -1; 1985 return 0; 1986 } 1987 early_param("kpti", parse_kpti); 1988 1989 #ifdef CONFIG_ARM64_HW_AFDBM 1990 static struct cpumask dbm_cpus __read_mostly; 1991 1992 static inline void __cpu_enable_hw_dbm(void) 1993 { 1994 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1995 1996 write_sysreg(tcr, tcr_el1); 1997 isb(); 1998 local_flush_tlb_all(); 1999 } 2000 2001 static bool cpu_has_broken_dbm(void) 2002 { 2003 /* List of CPUs which have broken DBM support. */ 2004 static const struct midr_range cpus[] = { 2005 #ifdef CONFIG_ARM64_ERRATUM_1024718 2006 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2007 /* Kryo4xx Silver (rdpe => r1p0) */ 2008 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2009 #endif 2010 #ifdef CONFIG_ARM64_ERRATUM_2051678 2011 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2012 #endif 2013 {}, 2014 }; 2015 2016 return is_midr_in_range_list(read_cpuid_id(), cpus); 2017 } 2018 2019 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2020 { 2021 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2022 !cpu_has_broken_dbm(); 2023 } 2024 2025 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2026 { 2027 if (cpu_can_use_dbm(cap)) { 2028 __cpu_enable_hw_dbm(); 2029 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2030 } 2031 } 2032 2033 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2034 int __unused) 2035 { 2036 /* 2037 * DBM is a non-conflicting feature. i.e, the kernel can safely 2038 * run a mix of CPUs with and without the feature. So, we 2039 * unconditionally enable the capability to allow any late CPU 2040 * to use the feature. We only enable the control bits on the 2041 * CPU, if it is supported. 2042 */ 2043 2044 return true; 2045 } 2046 2047 #endif 2048 2049 #ifdef CONFIG_ARM64_AMU_EXTN 2050 2051 /* 2052 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2053 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2054 * information regarding all the events that it supports. When a CPU bit is 2055 * set in the cpumask, the user of this feature can only rely on the presence 2056 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2057 * counters are enabled or access to these counters is enabled by code 2058 * executed at higher exception levels (firmware). 2059 */ 2060 static struct cpumask amu_cpus __read_mostly; 2061 2062 bool cpu_has_amu_feat(int cpu) 2063 { 2064 return cpumask_test_cpu(cpu, &amu_cpus); 2065 } 2066 2067 int get_cpu_with_amu_feat(void) 2068 { 2069 return cpumask_any(&amu_cpus); 2070 } 2071 2072 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2073 { 2074 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2075 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2076 2077 /* 0 reference values signal broken/disabled counters */ 2078 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2079 update_freq_counters_refs(); 2080 } 2081 } 2082 2083 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2084 int __unused) 2085 { 2086 /* 2087 * The AMU extension is a non-conflicting feature: the kernel can 2088 * safely run a mix of CPUs with and without support for the 2089 * activity monitors extension. Therefore, unconditionally enable 2090 * the capability to allow any late CPU to use the feature. 2091 * 2092 * With this feature unconditionally enabled, the cpu_enable 2093 * function will be called for all CPUs that match the criteria, 2094 * including secondary and hotplugged, marking this feature as 2095 * present on that respective CPU. The enable function will also 2096 * print a detection message. 2097 */ 2098 2099 return true; 2100 } 2101 #else 2102 int get_cpu_with_amu_feat(void) 2103 { 2104 return nr_cpu_ids; 2105 } 2106 #endif 2107 2108 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2109 { 2110 return is_kernel_in_hyp_mode(); 2111 } 2112 2113 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2114 { 2115 /* 2116 * Copy register values that aren't redirected by hardware. 2117 * 2118 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2119 * this value to tpidr_el2 before we patch the code. Once we've done 2120 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2121 * do anything here. 2122 */ 2123 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2124 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2125 } 2126 2127 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2128 int scope) 2129 { 2130 if (kvm_get_mode() != KVM_MODE_NV) 2131 return false; 2132 2133 if (!has_cpuid_feature(cap, scope)) { 2134 pr_warn("unavailable: %s\n", cap->desc); 2135 return false; 2136 } 2137 2138 return true; 2139 } 2140 2141 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2142 int __unused) 2143 { 2144 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2145 } 2146 2147 #ifdef CONFIG_ARM64_PAN 2148 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2149 { 2150 /* 2151 * We modify PSTATE. This won't work from irq context as the PSTATE 2152 * is discarded once we return from the exception. 2153 */ 2154 WARN_ON_ONCE(in_interrupt()); 2155 2156 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2157 set_pstate_pan(1); 2158 } 2159 #endif /* CONFIG_ARM64_PAN */ 2160 2161 #ifdef CONFIG_ARM64_RAS_EXTN 2162 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2163 { 2164 /* Firmware may have left a deferred SError in this register. */ 2165 write_sysreg_s(0, SYS_DISR_EL1); 2166 } 2167 #endif /* CONFIG_ARM64_RAS_EXTN */ 2168 2169 #ifdef CONFIG_ARM64_PTR_AUTH 2170 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2171 { 2172 int boot_val, sec_val; 2173 2174 /* We don't expect to be called with SCOPE_SYSTEM */ 2175 WARN_ON(scope == SCOPE_SYSTEM); 2176 /* 2177 * The ptr-auth feature levels are not intercompatible with lower 2178 * levels. Hence we must match ptr-auth feature level of the secondary 2179 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2180 * from the sanitised register whereas direct register read is done for 2181 * the secondary CPUs. 2182 * The sanitised feature state is guaranteed to match that of the 2183 * boot CPU as a mismatched secondary CPU is parked before it gets 2184 * a chance to update the state, with the capability. 2185 */ 2186 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2187 entry->field_pos, entry->sign); 2188 if (scope & SCOPE_BOOT_CPU) 2189 return boot_val >= entry->min_field_value; 2190 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2191 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2192 entry->field_pos, entry->sign); 2193 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2194 } 2195 2196 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2197 int scope) 2198 { 2199 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2200 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2201 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2202 2203 return apa || apa3 || api; 2204 } 2205 2206 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2207 int __unused) 2208 { 2209 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2210 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2211 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2212 2213 return gpa || gpa3 || gpi; 2214 } 2215 #endif /* CONFIG_ARM64_PTR_AUTH */ 2216 2217 #ifdef CONFIG_ARM64_E0PD 2218 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2219 { 2220 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2221 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2222 } 2223 #endif /* CONFIG_ARM64_E0PD */ 2224 2225 #ifdef CONFIG_ARM64_PSEUDO_NMI 2226 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2227 int scope) 2228 { 2229 /* 2230 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2231 * feature, so will be detected earlier. 2232 */ 2233 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2234 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2235 return false; 2236 2237 return enable_pseudo_nmi; 2238 } 2239 2240 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2241 int scope) 2242 { 2243 /* 2244 * If we're not using priority masking then we won't be poking PMR_EL1, 2245 * and there's no need to relax synchronization of writes to it, and 2246 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2247 * that. 2248 * 2249 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2250 * feature, so will be detected earlier. 2251 */ 2252 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2253 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2254 return false; 2255 2256 /* 2257 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2258 * hint for interrupt distribution, a DSB is not necessary when 2259 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2260 * 2261 * Linux itself doesn't use 1:N distribution, so has no need to 2262 * set PMHE. The only reason to have it set is if EL3 requires it 2263 * (and we can't change it). 2264 */ 2265 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2266 } 2267 #endif 2268 2269 #ifdef CONFIG_ARM64_BTI 2270 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2271 { 2272 /* 2273 * Use of X16/X17 for tail-calls and trampolines that jump to 2274 * function entry points using BR is a requirement for 2275 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2276 * So, be strict and forbid other BRs using other registers to 2277 * jump onto a PACIxSP instruction: 2278 */ 2279 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2280 isb(); 2281 } 2282 #endif /* CONFIG_ARM64_BTI */ 2283 2284 #ifdef CONFIG_ARM64_MTE 2285 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2286 { 2287 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2288 2289 mte_cpu_setup(); 2290 2291 /* 2292 * Clear the tags in the zero page. This needs to be done via the 2293 * linear map which has the Tagged attribute. 2294 */ 2295 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2296 mte_clear_page_tags(lm_alias(empty_zero_page)); 2297 set_page_mte_tagged(ZERO_PAGE(0)); 2298 } 2299 2300 kasan_init_hw_tags_cpu(); 2301 } 2302 #endif /* CONFIG_ARM64_MTE */ 2303 2304 static void user_feature_fixup(void) 2305 { 2306 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2307 struct arm64_ftr_reg *regp; 2308 2309 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2310 if (regp) 2311 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2312 } 2313 2314 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2315 struct arm64_ftr_reg *regp; 2316 2317 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2318 if (regp) 2319 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2320 } 2321 } 2322 2323 static void elf_hwcap_fixup(void) 2324 { 2325 #ifdef CONFIG_COMPAT 2326 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2327 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2328 #endif /* CONFIG_COMPAT */ 2329 } 2330 2331 #ifdef CONFIG_KVM 2332 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2333 { 2334 return kvm_get_mode() == KVM_MODE_PROTECTED; 2335 } 2336 #endif /* CONFIG_KVM */ 2337 2338 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2339 { 2340 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2341 } 2342 2343 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2344 { 2345 set_pstate_dit(1); 2346 } 2347 2348 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2349 { 2350 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2351 } 2352 2353 #ifdef CONFIG_ARM64_POE 2354 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2355 { 2356 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); 2357 sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); 2358 } 2359 #endif 2360 2361 /* Internal helper functions to match cpu capability type */ 2362 static bool 2363 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2364 { 2365 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2366 } 2367 2368 static bool 2369 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2370 { 2371 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2372 } 2373 2374 static bool 2375 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2376 { 2377 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2378 } 2379 2380 static const struct arm64_cpu_capabilities arm64_features[] = { 2381 { 2382 .capability = ARM64_ALWAYS_BOOT, 2383 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2384 .matches = has_always, 2385 }, 2386 { 2387 .capability = ARM64_ALWAYS_SYSTEM, 2388 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2389 .matches = has_always, 2390 }, 2391 { 2392 .desc = "GIC system register CPU interface", 2393 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2394 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2395 .matches = has_useable_gicv3_cpuif, 2396 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2397 }, 2398 { 2399 .desc = "Enhanced Counter Virtualization", 2400 .capability = ARM64_HAS_ECV, 2401 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2402 .matches = has_cpuid_feature, 2403 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2404 }, 2405 { 2406 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2407 .capability = ARM64_HAS_ECV_CNTPOFF, 2408 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2409 .matches = has_cpuid_feature, 2410 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2411 }, 2412 #ifdef CONFIG_ARM64_PAN 2413 { 2414 .desc = "Privileged Access Never", 2415 .capability = ARM64_HAS_PAN, 2416 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2417 .matches = has_cpuid_feature, 2418 .cpu_enable = cpu_enable_pan, 2419 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2420 }, 2421 #endif /* CONFIG_ARM64_PAN */ 2422 #ifdef CONFIG_ARM64_EPAN 2423 { 2424 .desc = "Enhanced Privileged Access Never", 2425 .capability = ARM64_HAS_EPAN, 2426 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2427 .matches = has_cpuid_feature, 2428 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2429 }, 2430 #endif /* CONFIG_ARM64_EPAN */ 2431 #ifdef CONFIG_ARM64_LSE_ATOMICS 2432 { 2433 .desc = "LSE atomic instructions", 2434 .capability = ARM64_HAS_LSE_ATOMICS, 2435 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2436 .matches = has_cpuid_feature, 2437 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2438 }, 2439 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2440 { 2441 .desc = "Virtualization Host Extensions", 2442 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2443 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2444 .matches = runs_at_el2, 2445 .cpu_enable = cpu_copy_el2regs, 2446 }, 2447 { 2448 .desc = "Nested Virtualization Support", 2449 .capability = ARM64_HAS_NESTED_VIRT, 2450 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2451 .matches = has_nested_virt_support, 2452 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2453 }, 2454 { 2455 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2456 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2457 .matches = has_32bit_el0, 2458 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2459 }, 2460 #ifdef CONFIG_KVM 2461 { 2462 .desc = "32-bit EL1 Support", 2463 .capability = ARM64_HAS_32BIT_EL1, 2464 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2465 .matches = has_cpuid_feature, 2466 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2467 }, 2468 { 2469 .desc = "Protected KVM", 2470 .capability = ARM64_KVM_PROTECTED_MODE, 2471 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2472 .matches = is_kvm_protected_mode, 2473 }, 2474 { 2475 .desc = "HCRX_EL2 register", 2476 .capability = ARM64_HAS_HCX, 2477 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2478 .matches = has_cpuid_feature, 2479 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2480 }, 2481 #endif 2482 { 2483 .desc = "Kernel page table isolation (KPTI)", 2484 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2485 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2486 .cpu_enable = cpu_enable_kpti, 2487 .matches = unmap_kernel_at_el0, 2488 /* 2489 * The ID feature fields below are used to indicate that 2490 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2491 * more details. 2492 */ 2493 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2494 }, 2495 { 2496 .capability = ARM64_HAS_FPSIMD, 2497 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2498 .matches = has_cpuid_feature, 2499 .cpu_enable = cpu_enable_fpsimd, 2500 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2501 }, 2502 #ifdef CONFIG_ARM64_PMEM 2503 { 2504 .desc = "Data cache clean to Point of Persistence", 2505 .capability = ARM64_HAS_DCPOP, 2506 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2507 .matches = has_cpuid_feature, 2508 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2509 }, 2510 { 2511 .desc = "Data cache clean to Point of Deep Persistence", 2512 .capability = ARM64_HAS_DCPODP, 2513 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2514 .matches = has_cpuid_feature, 2515 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2516 }, 2517 #endif 2518 #ifdef CONFIG_ARM64_SVE 2519 { 2520 .desc = "Scalable Vector Extension", 2521 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2522 .capability = ARM64_SVE, 2523 .cpu_enable = cpu_enable_sve, 2524 .matches = has_cpuid_feature, 2525 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2526 }, 2527 #endif /* CONFIG_ARM64_SVE */ 2528 #ifdef CONFIG_ARM64_RAS_EXTN 2529 { 2530 .desc = "RAS Extension Support", 2531 .capability = ARM64_HAS_RAS_EXTN, 2532 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2533 .matches = has_cpuid_feature, 2534 .cpu_enable = cpu_clear_disr, 2535 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2536 }, 2537 #endif /* CONFIG_ARM64_RAS_EXTN */ 2538 #ifdef CONFIG_ARM64_AMU_EXTN 2539 { 2540 .desc = "Activity Monitors Unit (AMU)", 2541 .capability = ARM64_HAS_AMU_EXTN, 2542 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2543 .matches = has_amu, 2544 .cpu_enable = cpu_amu_enable, 2545 .cpus = &amu_cpus, 2546 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2547 }, 2548 #endif /* CONFIG_ARM64_AMU_EXTN */ 2549 { 2550 .desc = "Data cache clean to the PoU not required for I/D coherence", 2551 .capability = ARM64_HAS_CACHE_IDC, 2552 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2553 .matches = has_cache_idc, 2554 .cpu_enable = cpu_emulate_effective_ctr, 2555 }, 2556 { 2557 .desc = "Instruction cache invalidation not required for I/D coherence", 2558 .capability = ARM64_HAS_CACHE_DIC, 2559 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2560 .matches = has_cache_dic, 2561 }, 2562 { 2563 .desc = "Stage-2 Force Write-Back", 2564 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2565 .capability = ARM64_HAS_STAGE2_FWB, 2566 .matches = has_cpuid_feature, 2567 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2568 }, 2569 { 2570 .desc = "ARMv8.4 Translation Table Level", 2571 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2572 .capability = ARM64_HAS_ARMv8_4_TTL, 2573 .matches = has_cpuid_feature, 2574 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2575 }, 2576 { 2577 .desc = "TLB range maintenance instructions", 2578 .capability = ARM64_HAS_TLB_RANGE, 2579 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2580 .matches = has_cpuid_feature, 2581 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2582 }, 2583 #ifdef CONFIG_ARM64_HW_AFDBM 2584 { 2585 .desc = "Hardware dirty bit management", 2586 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2587 .capability = ARM64_HW_DBM, 2588 .matches = has_hw_dbm, 2589 .cpu_enable = cpu_enable_hw_dbm, 2590 .cpus = &dbm_cpus, 2591 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2592 }, 2593 #endif 2594 { 2595 .desc = "CRC32 instructions", 2596 .capability = ARM64_HAS_CRC32, 2597 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2598 .matches = has_cpuid_feature, 2599 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2600 }, 2601 { 2602 .desc = "Speculative Store Bypassing Safe (SSBS)", 2603 .capability = ARM64_SSBS, 2604 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2605 .matches = has_cpuid_feature, 2606 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2607 }, 2608 #ifdef CONFIG_ARM64_CNP 2609 { 2610 .desc = "Common not Private translations", 2611 .capability = ARM64_HAS_CNP, 2612 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2613 .matches = has_useable_cnp, 2614 .cpu_enable = cpu_enable_cnp, 2615 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2616 }, 2617 #endif 2618 { 2619 .desc = "Speculation barrier (SB)", 2620 .capability = ARM64_HAS_SB, 2621 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2622 .matches = has_cpuid_feature, 2623 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2624 }, 2625 #ifdef CONFIG_ARM64_PTR_AUTH 2626 { 2627 .desc = "Address authentication (architected QARMA5 algorithm)", 2628 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2629 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2630 .matches = has_address_auth_cpucap, 2631 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2632 }, 2633 { 2634 .desc = "Address authentication (architected QARMA3 algorithm)", 2635 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2636 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2637 .matches = has_address_auth_cpucap, 2638 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2639 }, 2640 { 2641 .desc = "Address authentication (IMP DEF algorithm)", 2642 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2643 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2644 .matches = has_address_auth_cpucap, 2645 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2646 }, 2647 { 2648 .capability = ARM64_HAS_ADDRESS_AUTH, 2649 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2650 .matches = has_address_auth_metacap, 2651 }, 2652 { 2653 .desc = "Generic authentication (architected QARMA5 algorithm)", 2654 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2655 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2656 .matches = has_cpuid_feature, 2657 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2658 }, 2659 { 2660 .desc = "Generic authentication (architected QARMA3 algorithm)", 2661 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2662 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2663 .matches = has_cpuid_feature, 2664 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2665 }, 2666 { 2667 .desc = "Generic authentication (IMP DEF algorithm)", 2668 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2669 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2670 .matches = has_cpuid_feature, 2671 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2672 }, 2673 { 2674 .capability = ARM64_HAS_GENERIC_AUTH, 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .matches = has_generic_auth, 2677 }, 2678 #endif /* CONFIG_ARM64_PTR_AUTH */ 2679 #ifdef CONFIG_ARM64_PSEUDO_NMI 2680 { 2681 /* 2682 * Depends on having GICv3 2683 */ 2684 .desc = "IRQ priority masking", 2685 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2686 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2687 .matches = can_use_gic_priorities, 2688 }, 2689 { 2690 /* 2691 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2692 */ 2693 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2694 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2695 .matches = has_gic_prio_relaxed_sync, 2696 }, 2697 #endif 2698 #ifdef CONFIG_ARM64_E0PD 2699 { 2700 .desc = "E0PD", 2701 .capability = ARM64_HAS_E0PD, 2702 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2703 .cpu_enable = cpu_enable_e0pd, 2704 .matches = has_cpuid_feature, 2705 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2706 }, 2707 #endif 2708 { 2709 .desc = "Random Number Generator", 2710 .capability = ARM64_HAS_RNG, 2711 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2712 .matches = has_cpuid_feature, 2713 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2714 }, 2715 #ifdef CONFIG_ARM64_BTI 2716 { 2717 .desc = "Branch Target Identification", 2718 .capability = ARM64_BTI, 2719 #ifdef CONFIG_ARM64_BTI_KERNEL 2720 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2721 #else 2722 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2723 #endif 2724 .matches = has_cpuid_feature, 2725 .cpu_enable = bti_enable, 2726 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2727 }, 2728 #endif 2729 #ifdef CONFIG_ARM64_MTE 2730 { 2731 .desc = "Memory Tagging Extension", 2732 .capability = ARM64_MTE, 2733 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2734 .matches = has_cpuid_feature, 2735 .cpu_enable = cpu_enable_mte, 2736 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2737 }, 2738 { 2739 .desc = "Asymmetric MTE Tag Check Fault", 2740 .capability = ARM64_MTE_ASYMM, 2741 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2742 .matches = has_cpuid_feature, 2743 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2744 }, 2745 #endif /* CONFIG_ARM64_MTE */ 2746 { 2747 .desc = "RCpc load-acquire (LDAPR)", 2748 .capability = ARM64_HAS_LDAPR, 2749 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2750 .matches = has_cpuid_feature, 2751 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2752 }, 2753 { 2754 .desc = "Fine Grained Traps", 2755 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2756 .capability = ARM64_HAS_FGT, 2757 .matches = has_cpuid_feature, 2758 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2759 }, 2760 #ifdef CONFIG_ARM64_SME 2761 { 2762 .desc = "Scalable Matrix Extension", 2763 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2764 .capability = ARM64_SME, 2765 .matches = has_cpuid_feature, 2766 .cpu_enable = cpu_enable_sme, 2767 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2768 }, 2769 /* FA64 should be sorted after the base SME capability */ 2770 { 2771 .desc = "FA64", 2772 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2773 .capability = ARM64_SME_FA64, 2774 .matches = has_cpuid_feature, 2775 .cpu_enable = cpu_enable_fa64, 2776 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2777 }, 2778 { 2779 .desc = "SME2", 2780 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2781 .capability = ARM64_SME2, 2782 .matches = has_cpuid_feature, 2783 .cpu_enable = cpu_enable_sme2, 2784 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2785 }, 2786 #endif /* CONFIG_ARM64_SME */ 2787 { 2788 .desc = "WFx with timeout", 2789 .capability = ARM64_HAS_WFXT, 2790 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2791 .matches = has_cpuid_feature, 2792 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2793 }, 2794 { 2795 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2796 .capability = ARM64_HAS_TIDCP1, 2797 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2798 .matches = has_cpuid_feature, 2799 .cpu_enable = cpu_trap_el0_impdef, 2800 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2801 }, 2802 { 2803 .desc = "Data independent timing control (DIT)", 2804 .capability = ARM64_HAS_DIT, 2805 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2806 .matches = has_cpuid_feature, 2807 .cpu_enable = cpu_enable_dit, 2808 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2809 }, 2810 { 2811 .desc = "Memory Copy and Memory Set instructions", 2812 .capability = ARM64_HAS_MOPS, 2813 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2814 .matches = has_cpuid_feature, 2815 .cpu_enable = cpu_enable_mops, 2816 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2817 }, 2818 { 2819 .capability = ARM64_HAS_TCR2, 2820 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2821 .matches = has_cpuid_feature, 2822 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2823 }, 2824 { 2825 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2826 .capability = ARM64_HAS_S1PIE, 2827 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2828 .matches = has_cpuid_feature, 2829 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2830 }, 2831 { 2832 .desc = "VHE for hypervisor only", 2833 .capability = ARM64_KVM_HVHE, 2834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2835 .matches = hvhe_possible, 2836 }, 2837 { 2838 .desc = "Enhanced Virtualization Traps", 2839 .capability = ARM64_HAS_EVT, 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .matches = has_cpuid_feature, 2842 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2843 }, 2844 { 2845 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2846 .capability = ARM64_HAS_LPA2, 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .matches = has_lpa2, 2849 }, 2850 { 2851 .desc = "FPMR", 2852 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2853 .capability = ARM64_HAS_FPMR, 2854 .matches = has_cpuid_feature, 2855 .cpu_enable = cpu_enable_fpmr, 2856 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2857 }, 2858 #ifdef CONFIG_ARM64_VA_BITS_52 2859 { 2860 .capability = ARM64_HAS_VA52, 2861 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2862 .matches = has_cpuid_feature, 2863 #ifdef CONFIG_ARM64_64K_PAGES 2864 .desc = "52-bit Virtual Addressing (LVA)", 2865 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2866 #else 2867 .desc = "52-bit Virtual Addressing (LPA2)", 2868 #ifdef CONFIG_ARM64_4K_PAGES 2869 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2870 #else 2871 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2872 #endif 2873 #endif 2874 }, 2875 #endif 2876 { 2877 .desc = "NV1", 2878 .capability = ARM64_HAS_HCR_NV1, 2879 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2880 .matches = has_nv1, 2881 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2882 }, 2883 #ifdef CONFIG_ARM64_POE 2884 { 2885 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2886 .capability = ARM64_HAS_S1POE, 2887 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2888 .matches = has_cpuid_feature, 2889 .cpu_enable = cpu_enable_poe, 2890 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2891 }, 2892 #endif 2893 {}, 2894 }; 2895 2896 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2897 .matches = has_user_cpuid_feature, \ 2898 ARM64_CPUID_FIELDS(reg, field, min_value) 2899 2900 #define __HWCAP_CAP(name, cap_type, cap) \ 2901 .desc = name, \ 2902 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2903 .hwcap_type = cap_type, \ 2904 .hwcap = cap, \ 2905 2906 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2907 { \ 2908 __HWCAP_CAP(#cap, cap_type, cap) \ 2909 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2910 } 2911 2912 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2913 { \ 2914 __HWCAP_CAP(#cap, cap_type, cap) \ 2915 .matches = cpucap_multi_entry_cap_matches, \ 2916 .match_list = list, \ 2917 } 2918 2919 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2920 { \ 2921 __HWCAP_CAP(#cap, cap_type, cap) \ 2922 .matches = match, \ 2923 } 2924 2925 #ifdef CONFIG_ARM64_PTR_AUTH 2926 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2927 { 2928 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2929 }, 2930 { 2931 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2932 }, 2933 { 2934 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2935 }, 2936 {}, 2937 }; 2938 2939 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2940 { 2941 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2942 }, 2943 { 2944 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2945 }, 2946 { 2947 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2948 }, 2949 {}, 2950 }; 2951 #endif 2952 2953 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2954 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2955 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2956 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2957 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2958 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2959 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2960 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2961 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2962 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2963 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2964 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 2965 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 2966 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2967 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2968 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2969 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2970 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 2971 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 2972 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2973 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2974 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2975 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 2976 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 2977 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2978 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2979 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2980 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2981 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2982 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2983 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 2984 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2985 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 2986 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 2987 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 2988 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 2989 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2990 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 2991 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 2992 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2993 #ifdef CONFIG_ARM64_SVE 2994 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 2995 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 2996 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2997 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2998 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2999 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3000 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3001 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3002 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3003 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3004 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3005 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3006 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3007 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3008 #endif 3009 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3010 #ifdef CONFIG_ARM64_BTI 3011 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3012 #endif 3013 #ifdef CONFIG_ARM64_PTR_AUTH 3014 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3015 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3016 #endif 3017 #ifdef CONFIG_ARM64_MTE 3018 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3019 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3020 #endif /* CONFIG_ARM64_MTE */ 3021 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3022 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3023 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3024 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3025 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3026 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3027 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3028 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3029 #ifdef CONFIG_ARM64_SME 3030 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3031 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3032 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3033 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3034 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3035 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3036 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3037 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3038 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3039 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3040 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3041 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3042 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3043 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3044 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3045 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3046 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3047 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3048 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3049 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3050 #endif /* CONFIG_ARM64_SME */ 3051 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3052 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3053 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3054 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3055 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3056 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3057 #ifdef CONFIG_ARM64_POE 3058 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3059 #endif 3060 {}, 3061 }; 3062 3063 #ifdef CONFIG_COMPAT 3064 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3065 { 3066 /* 3067 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3068 * in line with that of arm32 as in vfp_init(). We make sure that the 3069 * check is future proof, by making sure value is non-zero. 3070 */ 3071 u32 mvfr1; 3072 3073 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3074 if (scope == SCOPE_SYSTEM) 3075 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3076 else 3077 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3078 3079 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3080 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3081 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3082 } 3083 #endif 3084 3085 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3086 #ifdef CONFIG_COMPAT 3087 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3088 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3089 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3090 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3091 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3092 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3093 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3094 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3095 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3096 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3097 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3098 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3099 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3100 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3101 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3102 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3103 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3104 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3105 #endif 3106 {}, 3107 }; 3108 3109 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3110 { 3111 switch (cap->hwcap_type) { 3112 case CAP_HWCAP: 3113 cpu_set_feature(cap->hwcap); 3114 break; 3115 #ifdef CONFIG_COMPAT 3116 case CAP_COMPAT_HWCAP: 3117 compat_elf_hwcap |= (u32)cap->hwcap; 3118 break; 3119 case CAP_COMPAT_HWCAP2: 3120 compat_elf_hwcap2 |= (u32)cap->hwcap; 3121 break; 3122 #endif 3123 default: 3124 WARN_ON(1); 3125 break; 3126 } 3127 } 3128 3129 /* Check if we have a particular HWCAP enabled */ 3130 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3131 { 3132 bool rc; 3133 3134 switch (cap->hwcap_type) { 3135 case CAP_HWCAP: 3136 rc = cpu_have_feature(cap->hwcap); 3137 break; 3138 #ifdef CONFIG_COMPAT 3139 case CAP_COMPAT_HWCAP: 3140 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3141 break; 3142 case CAP_COMPAT_HWCAP2: 3143 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3144 break; 3145 #endif 3146 default: 3147 WARN_ON(1); 3148 rc = false; 3149 } 3150 3151 return rc; 3152 } 3153 3154 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3155 { 3156 /* We support emulation of accesses to CPU ID feature registers */ 3157 cpu_set_named_feature(CPUID); 3158 for (; hwcaps->matches; hwcaps++) 3159 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3160 cap_set_elf_hwcap(hwcaps); 3161 } 3162 3163 static void update_cpu_capabilities(u16 scope_mask) 3164 { 3165 int i; 3166 const struct arm64_cpu_capabilities *caps; 3167 3168 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3169 for (i = 0; i < ARM64_NCAPS; i++) { 3170 caps = cpucap_ptrs[i]; 3171 if (!caps || !(caps->type & scope_mask) || 3172 cpus_have_cap(caps->capability) || 3173 !caps->matches(caps, cpucap_default_scope(caps))) 3174 continue; 3175 3176 if (caps->desc && !caps->cpus) 3177 pr_info("detected: %s\n", caps->desc); 3178 3179 __set_bit(caps->capability, system_cpucaps); 3180 3181 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3182 set_bit(caps->capability, boot_cpucaps); 3183 } 3184 } 3185 3186 /* 3187 * Enable all the available capabilities on this CPU. The capabilities 3188 * with BOOT_CPU scope are handled separately and hence skipped here. 3189 */ 3190 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3191 { 3192 int i; 3193 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3194 3195 for_each_available_cap(i) { 3196 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3197 3198 if (WARN_ON(!cap)) 3199 continue; 3200 3201 if (!(cap->type & non_boot_scope)) 3202 continue; 3203 3204 if (cap->cpu_enable) 3205 cap->cpu_enable(cap); 3206 } 3207 return 0; 3208 } 3209 3210 /* 3211 * Run through the enabled capabilities and enable() it on all active 3212 * CPUs 3213 */ 3214 static void __init enable_cpu_capabilities(u16 scope_mask) 3215 { 3216 int i; 3217 const struct arm64_cpu_capabilities *caps; 3218 bool boot_scope; 3219 3220 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3221 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3222 3223 for (i = 0; i < ARM64_NCAPS; i++) { 3224 caps = cpucap_ptrs[i]; 3225 if (!caps || !(caps->type & scope_mask) || 3226 !cpus_have_cap(caps->capability)) 3227 continue; 3228 3229 if (boot_scope && caps->cpu_enable) 3230 /* 3231 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3232 * before any secondary CPU boots. Thus, each secondary 3233 * will enable the capability as appropriate via 3234 * check_local_cpu_capabilities(). The only exception is 3235 * the boot CPU, for which the capability must be 3236 * enabled here. This approach avoids costly 3237 * stop_machine() calls for this case. 3238 */ 3239 caps->cpu_enable(caps); 3240 } 3241 3242 /* 3243 * For all non-boot scope capabilities, use stop_machine() 3244 * as it schedules the work allowing us to modify PSTATE, 3245 * instead of on_each_cpu() which uses an IPI, giving us a 3246 * PSTATE that disappears when we return. 3247 */ 3248 if (!boot_scope) 3249 stop_machine(cpu_enable_non_boot_scope_capabilities, 3250 NULL, cpu_online_mask); 3251 } 3252 3253 /* 3254 * Run through the list of capabilities to check for conflicts. 3255 * If the system has already detected a capability, take necessary 3256 * action on this CPU. 3257 */ 3258 static void verify_local_cpu_caps(u16 scope_mask) 3259 { 3260 int i; 3261 bool cpu_has_cap, system_has_cap; 3262 const struct arm64_cpu_capabilities *caps; 3263 3264 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3265 3266 for (i = 0; i < ARM64_NCAPS; i++) { 3267 caps = cpucap_ptrs[i]; 3268 if (!caps || !(caps->type & scope_mask)) 3269 continue; 3270 3271 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3272 system_has_cap = cpus_have_cap(caps->capability); 3273 3274 if (system_has_cap) { 3275 /* 3276 * Check if the new CPU misses an advertised feature, 3277 * which is not safe to miss. 3278 */ 3279 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3280 break; 3281 /* 3282 * We have to issue cpu_enable() irrespective of 3283 * whether the CPU has it or not, as it is enabeld 3284 * system wide. It is upto the call back to take 3285 * appropriate action on this CPU. 3286 */ 3287 if (caps->cpu_enable) 3288 caps->cpu_enable(caps); 3289 } else { 3290 /* 3291 * Check if the CPU has this capability if it isn't 3292 * safe to have when the system doesn't. 3293 */ 3294 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3295 break; 3296 } 3297 } 3298 3299 if (i < ARM64_NCAPS) { 3300 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3301 smp_processor_id(), caps->capability, 3302 caps->desc, system_has_cap, cpu_has_cap); 3303 3304 if (cpucap_panic_on_conflict(caps)) 3305 cpu_panic_kernel(); 3306 else 3307 cpu_die_early(); 3308 } 3309 } 3310 3311 /* 3312 * Check for CPU features that are used in early boot 3313 * based on the Boot CPU value. 3314 */ 3315 static void check_early_cpu_features(void) 3316 { 3317 verify_cpu_asid_bits(); 3318 3319 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3320 } 3321 3322 static void 3323 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3324 { 3325 3326 for (; caps->matches; caps++) 3327 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3328 pr_crit("CPU%d: missing HWCAP: %s\n", 3329 smp_processor_id(), caps->desc); 3330 cpu_die_early(); 3331 } 3332 } 3333 3334 static void verify_local_elf_hwcaps(void) 3335 { 3336 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3337 3338 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3339 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3340 } 3341 3342 static void verify_sve_features(void) 3343 { 3344 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3345 3346 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3347 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3348 smp_processor_id()); 3349 cpu_die_early(); 3350 } 3351 3352 cpacr_restore(cpacr); 3353 } 3354 3355 static void verify_sme_features(void) 3356 { 3357 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3358 3359 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3360 pr_crit("CPU%d: SME: vector length support mismatch\n", 3361 smp_processor_id()); 3362 cpu_die_early(); 3363 } 3364 3365 cpacr_restore(cpacr); 3366 } 3367 3368 static void verify_hyp_capabilities(void) 3369 { 3370 u64 safe_mmfr1, mmfr0, mmfr1; 3371 int parange, ipa_max; 3372 unsigned int safe_vmid_bits, vmid_bits; 3373 3374 if (!IS_ENABLED(CONFIG_KVM)) 3375 return; 3376 3377 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3378 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3379 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3380 3381 /* Verify VMID bits */ 3382 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3383 vmid_bits = get_vmid_bits(mmfr1); 3384 if (vmid_bits < safe_vmid_bits) { 3385 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3386 cpu_die_early(); 3387 } 3388 3389 /* Verify IPA range */ 3390 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3391 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3392 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3393 if (ipa_max < get_kvm_ipa_limit()) { 3394 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3395 cpu_die_early(); 3396 } 3397 } 3398 3399 /* 3400 * Run through the enabled system capabilities and enable() it on this CPU. 3401 * The capabilities were decided based on the available CPUs at the boot time. 3402 * Any new CPU should match the system wide status of the capability. If the 3403 * new CPU doesn't have a capability which the system now has enabled, we 3404 * cannot do anything to fix it up and could cause unexpected failures. So 3405 * we park the CPU. 3406 */ 3407 static void verify_local_cpu_capabilities(void) 3408 { 3409 /* 3410 * The capabilities with SCOPE_BOOT_CPU are checked from 3411 * check_early_cpu_features(), as they need to be verified 3412 * on all secondary CPUs. 3413 */ 3414 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3415 verify_local_elf_hwcaps(); 3416 3417 if (system_supports_sve()) 3418 verify_sve_features(); 3419 3420 if (system_supports_sme()) 3421 verify_sme_features(); 3422 3423 if (is_hyp_mode_available()) 3424 verify_hyp_capabilities(); 3425 } 3426 3427 void check_local_cpu_capabilities(void) 3428 { 3429 /* 3430 * All secondary CPUs should conform to the early CPU features 3431 * in use by the kernel based on boot CPU. 3432 */ 3433 check_early_cpu_features(); 3434 3435 /* 3436 * If we haven't finalised the system capabilities, this CPU gets 3437 * a chance to update the errata work arounds and local features. 3438 * Otherwise, this CPU should verify that it has all the system 3439 * advertised capabilities. 3440 */ 3441 if (!system_capabilities_finalized()) 3442 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3443 else 3444 verify_local_cpu_capabilities(); 3445 } 3446 3447 bool this_cpu_has_cap(unsigned int n) 3448 { 3449 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3450 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3451 3452 if (cap) 3453 return cap->matches(cap, SCOPE_LOCAL_CPU); 3454 } 3455 3456 return false; 3457 } 3458 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3459 3460 /* 3461 * This helper function is used in a narrow window when, 3462 * - The system wide safe registers are set with all the SMP CPUs and, 3463 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3464 */ 3465 static bool __maybe_unused __system_matches_cap(unsigned int n) 3466 { 3467 if (n < ARM64_NCAPS) { 3468 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3469 3470 if (cap) 3471 return cap->matches(cap, SCOPE_SYSTEM); 3472 } 3473 return false; 3474 } 3475 3476 void cpu_set_feature(unsigned int num) 3477 { 3478 set_bit(num, elf_hwcap); 3479 } 3480 3481 bool cpu_have_feature(unsigned int num) 3482 { 3483 return test_bit(num, elf_hwcap); 3484 } 3485 EXPORT_SYMBOL_GPL(cpu_have_feature); 3486 3487 unsigned long cpu_get_elf_hwcap(void) 3488 { 3489 /* 3490 * We currently only populate the first 32 bits of AT_HWCAP. Please 3491 * note that for userspace compatibility we guarantee that bits 62 3492 * and 63 will always be returned as 0. 3493 */ 3494 return elf_hwcap[0]; 3495 } 3496 3497 unsigned long cpu_get_elf_hwcap2(void) 3498 { 3499 return elf_hwcap[1]; 3500 } 3501 3502 static void __init setup_boot_cpu_capabilities(void) 3503 { 3504 /* 3505 * The boot CPU's feature register values have been recorded. Detect 3506 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3507 * patch alternatives for the available boot cpucaps. 3508 */ 3509 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3510 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3511 apply_boot_alternatives(); 3512 } 3513 3514 void __init setup_boot_cpu_features(void) 3515 { 3516 /* 3517 * Initialize the indirect array of CPU capabilities pointers before we 3518 * handle the boot CPU. 3519 */ 3520 init_cpucap_indirect_list(); 3521 3522 /* 3523 * Detect broken pseudo-NMI. Must be called _before_ the call to 3524 * setup_boot_cpu_capabilities() since it interacts with 3525 * can_use_gic_priorities(). 3526 */ 3527 detect_system_supports_pseudo_nmi(); 3528 3529 setup_boot_cpu_capabilities(); 3530 } 3531 3532 static void __init setup_system_capabilities(void) 3533 { 3534 /* 3535 * The system-wide safe feature register values have been finalized. 3536 * Detect, enable, and patch alternatives for the available system 3537 * cpucaps. 3538 */ 3539 update_cpu_capabilities(SCOPE_SYSTEM); 3540 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3541 apply_alternatives_all(); 3542 3543 /* 3544 * Log any cpucaps with a cpumask as these aren't logged by 3545 * update_cpu_capabilities(). 3546 */ 3547 for (int i = 0; i < ARM64_NCAPS; i++) { 3548 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3549 3550 if (caps && caps->cpus && caps->desc && 3551 cpumask_any(caps->cpus) < nr_cpu_ids) 3552 pr_info("detected: %s on CPU%*pbl\n", 3553 caps->desc, cpumask_pr_args(caps->cpus)); 3554 } 3555 3556 /* 3557 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3558 */ 3559 if (system_uses_ttbr0_pan()) 3560 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3561 } 3562 3563 void __init setup_system_features(void) 3564 { 3565 setup_system_capabilities(); 3566 3567 kpti_install_ng_mappings(); 3568 3569 sve_setup(); 3570 sme_setup(); 3571 3572 /* 3573 * Check for sane CTR_EL0.CWG value. 3574 */ 3575 if (!cache_type_cwg()) 3576 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3577 ARCH_DMA_MINALIGN); 3578 } 3579 3580 void __init setup_user_features(void) 3581 { 3582 user_feature_fixup(); 3583 3584 setup_elf_hwcaps(arm64_elf_hwcaps); 3585 3586 if (system_supports_32bit_el0()) { 3587 setup_elf_hwcaps(compat_elf_hwcaps); 3588 elf_hwcap_fixup(); 3589 } 3590 3591 minsigstksz_setup(); 3592 } 3593 3594 static int enable_mismatched_32bit_el0(unsigned int cpu) 3595 { 3596 /* 3597 * The first 32-bit-capable CPU we detected and so can no longer 3598 * be offlined by userspace. -1 indicates we haven't yet onlined 3599 * a 32-bit-capable CPU. 3600 */ 3601 static int lucky_winner = -1; 3602 3603 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3604 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3605 3606 if (cpu_32bit) { 3607 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3608 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3609 } 3610 3611 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3612 return 0; 3613 3614 if (lucky_winner >= 0) 3615 return 0; 3616 3617 /* 3618 * We've detected a mismatch. We need to keep one of our CPUs with 3619 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3620 * every CPU in the system for a 32-bit task. 3621 */ 3622 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3623 cpu_active_mask); 3624 get_cpu_device(lucky_winner)->offline_disabled = true; 3625 setup_elf_hwcaps(compat_elf_hwcaps); 3626 elf_hwcap_fixup(); 3627 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3628 cpu, lucky_winner); 3629 return 0; 3630 } 3631 3632 static int __init init_32bit_el0_mask(void) 3633 { 3634 if (!allow_mismatched_32bit_el0) 3635 return 0; 3636 3637 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3638 return -ENOMEM; 3639 3640 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3641 "arm64/mismatched_32bit_el0:online", 3642 enable_mismatched_32bit_el0, NULL); 3643 } 3644 subsys_initcall_sync(init_32bit_el0_mask); 3645 3646 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3647 { 3648 cpu_enable_swapper_cnp(); 3649 } 3650 3651 /* 3652 * We emulate only the following system register space. 3653 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3654 * See Table C5-6 System instruction encodings for System register accesses, 3655 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3656 */ 3657 static inline bool __attribute_const__ is_emulated(u32 id) 3658 { 3659 return (sys_reg_Op0(id) == 0x3 && 3660 sys_reg_CRn(id) == 0x0 && 3661 sys_reg_Op1(id) == 0x0 && 3662 (sys_reg_CRm(id) == 0 || 3663 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3664 } 3665 3666 /* 3667 * With CRm == 0, reg should be one of : 3668 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3669 */ 3670 static inline int emulate_id_reg(u32 id, u64 *valp) 3671 { 3672 switch (id) { 3673 case SYS_MIDR_EL1: 3674 *valp = read_cpuid_id(); 3675 break; 3676 case SYS_MPIDR_EL1: 3677 *valp = SYS_MPIDR_SAFE_VAL; 3678 break; 3679 case SYS_REVIDR_EL1: 3680 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3681 *valp = 0; 3682 break; 3683 default: 3684 return -EINVAL; 3685 } 3686 3687 return 0; 3688 } 3689 3690 static int emulate_sys_reg(u32 id, u64 *valp) 3691 { 3692 struct arm64_ftr_reg *regp; 3693 3694 if (!is_emulated(id)) 3695 return -EINVAL; 3696 3697 if (sys_reg_CRm(id) == 0) 3698 return emulate_id_reg(id, valp); 3699 3700 regp = get_arm64_ftr_reg_nowarn(id); 3701 if (regp) 3702 *valp = arm64_ftr_reg_user_value(regp); 3703 else 3704 /* 3705 * The untracked registers are either IMPLEMENTATION DEFINED 3706 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3707 */ 3708 *valp = 0; 3709 return 0; 3710 } 3711 3712 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3713 { 3714 int rc; 3715 u64 val; 3716 3717 rc = emulate_sys_reg(sys_reg, &val); 3718 if (!rc) { 3719 pt_regs_write_reg(regs, rt, val); 3720 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3721 } 3722 return rc; 3723 } 3724 3725 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3726 { 3727 u32 sys_reg, rt; 3728 3729 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3730 return false; 3731 3732 /* 3733 * sys_reg values are defined as used in mrs/msr instruction. 3734 * shift the imm value to get the encoding. 3735 */ 3736 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3737 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3738 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3739 } 3740 3741 enum mitigation_state arm64_get_meltdown_state(void) 3742 { 3743 if (__meltdown_safe) 3744 return SPECTRE_UNAFFECTED; 3745 3746 if (arm64_kernel_unmapped_at_el0()) 3747 return SPECTRE_MITIGATED; 3748 3749 return SPECTRE_VULNERABLE; 3750 } 3751 3752 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3753 char *buf) 3754 { 3755 switch (arm64_get_meltdown_state()) { 3756 case SPECTRE_UNAFFECTED: 3757 return sprintf(buf, "Not affected\n"); 3758 3759 case SPECTRE_MITIGATED: 3760 return sprintf(buf, "Mitigation: PTI\n"); 3761 3762 default: 3763 return sprintf(buf, "Vulnerable\n"); 3764 } 3765 } 3766