1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 static struct cpuinfo_arm64 boot_cpu_data; 121 122 /* 123 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 124 * ends up in the .bss section where it is initialized in early_map_kernel() 125 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 126 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 127 * may end up generating an incorrect idmap page table attributes. 128 */ 129 bool arm64_use_ng_mappings __read_mostly = false; 130 EXPORT_SYMBOL(arm64_use_ng_mappings); 131 132 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 133 134 /* 135 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 136 * support it? 137 */ 138 static bool __read_mostly allow_mismatched_32bit_el0; 139 140 /* 141 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 142 * seen at least one CPU capable of 32-bit EL0. 143 */ 144 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 145 146 /* 147 * Mask of CPUs supporting 32-bit EL0. 148 * Only valid if arm64_mismatched_32bit_el0 is enabled. 149 */ 150 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 151 152 void dump_cpu_features(void) 153 { 154 /* file-wide pr_fmt adds "CPU features: " prefix */ 155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 156 } 157 158 #define __ARM64_MAX_POSITIVE(reg, field) \ 159 ((reg##_##field##_SIGNED ? \ 160 BIT(reg##_##field##_WIDTH - 1) : \ 161 BIT(reg##_##field##_WIDTH)) - 1) 162 163 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 164 165 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 166 .sys_reg = SYS_##reg, \ 167 .field_pos = reg##_##field##_SHIFT, \ 168 .field_width = reg##_##field##_WIDTH, \ 169 .sign = reg##_##field##_SIGNED, \ 170 .min_field_value = min_value, \ 171 .max_field_value = max_value, 172 173 /* 174 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 175 * an implicit maximum that depends on the sign-ess of the field. 176 * 177 * An unsigned field will be capped at all ones, while a signed field 178 * will be limited to the positive half only. 179 */ 180 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 181 __ARM64_CPUID_FIELDS(reg, field, \ 182 SYS_FIELD_VALUE(reg, field, min_value), \ 183 __ARM64_MAX_POSITIVE(reg, field)) 184 185 /* 186 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 187 * implicit minimal value to max_value. This should be used when 188 * matching a non-implemented property. 189 */ 190 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 191 __ARM64_CPUID_FIELDS(reg, field, \ 192 __ARM64_MIN_NEGATIVE(reg, field), \ 193 SYS_FIELD_VALUE(reg, field, max_value)) 194 195 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 196 { \ 197 .sign = SIGNED, \ 198 .visible = VISIBLE, \ 199 .strict = STRICT, \ 200 .type = TYPE, \ 201 .shift = SHIFT, \ 202 .width = WIDTH, \ 203 .safe_val = SAFE_VAL, \ 204 } 205 206 /* Define a feature with unsigned values */ 207 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 208 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 209 210 /* Define a feature with a signed value */ 211 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 212 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 213 214 #define ARM64_FTR_END \ 215 { \ 216 .width = 0, \ 217 } 218 219 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 220 221 static bool __system_matches_cap(unsigned int n); 222 223 /* 224 * NOTE: Any changes to the visibility of features should be kept in 225 * sync with the documentation of the CPU feature register ABI. 226 */ 227 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 242 ARM64_FTR_END, 243 }; 244 245 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 257 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 266 ARM64_FTR_END, 267 }; 268 269 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_ATS1A_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 278 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 283 ARM64_FTR_END, 284 }; 285 286 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 287 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 289 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 291 ARM64_FTR_END, 292 }; 293 294 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RME_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 303 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 306 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 307 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 312 ARM64_FTR_END, 313 }; 314 315 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 319 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 327 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 328 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 329 ARM64_FTR_END, 330 }; 331 332 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 335 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 336 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 337 ARM64_FTR_END, 338 }; 339 340 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 358 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 360 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 362 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 364 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 365 ARM64_FTR_END, 366 }; 367 368 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 408 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 410 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 412 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 414 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 416 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 417 ARM64_FTR_END, 418 }; 419 420 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 427 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM2_SHIFT, 1, 0), 428 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 429 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 430 ARM64_FTR_END, 431 }; 432 433 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 434 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 437 /* 438 * Page size not being supported at Stage-2 is not fatal. You 439 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 440 * your favourite nesting hypervisor. 441 * 442 * There is a small corner case where the hypervisor explicitly 443 * advertises a given granule size at Stage-2 (value 2) on some 444 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 445 * vCPUs. Although this is not forbidden by the architecture, it 446 * indicates that the hypervisor is being silly (or buggy). 447 * 448 * We make no effort to cope with this and pretend that if these 449 * fields are inconsistent across vCPUs, then it isn't worth 450 * trying to bring KVM up. 451 */ 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 455 /* 456 * We already refuse to boot CPUs that don't support our configured 457 * page size, so we can only detect mismatches for a page size other 458 * than the one we're currently using. Unfortunately, SoCs like this 459 * exist in the wild so, even though we don't like it, we'll have to go 460 * along with it and treat them as non-strict. 461 */ 462 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 463 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 465 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 467 /* Linux shouldn't care about secure memory */ 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 471 /* 472 * Differing PARange is fine as long as all peripherals and memory are mapped 473 * within the minimum PARange of all CPUs 474 */ 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 476 ARM64_FTR_END, 477 }; 478 479 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 494 ARM64_FTR_END, 495 }; 496 497 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 513 ARM64_FTR_END, 514 }; 515 516 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 517 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 518 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 522 ARM64_FTR_END, 523 }; 524 525 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 526 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static const struct arm64_ftr_bits ftr_ctr[] = { 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 535 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 536 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 537 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 538 /* 539 * Linux can handle differing I-cache policies. Userspace JITs will 540 * make use of *minLine. 541 * If we have differing I-cache policies, report it as the weakest - VIPT. 542 */ 543 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 544 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 545 ARM64_FTR_END, 546 }; 547 548 static struct arm64_ftr_override __ro_after_init no_override = { }; 549 550 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 551 .name = "SYS_CTR_EL0", 552 .ftr_bits = ftr_ctr, 553 .override = &no_override, 554 }; 555 556 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 557 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 562 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 564 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 565 ARM64_FTR_END, 566 }; 567 568 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 569 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 574 /* 575 * We can instantiate multiple PMU instances with different levels 576 * of support. 577 */ 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 580 ARM64_FTR_END, 581 }; 582 583 static const struct arm64_ftr_bits ftr_mvfr0[] = { 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 592 ARM64_FTR_END, 593 }; 594 595 static const struct arm64_ftr_bits ftr_mvfr1[] = { 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 604 ARM64_FTR_END, 605 }; 606 607 static const struct arm64_ftr_bits ftr_mvfr2[] = { 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 610 ARM64_FTR_END, 611 }; 612 613 static const struct arm64_ftr_bits ftr_dczid[] = { 614 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 615 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 616 ARM64_FTR_END, 617 }; 618 619 static const struct arm64_ftr_bits ftr_gmid[] = { 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 621 ARM64_FTR_END, 622 }; 623 624 static const struct arm64_ftr_bits ftr_id_isar0[] = { 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_isar5[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 642 ARM64_FTR_END, 643 }; 644 645 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 653 654 /* 655 * SpecSEI = 1 indicates that the PE might generate an SError on an 656 * external abort on speculative read. It is safe to assume that an 657 * SError might be generated than it will not be. Hence it has been 658 * classified as FTR_HIGHER_SAFE. 659 */ 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 661 ARM64_FTR_END, 662 }; 663 664 static const struct arm64_ftr_bits ftr_id_isar4[] = { 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 673 ARM64_FTR_END, 674 }; 675 676 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 678 ARM64_FTR_END, 679 }; 680 681 static const struct arm64_ftr_bits ftr_id_isar6[] = { 682 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 689 ARM64_FTR_END, 690 }; 691 692 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 699 ARM64_FTR_END, 700 }; 701 702 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 711 ARM64_FTR_END, 712 }; 713 714 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 715 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 717 ARM64_FTR_END, 718 }; 719 720 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 721 /* [31:28] TraceFilt */ 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 729 ARM64_FTR_END, 730 }; 731 732 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 733 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 734 ARM64_FTR_END, 735 }; 736 737 static const struct arm64_ftr_bits ftr_mpamidr[] = { 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 742 ARM64_FTR_END, 743 }; 744 745 /* 746 * Common ftr bits for a 32bit register with all hidden, strict 747 * attributes, with 4bit feature fields and a default safe value of 748 * 0. Covers the following 32bit registers: 749 * id_isar[1-3], id_mmfr[1-3] 750 */ 751 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 756 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 757 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 758 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 759 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 760 ARM64_FTR_END, 761 }; 762 763 /* Table for a single 32bit feature value */ 764 static const struct arm64_ftr_bits ftr_single32[] = { 765 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 766 ARM64_FTR_END, 767 }; 768 769 static const struct arm64_ftr_bits ftr_raz[] = { 770 ARM64_FTR_END, 771 }; 772 773 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 774 .sys_id = id, \ 775 .reg = &(struct arm64_ftr_reg){ \ 776 .name = id_str, \ 777 .override = (ovr), \ 778 .ftr_bits = &((table)[0]), \ 779 }} 780 781 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 782 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 783 784 #define ARM64_FTR_REG(id, table) \ 785 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 786 787 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 788 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 789 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 790 struct arm64_ftr_override __read_mostly id_aa64mmfr4_override; 791 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 792 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 793 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 794 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 795 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 796 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 797 798 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 799 800 static const struct __ftr_reg_entry { 801 u32 sys_id; 802 struct arm64_ftr_reg *reg; 803 } arm64_ftr_regs[] = { 804 805 /* Op1 = 0, CRn = 0, CRm = 1 */ 806 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 807 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 808 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 809 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 810 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 811 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 812 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 813 814 /* Op1 = 0, CRn = 0, CRm = 2 */ 815 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 816 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 817 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 818 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 819 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 820 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 821 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 822 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 823 824 /* Op1 = 0, CRn = 0, CRm = 3 */ 825 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 826 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 827 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 828 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 829 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 830 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 831 832 /* Op1 = 0, CRn = 0, CRm = 4 */ 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 834 &id_aa64pfr0_override), 835 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 836 &id_aa64pfr1_override), 837 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 839 &id_aa64zfr0_override), 840 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 841 &id_aa64smfr0_override), 842 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 843 844 /* Op1 = 0, CRn = 0, CRm = 5 */ 845 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 846 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 847 848 /* Op1 = 0, CRn = 0, CRm = 6 */ 849 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 850 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 851 &id_aa64isar1_override), 852 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 853 &id_aa64isar2_override), 854 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 855 856 /* Op1 = 0, CRn = 0, CRm = 7 */ 857 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 858 &id_aa64mmfr0_override), 859 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 860 &id_aa64mmfr1_override), 861 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 862 &id_aa64mmfr2_override), 863 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 864 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4, 865 &id_aa64mmfr4_override), 866 867 /* Op1 = 0, CRn = 10, CRm = 4 */ 868 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 869 870 /* Op1 = 1, CRn = 0, CRm = 0 */ 871 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 872 873 /* Op1 = 3, CRn = 0, CRm = 0 */ 874 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 875 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 876 877 /* Op1 = 3, CRn = 14, CRm = 0 */ 878 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 879 }; 880 881 static int search_cmp_ftr_reg(const void *id, const void *regp) 882 { 883 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 884 } 885 886 /* 887 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 888 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 889 * ascending order of sys_id, we use binary search to find a matching 890 * entry. 891 * 892 * returns - Upon success, matching ftr_reg entry for id. 893 * - NULL on failure. It is up to the caller to decide 894 * the impact of a failure. 895 */ 896 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 897 { 898 const struct __ftr_reg_entry *ret; 899 900 ret = bsearch((const void *)(unsigned long)sys_id, 901 arm64_ftr_regs, 902 ARRAY_SIZE(arm64_ftr_regs), 903 sizeof(arm64_ftr_regs[0]), 904 search_cmp_ftr_reg); 905 if (ret) 906 return ret->reg; 907 return NULL; 908 } 909 910 /* 911 * get_arm64_ftr_reg - Looks up a feature register entry using 912 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 913 * 914 * returns - Upon success, matching ftr_reg entry for id. 915 * - NULL on failure but with an WARN_ON(). 916 */ 917 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 918 { 919 struct arm64_ftr_reg *reg; 920 921 reg = get_arm64_ftr_reg_nowarn(sys_id); 922 923 /* 924 * Requesting a non-existent register search is an error. Warn 925 * and let the caller handle it. 926 */ 927 WARN_ON(!reg); 928 return reg; 929 } 930 931 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 932 s64 ftr_val) 933 { 934 u64 mask = arm64_ftr_mask(ftrp); 935 936 reg &= ~mask; 937 reg |= (ftr_val << ftrp->shift) & mask; 938 return reg; 939 } 940 941 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 942 s64 cur) 943 { 944 s64 ret = 0; 945 946 switch (ftrp->type) { 947 case FTR_EXACT: 948 ret = ftrp->safe_val; 949 break; 950 case FTR_LOWER_SAFE: 951 ret = min(new, cur); 952 break; 953 case FTR_HIGHER_OR_ZERO_SAFE: 954 if (!cur || !new) 955 break; 956 fallthrough; 957 case FTR_HIGHER_SAFE: 958 ret = max(new, cur); 959 break; 960 default: 961 BUG(); 962 } 963 964 return ret; 965 } 966 967 u64 arm64_ftr_reg_override(u32 sys_id, u64 val) 968 { 969 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_id); 970 const struct arm64_ftr_bits *ftrp; 971 972 if (!reg || !reg->override->mask) 973 return val; 974 975 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 976 u64 ftr_mask = arm64_ftr_mask(ftrp); 977 s64 ftr_new, ftr_ovr; 978 979 if ((ftr_mask & reg->override->mask) != ftr_mask) 980 continue; 981 982 ftr_new = arm64_ftr_value(ftrp, val); 983 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 984 985 /* An unsafe override is left for init_cpu_ftr_reg() to remove. */ 986 if (arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new) == ftr_ovr) 987 val = arm64_ftr_set_value(ftrp, val, ftr_ovr); 988 } 989 990 return val; 991 } 992 993 void __init validate_ftr_regs(void) 994 { 995 unsigned int i; 996 997 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 998 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 999 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 1000 unsigned int j = 0; 1001 1002 /* 1003 * Features here must be sorted in descending order with respect 1004 * to their shift values and should not overlap with each other. 1005 */ 1006 for (; ftr_bits->width != 0; ftr_bits++, j++) { 1007 unsigned int width = ftr_reg->ftr_bits[j].width; 1008 unsigned int shift = ftr_reg->ftr_bits[j].shift; 1009 unsigned int prev_shift; 1010 1011 WARN((shift + width) > 64, 1012 "%s has invalid feature at shift %d\n", 1013 ftr_reg->name, shift); 1014 1015 /* 1016 * Skip the first feature. There is nothing to 1017 * compare against for now. 1018 */ 1019 if (j == 0) 1020 continue; 1021 1022 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 1023 WARN((shift + width) > prev_shift, 1024 "%s has feature overlap at shift %d\n", 1025 ftr_reg->name, shift); 1026 } 1027 1028 /* 1029 * Skip the first register. There is nothing to 1030 * compare against for now. 1031 */ 1032 if (i == 0) 1033 continue; 1034 /* 1035 * Registers here must be sorted in ascending order with respect 1036 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1037 * to work correctly. 1038 */ 1039 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1040 } 1041 } 1042 1043 /* 1044 * Initialise the CPU feature register from Boot CPU values. 1045 * Also initialises the strict_mask for the register. 1046 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1047 * RES0 for the system-wide value, and must strictly match. 1048 * @new has been through arm64_ftr_reg_override(), so a valid override is 1049 * already applied to it. Only an unsafe one is left to remove here. 1050 */ 1051 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1052 { 1053 u64 val = 0; 1054 u64 strict_mask = ~0x0ULL; 1055 u64 user_mask = 0; 1056 u64 valid_mask = 0; 1057 1058 const struct arm64_ftr_bits *ftrp; 1059 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1060 1061 if (!reg) 1062 return; 1063 1064 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1065 u64 ftr_mask = arm64_ftr_mask(ftrp); 1066 s64 ftr_new = arm64_ftr_value(ftrp, new); 1067 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1068 1069 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1070 char *str = "forced"; 1071 1072 if (arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new) != ftr_ovr) { 1073 /* Unsafe, remove the override */ 1074 reg->override->mask &= ~ftr_mask; 1075 reg->override->val &= ~ftr_mask; 1076 str = "ignoring override"; 1077 } 1078 1079 pr_warn("%s[%d:%d]: %s to %llx\n", 1080 reg->name, 1081 ftrp->shift + ftrp->width - 1, 1082 ftrp->shift, str, 1083 ftr_ovr & (BIT(ftrp->width) - 1)); 1084 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1085 reg->override->val &= ~ftr_mask; 1086 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1087 reg->name, 1088 ftrp->shift + ftrp->width - 1, 1089 ftrp->shift); 1090 } 1091 1092 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1093 1094 valid_mask |= ftr_mask; 1095 if (!ftrp->strict) 1096 strict_mask &= ~ftr_mask; 1097 if (ftrp->visible) 1098 user_mask |= ftr_mask; 1099 else 1100 reg->user_val = arm64_ftr_set_value(ftrp, 1101 reg->user_val, 1102 ftrp->safe_val); 1103 } 1104 1105 val &= valid_mask; 1106 1107 reg->sys_val = val; 1108 reg->strict_mask = strict_mask; 1109 reg->user_mask = user_mask; 1110 } 1111 1112 extern const struct arm64_cpu_capabilities arm64_errata[]; 1113 static const struct arm64_cpu_capabilities arm64_features[]; 1114 1115 static void __init 1116 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1117 { 1118 for (; caps->matches; caps++) { 1119 if (WARN(caps->capability >= ARM64_NCAPS, 1120 "Invalid capability %d\n", caps->capability)) 1121 continue; 1122 if (WARN(cpucap_ptrs[caps->capability], 1123 "Duplicate entry for capability %d\n", 1124 caps->capability)) 1125 continue; 1126 cpucap_ptrs[caps->capability] = caps; 1127 } 1128 } 1129 1130 static void __init init_cpucap_indirect_list(void) 1131 { 1132 init_cpucap_indirect_list_from_array(arm64_features); 1133 init_cpucap_indirect_list_from_array(arm64_errata); 1134 } 1135 1136 static void __init setup_boot_cpu_capabilities(void); 1137 1138 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1139 { 1140 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1141 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1142 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1143 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1144 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1145 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1146 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1147 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1148 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1149 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1150 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1151 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1152 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1153 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1154 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1155 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1156 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1157 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1158 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1159 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1160 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1161 } 1162 1163 #ifdef CONFIG_ARM64_PSEUDO_NMI 1164 static bool enable_pseudo_nmi; 1165 1166 static int __init early_enable_pseudo_nmi(char *p) 1167 { 1168 return kstrtobool(p, &enable_pseudo_nmi); 1169 } 1170 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1171 1172 static __init void detect_system_supports_pseudo_nmi(void) 1173 { 1174 struct device_node *np; 1175 1176 if (!enable_pseudo_nmi) 1177 return; 1178 1179 /* 1180 * Detect broken MediaTek firmware that doesn't properly save and 1181 * restore GIC priorities. 1182 */ 1183 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1184 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1185 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1186 enable_pseudo_nmi = false; 1187 } 1188 of_node_put(np); 1189 } 1190 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1191 static inline void detect_system_supports_pseudo_nmi(void) { } 1192 #endif 1193 1194 static bool detect_ftr_has_mpam(void) 1195 { 1196 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1197 u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1198 1199 return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); 1200 } 1201 1202 static void __init init_cpu_features(void) 1203 { 1204 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 1205 1206 /* 1207 * We keep a copy of the boot CPU registers so that physical hotplug 1208 * of CPU 0 can still be properly checked. 1209 */ 1210 boot_cpu_data = *info; 1211 1212 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1213 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1214 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1215 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1216 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1217 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1218 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1219 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1220 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1221 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1222 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1223 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1224 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1225 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1226 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1227 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1228 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1229 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1230 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1231 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1232 1233 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1234 init_32bit_cpu_features(&info->aarch32); 1235 1236 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1237 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1238 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1239 1240 vec_init_vq_map(ARM64_VEC_SVE); 1241 1242 cpacr_restore(cpacr); 1243 } 1244 1245 if (IS_ENABLED(CONFIG_ARM64_SME) && 1246 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1247 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1248 1249 vec_init_vq_map(ARM64_VEC_SME); 1250 1251 cpacr_restore(cpacr); 1252 } 1253 1254 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0) || id_aa64pfr1_mpamfrac(info->reg_id_aa64pfr1)) 1255 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1256 1257 if (IS_ENABLED(CONFIG_ARM64_MTE) && id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1258 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1259 } 1260 1261 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1262 { 1263 const struct arm64_ftr_bits *ftrp; 1264 1265 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1266 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1267 s64 ftr_new = arm64_ftr_value(ftrp, new); 1268 1269 if (ftr_cur == ftr_new) 1270 continue; 1271 /* Find a safe value */ 1272 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1273 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1274 } 1275 1276 } 1277 1278 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1279 { 1280 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1281 1282 if (!regp) 1283 return 0; 1284 1285 update_cpu_ftr_reg(regp, val); 1286 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1287 return 0; 1288 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1289 regp->name, boot, cpu, val); 1290 return 1; 1291 } 1292 1293 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1294 { 1295 const struct arm64_ftr_bits *ftrp; 1296 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1297 1298 if (!regp) 1299 return; 1300 1301 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1302 if (ftrp->shift == field) { 1303 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1304 break; 1305 } 1306 } 1307 1308 /* Bogus field? */ 1309 WARN_ON(!ftrp->width); 1310 } 1311 1312 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1313 struct cpuinfo_arm64 *boot) 1314 { 1315 static bool boot_cpu_32bit_regs_overridden = false; 1316 1317 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1318 return; 1319 1320 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1321 return; 1322 1323 boot->aarch32 = info->aarch32; 1324 init_32bit_cpu_features(&boot->aarch32); 1325 boot_cpu_32bit_regs_overridden = true; 1326 } 1327 1328 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1329 struct cpuinfo_32bit *boot) 1330 { 1331 int taint = 0; 1332 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1333 1334 /* 1335 * If we don't have AArch32 at EL1, then relax the strictness of 1336 * EL1-dependent register fields to avoid spurious sanity check fails. 1337 */ 1338 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1339 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1340 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1341 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1342 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1343 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1344 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1345 } 1346 1347 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1348 info->reg_id_dfr0, boot->reg_id_dfr0); 1349 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1350 info->reg_id_dfr1, boot->reg_id_dfr1); 1351 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1352 info->reg_id_isar0, boot->reg_id_isar0); 1353 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1354 info->reg_id_isar1, boot->reg_id_isar1); 1355 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1356 info->reg_id_isar2, boot->reg_id_isar2); 1357 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1358 info->reg_id_isar3, boot->reg_id_isar3); 1359 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1360 info->reg_id_isar4, boot->reg_id_isar4); 1361 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1362 info->reg_id_isar5, boot->reg_id_isar5); 1363 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1364 info->reg_id_isar6, boot->reg_id_isar6); 1365 1366 /* 1367 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1368 * ACTLR formats could differ across CPUs and therefore would have to 1369 * be trapped for virtualization anyway. 1370 */ 1371 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1372 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1373 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1374 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1375 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1376 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1377 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1378 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1379 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1380 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1381 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1382 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1383 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1384 info->reg_id_pfr0, boot->reg_id_pfr0); 1385 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1386 info->reg_id_pfr1, boot->reg_id_pfr1); 1387 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1388 info->reg_id_pfr2, boot->reg_id_pfr2); 1389 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1390 info->reg_mvfr0, boot->reg_mvfr0); 1391 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1392 info->reg_mvfr1, boot->reg_mvfr1); 1393 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1394 info->reg_mvfr2, boot->reg_mvfr2); 1395 1396 return taint; 1397 } 1398 1399 u64 read_sanitised_ftr_reg(u32 id) 1400 { 1401 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1402 1403 if (!regp) 1404 return 0; 1405 return regp->sys_val; 1406 } 1407 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1408 1409 #define read_sysreg_case(r) \ 1410 case r: val = read_sysreg_s(r); break; 1411 1412 /* 1413 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1414 * Read the system register on the current CPU 1415 */ 1416 u64 __read_sysreg_by_encoding(u32 sys_id) 1417 { 1418 struct arm64_ftr_reg *regp; 1419 u64 val; 1420 1421 switch (sys_id) { 1422 read_sysreg_case(SYS_ID_PFR0_EL1); 1423 read_sysreg_case(SYS_ID_PFR1_EL1); 1424 read_sysreg_case(SYS_ID_PFR2_EL1); 1425 read_sysreg_case(SYS_ID_DFR0_EL1); 1426 read_sysreg_case(SYS_ID_DFR1_EL1); 1427 read_sysreg_case(SYS_ID_MMFR0_EL1); 1428 read_sysreg_case(SYS_ID_MMFR1_EL1); 1429 read_sysreg_case(SYS_ID_MMFR2_EL1); 1430 read_sysreg_case(SYS_ID_MMFR3_EL1); 1431 read_sysreg_case(SYS_ID_MMFR4_EL1); 1432 read_sysreg_case(SYS_ID_MMFR5_EL1); 1433 read_sysreg_case(SYS_ID_ISAR0_EL1); 1434 read_sysreg_case(SYS_ID_ISAR1_EL1); 1435 read_sysreg_case(SYS_ID_ISAR2_EL1); 1436 read_sysreg_case(SYS_ID_ISAR3_EL1); 1437 read_sysreg_case(SYS_ID_ISAR4_EL1); 1438 read_sysreg_case(SYS_ID_ISAR5_EL1); 1439 read_sysreg_case(SYS_ID_ISAR6_EL1); 1440 read_sysreg_case(SYS_MVFR0_EL1); 1441 read_sysreg_case(SYS_MVFR1_EL1); 1442 read_sysreg_case(SYS_MVFR2_EL1); 1443 1444 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1445 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1446 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1447 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1448 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1449 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1450 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1451 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1452 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1453 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1454 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1455 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1456 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1457 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1458 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1459 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1460 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1461 1462 read_sysreg_case(SYS_CNTFRQ_EL0); 1463 read_sysreg_case(SYS_CTR_EL0); 1464 read_sysreg_case(SYS_DCZID_EL0); 1465 1466 default: 1467 BUG(); 1468 return 0; 1469 } 1470 1471 regp = get_arm64_ftr_reg(sys_id); 1472 if (regp) { 1473 val &= ~regp->override->mask; 1474 val |= (regp->override->val & regp->override->mask); 1475 } 1476 1477 return val; 1478 } 1479 1480 #include <linux/irqchip/arm-gic-v3.h> 1481 1482 static bool 1483 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1484 { 1485 return true; 1486 } 1487 1488 static bool 1489 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1490 { 1491 int val, min, max; 1492 u64 tmp; 1493 1494 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1495 entry->field_width, 1496 entry->sign); 1497 1498 tmp = entry->min_field_value; 1499 tmp <<= entry->field_pos; 1500 1501 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1502 entry->field_width, 1503 entry->sign); 1504 1505 tmp = entry->max_field_value; 1506 tmp <<= entry->field_pos; 1507 1508 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1509 entry->field_width, 1510 entry->sign); 1511 1512 return val >= min && val <= max; 1513 } 1514 1515 static u64 1516 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1517 { 1518 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1519 if (scope == SCOPE_SYSTEM) 1520 return read_sanitised_ftr_reg(entry->sys_reg); 1521 else 1522 return __read_sysreg_by_encoding(entry->sys_reg); 1523 } 1524 1525 static bool 1526 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1527 { 1528 int mask; 1529 struct arm64_ftr_reg *regp; 1530 u64 val = read_scoped_sysreg(entry, scope); 1531 1532 regp = get_arm64_ftr_reg(entry->sys_reg); 1533 if (!regp) 1534 return false; 1535 1536 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1537 entry->field_pos, 1538 entry->field_width); 1539 if (!mask) 1540 return false; 1541 1542 return feature_matches(val, entry); 1543 } 1544 1545 static bool 1546 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1547 { 1548 u64 val = read_scoped_sysreg(entry, scope); 1549 return feature_matches(val, entry); 1550 } 1551 1552 const struct cpumask *system_32bit_el0_cpumask(void) 1553 { 1554 if (!system_supports_32bit_el0()) 1555 return cpu_none_mask; 1556 1557 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1558 return cpu_32bit_el0_mask; 1559 1560 return cpu_possible_mask; 1561 } 1562 1563 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1564 { 1565 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1566 } 1567 1568 static int __init parse_32bit_el0_param(char *str) 1569 { 1570 allow_mismatched_32bit_el0 = true; 1571 return 0; 1572 } 1573 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1574 1575 static ssize_t aarch32_el0_show(struct device *dev, 1576 struct device_attribute *attr, char *buf) 1577 { 1578 const struct cpumask *mask = system_32bit_el0_cpumask(); 1579 1580 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1581 } 1582 static const DEVICE_ATTR_RO(aarch32_el0); 1583 1584 static int __init aarch32_el0_sysfs_init(void) 1585 { 1586 struct device *dev_root; 1587 int ret = 0; 1588 1589 if (!allow_mismatched_32bit_el0) 1590 return 0; 1591 1592 dev_root = bus_get_dev_root(&cpu_subsys); 1593 if (dev_root) { 1594 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1595 put_device(dev_root); 1596 } 1597 return ret; 1598 } 1599 device_initcall(aarch32_el0_sysfs_init); 1600 1601 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1602 { 1603 if (!has_cpuid_feature(entry, scope)) 1604 return allow_mismatched_32bit_el0; 1605 1606 if (scope == SCOPE_SYSTEM) 1607 pr_info("detected: 32-bit EL0 Support\n"); 1608 1609 return true; 1610 } 1611 1612 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1613 { 1614 bool has_sre; 1615 1616 if (!has_cpuid_feature(entry, scope)) 1617 return false; 1618 1619 has_sre = gic_enable_sre(); 1620 if (!has_sre) 1621 pr_warn_once("%s present but disabled by higher exception level\n", 1622 entry->desc); 1623 1624 return has_sre; 1625 } 1626 1627 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1628 int scope) 1629 { 1630 u64 ctr; 1631 1632 if (scope == SCOPE_SYSTEM) 1633 ctr = arm64_ftr_reg_ctrel0.sys_val; 1634 else 1635 ctr = read_cpuid_effective_cachetype(); 1636 1637 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1638 } 1639 1640 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1641 { 1642 /* 1643 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1644 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1645 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1646 * value. 1647 */ 1648 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1649 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1650 } 1651 1652 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1653 int scope) 1654 { 1655 u64 ctr; 1656 1657 if (scope == SCOPE_SYSTEM) 1658 ctr = arm64_ftr_reg_ctrel0.sys_val; 1659 else 1660 ctr = read_cpuid_cachetype(); 1661 1662 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1663 } 1664 1665 static bool __maybe_unused 1666 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1667 { 1668 /* 1669 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1670 * may share TLB entries with a CPU stuck in the crashed 1671 * kernel. 1672 */ 1673 if (is_kdump_kernel()) 1674 return false; 1675 1676 if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) 1677 return false; 1678 1679 return has_cpuid_feature(entry, scope); 1680 } 1681 1682 static bool __meltdown_safe = true; 1683 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1684 1685 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1686 int scope) 1687 { 1688 /* List of CPUs that are not vulnerable and don't need KPTI */ 1689 static const struct midr_range kpti_safe_list[] = { 1690 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1691 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1692 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1693 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1694 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1695 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1696 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1697 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1698 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1699 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1700 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1701 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1702 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1703 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1704 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1705 { /* sentinel */ } 1706 }; 1707 char const *str = "kpti command line option"; 1708 bool meltdown_safe; 1709 1710 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1711 1712 /* Defer to CPU feature registers */ 1713 if (has_cpuid_feature(entry, scope)) 1714 meltdown_safe = true; 1715 1716 if (!meltdown_safe) 1717 __meltdown_safe = false; 1718 1719 /* 1720 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1721 * ThunderX leads to apparent I-cache corruption of kernel text, which 1722 * ends as well as you might imagine. Don't even try. We cannot rely 1723 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1724 * because cpucap detection order may change. However, since we know 1725 * affected CPUs are always in a homogeneous configuration, it is 1726 * safe to rely on this_cpu_has_cap() here. 1727 */ 1728 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1729 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1730 __kpti_forced = -1; 1731 } 1732 1733 /* Useful for KASLR robustness */ 1734 if (kaslr_enabled() && kaslr_requires_kpti()) { 1735 if (!__kpti_forced) { 1736 str = "KASLR"; 1737 __kpti_forced = 1; 1738 } 1739 } 1740 1741 if (cpu_mitigations_off() && !__kpti_forced) { 1742 str = "mitigations=off"; 1743 __kpti_forced = -1; 1744 } 1745 1746 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1747 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1748 return false; 1749 } 1750 1751 /* Forced? */ 1752 if (__kpti_forced) { 1753 pr_info_once("kernel page table isolation forced %s by %s\n", 1754 __kpti_forced > 0 ? "ON" : "OFF", str); 1755 return __kpti_forced > 0; 1756 } 1757 1758 return !meltdown_safe; 1759 } 1760 1761 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1762 { 1763 /* 1764 * Although the Apple M2 family appears to support NV1, the 1765 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1766 * that it doesn't support NV1 at all. 1767 */ 1768 static const struct midr_range nv1_ni_list[] = { 1769 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1770 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1771 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1772 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1773 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1774 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1775 {} 1776 }; 1777 1778 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1779 !(has_cpuid_feature(entry, scope) || 1780 is_midr_in_range_list(nv1_ni_list))); 1781 } 1782 1783 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) 1784 static bool has_lpa2_at_stage1(u64 mmfr0) 1785 { 1786 unsigned int tgran; 1787 1788 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1789 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1790 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1791 } 1792 1793 static bool has_lpa2_at_stage2(u64 mmfr0) 1794 { 1795 unsigned int tgran; 1796 1797 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1798 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1799 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1800 } 1801 1802 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1803 { 1804 u64 mmfr0; 1805 1806 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1807 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1808 } 1809 #else 1810 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1811 { 1812 return false; 1813 } 1814 #endif 1815 1816 #ifdef CONFIG_HW_PERF_EVENTS 1817 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1818 { 1819 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1820 unsigned int pmuver; 1821 1822 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1823 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1824 1825 return pmuv3_implemented(pmuver); 1826 } 1827 #endif 1828 1829 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1830 { 1831 if (__this_cpu_read(this_cpu_vector) == vectors) { 1832 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1833 1834 __this_cpu_write(this_cpu_vector, v); 1835 } 1836 1837 } 1838 1839 static int __init parse_kpti(char *str) 1840 { 1841 bool enabled; 1842 int ret = kstrtobool(str, &enabled); 1843 1844 if (ret) 1845 return ret; 1846 1847 __kpti_forced = enabled ? 1 : -1; 1848 return 0; 1849 } 1850 early_param("kpti", parse_kpti); 1851 1852 #ifdef CONFIG_ARM64_HW_AFDBM 1853 static struct cpumask dbm_cpus __read_mostly; 1854 1855 static inline void __cpu_enable_hw_dbm(void) 1856 { 1857 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1858 1859 write_sysreg(tcr, tcr_el1); 1860 isb(); 1861 local_flush_tlb_all(); 1862 } 1863 1864 static bool cpu_has_broken_dbm(void) 1865 { 1866 /* List of CPUs which have broken DBM support. */ 1867 static const struct midr_range cpus[] = { 1868 #ifdef CONFIG_ARM64_ERRATUM_1024718 1869 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1870 /* Kryo4xx Silver (rdpe => r1p0) */ 1871 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1872 #endif 1873 #ifdef CONFIG_ARM64_ERRATUM_2051678 1874 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1875 #endif 1876 {}, 1877 }; 1878 1879 return is_midr_in_range_list(cpus); 1880 } 1881 1882 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1883 { 1884 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1885 !cpu_has_broken_dbm(); 1886 } 1887 1888 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1889 { 1890 if (cpu_can_use_dbm(cap)) { 1891 __cpu_enable_hw_dbm(); 1892 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 1893 } 1894 } 1895 1896 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1897 int __unused) 1898 { 1899 /* 1900 * DBM is a non-conflicting feature. i.e, the kernel can safely 1901 * run a mix of CPUs with and without the feature. So, we 1902 * unconditionally enable the capability to allow any late CPU 1903 * to use the feature. We only enable the control bits on the 1904 * CPU, if it is supported. 1905 */ 1906 1907 return true; 1908 } 1909 1910 #endif 1911 1912 #ifdef CONFIG_ARM64_AMU_EXTN 1913 1914 /* 1915 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1916 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1917 * information regarding all the events that it supports. When a CPU bit is 1918 * set in the cpumask, the user of this feature can only rely on the presence 1919 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1920 * counters are enabled or access to these counters is enabled by code 1921 * executed at higher exception levels (firmware). 1922 */ 1923 static struct cpumask amu_cpus __read_mostly; 1924 1925 bool cpu_has_amu_feat(int cpu) 1926 { 1927 return cpumask_test_cpu(cpu, &amu_cpus); 1928 } 1929 1930 int get_cpu_with_amu_feat(void) 1931 { 1932 return cpumask_any(&amu_cpus); 1933 } 1934 1935 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1936 { 1937 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1938 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1939 1940 /* 0 reference values signal broken/disabled counters */ 1941 if (!this_cpu_has_cap(ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT)) 1942 update_freq_counters_refs(); 1943 } 1944 } 1945 1946 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1947 int __unused) 1948 { 1949 /* 1950 * The AMU extension is a non-conflicting feature: the kernel can 1951 * safely run a mix of CPUs with and without support for the 1952 * activity monitors extension. Therefore, unconditionally enable 1953 * the capability to allow any late CPU to use the feature. 1954 * 1955 * With this feature unconditionally enabled, the cpu_enable 1956 * function will be called for all CPUs that match the criteria, 1957 * including secondary and hotplugged, marking this feature as 1958 * present on that respective CPU. The enable function will also 1959 * print a detection message. 1960 */ 1961 1962 return true; 1963 } 1964 #else 1965 int get_cpu_with_amu_feat(void) 1966 { 1967 return nr_cpu_ids; 1968 } 1969 #endif 1970 1971 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1972 { 1973 return is_kernel_in_hyp_mode(); 1974 } 1975 1976 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1977 { 1978 /* 1979 * Copy register values that aren't redirected by hardware. 1980 * 1981 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1982 * this value to tpidr_el2 before we patch the code. Once we've done 1983 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1984 * do anything here. 1985 */ 1986 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1987 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1988 } 1989 1990 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 1991 int scope) 1992 { 1993 if (kvm_get_mode() != KVM_MODE_NV) 1994 return false; 1995 1996 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 1997 pr_warn("unavailable: %s\n", cap->desc); 1998 return false; 1999 } 2000 2001 return true; 2002 } 2003 2004 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2005 int __unused) 2006 { 2007 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2008 } 2009 2010 bool cpu_supports_bbml3(void) 2011 { 2012 /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ 2013 static const struct midr_range supports_bbml3_list[] = { 2014 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2015 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2016 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2017 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2018 MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL), 2019 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2020 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2021 MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), 2022 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 2023 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 2024 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 2025 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 2026 MIDR_ALL_VERSIONS(MIDR_C1_NANO), 2027 MIDR_ALL_VERSIONS(MIDR_C1_PRO), 2028 /* Erratum 3683289 fixed in r1p1 */ 2029 MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), 2030 MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), 2031 {} 2032 }; 2033 u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); 2034 2035 if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) 2036 return true; 2037 2038 return is_midr_in_range_list(supports_bbml3_list); 2039 } 2040 2041 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) 2042 { 2043 return cpu_supports_bbml3(); 2044 } 2045 2046 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2047 { 2048 /* 2049 * We modify PSTATE. This won't work from irq context as the PSTATE 2050 * is discarded once we return from the exception. 2051 */ 2052 WARN_ON_ONCE(in_interrupt()); 2053 2054 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2055 set_pstate_pan(1); 2056 } 2057 2058 #ifdef CONFIG_ARM64_RAS_EXTN 2059 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2060 { 2061 /* Firmware may have left a deferred SError in this register. */ 2062 write_sysreg_s(0, SYS_DISR_EL1); 2063 } 2064 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2065 { 2066 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2067 { 2068 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2069 }, 2070 { 2071 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2072 }, 2073 { 2074 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2075 }, 2076 }; 2077 2078 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2079 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2080 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2081 } 2082 #endif /* CONFIG_ARM64_RAS_EXTN */ 2083 2084 #ifdef CONFIG_ARM64_PTR_AUTH 2085 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2086 { 2087 int boot_val, sec_val; 2088 2089 /* We don't expect to be called with SCOPE_SYSTEM */ 2090 WARN_ON(scope == SCOPE_SYSTEM); 2091 /* 2092 * The ptr-auth feature levels are not intercompatible with lower 2093 * levels. Hence we must match ptr-auth feature level of the secondary 2094 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2095 * from the sanitised register whereas direct register read is done for 2096 * the secondary CPUs. 2097 * The sanitised feature state is guaranteed to match that of the 2098 * boot CPU as a mismatched secondary CPU is parked before it gets 2099 * a chance to update the state, with the capability. 2100 */ 2101 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2102 entry->field_pos, entry->sign); 2103 if (scope & SCOPE_BOOT_CPU) 2104 return boot_val >= entry->min_field_value; 2105 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2106 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2107 entry->field_pos, entry->sign); 2108 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2109 } 2110 2111 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2112 int scope) 2113 { 2114 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2115 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2116 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2117 2118 return apa || apa3 || api; 2119 } 2120 2121 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2122 int __unused) 2123 { 2124 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2125 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2126 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2127 2128 return gpa || gpa3 || gpi; 2129 } 2130 #endif /* CONFIG_ARM64_PTR_AUTH */ 2131 2132 #ifdef CONFIG_ARM64_E0PD 2133 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2134 { 2135 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2136 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2137 } 2138 #endif /* CONFIG_ARM64_E0PD */ 2139 2140 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2141 { 2142 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2143 } 2144 2145 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2146 { 2147 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2148 } 2149 2150 #ifdef CONFIG_ARM64_PSEUDO_NMI 2151 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2152 int scope) 2153 { 2154 /* 2155 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2156 * feature, so will be detected earlier. 2157 */ 2158 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2159 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2160 return false; 2161 2162 return enable_pseudo_nmi; 2163 } 2164 2165 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2166 int scope) 2167 { 2168 /* 2169 * If we're not using priority masking then we won't be poking PMR_EL1, 2170 * and there's no need to relax synchronization of writes to it, and 2171 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2172 * that. 2173 * 2174 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2175 * feature, so will be detected earlier. 2176 */ 2177 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2178 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2179 return false; 2180 2181 /* 2182 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2183 * hint for interrupt distribution, a DSB is not necessary when 2184 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2185 * 2186 * Linux itself doesn't use 1:N distribution, so has no need to 2187 * set PMHE. The only reason to have it set is if EL3 requires it 2188 * (and we can't change it). 2189 */ 2190 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2191 } 2192 #endif 2193 2194 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2195 int scope) 2196 { 2197 static const struct midr_range has_vgic_v3[] = { 2198 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2199 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2200 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2201 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2202 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2203 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2204 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2205 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2206 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2207 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2208 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2209 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2210 {}, 2211 }; 2212 struct arm_smccc_res res = {}; 2213 2214 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2215 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2216 if (!is_hyp_mode_available()) 2217 return false; 2218 2219 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2220 return true; 2221 2222 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2223 !is_midr_in_range_list(has_vgic_v3)) 2224 return false; 2225 2226 /* 2227 * pKVM prevents late onlining of CPUs. This means that whatever 2228 * state the capability is in after deprivilege cannot be affected 2229 * by a new CPU booting -- this is garanteed to be a CPU we have 2230 * already seen, and the cap is therefore unchanged. 2231 */ 2232 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2233 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2234 2235 if (is_kernel_in_hyp_mode()) 2236 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2237 else 2238 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2239 2240 if (res.a0 == HVC_STUB_ERR) 2241 return false; 2242 2243 return res.a1 & ICH_VTR_EL2_TDS; 2244 } 2245 2246 #ifdef CONFIG_ARM64_BTI 2247 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2248 { 2249 /* 2250 * Use of X16/X17 for tail-calls and trampolines that jump to 2251 * function entry points using BR is a requirement for 2252 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2253 * So, be strict and forbid other BRs using other registers to 2254 * jump onto a PACIxSP instruction: 2255 */ 2256 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2257 isb(); 2258 } 2259 #endif /* CONFIG_ARM64_BTI */ 2260 2261 #ifdef CONFIG_ARM64_MTE 2262 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2263 { 2264 static bool cleared_zero_page = false; 2265 2266 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2267 2268 mte_cpu_setup(); 2269 2270 /* 2271 * Clear the tags in the zero page. This needs to be done via the 2272 * linear map which has the Tagged attribute. Since this page is 2273 * always mapped as pte_special(), set_pte_at() will not attempt to 2274 * clear the tags or set PG_mte_tagged. 2275 */ 2276 if (!cleared_zero_page) { 2277 cleared_zero_page = true; 2278 mte_clear_page_tags(lm_alias(empty_zero_page)); 2279 } 2280 2281 kasan_init_hw_tags_cpu(); 2282 } 2283 #endif /* CONFIG_ARM64_MTE */ 2284 2285 static void user_feature_fixup(void) 2286 { 2287 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2288 struct arm64_ftr_reg *regp; 2289 2290 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2291 if (regp) 2292 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2293 } 2294 2295 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2296 struct arm64_ftr_reg *regp; 2297 2298 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2299 if (regp) 2300 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2301 } 2302 } 2303 2304 static void elf_hwcap_fixup(void) 2305 { 2306 #ifdef CONFIG_COMPAT 2307 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2308 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2309 #endif /* CONFIG_COMPAT */ 2310 } 2311 2312 #ifdef CONFIG_KVM 2313 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2314 { 2315 return kvm_get_mode() == KVM_MODE_PROTECTED; 2316 } 2317 #endif /* CONFIG_KVM */ 2318 2319 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2320 { 2321 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2322 } 2323 2324 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2325 { 2326 set_pstate_dit(1); 2327 } 2328 2329 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2330 { 2331 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2332 } 2333 2334 #ifdef CONFIG_ARM64_POE 2335 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2336 { 2337 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2338 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2339 } 2340 #endif 2341 2342 #ifdef CONFIG_ARM64_GCS 2343 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2344 { 2345 /* GCSPR_EL0 is always readable */ 2346 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2347 } 2348 #endif 2349 2350 /* Internal helper functions to match cpu capability type */ 2351 static bool 2352 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2353 { 2354 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2355 } 2356 2357 static bool 2358 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2359 { 2360 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2361 } 2362 2363 static bool 2364 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2365 { 2366 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2367 } 2368 2369 static bool 2370 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2371 { 2372 if (!detect_ftr_has_mpam()) 2373 return false; 2374 2375 /* Check firmware actually enabled MPAM on this cpu. */ 2376 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2377 } 2378 2379 static void 2380 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2381 { 2382 int cpu = smp_processor_id(); 2383 u64 regval = 0; 2384 2385 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2386 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2387 2388 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2389 if (cpus_have_cap(ARM64_SME)) 2390 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2391 isb(); 2392 2393 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2394 write_sysreg_s(regval, SYS_MPAM0_EL1); 2395 } 2396 2397 static bool 2398 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2399 { 2400 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2401 2402 return idr & MPAMIDR_EL1_HAS_HCR; 2403 } 2404 2405 static bool 2406 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2407 { 2408 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2409 return false; 2410 2411 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2412 } 2413 2414 static const struct arm64_cpu_capabilities arm64_features[] = { 2415 { 2416 .capability = ARM64_ALWAYS_BOOT, 2417 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2418 .matches = has_always, 2419 }, 2420 { 2421 .capability = ARM64_ALWAYS_SYSTEM, 2422 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2423 .matches = has_always, 2424 }, 2425 { 2426 .desc = "GICv3 CPU interface", 2427 .capability = ARM64_HAS_GICV3_CPUIF, 2428 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2429 .matches = has_useable_gicv3_cpuif, 2430 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2431 }, 2432 { 2433 .desc = "Enhanced Counter Virtualization", 2434 .capability = ARM64_HAS_ECV, 2435 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2436 .matches = has_cpuid_feature, 2437 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2438 }, 2439 { 2440 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2441 .capability = ARM64_HAS_ECV_CNTPOFF, 2442 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2443 .matches = has_cpuid_feature, 2444 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2445 }, 2446 { 2447 .desc = "Privileged Access Never", 2448 .capability = ARM64_HAS_PAN, 2449 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2450 .matches = has_cpuid_feature, 2451 .cpu_enable = cpu_enable_pan, 2452 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2453 }, 2454 #ifdef CONFIG_ARM64_EPAN 2455 { 2456 .desc = "Enhanced Privileged Access Never", 2457 .capability = ARM64_HAS_EPAN, 2458 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2459 .matches = has_cpuid_feature, 2460 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2461 }, 2462 #endif /* CONFIG_ARM64_EPAN */ 2463 { 2464 .desc = "LSE atomic instructions", 2465 .capability = ARM64_HAS_LSE_ATOMICS, 2466 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2467 .matches = has_cpuid_feature, 2468 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2469 }, 2470 { 2471 .desc = "Virtualization Host Extensions", 2472 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2473 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2474 .matches = runs_at_el2, 2475 .cpu_enable = cpu_copy_el2regs, 2476 }, 2477 { 2478 .desc = "Nested Virtualization Support", 2479 .capability = ARM64_HAS_NESTED_VIRT, 2480 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2481 .matches = has_nested_virt_support, 2482 .match_list = (const struct arm64_cpu_capabilities []){ 2483 { 2484 .matches = has_cpuid_feature, 2485 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2486 }, 2487 { 2488 .matches = has_cpuid_feature, 2489 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2490 }, 2491 { /* Sentinel */ } 2492 }, 2493 }, 2494 { 2495 .desc = "FEAT_NV2p1", 2496 .capability = ARM64_HAS_NV2P1, 2497 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2498 .matches = has_cpuid_feature, 2499 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2P1) 2500 }, 2501 { 2502 .desc = "FEAT_NV3", 2503 .capability = ARM64_HAS_NV3, 2504 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2505 .matches = has_cpuid_feature, 2506 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV3) 2507 }, 2508 { 2509 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2510 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2511 .matches = has_32bit_el0, 2512 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2513 }, 2514 #ifdef CONFIG_KVM 2515 { 2516 .desc = "32-bit EL1 Support", 2517 .capability = ARM64_HAS_32BIT_EL1, 2518 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2519 .matches = has_cpuid_feature, 2520 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2521 }, 2522 { 2523 .desc = "Protected KVM", 2524 .capability = ARM64_KVM_PROTECTED_MODE, 2525 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2526 .matches = is_kvm_protected_mode, 2527 }, 2528 { 2529 .desc = "HCRX_EL2 register", 2530 .capability = ARM64_HAS_HCX, 2531 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2532 .matches = has_cpuid_feature, 2533 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2534 }, 2535 #endif 2536 { 2537 .desc = "Kernel page table isolation (KPTI)", 2538 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2539 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2540 .cpu_enable = cpu_enable_kpti, 2541 .matches = unmap_kernel_at_el0, 2542 /* 2543 * The ID feature fields below are used to indicate that 2544 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2545 * more details. 2546 */ 2547 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2548 }, 2549 { 2550 .capability = ARM64_HAS_FPSIMD, 2551 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2552 .matches = has_cpuid_feature, 2553 .cpu_enable = cpu_enable_fpsimd, 2554 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2555 }, 2556 #ifdef CONFIG_ARM64_PMEM 2557 { 2558 .desc = "Data cache clean to Point of Persistence", 2559 .capability = ARM64_HAS_DCPOP, 2560 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2561 .matches = has_cpuid_feature, 2562 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2563 }, 2564 { 2565 .desc = "Data cache clean to Point of Deep Persistence", 2566 .capability = ARM64_HAS_DCPODP, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_cpuid_feature, 2569 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2570 }, 2571 #endif 2572 #ifdef CONFIG_ARM64_SVE 2573 { 2574 .desc = "Scalable Vector Extension", 2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2576 .capability = ARM64_SVE, 2577 .cpu_enable = cpu_enable_sve, 2578 .matches = has_cpuid_feature, 2579 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2580 }, 2581 #endif /* CONFIG_ARM64_SVE */ 2582 #ifdef CONFIG_ARM64_RAS_EXTN 2583 { 2584 .desc = "RAS Extension Support", 2585 .capability = ARM64_HAS_RAS_EXTN, 2586 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2587 .matches = has_cpuid_feature, 2588 .cpu_enable = cpu_clear_disr, 2589 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2590 }, 2591 { 2592 .desc = "RASv1p1 Extension Support", 2593 .capability = ARM64_HAS_RASV1P1_EXTN, 2594 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2595 .matches = has_rasv1p1, 2596 }, 2597 #endif /* CONFIG_ARM64_RAS_EXTN */ 2598 #ifdef CONFIG_ARM64_AMU_EXTN 2599 { 2600 .desc = "Activity Monitors Unit (AMU)", 2601 .capability = ARM64_HAS_AMU_EXTN, 2602 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2603 .matches = has_amu, 2604 .cpu_enable = cpu_amu_enable, 2605 .cpus = &amu_cpus, 2606 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2607 }, 2608 #endif /* CONFIG_ARM64_AMU_EXTN */ 2609 { 2610 .desc = "Data cache clean to the PoU not required for I/D coherence", 2611 .capability = ARM64_HAS_CACHE_IDC, 2612 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2613 .matches = has_cache_idc, 2614 .cpu_enable = cpu_emulate_effective_ctr, 2615 }, 2616 { 2617 .desc = "Instruction cache invalidation not required for I/D coherence", 2618 .capability = ARM64_HAS_CACHE_DIC, 2619 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2620 .matches = has_cache_dic, 2621 }, 2622 { 2623 .desc = "Stage-2 Force Write-Back", 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .capability = ARM64_HAS_STAGE2_FWB, 2626 .matches = has_cpuid_feature, 2627 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2628 }, 2629 { 2630 .desc = "ARMv8.4 Translation Table Level", 2631 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2632 .capability = ARM64_HAS_ARMv8_4_TTL, 2633 .matches = has_cpuid_feature, 2634 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2635 }, 2636 { 2637 .desc = "TLB range maintenance instructions", 2638 .capability = ARM64_HAS_TLB_RANGE, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = has_cpuid_feature, 2641 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2642 }, 2643 #ifdef CONFIG_ARM64_HW_AFDBM 2644 { 2645 .desc = "Hardware dirty bit management", 2646 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2647 .capability = ARM64_HW_DBM, 2648 .matches = has_hw_dbm, 2649 .cpu_enable = cpu_enable_hw_dbm, 2650 .cpus = &dbm_cpus, 2651 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2652 }, 2653 #endif 2654 #ifdef CONFIG_ARM64_HAFT 2655 { 2656 .desc = "Hardware managed Access Flag for Table Descriptors", 2657 /* 2658 * Contrary to the page/block access flag, the table access flag 2659 * cannot be emulated in software (no access fault will occur). 2660 * Therefore this should be used only if it's supported system 2661 * wide. 2662 */ 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .capability = ARM64_HAFT, 2665 .matches = has_cpuid_feature, 2666 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2667 }, 2668 #endif 2669 { 2670 .desc = "CRC32 instructions", 2671 .capability = ARM64_HAS_CRC32, 2672 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2673 .matches = has_cpuid_feature, 2674 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2675 }, 2676 { 2677 .desc = "Speculative Store Bypassing Safe (SSBS)", 2678 .capability = ARM64_SSBS, 2679 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2680 .matches = has_cpuid_feature, 2681 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2682 }, 2683 #ifdef CONFIG_ARM64_CNP 2684 { 2685 .desc = "Common not Private translations", 2686 .capability = ARM64_HAS_CNP, 2687 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2688 .matches = has_useable_cnp, 2689 .cpu_enable = cpu_enable_cnp, 2690 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2691 }, 2692 #endif 2693 { 2694 .desc = "Speculation barrier (SB)", 2695 .capability = ARM64_HAS_SB, 2696 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2697 .matches = has_cpuid_feature, 2698 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2699 }, 2700 #ifdef CONFIG_ARM64_PTR_AUTH 2701 { 2702 .desc = "Address authentication (architected QARMA5 algorithm)", 2703 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2704 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2705 .matches = has_address_auth_cpucap, 2706 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2707 }, 2708 { 2709 .desc = "Address authentication (architected QARMA3 algorithm)", 2710 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2711 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2712 .matches = has_address_auth_cpucap, 2713 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2714 }, 2715 { 2716 .desc = "Address authentication (IMP DEF algorithm)", 2717 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2718 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2719 .matches = has_address_auth_cpucap, 2720 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2721 }, 2722 { 2723 .capability = ARM64_HAS_ADDRESS_AUTH, 2724 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2725 .matches = has_address_auth_metacap, 2726 }, 2727 { 2728 .desc = "Generic authentication (architected QARMA5 algorithm)", 2729 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2730 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2731 .matches = has_cpuid_feature, 2732 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2733 }, 2734 { 2735 .desc = "Generic authentication (architected QARMA3 algorithm)", 2736 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2737 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2738 .matches = has_cpuid_feature, 2739 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2740 }, 2741 { 2742 .desc = "Generic authentication (IMP DEF algorithm)", 2743 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2744 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2745 .matches = has_cpuid_feature, 2746 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2747 }, 2748 { 2749 .capability = ARM64_HAS_GENERIC_AUTH, 2750 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2751 .matches = has_generic_auth, 2752 }, 2753 #endif /* CONFIG_ARM64_PTR_AUTH */ 2754 #ifdef CONFIG_ARM64_PSEUDO_NMI 2755 { 2756 /* 2757 * Depends on having GICv3 2758 */ 2759 .desc = "IRQ priority masking", 2760 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2761 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2762 .matches = can_use_gic_priorities, 2763 }, 2764 { 2765 /* 2766 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2767 */ 2768 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2769 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2770 .matches = has_gic_prio_relaxed_sync, 2771 }, 2772 #endif 2773 { 2774 /* 2775 * Depends on having GICv3 2776 */ 2777 .desc = "ICV_DIR_EL1 trapping", 2778 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2779 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2780 .matches = can_trap_icv_dir_el1, 2781 }, 2782 #ifdef CONFIG_ARM64_E0PD 2783 { 2784 .desc = "E0PD", 2785 .capability = ARM64_HAS_E0PD, 2786 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2787 .cpu_enable = cpu_enable_e0pd, 2788 .matches = has_cpuid_feature, 2789 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2790 }, 2791 #endif 2792 { 2793 .desc = "Random Number Generator", 2794 .capability = ARM64_HAS_RNG, 2795 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2796 .matches = has_cpuid_feature, 2797 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2798 }, 2799 #ifdef CONFIG_ARM64_BTI 2800 { 2801 .desc = "Branch Target Identification", 2802 .capability = ARM64_BTI, 2803 #ifdef CONFIG_ARM64_BTI_KERNEL 2804 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2805 #else 2806 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2807 #endif 2808 .matches = has_cpuid_feature, 2809 .cpu_enable = bti_enable, 2810 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2811 }, 2812 #endif 2813 #ifdef CONFIG_ARM64_MTE 2814 { 2815 .desc = "Memory Tagging Extension", 2816 .capability = ARM64_MTE, 2817 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2818 .matches = has_cpuid_feature, 2819 .cpu_enable = cpu_enable_mte, 2820 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2821 }, 2822 { 2823 .desc = "Asymmetric MTE Tag Check Fault", 2824 .capability = ARM64_MTE_ASYMM, 2825 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2826 .matches = has_cpuid_feature, 2827 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2828 }, 2829 { 2830 .desc = "FAR on MTE Tag Check Fault", 2831 .capability = ARM64_MTE_FAR, 2832 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2833 .matches = has_cpuid_feature, 2834 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2835 }, 2836 { 2837 .desc = "Store Only MTE Tag Check", 2838 .capability = ARM64_MTE_STORE_ONLY, 2839 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2840 .matches = has_cpuid_feature, 2841 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2842 }, 2843 #endif /* CONFIG_ARM64_MTE */ 2844 { 2845 .desc = "RCpc load-acquire (LDAPR)", 2846 .capability = ARM64_HAS_LDAPR, 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .matches = has_cpuid_feature, 2849 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2850 }, 2851 { 2852 .desc = "Fine Grained Traps", 2853 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2854 .capability = ARM64_HAS_FGT, 2855 .matches = has_cpuid_feature, 2856 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2857 }, 2858 { 2859 .desc = "Fine Grained Traps 2", 2860 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2861 .capability = ARM64_HAS_FGT2, 2862 .matches = has_cpuid_feature, 2863 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2864 }, 2865 #ifdef CONFIG_ARM64_SME 2866 { 2867 .desc = "Scalable Matrix Extension", 2868 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2869 .capability = ARM64_SME, 2870 .matches = has_cpuid_feature, 2871 .cpu_enable = cpu_enable_sme, 2872 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2873 }, 2874 /* FA64 should be sorted after the base SME capability */ 2875 { 2876 .desc = "FA64", 2877 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2878 .capability = ARM64_SME_FA64, 2879 .matches = has_cpuid_feature, 2880 .cpu_enable = cpu_enable_fa64, 2881 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2882 }, 2883 { 2884 .desc = "SME2", 2885 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2886 .capability = ARM64_SME2, 2887 .matches = has_cpuid_feature, 2888 .cpu_enable = cpu_enable_sme2, 2889 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2890 }, 2891 #endif /* CONFIG_ARM64_SME */ 2892 { 2893 .desc = "WFx with timeout", 2894 .capability = ARM64_HAS_WFXT, 2895 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2896 .matches = has_cpuid_feature, 2897 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2898 }, 2899 { 2900 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2901 .capability = ARM64_HAS_TIDCP1, 2902 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2903 .matches = has_cpuid_feature, 2904 .cpu_enable = cpu_trap_el0_impdef, 2905 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2906 }, 2907 { 2908 .desc = "Data independent timing control (DIT)", 2909 .capability = ARM64_HAS_DIT, 2910 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2911 .matches = has_cpuid_feature, 2912 .cpu_enable = cpu_enable_dit, 2913 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2914 }, 2915 { 2916 .desc = "Memory Copy and Memory Set instructions", 2917 .capability = ARM64_HAS_MOPS, 2918 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2919 .matches = has_cpuid_feature, 2920 .cpu_enable = cpu_enable_mops, 2921 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2922 }, 2923 { 2924 .capability = ARM64_HAS_TCR2, 2925 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2926 .matches = has_cpuid_feature, 2927 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2928 }, 2929 { 2930 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2931 .capability = ARM64_HAS_S1PIE, 2932 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2933 .matches = has_cpuid_feature, 2934 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2935 }, 2936 { 2937 .desc = "VHE for hypervisor only", 2938 .capability = ARM64_KVM_HVHE, 2939 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2940 .matches = hvhe_possible, 2941 }, 2942 { 2943 .desc = "Enhanced Virtualization Traps", 2944 .capability = ARM64_HAS_EVT, 2945 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2946 .matches = has_cpuid_feature, 2947 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2948 }, 2949 { 2950 .desc = "BBM Level 3", 2951 .capability = ARM64_HAS_BBML3, 2952 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2953 .matches = has_bbml3, 2954 }, 2955 { 2956 .desc = "52-bit Virtual-Physical Addressing for S1 and S2 (LPA2)", 2957 .capability = ARM64_HAS_LPA2, 2958 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2959 .matches = has_lpa2, 2960 }, 2961 { 2962 .desc = "FPMR", 2963 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2964 .capability = ARM64_HAS_FPMR, 2965 .matches = has_cpuid_feature, 2966 .cpu_enable = cpu_enable_fpmr, 2967 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2968 }, 2969 #ifdef CONFIG_ARM64_VA_BITS_52 2970 { 2971 .capability = ARM64_HAS_VA52, 2972 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2973 .matches = has_cpuid_feature, 2974 #ifdef CONFIG_ARM64_64K_PAGES 2975 .desc = "52-bit Virtual Addressing (LVA)", 2976 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2977 #else 2978 .desc = "52-bit Virtual Addressing (LPA2)", 2979 #ifdef CONFIG_ARM64_4K_PAGES 2980 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2981 #else 2982 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2983 #endif 2984 #endif 2985 }, 2986 #endif 2987 { 2988 .desc = "Memory Partitioning And Monitoring", 2989 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2990 .capability = ARM64_MPAM, 2991 .matches = test_has_mpam, 2992 .cpu_enable = cpu_enable_mpam, 2993 }, 2994 { 2995 .desc = "Memory Partitioning And Monitoring Virtualisation", 2996 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2997 .capability = ARM64_MPAM_HCR, 2998 .matches = test_has_mpam_hcr, 2999 }, 3000 { 3001 .desc = "NV1", 3002 .capability = ARM64_HAS_HCR_NV1, 3003 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3004 .matches = has_nv1, 3005 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3006 }, 3007 #ifdef CONFIG_ARM64_POE 3008 { 3009 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3010 .capability = ARM64_HAS_S1POE, 3011 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3012 .matches = has_cpuid_feature, 3013 .cpu_enable = cpu_enable_poe, 3014 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3015 }, 3016 #endif 3017 #ifdef CONFIG_ARM64_GCS 3018 { 3019 .desc = "Guarded Control Stack (GCS)", 3020 .capability = ARM64_HAS_GCS, 3021 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3022 .cpu_enable = cpu_enable_gcs, 3023 .matches = has_cpuid_feature, 3024 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3025 }, 3026 #endif 3027 #ifdef CONFIG_HW_PERF_EVENTS 3028 { 3029 .desc = "PMUv3", 3030 .capability = ARM64_HAS_PMUV3, 3031 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3032 .matches = has_pmuv3, 3033 }, 3034 #endif 3035 { 3036 .desc = "SCTLR2", 3037 .capability = ARM64_HAS_SCTLR2, 3038 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3039 .matches = has_cpuid_feature, 3040 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3041 }, 3042 { 3043 .desc = "GICv5 CPU interface", 3044 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3045 .capability = ARM64_HAS_GICV5_CPUIF, 3046 .matches = has_cpuid_feature, 3047 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3048 }, 3049 { 3050 .desc = "GICv5 Legacy vCPU interface", 3051 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3052 .capability = ARM64_HAS_GICV5_LEGACY, 3053 .matches = test_has_gicv5_legacy, 3054 }, 3055 { 3056 .desc = "XNX", 3057 .capability = ARM64_HAS_XNX, 3058 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3059 .matches = has_cpuid_feature, 3060 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3061 }, 3062 { 3063 .desc = "LS64", 3064 .capability = ARM64_HAS_LS64, 3065 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3066 .matches = has_cpuid_feature, 3067 .cpu_enable = cpu_enable_ls64, 3068 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3069 }, 3070 { 3071 .desc = "LS64_V", 3072 .capability = ARM64_HAS_LS64_V, 3073 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3074 .matches = has_cpuid_feature, 3075 .cpu_enable = cpu_enable_ls64_v, 3076 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3077 }, 3078 #ifdef CONFIG_ARM64_LSUI 3079 { 3080 .desc = "Unprivileged Load Store Instructions (LSUI)", 3081 .capability = ARM64_HAS_LSUI, 3082 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3083 .matches = has_cpuid_feature, 3084 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3085 }, 3086 #endif 3087 {}, 3088 }; 3089 3090 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3091 .matches = has_user_cpuid_feature, \ 3092 ARM64_CPUID_FIELDS(reg, field, min_value) 3093 3094 #define __HWCAP_CAP(name, cap_type, cap) \ 3095 .desc = name, \ 3096 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3097 .hwcap_type = cap_type, \ 3098 .hwcap = cap, \ 3099 3100 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3101 { \ 3102 __HWCAP_CAP(#cap, cap_type, cap) \ 3103 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3104 } 3105 3106 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3107 { \ 3108 __HWCAP_CAP(#cap, cap_type, cap) \ 3109 .matches = cpucap_multi_entry_cap_matches, \ 3110 .match_list = list, \ 3111 } 3112 3113 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3114 { \ 3115 __HWCAP_CAP(#cap, cap_type, cap) \ 3116 .matches = match, \ 3117 } 3118 3119 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3120 { \ 3121 __HWCAP_CAP(#cap, cap_type, cap) \ 3122 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3123 .matches = match, \ 3124 } 3125 3126 #ifdef CONFIG_ARM64_PTR_AUTH 3127 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3128 { 3129 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3130 }, 3131 { 3132 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3133 }, 3134 { 3135 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3136 }, 3137 {}, 3138 }; 3139 3140 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3141 { 3142 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3143 }, 3144 { 3145 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3146 }, 3147 { 3148 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3149 }, 3150 {}, 3151 }; 3152 #endif 3153 3154 #ifdef CONFIG_ARM64_SVE 3155 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3156 { 3157 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3158 } 3159 #endif 3160 3161 #ifdef CONFIG_ARM64_SME 3162 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3163 { 3164 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3165 } 3166 #endif 3167 3168 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3169 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3170 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3171 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3172 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3173 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3174 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3175 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3176 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3177 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3178 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3179 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3180 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3181 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3182 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3183 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F32DOT), 3184 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32MM), 3185 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3186 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3187 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3188 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3189 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3190 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3191 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3192 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3193 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3194 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3195 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3196 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3197 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3198 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3199 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3200 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3201 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3202 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3203 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3204 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3205 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3206 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3207 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3208 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3209 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3210 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3211 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3212 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3213 #ifdef CONFIG_ARM64_SVE 3214 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_SVE_LUT6), 3215 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3216 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_HWCAP, KERNEL_HWCAP_SVE2P3), 3217 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3218 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3219 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3220 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3221 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3222 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3223 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3224 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3225 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3226 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_HWCAP, KERNEL_HWCAP_SVE_B16MM), 3227 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3228 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3229 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3230 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3231 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3232 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3233 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3234 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3235 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3236 #endif 3237 #ifdef CONFIG_ARM64_GCS 3238 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3239 #endif 3240 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3241 #ifdef CONFIG_ARM64_BTI 3242 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3243 #endif 3244 #ifdef CONFIG_ARM64_PTR_AUTH 3245 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3246 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3247 #endif 3248 #ifdef CONFIG_ARM64_MTE 3249 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3250 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3251 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3252 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3253 #endif /* CONFIG_ARM64_MTE */ 3254 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3255 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3256 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3257 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3258 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3259 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3260 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3261 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3262 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3263 #ifdef CONFIG_ARM64_SME 3264 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3265 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3266 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUT6), 3267 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3268 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP_HWCAP, KERNEL_HWCAP_SME2P3), 3269 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3270 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3271 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3272 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3273 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3274 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3275 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3276 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3277 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3278 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3279 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3280 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3281 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3282 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3283 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3284 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3285 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3286 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3287 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3288 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3289 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3290 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3291 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3292 #endif /* CONFIG_ARM64_SME */ 3293 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3294 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3295 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3296 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3297 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3298 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3299 HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), 3300 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3301 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3302 #ifdef CONFIG_ARM64_POE 3303 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3304 #endif 3305 {}, 3306 }; 3307 3308 #ifdef CONFIG_COMPAT 3309 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3310 { 3311 /* 3312 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3313 * in line with that of arm32 as in vfp_init(). We make sure that the 3314 * check is future proof, by making sure value is non-zero. 3315 */ 3316 u32 mvfr1; 3317 3318 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3319 if (scope == SCOPE_SYSTEM) 3320 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3321 else 3322 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3323 3324 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3325 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3326 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3327 } 3328 #endif 3329 3330 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3331 #ifdef CONFIG_COMPAT 3332 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3333 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3334 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3335 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3336 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3337 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3338 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3339 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3340 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3341 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3342 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3343 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3344 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3345 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3346 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3347 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3348 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3349 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3350 #endif 3351 {}, 3352 }; 3353 3354 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3355 { 3356 switch (cap->hwcap_type) { 3357 case CAP_HWCAP: 3358 cpu_set_feature(cap->hwcap); 3359 break; 3360 #ifdef CONFIG_COMPAT 3361 case CAP_COMPAT_HWCAP: 3362 compat_elf_hwcap |= (u32)cap->hwcap; 3363 break; 3364 case CAP_COMPAT_HWCAP2: 3365 compat_elf_hwcap2 |= (u32)cap->hwcap; 3366 break; 3367 #endif 3368 default: 3369 WARN_ON(1); 3370 break; 3371 } 3372 } 3373 3374 /* Check if we have a particular HWCAP enabled */ 3375 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3376 { 3377 bool rc; 3378 3379 switch (cap->hwcap_type) { 3380 case CAP_HWCAP: 3381 rc = cpu_have_feature(cap->hwcap); 3382 break; 3383 #ifdef CONFIG_COMPAT 3384 case CAP_COMPAT_HWCAP: 3385 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3386 break; 3387 case CAP_COMPAT_HWCAP2: 3388 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3389 break; 3390 #endif 3391 default: 3392 WARN_ON(1); 3393 rc = false; 3394 } 3395 3396 return rc; 3397 } 3398 3399 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3400 { 3401 /* We support emulation of accesses to CPU ID feature registers */ 3402 cpu_set_named_feature(CPUID); 3403 for (; hwcaps->matches; hwcaps++) 3404 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3405 cap_set_elf_hwcap(hwcaps); 3406 } 3407 3408 static void update_cpu_capabilities(u16 scope_mask) 3409 { 3410 int i; 3411 const struct arm64_cpu_capabilities *caps; 3412 3413 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3414 for (i = 0; i < ARM64_NCAPS; i++) { 3415 bool match_all = false; 3416 bool caps_set = false; 3417 bool boot_cpu = false; 3418 3419 caps = cpucap_ptrs[i]; 3420 if (!caps || !(caps->type & scope_mask)) 3421 continue; 3422 3423 match_all = cpucap_match_all_early_cpus(caps); 3424 caps_set = cpus_have_cap(caps->capability); 3425 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3426 3427 /* 3428 * Unless it's a match-all CPUs feature, avoid probing if 3429 * already detected. 3430 */ 3431 if (!match_all && caps_set) 3432 continue; 3433 3434 /* 3435 * A match-all CPUs capability is only set when probing the 3436 * boot CPU. It may be cleared subsequently if not detected on 3437 * secondary ones. 3438 */ 3439 if (match_all && !caps_set && !boot_cpu) 3440 continue; 3441 3442 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3443 if (match_all) 3444 __clear_bit(caps->capability, system_cpucaps); 3445 continue; 3446 } 3447 3448 /* 3449 * Match-all CPUs capabilities are logged later when the 3450 * system capabilities are finalised. 3451 */ 3452 if (!match_all && caps->desc && !caps->cpus) 3453 pr_info("detected: %s\n", caps->desc); 3454 3455 __set_bit(caps->capability, system_cpucaps); 3456 3457 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3458 set_bit(caps->capability, boot_cpucaps); 3459 } 3460 } 3461 3462 /* 3463 * Enable all the available capabilities on this CPU. The capabilities 3464 * with BOOT_CPU scope are handled separately and hence skipped here. 3465 */ 3466 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3467 { 3468 int i; 3469 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3470 3471 for_each_available_cap(i) { 3472 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3473 3474 if (WARN_ON(!cap)) 3475 continue; 3476 3477 if (!(cap->type & non_boot_scope)) 3478 continue; 3479 3480 if (cap->cpu_enable) 3481 cap->cpu_enable(cap); 3482 } 3483 return 0; 3484 } 3485 3486 /* 3487 * Run through the enabled capabilities and enable() it on all active 3488 * CPUs 3489 */ 3490 static void __init enable_cpu_capabilities(u16 scope_mask) 3491 { 3492 int i; 3493 const struct arm64_cpu_capabilities *caps; 3494 bool boot_scope; 3495 3496 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3497 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3498 3499 for (i = 0; i < ARM64_NCAPS; i++) { 3500 caps = cpucap_ptrs[i]; 3501 if (!caps || !(caps->type & scope_mask) || 3502 !cpus_have_cap(caps->capability)) 3503 continue; 3504 3505 if (boot_scope && caps->cpu_enable) 3506 /* 3507 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3508 * before any secondary CPU boots. Thus, each secondary 3509 * will enable the capability as appropriate via 3510 * check_local_cpu_capabilities(). The only exception is 3511 * the boot CPU, for which the capability must be 3512 * enabled here. This approach avoids costly 3513 * stop_machine() calls for this case. 3514 */ 3515 caps->cpu_enable(caps); 3516 } 3517 3518 /* 3519 * For all non-boot scope capabilities, use stop_machine() 3520 * as it schedules the work allowing us to modify PSTATE, 3521 * instead of on_each_cpu() which uses an IPI, giving us a 3522 * PSTATE that disappears when we return. 3523 */ 3524 if (!boot_scope) 3525 stop_machine(cpu_enable_non_boot_scope_capabilities, 3526 NULL, cpu_online_mask); 3527 } 3528 3529 /* 3530 * Run through the list of capabilities to check for conflicts. 3531 * If the system has already detected a capability, take necessary 3532 * action on this CPU. 3533 */ 3534 static void verify_local_cpu_caps(u16 scope_mask) 3535 { 3536 int i; 3537 bool cpu_has_cap, system_has_cap; 3538 const struct arm64_cpu_capabilities *caps; 3539 3540 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3541 3542 for (i = 0; i < ARM64_NCAPS; i++) { 3543 caps = cpucap_ptrs[i]; 3544 if (!caps || !(caps->type & scope_mask)) 3545 continue; 3546 3547 system_has_cap = cpus_have_cap(caps->capability); 3548 if (cpucap_probe_once(caps)) 3549 cpu_has_cap = system_has_cap; 3550 else 3551 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3552 3553 if (system_has_cap) { 3554 /* 3555 * Check if the new CPU misses an advertised feature, 3556 * which is not safe to miss. 3557 */ 3558 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3559 break; 3560 /* 3561 * We have to issue cpu_enable() irrespective of 3562 * whether the CPU has it or not, as it is enabeld 3563 * system wide. It is up to the call back to take 3564 * appropriate action on this CPU. 3565 */ 3566 if (caps->cpu_enable) 3567 caps->cpu_enable(caps); 3568 } else { 3569 /* 3570 * Check if the CPU has this capability if it isn't 3571 * safe to have when the system doesn't. 3572 */ 3573 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3574 break; 3575 } 3576 } 3577 3578 if (i < ARM64_NCAPS) { 3579 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3580 smp_processor_id(), caps->capability, 3581 caps->desc, system_has_cap, cpu_has_cap); 3582 3583 if (cpucap_panic_on_conflict(caps)) 3584 cpu_panic_kernel(); 3585 else 3586 cpu_die_early(); 3587 } 3588 } 3589 3590 /* 3591 * Check for CPU features that are used in early boot 3592 * based on the Boot CPU value. 3593 */ 3594 static void check_early_cpu_features(void) 3595 { 3596 verify_cpu_asid_bits(); 3597 3598 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3599 } 3600 3601 static void 3602 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3603 { 3604 3605 for (; caps->matches; caps++) 3606 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3607 pr_crit("CPU%d: missing HWCAP: %s\n", 3608 smp_processor_id(), caps->desc); 3609 cpu_die_early(); 3610 } 3611 } 3612 3613 static void verify_local_elf_hwcaps(void) 3614 { 3615 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3616 3617 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3618 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3619 } 3620 3621 static void verify_sve_features(void) 3622 { 3623 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3624 3625 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3626 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3627 smp_processor_id()); 3628 cpu_die_early(); 3629 } 3630 3631 cpacr_restore(cpacr); 3632 } 3633 3634 static void verify_sme_features(void) 3635 { 3636 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3637 3638 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3639 pr_crit("CPU%d: SME: vector length support mismatch\n", 3640 smp_processor_id()); 3641 cpu_die_early(); 3642 } 3643 3644 cpacr_restore(cpacr); 3645 } 3646 3647 static void verify_hyp_capabilities(void) 3648 { 3649 u64 safe_mmfr1, mmfr0, mmfr1; 3650 int parange, ipa_max; 3651 unsigned int safe_vmid_bits, vmid_bits; 3652 3653 if (!IS_ENABLED(CONFIG_KVM)) 3654 return; 3655 3656 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3657 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3658 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3659 3660 /* Verify VMID bits */ 3661 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3662 vmid_bits = get_vmid_bits(mmfr1); 3663 if (vmid_bits < safe_vmid_bits) { 3664 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3665 cpu_die_early(); 3666 } 3667 3668 /* Verify IPA range */ 3669 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3670 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3671 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3672 if (ipa_max < get_kvm_ipa_limit()) { 3673 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3674 cpu_die_early(); 3675 } 3676 } 3677 3678 static void verify_mpam_capabilities(void) 3679 { 3680 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3681 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3682 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3683 3684 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3685 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3686 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3687 cpu_die_early(); 3688 } 3689 3690 cpu_idr = read_cpuid(MPAMIDR_EL1); 3691 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3692 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3693 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3694 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3695 cpu_die_early(); 3696 } 3697 3698 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3699 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3700 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3701 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3702 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3703 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3704 cpu_die_early(); 3705 } 3706 } 3707 3708 /* 3709 * Run through the enabled system capabilities and enable() it on this CPU. 3710 * The capabilities were decided based on the available CPUs at the boot time. 3711 * Any new CPU should match the system wide status of the capability. If the 3712 * new CPU doesn't have a capability which the system now has enabled, we 3713 * cannot do anything to fix it up and could cause unexpected failures. So 3714 * we park the CPU. 3715 */ 3716 static void verify_local_cpu_capabilities(void) 3717 { 3718 /* 3719 * The capabilities with SCOPE_BOOT_CPU are checked from 3720 * check_early_cpu_features(), as they need to be verified 3721 * on all secondary CPUs. 3722 */ 3723 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3724 verify_local_elf_hwcaps(); 3725 3726 if (system_supports_sve()) 3727 verify_sve_features(); 3728 3729 if (system_supports_sme()) 3730 verify_sme_features(); 3731 3732 if (is_hyp_mode_available()) 3733 verify_hyp_capabilities(); 3734 3735 if (system_supports_mpam()) 3736 verify_mpam_capabilities(); 3737 } 3738 3739 void check_local_cpu_capabilities(void) 3740 { 3741 /* 3742 * All secondary CPUs should conform to the early CPU features 3743 * in use by the kernel based on boot CPU. 3744 */ 3745 check_early_cpu_features(); 3746 3747 /* 3748 * Verify that this CPU has all the system advertised 3749 * capabilities. 3750 */ 3751 if (system_capabilities_finalized()) 3752 verify_local_cpu_capabilities(); 3753 } 3754 3755 /* 3756 * Update system wide CPU feature registers with the values from a 3757 * non-boot CPU. Also performs SANITY checks to make sure that there 3758 * aren't any insane variations from that of the boot CPU. 3759 */ 3760 void update_cpu_features(int cpu) 3761 { 3762 struct cpuinfo_arm64 *boot, *info; 3763 int taint = 0; 3764 3765 /* 3766 * If we haven't finalised the system capabilities, this CPU gets 3767 * a chance to update the errata work arounds and local features. 3768 */ 3769 if (!system_capabilities_finalized()) 3770 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3771 3772 boot = &boot_cpu_data; 3773 info = per_cpu_ptr(&cpu_data, cpu); 3774 3775 /* 3776 * The kernel can handle differing I-cache policies, but otherwise 3777 * caches should look identical. Userspace JITs will make use of 3778 * *minLine. 3779 */ 3780 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 3781 info->reg_ctr, boot->reg_ctr); 3782 3783 /* 3784 * Userspace may perform DC ZVA instructions. Mismatched block sizes 3785 * could result in too much or too little memory being zeroed if a 3786 * process is preempted and migrated between CPUs. 3787 */ 3788 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 3789 info->reg_dczid, boot->reg_dczid); 3790 3791 /* If different, timekeeping will be broken (especially with KVM) */ 3792 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 3793 info->reg_cntfrq, boot->reg_cntfrq); 3794 3795 /* 3796 * The kernel uses self-hosted debug features and expects CPUs to 3797 * support identical debug features. We presently need CTX_CMPs, WRPs, 3798 * and BRPs to be identical. 3799 * ID_AA64DFR1 is currently RES0. 3800 */ 3801 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 3802 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 3803 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 3804 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 3805 /* 3806 * Even in big.LITTLE, processors should be identical instruction-set 3807 * wise. 3808 */ 3809 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 3810 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 3811 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 3812 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 3813 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 3814 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 3815 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 3816 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 3817 3818 /* 3819 * Differing PARange support is fine as long as all peripherals and 3820 * memory are mapped within the minimum PARange of all CPUs. 3821 * Linux should not care about secure memory. 3822 */ 3823 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 3824 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 3825 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 3826 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 3827 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 3828 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 3829 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 3830 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 3831 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 3832 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 3833 3834 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 3835 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 3836 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 3837 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 3838 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 3839 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 3840 3841 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 3842 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 3843 3844 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 3845 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 3846 3847 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 3848 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 3849 3850 /* Probe vector lengths */ 3851 if (IS_ENABLED(CONFIG_ARM64_SVE) && 3852 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 3853 if (!system_capabilities_finalized()) { 3854 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3855 3856 vec_update_vq_map(ARM64_VEC_SVE); 3857 3858 cpacr_restore(cpacr); 3859 } 3860 } 3861 3862 if (IS_ENABLED(CONFIG_ARM64_SME) && 3863 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 3864 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3865 3866 /* Probe vector lengths */ 3867 if (!system_capabilities_finalized()) 3868 vec_update_vq_map(ARM64_VEC_SME); 3869 3870 cpacr_restore(cpacr); 3871 } 3872 3873 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0) || id_aa64pfr1_mpamfrac(info->reg_id_aa64pfr1)) 3874 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 3875 info->reg_mpamidr, boot->reg_mpamidr); 3876 3877 /* 3878 * The kernel uses the LDGM/STGM instructions and the number of tags 3879 * they read/write depends on the GMID_EL1.BS field. Check that the 3880 * value is the same on all CPUs. 3881 */ 3882 if (IS_ENABLED(CONFIG_ARM64_MTE) && id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 3883 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 3884 info->reg_gmid, boot->reg_gmid); 3885 3886 /* 3887 * If we don't have AArch32 at all then skip the checks entirely 3888 * as the register values may be UNKNOWN and we're not going to be 3889 * using them for anything. 3890 * 3891 * This relies on a sanitised view of the AArch64 ID registers 3892 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 3893 */ 3894 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3895 lazy_init_32bit_cpu_features(info, boot); 3896 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 3897 &boot->aarch32); 3898 } 3899 3900 /* 3901 * Mismatched CPU features are a recipe for disaster. Don't even 3902 * pretend to support them. 3903 */ 3904 if (taint) { 3905 pr_warn_once("Unsupported CPU feature variation detected.\n"); 3906 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 3907 } 3908 } 3909 3910 bool this_cpu_has_cap(unsigned int n) 3911 { 3912 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3913 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3914 3915 if (cap) 3916 return cap->matches(cap, SCOPE_LOCAL_CPU); 3917 } 3918 3919 return false; 3920 } 3921 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3922 3923 /* 3924 * This helper function is used in a narrow window when, 3925 * - The system wide safe registers are set with all the SMP CPUs and, 3926 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3927 */ 3928 static bool __maybe_unused __system_matches_cap(unsigned int n) 3929 { 3930 if (n < ARM64_NCAPS) { 3931 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3932 3933 if (cap) 3934 return cap->matches(cap, SCOPE_SYSTEM); 3935 } 3936 return false; 3937 } 3938 3939 void cpu_set_feature(unsigned int num) 3940 { 3941 set_bit(num, elf_hwcap); 3942 } 3943 3944 bool cpu_have_feature(unsigned int num) 3945 { 3946 return test_bit(num, elf_hwcap); 3947 } 3948 EXPORT_SYMBOL_GPL(cpu_have_feature); 3949 3950 unsigned long cpu_get_elf_hwcap(void) 3951 { 3952 /* 3953 * We currently only populate the first 32 bits of AT_HWCAP. Please 3954 * note that for userspace compatibility we guarantee that bits 62 3955 * and 63 will always be returned as 0. 3956 */ 3957 return elf_hwcap[0]; 3958 } 3959 3960 unsigned long cpu_get_elf_hwcap2(void) 3961 { 3962 return elf_hwcap[1]; 3963 } 3964 3965 unsigned long cpu_get_elf_hwcap3(void) 3966 { 3967 return elf_hwcap[2]; 3968 } 3969 3970 static void __init setup_boot_cpu_capabilities(void) 3971 { 3972 kvm_arm_target_impl_cpu_init(); 3973 /* 3974 * The boot CPU's feature register values have been recorded. Detect 3975 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3976 * patch alternatives for the available boot cpucaps. 3977 */ 3978 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3979 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3980 apply_boot_alternatives(); 3981 } 3982 3983 void __init setup_boot_cpu_features(void) 3984 { 3985 init_cpu_features(); 3986 3987 /* 3988 * Initialize the indirect array of CPU capabilities pointers before we 3989 * handle the boot CPU. 3990 */ 3991 init_cpucap_indirect_list(); 3992 3993 /* 3994 * Detect broken pseudo-NMI. Must be called _before_ the call to 3995 * setup_boot_cpu_capabilities() since it interacts with 3996 * can_use_gic_priorities(). 3997 */ 3998 detect_system_supports_pseudo_nmi(); 3999 4000 setup_boot_cpu_capabilities(); 4001 } 4002 4003 static void __init setup_system_capabilities(void) 4004 { 4005 /* 4006 * The system-wide safe feature register values have been finalized. 4007 * Detect, enable, and patch alternatives for the available system 4008 * cpucaps. 4009 */ 4010 update_cpu_capabilities(SCOPE_SYSTEM); 4011 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 4012 apply_alternatives_all(); 4013 4014 for (int i = 0; i < ARM64_NCAPS; i++) { 4015 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 4016 4017 if (!caps || !caps->desc) 4018 continue; 4019 4020 /* 4021 * Log any cpucaps with a cpumask as these aren't logged by 4022 * update_cpu_capabilities(). 4023 */ 4024 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 4025 pr_info("detected: %s on CPU%*pbl\n", 4026 caps->desc, cpumask_pr_args(caps->cpus)); 4027 4028 /* Log match-all CPUs capabilities */ 4029 if (cpucap_match_all_early_cpus(caps) && 4030 cpus_have_cap(caps->capability)) 4031 pr_info("detected: %s\n", caps->desc); 4032 } 4033 4034 /* 4035 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 4036 */ 4037 if (system_uses_ttbr0_pan()) 4038 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 4039 4040 /* 4041 * Report Spectre mitigations status. 4042 */ 4043 spectre_print_disabled_mitigations(); 4044 } 4045 4046 void __init setup_system_features(void) 4047 { 4048 setup_system_capabilities(); 4049 4050 linear_map_maybe_split_to_ptes(); 4051 kpti_install_ng_mappings(); 4052 4053 sve_setup(); 4054 sme_setup(); 4055 4056 /* 4057 * Check for sane CTR_EL0.CWG value. 4058 */ 4059 if (!cache_type_cwg()) 4060 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4061 ARCH_DMA_MINALIGN); 4062 } 4063 4064 void __init setup_user_features(void) 4065 { 4066 user_feature_fixup(); 4067 4068 setup_elf_hwcaps(arm64_elf_hwcaps); 4069 4070 if (system_supports_32bit_el0()) { 4071 setup_elf_hwcaps(compat_elf_hwcaps); 4072 elf_hwcap_fixup(); 4073 } 4074 4075 minsigstksz_setup(); 4076 } 4077 4078 static int enable_mismatched_32bit_el0(unsigned int cpu) 4079 { 4080 /* 4081 * The first 32-bit-capable CPU we detected and so can no longer 4082 * be offlined by userspace. -1 indicates we haven't yet onlined 4083 * a 32-bit-capable CPU. 4084 */ 4085 static int lucky_winner = -1; 4086 4087 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4088 bool cpu_32bit = false; 4089 4090 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4091 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4092 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4093 else 4094 cpu_32bit = true; 4095 } 4096 4097 if (cpu_32bit) { 4098 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4099 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4100 } 4101 4102 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4103 return 0; 4104 4105 if (lucky_winner >= 0) 4106 return 0; 4107 4108 /* 4109 * We've detected a mismatch. We need to keep one of our CPUs with 4110 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4111 * every CPU in the system for a 32-bit task. 4112 */ 4113 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4114 cpu_active_mask); 4115 dev_set_offline_disabled(get_cpu_device(lucky_winner)); 4116 setup_elf_hwcaps(compat_elf_hwcaps); 4117 elf_hwcap_fixup(); 4118 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4119 cpu, lucky_winner); 4120 return 0; 4121 } 4122 4123 static int __init init_32bit_el0_mask(void) 4124 { 4125 if (!allow_mismatched_32bit_el0) 4126 return 0; 4127 4128 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4129 return -ENOMEM; 4130 4131 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4132 "arm64/mismatched_32bit_el0:online", 4133 enable_mismatched_32bit_el0, NULL); 4134 } 4135 subsys_initcall_sync(init_32bit_el0_mask); 4136 4137 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4138 { 4139 cpu_enable_swapper_cnp(); 4140 } 4141 4142 /* 4143 * We emulate only the following system register space. 4144 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4145 * See Table C5-6 System instruction encodings for System register accesses, 4146 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4147 */ 4148 static inline bool __attribute_const__ is_emulated(u32 id) 4149 { 4150 return (sys_reg_Op0(id) == 0x3 && 4151 sys_reg_CRn(id) == 0x0 && 4152 sys_reg_Op1(id) == 0x0 && 4153 (sys_reg_CRm(id) == 0 || 4154 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4155 } 4156 4157 /* 4158 * With CRm == 0, reg should be one of : 4159 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4160 */ 4161 static inline int emulate_id_reg(u32 id, u64 *valp) 4162 { 4163 switch (id) { 4164 case SYS_MIDR_EL1: 4165 *valp = read_cpuid_id(); 4166 break; 4167 case SYS_MPIDR_EL1: 4168 *valp = SYS_MPIDR_SAFE_VAL; 4169 break; 4170 case SYS_REVIDR_EL1: 4171 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4172 *valp = 0; 4173 break; 4174 default: 4175 return -EINVAL; 4176 } 4177 4178 return 0; 4179 } 4180 4181 static int emulate_sys_reg(u32 id, u64 *valp) 4182 { 4183 struct arm64_ftr_reg *regp; 4184 4185 if (!is_emulated(id)) 4186 return -EINVAL; 4187 4188 if (sys_reg_CRm(id) == 0) 4189 return emulate_id_reg(id, valp); 4190 4191 regp = get_arm64_ftr_reg_nowarn(id); 4192 if (regp) 4193 *valp = arm64_ftr_reg_user_value(regp); 4194 else 4195 /* 4196 * The untracked registers are either IMPLEMENTATION DEFINED 4197 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4198 */ 4199 *valp = 0; 4200 return 0; 4201 } 4202 4203 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4204 { 4205 int rc; 4206 u64 val; 4207 4208 rc = emulate_sys_reg(sys_reg, &val); 4209 if (!rc) { 4210 pt_regs_write_reg(regs, rt, val); 4211 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4212 } 4213 return rc; 4214 } 4215 4216 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4217 { 4218 u32 sys_reg, rt; 4219 4220 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4221 return false; 4222 4223 /* 4224 * sys_reg values are defined as used in mrs/msr instruction. 4225 * shift the imm value to get the encoding. 4226 */ 4227 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4228 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4229 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4230 } 4231 4232 enum mitigation_state arm64_get_meltdown_state(void) 4233 { 4234 if (__meltdown_safe) 4235 return SPECTRE_UNAFFECTED; 4236 4237 if (arm64_kernel_unmapped_at_el0()) 4238 return SPECTRE_MITIGATED; 4239 4240 return SPECTRE_VULNERABLE; 4241 } 4242 4243 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4244 char *buf) 4245 { 4246 switch (arm64_get_meltdown_state()) { 4247 case SPECTRE_UNAFFECTED: 4248 return sprintf(buf, "Not affected\n"); 4249 4250 case SPECTRE_MITIGATED: 4251 return sprintf(buf, "Mitigation: PTI\n"); 4252 4253 default: 4254 return sprintf(buf, "Vulnerable\n"); 4255 } 4256 } 4257