1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/hypervisor.h> 90 #include <asm/processor.h> 91 #include <asm/smp.h> 92 #include <asm/sysreg.h> 93 #include <asm/traps.h> 94 #include <asm/vectors.h> 95 #include <asm/virt.h> 96 97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 99 100 #ifdef CONFIG_COMPAT 101 #define COMPAT_ELF_HWCAP_DEFAULT \ 102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 105 COMPAT_HWCAP_LPAE) 106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 107 unsigned int compat_elf_hwcap2 __read_mostly; 108 unsigned int compat_elf_hwcap3 __read_mostly; 109 #endif 110 111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 112 EXPORT_SYMBOL(system_cpucaps); 113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 114 115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 116 117 /* 118 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 119 * ends up in the .bss section where it is initialized in early_map_kernel() 120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 122 * may end up generating an incorrect idmap page table attributes. 123 */ 124 bool arm64_use_ng_mappings __read_mostly = false; 125 EXPORT_SYMBOL(arm64_use_ng_mappings); 126 127 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 128 129 /* 130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 131 * support it? 132 */ 133 static bool __read_mostly allow_mismatched_32bit_el0; 134 135 /* 136 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 137 * seen at least one CPU capable of 32-bit EL0. 138 */ 139 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 140 141 /* 142 * Mask of CPUs supporting 32-bit EL0. 143 * Only valid if arm64_mismatched_32bit_el0 is enabled. 144 */ 145 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 151 } 152 153 #define __ARM64_MAX_POSITIVE(reg, field) \ 154 ((reg##_##field##_SIGNED ? \ 155 BIT(reg##_##field##_WIDTH - 1) : \ 156 BIT(reg##_##field##_WIDTH)) - 1) 157 158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 159 160 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 161 .sys_reg = SYS_##reg, \ 162 .field_pos = reg##_##field##_SHIFT, \ 163 .field_width = reg##_##field##_WIDTH, \ 164 .sign = reg##_##field##_SIGNED, \ 165 .min_field_value = min_value, \ 166 .max_field_value = max_value, 167 168 /* 169 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 170 * an implicit maximum that depends on the sign-ess of the field. 171 * 172 * An unsigned field will be capped at all ones, while a signed field 173 * will be limited to the positive half only. 174 */ 175 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 176 __ARM64_CPUID_FIELDS(reg, field, \ 177 SYS_FIELD_VALUE(reg, field, min_value), \ 178 __ARM64_MAX_POSITIVE(reg, field)) 179 180 /* 181 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 182 * implicit minimal value to max_value. This should be used when 183 * matching a non-implemented property. 184 */ 185 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 186 __ARM64_CPUID_FIELDS(reg, field, \ 187 __ARM64_MIN_NEGATIVE(reg, field), \ 188 SYS_FIELD_VALUE(reg, field, max_value)) 189 190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 191 { \ 192 .sign = SIGNED, \ 193 .visible = VISIBLE, \ 194 .strict = STRICT, \ 195 .type = TYPE, \ 196 .shift = SHIFT, \ 197 .width = WIDTH, \ 198 .safe_val = SAFE_VAL, \ 199 } 200 201 /* Define a feature with unsigned values */ 202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 204 205 /* Define a feature with a signed value */ 206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 #define ARM64_FTR_END \ 210 { \ 211 .width = 0, \ 212 } 213 214 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 215 216 static bool __system_matches_cap(unsigned int n); 217 218 /* 219 * NOTE: Any changes to the visibility of features should be kept in 220 * sync with the documentation of the CPU feature register ABI. 221 */ 222 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 237 ARM64_FTR_END, 238 }; 239 240 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 276 ARM64_FTR_END, 277 }; 278 279 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 296 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 297 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 308 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 309 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 311 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 316 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 319 ARM64_FTR_END, 320 }; 321 322 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 325 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 326 ARM64_FTR_END, 327 }; 328 329 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 353 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 354 ARM64_FTR_END, 355 }; 356 357 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 403 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 404 ARM64_FTR_END, 405 }; 406 407 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 416 ARM64_FTR_END, 417 }; 418 419 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 423 /* 424 * Page size not being supported at Stage-2 is not fatal. You 425 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 426 * your favourite nesting hypervisor. 427 * 428 * There is a small corner case where the hypervisor explicitly 429 * advertises a given granule size at Stage-2 (value 2) on some 430 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 431 * vCPUs. Although this is not forbidden by the architecture, it 432 * indicates that the hypervisor is being silly (or buggy). 433 * 434 * We make no effort to cope with this and pretend that if these 435 * fields are inconsistent across vCPUs, then it isn't worth 436 * trying to bring KVM up. 437 */ 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 441 /* 442 * We already refuse to boot CPUs that don't support our configured 443 * page size, so we can only detect mismatches for a page size other 444 * than the one we're currently using. Unfortunately, SoCs like this 445 * exist in the wild so, even though we don't like it, we'll have to go 446 * along with it and treat them as non-strict. 447 */ 448 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 449 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 451 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 453 /* Linux shouldn't care about secure memory */ 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 457 /* 458 * Differing PARange is fine as long as all peripherals and memory are mapped 459 * within the minimum PARange of all CPUs 460 */ 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 462 ARM64_FTR_END, 463 }; 464 465 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 480 ARM64_FTR_END, 481 }; 482 483 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 503 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 504 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 508 ARM64_FTR_END, 509 }; 510 511 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 512 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 514 ARM64_FTR_END, 515 }; 516 517 static const struct arm64_ftr_bits ftr_ctr[] = { 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 520 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 521 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 522 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 523 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 524 /* 525 * Linux can handle differing I-cache policies. Userspace JITs will 526 * make use of *minLine. 527 * If we have differing I-cache policies, report it as the weakest - VIPT. 528 */ 529 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 531 ARM64_FTR_END, 532 }; 533 534 static struct arm64_ftr_override __ro_after_init no_override = { }; 535 536 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 537 .name = "SYS_CTR_EL0", 538 .ftr_bits = ftr_ctr, 539 .override = &no_override, 540 }; 541 542 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 543 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 548 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 551 ARM64_FTR_END, 552 }; 553 554 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 555 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 560 /* 561 * We can instantiate multiple PMU instances with different levels 562 * of support. 563 */ 564 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 566 ARM64_FTR_END, 567 }; 568 569 static const struct arm64_ftr_bits ftr_mvfr0[] = { 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_mvfr1[] = { 582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_mvfr2[] = { 594 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_dczid[] = { 600 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 601 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 602 ARM64_FTR_END, 603 }; 604 605 static const struct arm64_ftr_bits ftr_gmid[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 607 ARM64_FTR_END, 608 }; 609 610 static const struct arm64_ftr_bits ftr_id_isar0[] = { 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 618 ARM64_FTR_END, 619 }; 620 621 static const struct arm64_ftr_bits ftr_id_isar5[] = { 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 628 ARM64_FTR_END, 629 }; 630 631 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 639 640 /* 641 * SpecSEI = 1 indicates that the PE might generate an SError on an 642 * external abort on speculative read. It is safe to assume that an 643 * SError might be generated than it will not be. Hence it has been 644 * classified as FTR_HIGHER_SAFE. 645 */ 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 647 ARM64_FTR_END, 648 }; 649 650 static const struct arm64_ftr_bits ftr_id_isar4[] = { 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 659 ARM64_FTR_END, 660 }; 661 662 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 664 ARM64_FTR_END, 665 }; 666 667 static const struct arm64_ftr_bits ftr_id_isar6[] = { 668 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 675 ARM64_FTR_END, 676 }; 677 678 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 685 ARM64_FTR_END, 686 }; 687 688 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 697 ARM64_FTR_END, 698 }; 699 700 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 701 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 703 ARM64_FTR_END, 704 }; 705 706 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 707 /* [31:28] TraceFilt */ 708 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 715 ARM64_FTR_END, 716 }; 717 718 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 719 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 720 ARM64_FTR_END, 721 }; 722 723 static const struct arm64_ftr_bits ftr_mpamidr[] = { 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 728 ARM64_FTR_END, 729 }; 730 731 /* 732 * Common ftr bits for a 32bit register with all hidden, strict 733 * attributes, with 4bit feature fields and a default safe value of 734 * 0. Covers the following 32bit registers: 735 * id_isar[1-3], id_mmfr[1-3] 736 */ 737 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 744 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 745 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 746 ARM64_FTR_END, 747 }; 748 749 /* Table for a single 32bit feature value */ 750 static const struct arm64_ftr_bits ftr_single32[] = { 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 752 ARM64_FTR_END, 753 }; 754 755 static const struct arm64_ftr_bits ftr_raz[] = { 756 ARM64_FTR_END, 757 }; 758 759 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 760 .sys_id = id, \ 761 .reg = &(struct arm64_ftr_reg){ \ 762 .name = id_str, \ 763 .override = (ovr), \ 764 .ftr_bits = &((table)[0]), \ 765 }} 766 767 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 768 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 769 770 #define ARM64_FTR_REG(id, table) \ 771 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 772 773 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 774 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 775 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 776 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 777 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 778 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 779 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 780 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 781 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 782 783 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 784 785 static const struct __ftr_reg_entry { 786 u32 sys_id; 787 struct arm64_ftr_reg *reg; 788 } arm64_ftr_regs[] = { 789 790 /* Op1 = 0, CRn = 0, CRm = 1 */ 791 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 792 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 793 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 794 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 795 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 796 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 797 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 798 799 /* Op1 = 0, CRn = 0, CRm = 2 */ 800 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 801 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 802 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 803 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 804 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 805 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 806 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 807 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 808 809 /* Op1 = 0, CRn = 0, CRm = 3 */ 810 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 811 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 812 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 813 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 814 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 815 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 816 817 /* Op1 = 0, CRn = 0, CRm = 4 */ 818 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 819 &id_aa64pfr0_override), 820 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 821 &id_aa64pfr1_override), 822 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 824 &id_aa64zfr0_override), 825 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 826 &id_aa64smfr0_override), 827 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 828 829 /* Op1 = 0, CRn = 0, CRm = 5 */ 830 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 831 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 832 833 /* Op1 = 0, CRn = 0, CRm = 6 */ 834 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 835 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 836 &id_aa64isar1_override), 837 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 838 &id_aa64isar2_override), 839 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 840 841 /* Op1 = 0, CRn = 0, CRm = 7 */ 842 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 843 &id_aa64mmfr0_override), 844 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 845 &id_aa64mmfr1_override), 846 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 847 &id_aa64mmfr2_override), 848 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 849 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 850 851 /* Op1 = 0, CRn = 10, CRm = 4 */ 852 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 853 854 /* Op1 = 1, CRn = 0, CRm = 0 */ 855 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 856 857 /* Op1 = 3, CRn = 0, CRm = 0 */ 858 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 859 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 860 861 /* Op1 = 3, CRn = 14, CRm = 0 */ 862 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 863 }; 864 865 static int search_cmp_ftr_reg(const void *id, const void *regp) 866 { 867 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 868 } 869 870 /* 871 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 872 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 873 * ascending order of sys_id, we use binary search to find a matching 874 * entry. 875 * 876 * returns - Upon success, matching ftr_reg entry for id. 877 * - NULL on failure. It is upto the caller to decide 878 * the impact of a failure. 879 */ 880 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 881 { 882 const struct __ftr_reg_entry *ret; 883 884 ret = bsearch((const void *)(unsigned long)sys_id, 885 arm64_ftr_regs, 886 ARRAY_SIZE(arm64_ftr_regs), 887 sizeof(arm64_ftr_regs[0]), 888 search_cmp_ftr_reg); 889 if (ret) 890 return ret->reg; 891 return NULL; 892 } 893 894 /* 895 * get_arm64_ftr_reg - Looks up a feature register entry using 896 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 897 * 898 * returns - Upon success, matching ftr_reg entry for id. 899 * - NULL on failure but with an WARN_ON(). 900 */ 901 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 902 { 903 struct arm64_ftr_reg *reg; 904 905 reg = get_arm64_ftr_reg_nowarn(sys_id); 906 907 /* 908 * Requesting a non-existent register search is an error. Warn 909 * and let the caller handle it. 910 */ 911 WARN_ON(!reg); 912 return reg; 913 } 914 915 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 916 s64 ftr_val) 917 { 918 u64 mask = arm64_ftr_mask(ftrp); 919 920 reg &= ~mask; 921 reg |= (ftr_val << ftrp->shift) & mask; 922 return reg; 923 } 924 925 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 926 s64 cur) 927 { 928 s64 ret = 0; 929 930 switch (ftrp->type) { 931 case FTR_EXACT: 932 ret = ftrp->safe_val; 933 break; 934 case FTR_LOWER_SAFE: 935 ret = min(new, cur); 936 break; 937 case FTR_HIGHER_OR_ZERO_SAFE: 938 if (!cur || !new) 939 break; 940 fallthrough; 941 case FTR_HIGHER_SAFE: 942 ret = max(new, cur); 943 break; 944 default: 945 BUG(); 946 } 947 948 return ret; 949 } 950 951 static void __init sort_ftr_regs(void) 952 { 953 unsigned int i; 954 955 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 956 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 957 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 958 unsigned int j = 0; 959 960 /* 961 * Features here must be sorted in descending order with respect 962 * to their shift values and should not overlap with each other. 963 */ 964 for (; ftr_bits->width != 0; ftr_bits++, j++) { 965 unsigned int width = ftr_reg->ftr_bits[j].width; 966 unsigned int shift = ftr_reg->ftr_bits[j].shift; 967 unsigned int prev_shift; 968 969 WARN((shift + width) > 64, 970 "%s has invalid feature at shift %d\n", 971 ftr_reg->name, shift); 972 973 /* 974 * Skip the first feature. There is nothing to 975 * compare against for now. 976 */ 977 if (j == 0) 978 continue; 979 980 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 981 WARN((shift + width) > prev_shift, 982 "%s has feature overlap at shift %d\n", 983 ftr_reg->name, shift); 984 } 985 986 /* 987 * Skip the first register. There is nothing to 988 * compare against for now. 989 */ 990 if (i == 0) 991 continue; 992 /* 993 * Registers here must be sorted in ascending order with respect 994 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 995 * to work correctly. 996 */ 997 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 998 } 999 } 1000 1001 /* 1002 * Initialise the CPU feature register from Boot CPU values. 1003 * Also initiliases the strict_mask for the register. 1004 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1005 * RES0 for the system-wide value, and must strictly match. 1006 */ 1007 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1008 { 1009 u64 val = 0; 1010 u64 strict_mask = ~0x0ULL; 1011 u64 user_mask = 0; 1012 u64 valid_mask = 0; 1013 1014 const struct arm64_ftr_bits *ftrp; 1015 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1016 1017 if (!reg) 1018 return; 1019 1020 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1021 u64 ftr_mask = arm64_ftr_mask(ftrp); 1022 s64 ftr_new = arm64_ftr_value(ftrp, new); 1023 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1024 1025 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1026 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1027 char *str = NULL; 1028 1029 if (ftr_ovr != tmp) { 1030 /* Unsafe, remove the override */ 1031 reg->override->mask &= ~ftr_mask; 1032 reg->override->val &= ~ftr_mask; 1033 tmp = ftr_ovr; 1034 str = "ignoring override"; 1035 } else if (ftr_new != tmp) { 1036 /* Override was valid */ 1037 ftr_new = tmp; 1038 str = "forced"; 1039 } else { 1040 /* Override was the safe value */ 1041 str = "already set"; 1042 } 1043 1044 pr_warn("%s[%d:%d]: %s to %llx\n", 1045 reg->name, 1046 ftrp->shift + ftrp->width - 1, 1047 ftrp->shift, str, 1048 tmp & (BIT(ftrp->width) - 1)); 1049 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1050 reg->override->val &= ~ftr_mask; 1051 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1052 reg->name, 1053 ftrp->shift + ftrp->width - 1, 1054 ftrp->shift); 1055 } 1056 1057 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1058 1059 valid_mask |= ftr_mask; 1060 if (!ftrp->strict) 1061 strict_mask &= ~ftr_mask; 1062 if (ftrp->visible) 1063 user_mask |= ftr_mask; 1064 else 1065 reg->user_val = arm64_ftr_set_value(ftrp, 1066 reg->user_val, 1067 ftrp->safe_val); 1068 } 1069 1070 val &= valid_mask; 1071 1072 reg->sys_val = val; 1073 reg->strict_mask = strict_mask; 1074 reg->user_mask = user_mask; 1075 } 1076 1077 extern const struct arm64_cpu_capabilities arm64_errata[]; 1078 static const struct arm64_cpu_capabilities arm64_features[]; 1079 1080 static void __init 1081 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1082 { 1083 for (; caps->matches; caps++) { 1084 if (WARN(caps->capability >= ARM64_NCAPS, 1085 "Invalid capability %d\n", caps->capability)) 1086 continue; 1087 if (WARN(cpucap_ptrs[caps->capability], 1088 "Duplicate entry for capability %d\n", 1089 caps->capability)) 1090 continue; 1091 cpucap_ptrs[caps->capability] = caps; 1092 } 1093 } 1094 1095 static void __init init_cpucap_indirect_list(void) 1096 { 1097 init_cpucap_indirect_list_from_array(arm64_features); 1098 init_cpucap_indirect_list_from_array(arm64_errata); 1099 } 1100 1101 static void __init setup_boot_cpu_capabilities(void); 1102 1103 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1104 { 1105 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1106 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1107 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1108 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1109 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1110 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1111 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1112 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1113 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1114 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1115 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1116 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1117 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1118 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1119 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1120 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1121 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1122 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1123 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1124 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1125 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1126 } 1127 1128 #ifdef CONFIG_ARM64_PSEUDO_NMI 1129 static bool enable_pseudo_nmi; 1130 1131 static int __init early_enable_pseudo_nmi(char *p) 1132 { 1133 return kstrtobool(p, &enable_pseudo_nmi); 1134 } 1135 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1136 1137 static __init void detect_system_supports_pseudo_nmi(void) 1138 { 1139 struct device_node *np; 1140 1141 if (!enable_pseudo_nmi) 1142 return; 1143 1144 /* 1145 * Detect broken MediaTek firmware that doesn't properly save and 1146 * restore GIC priorities. 1147 */ 1148 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1149 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1150 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1151 enable_pseudo_nmi = false; 1152 } 1153 of_node_put(np); 1154 } 1155 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1156 static inline void detect_system_supports_pseudo_nmi(void) { } 1157 #endif 1158 1159 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1160 { 1161 /* Before we start using the tables, make sure it is sorted */ 1162 sort_ftr_regs(); 1163 1164 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1165 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1166 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1167 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1168 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1169 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1170 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1171 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1172 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1173 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1174 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1175 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1176 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1178 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1179 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1180 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1181 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1182 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1183 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1184 1185 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1186 init_32bit_cpu_features(&info->aarch32); 1187 1188 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1189 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1190 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1191 1192 vec_init_vq_map(ARM64_VEC_SVE); 1193 1194 cpacr_restore(cpacr); 1195 } 1196 1197 if (IS_ENABLED(CONFIG_ARM64_SME) && 1198 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1199 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1200 1201 vec_init_vq_map(ARM64_VEC_SME); 1202 1203 cpacr_restore(cpacr); 1204 } 1205 1206 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1207 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1208 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1209 } 1210 1211 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1212 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1213 } 1214 1215 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1216 { 1217 const struct arm64_ftr_bits *ftrp; 1218 1219 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1220 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1221 s64 ftr_new = arm64_ftr_value(ftrp, new); 1222 1223 if (ftr_cur == ftr_new) 1224 continue; 1225 /* Find a safe value */ 1226 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1227 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1228 } 1229 1230 } 1231 1232 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1233 { 1234 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1235 1236 if (!regp) 1237 return 0; 1238 1239 update_cpu_ftr_reg(regp, val); 1240 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1241 return 0; 1242 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1243 regp->name, boot, cpu, val); 1244 return 1; 1245 } 1246 1247 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1248 { 1249 const struct arm64_ftr_bits *ftrp; 1250 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1251 1252 if (!regp) 1253 return; 1254 1255 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1256 if (ftrp->shift == field) { 1257 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1258 break; 1259 } 1260 } 1261 1262 /* Bogus field? */ 1263 WARN_ON(!ftrp->width); 1264 } 1265 1266 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1267 struct cpuinfo_arm64 *boot) 1268 { 1269 static bool boot_cpu_32bit_regs_overridden = false; 1270 1271 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1272 return; 1273 1274 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1275 return; 1276 1277 boot->aarch32 = info->aarch32; 1278 init_32bit_cpu_features(&boot->aarch32); 1279 boot_cpu_32bit_regs_overridden = true; 1280 } 1281 1282 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1283 struct cpuinfo_32bit *boot) 1284 { 1285 int taint = 0; 1286 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1287 1288 /* 1289 * If we don't have AArch32 at EL1, then relax the strictness of 1290 * EL1-dependent register fields to avoid spurious sanity check fails. 1291 */ 1292 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1293 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1294 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1295 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1296 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1297 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1298 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1299 } 1300 1301 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1302 info->reg_id_dfr0, boot->reg_id_dfr0); 1303 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1304 info->reg_id_dfr1, boot->reg_id_dfr1); 1305 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1306 info->reg_id_isar0, boot->reg_id_isar0); 1307 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1308 info->reg_id_isar1, boot->reg_id_isar1); 1309 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1310 info->reg_id_isar2, boot->reg_id_isar2); 1311 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1312 info->reg_id_isar3, boot->reg_id_isar3); 1313 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1314 info->reg_id_isar4, boot->reg_id_isar4); 1315 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1316 info->reg_id_isar5, boot->reg_id_isar5); 1317 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1318 info->reg_id_isar6, boot->reg_id_isar6); 1319 1320 /* 1321 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1322 * ACTLR formats could differ across CPUs and therefore would have to 1323 * be trapped for virtualization anyway. 1324 */ 1325 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1326 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1327 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1328 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1329 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1330 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1331 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1332 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1333 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1334 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1335 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1336 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1337 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1338 info->reg_id_pfr0, boot->reg_id_pfr0); 1339 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1340 info->reg_id_pfr1, boot->reg_id_pfr1); 1341 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1342 info->reg_id_pfr2, boot->reg_id_pfr2); 1343 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1344 info->reg_mvfr0, boot->reg_mvfr0); 1345 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1346 info->reg_mvfr1, boot->reg_mvfr1); 1347 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1348 info->reg_mvfr2, boot->reg_mvfr2); 1349 1350 return taint; 1351 } 1352 1353 /* 1354 * Update system wide CPU feature registers with the values from a 1355 * non-boot CPU. Also performs SANITY checks to make sure that there 1356 * aren't any insane variations from that of the boot CPU. 1357 */ 1358 void update_cpu_features(int cpu, 1359 struct cpuinfo_arm64 *info, 1360 struct cpuinfo_arm64 *boot) 1361 { 1362 int taint = 0; 1363 1364 /* 1365 * The kernel can handle differing I-cache policies, but otherwise 1366 * caches should look identical. Userspace JITs will make use of 1367 * *minLine. 1368 */ 1369 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1370 info->reg_ctr, boot->reg_ctr); 1371 1372 /* 1373 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1374 * could result in too much or too little memory being zeroed if a 1375 * process is preempted and migrated between CPUs. 1376 */ 1377 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1378 info->reg_dczid, boot->reg_dczid); 1379 1380 /* If different, timekeeping will be broken (especially with KVM) */ 1381 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1382 info->reg_cntfrq, boot->reg_cntfrq); 1383 1384 /* 1385 * The kernel uses self-hosted debug features and expects CPUs to 1386 * support identical debug features. We presently need CTX_CMPs, WRPs, 1387 * and BRPs to be identical. 1388 * ID_AA64DFR1 is currently RES0. 1389 */ 1390 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1391 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1392 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1393 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1394 /* 1395 * Even in big.LITTLE, processors should be identical instruction-set 1396 * wise. 1397 */ 1398 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1399 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1400 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1401 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1402 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1403 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1404 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1405 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1406 1407 /* 1408 * Differing PARange support is fine as long as all peripherals and 1409 * memory are mapped within the minimum PARange of all CPUs. 1410 * Linux should not care about secure memory. 1411 */ 1412 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1413 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1414 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1415 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1416 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1417 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1418 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1419 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1420 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1421 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1422 1423 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1424 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1425 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1426 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1427 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1428 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1429 1430 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1431 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1432 1433 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1434 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1435 1436 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1437 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1438 1439 /* Probe vector lengths */ 1440 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1441 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1442 if (!system_capabilities_finalized()) { 1443 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1444 1445 vec_update_vq_map(ARM64_VEC_SVE); 1446 1447 cpacr_restore(cpacr); 1448 } 1449 } 1450 1451 if (IS_ENABLED(CONFIG_ARM64_SME) && 1452 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1453 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1454 1455 /* Probe vector lengths */ 1456 if (!system_capabilities_finalized()) 1457 vec_update_vq_map(ARM64_VEC_SME); 1458 1459 cpacr_restore(cpacr); 1460 } 1461 1462 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1463 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1464 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1465 info->reg_mpamidr, boot->reg_mpamidr); 1466 } 1467 1468 /* 1469 * The kernel uses the LDGM/STGM instructions and the number of tags 1470 * they read/write depends on the GMID_EL1.BS field. Check that the 1471 * value is the same on all CPUs. 1472 */ 1473 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1474 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1475 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1476 info->reg_gmid, boot->reg_gmid); 1477 } 1478 1479 /* 1480 * If we don't have AArch32 at all then skip the checks entirely 1481 * as the register values may be UNKNOWN and we're not going to be 1482 * using them for anything. 1483 * 1484 * This relies on a sanitised view of the AArch64 ID registers 1485 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1486 */ 1487 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1488 lazy_init_32bit_cpu_features(info, boot); 1489 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1490 &boot->aarch32); 1491 } 1492 1493 /* 1494 * Mismatched CPU features are a recipe for disaster. Don't even 1495 * pretend to support them. 1496 */ 1497 if (taint) { 1498 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1499 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1500 } 1501 } 1502 1503 u64 read_sanitised_ftr_reg(u32 id) 1504 { 1505 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1506 1507 if (!regp) 1508 return 0; 1509 return regp->sys_val; 1510 } 1511 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1512 1513 #define read_sysreg_case(r) \ 1514 case r: val = read_sysreg_s(r); break; 1515 1516 /* 1517 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1518 * Read the system register on the current CPU 1519 */ 1520 u64 __read_sysreg_by_encoding(u32 sys_id) 1521 { 1522 struct arm64_ftr_reg *regp; 1523 u64 val; 1524 1525 switch (sys_id) { 1526 read_sysreg_case(SYS_ID_PFR0_EL1); 1527 read_sysreg_case(SYS_ID_PFR1_EL1); 1528 read_sysreg_case(SYS_ID_PFR2_EL1); 1529 read_sysreg_case(SYS_ID_DFR0_EL1); 1530 read_sysreg_case(SYS_ID_DFR1_EL1); 1531 read_sysreg_case(SYS_ID_MMFR0_EL1); 1532 read_sysreg_case(SYS_ID_MMFR1_EL1); 1533 read_sysreg_case(SYS_ID_MMFR2_EL1); 1534 read_sysreg_case(SYS_ID_MMFR3_EL1); 1535 read_sysreg_case(SYS_ID_MMFR4_EL1); 1536 read_sysreg_case(SYS_ID_MMFR5_EL1); 1537 read_sysreg_case(SYS_ID_ISAR0_EL1); 1538 read_sysreg_case(SYS_ID_ISAR1_EL1); 1539 read_sysreg_case(SYS_ID_ISAR2_EL1); 1540 read_sysreg_case(SYS_ID_ISAR3_EL1); 1541 read_sysreg_case(SYS_ID_ISAR4_EL1); 1542 read_sysreg_case(SYS_ID_ISAR5_EL1); 1543 read_sysreg_case(SYS_ID_ISAR6_EL1); 1544 read_sysreg_case(SYS_MVFR0_EL1); 1545 read_sysreg_case(SYS_MVFR1_EL1); 1546 read_sysreg_case(SYS_MVFR2_EL1); 1547 1548 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1549 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1550 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1551 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1552 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1553 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1554 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1556 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1558 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1559 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1560 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1561 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1562 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1563 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1564 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1565 1566 read_sysreg_case(SYS_CNTFRQ_EL0); 1567 read_sysreg_case(SYS_CTR_EL0); 1568 read_sysreg_case(SYS_DCZID_EL0); 1569 1570 default: 1571 BUG(); 1572 return 0; 1573 } 1574 1575 regp = get_arm64_ftr_reg(sys_id); 1576 if (regp) { 1577 val &= ~regp->override->mask; 1578 val |= (regp->override->val & regp->override->mask); 1579 } 1580 1581 return val; 1582 } 1583 1584 #include <linux/irqchip/arm-gic-v3.h> 1585 1586 static bool 1587 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1588 { 1589 return true; 1590 } 1591 1592 static bool 1593 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1594 { 1595 int val, min, max; 1596 u64 tmp; 1597 1598 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1599 entry->field_width, 1600 entry->sign); 1601 1602 tmp = entry->min_field_value; 1603 tmp <<= entry->field_pos; 1604 1605 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1606 entry->field_width, 1607 entry->sign); 1608 1609 tmp = entry->max_field_value; 1610 tmp <<= entry->field_pos; 1611 1612 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1613 entry->field_width, 1614 entry->sign); 1615 1616 return val >= min && val <= max; 1617 } 1618 1619 static u64 1620 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1621 { 1622 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1623 if (scope == SCOPE_SYSTEM) 1624 return read_sanitised_ftr_reg(entry->sys_reg); 1625 else 1626 return __read_sysreg_by_encoding(entry->sys_reg); 1627 } 1628 1629 static bool 1630 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1631 { 1632 int mask; 1633 struct arm64_ftr_reg *regp; 1634 u64 val = read_scoped_sysreg(entry, scope); 1635 1636 regp = get_arm64_ftr_reg(entry->sys_reg); 1637 if (!regp) 1638 return false; 1639 1640 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1641 entry->field_pos, 1642 entry->field_width); 1643 if (!mask) 1644 return false; 1645 1646 return feature_matches(val, entry); 1647 } 1648 1649 static bool 1650 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1651 { 1652 u64 val = read_scoped_sysreg(entry, scope); 1653 return feature_matches(val, entry); 1654 } 1655 1656 const struct cpumask *system_32bit_el0_cpumask(void) 1657 { 1658 if (!system_supports_32bit_el0()) 1659 return cpu_none_mask; 1660 1661 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1662 return cpu_32bit_el0_mask; 1663 1664 return cpu_possible_mask; 1665 } 1666 1667 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1668 { 1669 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1670 } 1671 1672 static int __init parse_32bit_el0_param(char *str) 1673 { 1674 allow_mismatched_32bit_el0 = true; 1675 return 0; 1676 } 1677 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1678 1679 static ssize_t aarch32_el0_show(struct device *dev, 1680 struct device_attribute *attr, char *buf) 1681 { 1682 const struct cpumask *mask = system_32bit_el0_cpumask(); 1683 1684 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1685 } 1686 static const DEVICE_ATTR_RO(aarch32_el0); 1687 1688 static int __init aarch32_el0_sysfs_init(void) 1689 { 1690 struct device *dev_root; 1691 int ret = 0; 1692 1693 if (!allow_mismatched_32bit_el0) 1694 return 0; 1695 1696 dev_root = bus_get_dev_root(&cpu_subsys); 1697 if (dev_root) { 1698 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1699 put_device(dev_root); 1700 } 1701 return ret; 1702 } 1703 device_initcall(aarch32_el0_sysfs_init); 1704 1705 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1706 { 1707 if (!has_cpuid_feature(entry, scope)) 1708 return allow_mismatched_32bit_el0; 1709 1710 if (scope == SCOPE_SYSTEM) 1711 pr_info("detected: 32-bit EL0 Support\n"); 1712 1713 return true; 1714 } 1715 1716 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1717 { 1718 bool has_sre; 1719 1720 if (!has_cpuid_feature(entry, scope)) 1721 return false; 1722 1723 has_sre = gic_enable_sre(); 1724 if (!has_sre) 1725 pr_warn_once("%s present but disabled by higher exception level\n", 1726 entry->desc); 1727 1728 return has_sre; 1729 } 1730 1731 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1732 int scope) 1733 { 1734 u64 ctr; 1735 1736 if (scope == SCOPE_SYSTEM) 1737 ctr = arm64_ftr_reg_ctrel0.sys_val; 1738 else 1739 ctr = read_cpuid_effective_cachetype(); 1740 1741 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1742 } 1743 1744 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1745 { 1746 /* 1747 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1748 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1749 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1750 * value. 1751 */ 1752 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1753 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1754 } 1755 1756 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1757 int scope) 1758 { 1759 u64 ctr; 1760 1761 if (scope == SCOPE_SYSTEM) 1762 ctr = arm64_ftr_reg_ctrel0.sys_val; 1763 else 1764 ctr = read_cpuid_cachetype(); 1765 1766 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1767 } 1768 1769 static bool __maybe_unused 1770 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1771 { 1772 /* 1773 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1774 * may share TLB entries with a CPU stuck in the crashed 1775 * kernel. 1776 */ 1777 if (is_kdump_kernel()) 1778 return false; 1779 1780 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1781 return false; 1782 1783 return has_cpuid_feature(entry, scope); 1784 } 1785 1786 static bool __meltdown_safe = true; 1787 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1788 1789 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1790 int scope) 1791 { 1792 /* List of CPUs that are not vulnerable and don't need KPTI */ 1793 static const struct midr_range kpti_safe_list[] = { 1794 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1795 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1796 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1797 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1798 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1799 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1800 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1801 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1802 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1803 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1804 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1805 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1806 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1807 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1808 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1809 { /* sentinel */ } 1810 }; 1811 char const *str = "kpti command line option"; 1812 bool meltdown_safe; 1813 1814 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1815 1816 /* Defer to CPU feature registers */ 1817 if (has_cpuid_feature(entry, scope)) 1818 meltdown_safe = true; 1819 1820 if (!meltdown_safe) 1821 __meltdown_safe = false; 1822 1823 /* 1824 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1825 * ThunderX leads to apparent I-cache corruption of kernel text, which 1826 * ends as well as you might imagine. Don't even try. We cannot rely 1827 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1828 * because cpucap detection order may change. However, since we know 1829 * affected CPUs are always in a homogeneous configuration, it is 1830 * safe to rely on this_cpu_has_cap() here. 1831 */ 1832 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1833 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1834 __kpti_forced = -1; 1835 } 1836 1837 /* Useful for KASLR robustness */ 1838 if (kaslr_enabled() && kaslr_requires_kpti()) { 1839 if (!__kpti_forced) { 1840 str = "KASLR"; 1841 __kpti_forced = 1; 1842 } 1843 } 1844 1845 if (cpu_mitigations_off() && !__kpti_forced) { 1846 str = "mitigations=off"; 1847 __kpti_forced = -1; 1848 } 1849 1850 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1851 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1852 return false; 1853 } 1854 1855 /* Forced? */ 1856 if (__kpti_forced) { 1857 pr_info_once("kernel page table isolation forced %s by %s\n", 1858 __kpti_forced > 0 ? "ON" : "OFF", str); 1859 return __kpti_forced > 0; 1860 } 1861 1862 return !meltdown_safe; 1863 } 1864 1865 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1866 { 1867 /* 1868 * Although the Apple M2 family appears to support NV1, the 1869 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1870 * that it doesn't support NV1 at all. 1871 */ 1872 static const struct midr_range nv1_ni_list[] = { 1873 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1874 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1875 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1876 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1877 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1878 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1879 {} 1880 }; 1881 1882 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1883 !(has_cpuid_feature(entry, scope) || 1884 is_midr_in_range_list(nv1_ni_list))); 1885 } 1886 1887 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1888 static bool has_lpa2_at_stage1(u64 mmfr0) 1889 { 1890 unsigned int tgran; 1891 1892 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1893 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1894 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1895 } 1896 1897 static bool has_lpa2_at_stage2(u64 mmfr0) 1898 { 1899 unsigned int tgran; 1900 1901 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1902 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1903 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1904 } 1905 1906 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1907 { 1908 u64 mmfr0; 1909 1910 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1911 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1912 } 1913 #else 1914 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1915 { 1916 return false; 1917 } 1918 #endif 1919 1920 #ifdef CONFIG_HW_PERF_EVENTS 1921 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1922 { 1923 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1924 unsigned int pmuver; 1925 1926 /* 1927 * PMUVer follows the standard ID scheme for an unsigned field with the 1928 * exception of 0xF (IMP_DEF) which is treated specially and implies 1929 * FEAT_PMUv3 is not implemented. 1930 * 1931 * See DDI0487L.a D24.1.3.2 for more details. 1932 */ 1933 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1934 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1935 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1936 return false; 1937 1938 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1939 } 1940 #endif 1941 1942 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1943 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1944 1945 extern 1946 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1947 phys_addr_t size, pgprot_t prot, 1948 phys_addr_t (*pgtable_alloc)(int), int flags); 1949 1950 static phys_addr_t __initdata kpti_ng_temp_alloc; 1951 1952 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1953 { 1954 kpti_ng_temp_alloc -= PAGE_SIZE; 1955 return kpti_ng_temp_alloc; 1956 } 1957 1958 static int __init __kpti_install_ng_mappings(void *__unused) 1959 { 1960 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1961 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1962 kpti_remap_fn *remap_fn; 1963 1964 int cpu = smp_processor_id(); 1965 int levels = CONFIG_PGTABLE_LEVELS; 1966 int order = order_base_2(levels); 1967 u64 kpti_ng_temp_pgd_pa = 0; 1968 pgd_t *kpti_ng_temp_pgd; 1969 u64 alloc = 0; 1970 1971 if (levels == 5 && !pgtable_l5_enabled()) 1972 levels = 4; 1973 else if (levels == 4 && !pgtable_l4_enabled()) 1974 levels = 3; 1975 1976 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1977 1978 if (!cpu) { 1979 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1980 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1981 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1982 1983 // 1984 // Create a minimal page table hierarchy that permits us to map 1985 // the swapper page tables temporarily as we traverse them. 1986 // 1987 // The physical pages are laid out as follows: 1988 // 1989 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1990 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1991 // +--------+-\-------+-\------ +-\------ +-///--------+ 1992 // ^ 1993 // The first page is mapped into this hierarchy at a PMD_SHIFT 1994 // aligned virtual address, so that we can manipulate the PTE 1995 // level entries while the mapping is active. The first entry 1996 // covers the PTE[] page itself, the remaining entries are free 1997 // to be used as a ad-hoc fixmap. 1998 // 1999 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 2000 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 2001 kpti_ng_pgd_alloc, 0); 2002 } 2003 2004 cpu_install_idmap(); 2005 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 2006 cpu_uninstall_idmap(); 2007 2008 if (!cpu) { 2009 free_pages(alloc, order); 2010 arm64_use_ng_mappings = true; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static void __init kpti_install_ng_mappings(void) 2017 { 2018 /* Check whether KPTI is going to be used */ 2019 if (!arm64_kernel_unmapped_at_el0()) 2020 return; 2021 2022 /* 2023 * We don't need to rewrite the page-tables if either we've done 2024 * it already or we have KASLR enabled and therefore have not 2025 * created any global mappings at all. 2026 */ 2027 if (arm64_use_ng_mappings) 2028 return; 2029 2030 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 2031 } 2032 2033 #else 2034 static inline void kpti_install_ng_mappings(void) 2035 { 2036 } 2037 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 2038 2039 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 2040 { 2041 if (__this_cpu_read(this_cpu_vector) == vectors) { 2042 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2043 2044 __this_cpu_write(this_cpu_vector, v); 2045 } 2046 2047 } 2048 2049 static int __init parse_kpti(char *str) 2050 { 2051 bool enabled; 2052 int ret = kstrtobool(str, &enabled); 2053 2054 if (ret) 2055 return ret; 2056 2057 __kpti_forced = enabled ? 1 : -1; 2058 return 0; 2059 } 2060 early_param("kpti", parse_kpti); 2061 2062 #ifdef CONFIG_ARM64_HW_AFDBM 2063 static struct cpumask dbm_cpus __read_mostly; 2064 2065 static inline void __cpu_enable_hw_dbm(void) 2066 { 2067 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2068 2069 write_sysreg(tcr, tcr_el1); 2070 isb(); 2071 local_flush_tlb_all(); 2072 } 2073 2074 static bool cpu_has_broken_dbm(void) 2075 { 2076 /* List of CPUs which have broken DBM support. */ 2077 static const struct midr_range cpus[] = { 2078 #ifdef CONFIG_ARM64_ERRATUM_1024718 2079 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2080 /* Kryo4xx Silver (rdpe => r1p0) */ 2081 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2082 #endif 2083 #ifdef CONFIG_ARM64_ERRATUM_2051678 2084 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2085 #endif 2086 {}, 2087 }; 2088 2089 return is_midr_in_range_list(cpus); 2090 } 2091 2092 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2093 { 2094 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2095 !cpu_has_broken_dbm(); 2096 } 2097 2098 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2099 { 2100 if (cpu_can_use_dbm(cap)) { 2101 __cpu_enable_hw_dbm(); 2102 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2103 } 2104 } 2105 2106 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2107 int __unused) 2108 { 2109 /* 2110 * DBM is a non-conflicting feature. i.e, the kernel can safely 2111 * run a mix of CPUs with and without the feature. So, we 2112 * unconditionally enable the capability to allow any late CPU 2113 * to use the feature. We only enable the control bits on the 2114 * CPU, if it is supported. 2115 */ 2116 2117 return true; 2118 } 2119 2120 #endif 2121 2122 #ifdef CONFIG_ARM64_AMU_EXTN 2123 2124 /* 2125 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2126 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2127 * information regarding all the events that it supports. When a CPU bit is 2128 * set in the cpumask, the user of this feature can only rely on the presence 2129 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2130 * counters are enabled or access to these counters is enabled by code 2131 * executed at higher exception levels (firmware). 2132 */ 2133 static struct cpumask amu_cpus __read_mostly; 2134 2135 bool cpu_has_amu_feat(int cpu) 2136 { 2137 return cpumask_test_cpu(cpu, &amu_cpus); 2138 } 2139 2140 int get_cpu_with_amu_feat(void) 2141 { 2142 return cpumask_any(&amu_cpus); 2143 } 2144 2145 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2146 { 2147 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2148 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2149 2150 /* 0 reference values signal broken/disabled counters */ 2151 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2152 update_freq_counters_refs(); 2153 } 2154 } 2155 2156 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2157 int __unused) 2158 { 2159 /* 2160 * The AMU extension is a non-conflicting feature: the kernel can 2161 * safely run a mix of CPUs with and without support for the 2162 * activity monitors extension. Therefore, unconditionally enable 2163 * the capability to allow any late CPU to use the feature. 2164 * 2165 * With this feature unconditionally enabled, the cpu_enable 2166 * function will be called for all CPUs that match the criteria, 2167 * including secondary and hotplugged, marking this feature as 2168 * present on that respective CPU. The enable function will also 2169 * print a detection message. 2170 */ 2171 2172 return true; 2173 } 2174 #else 2175 int get_cpu_with_amu_feat(void) 2176 { 2177 return nr_cpu_ids; 2178 } 2179 #endif 2180 2181 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2182 { 2183 return is_kernel_in_hyp_mode(); 2184 } 2185 2186 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2187 { 2188 /* 2189 * Copy register values that aren't redirected by hardware. 2190 * 2191 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2192 * this value to tpidr_el2 before we patch the code. Once we've done 2193 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2194 * do anything here. 2195 */ 2196 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2197 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2198 } 2199 2200 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2201 int scope) 2202 { 2203 if (kvm_get_mode() != KVM_MODE_NV) 2204 return false; 2205 2206 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2207 pr_warn("unavailable: %s\n", cap->desc); 2208 return false; 2209 } 2210 2211 return true; 2212 } 2213 2214 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2215 int __unused) 2216 { 2217 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2218 } 2219 2220 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2221 { 2222 /* 2223 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2224 * as possible. This list is therefore an allow-list of known-good 2225 * implementations that both support BBML2 and additionally, fulfill the 2226 * extra constraint of never generating TLB conflict aborts when using 2227 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2228 * kernel contexts difficult to prove safe against recursive aborts). 2229 * 2230 * Note that implementations can only be considered "known-good" if their 2231 * implementors attest to the fact that the implementation never raises 2232 * TLB conflict aborts for BBML2 mapping granularity changes. 2233 */ 2234 static const struct midr_range supports_bbml2_noabort_list[] = { 2235 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2236 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2237 {} 2238 }; 2239 2240 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2241 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2242 return false; 2243 2244 /* 2245 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2246 * about whether the MIDR check passes. 2247 */ 2248 2249 return true; 2250 } 2251 2252 #ifdef CONFIG_ARM64_PAN 2253 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2254 { 2255 /* 2256 * We modify PSTATE. This won't work from irq context as the PSTATE 2257 * is discarded once we return from the exception. 2258 */ 2259 WARN_ON_ONCE(in_interrupt()); 2260 2261 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2262 set_pstate_pan(1); 2263 } 2264 #endif /* CONFIG_ARM64_PAN */ 2265 2266 #ifdef CONFIG_ARM64_RAS_EXTN 2267 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2268 { 2269 /* Firmware may have left a deferred SError in this register. */ 2270 write_sysreg_s(0, SYS_DISR_EL1); 2271 } 2272 #endif /* CONFIG_ARM64_RAS_EXTN */ 2273 2274 #ifdef CONFIG_ARM64_PTR_AUTH 2275 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2276 { 2277 int boot_val, sec_val; 2278 2279 /* We don't expect to be called with SCOPE_SYSTEM */ 2280 WARN_ON(scope == SCOPE_SYSTEM); 2281 /* 2282 * The ptr-auth feature levels are not intercompatible with lower 2283 * levels. Hence we must match ptr-auth feature level of the secondary 2284 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2285 * from the sanitised register whereas direct register read is done for 2286 * the secondary CPUs. 2287 * The sanitised feature state is guaranteed to match that of the 2288 * boot CPU as a mismatched secondary CPU is parked before it gets 2289 * a chance to update the state, with the capability. 2290 */ 2291 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2292 entry->field_pos, entry->sign); 2293 if (scope & SCOPE_BOOT_CPU) 2294 return boot_val >= entry->min_field_value; 2295 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2296 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2297 entry->field_pos, entry->sign); 2298 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2299 } 2300 2301 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2302 int scope) 2303 { 2304 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2305 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2306 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2307 2308 return apa || apa3 || api; 2309 } 2310 2311 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2312 int __unused) 2313 { 2314 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2315 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2316 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2317 2318 return gpa || gpa3 || gpi; 2319 } 2320 #endif /* CONFIG_ARM64_PTR_AUTH */ 2321 2322 #ifdef CONFIG_ARM64_E0PD 2323 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2324 { 2325 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2326 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2327 } 2328 #endif /* CONFIG_ARM64_E0PD */ 2329 2330 #ifdef CONFIG_ARM64_PSEUDO_NMI 2331 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2332 int scope) 2333 { 2334 /* 2335 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2336 * feature, so will be detected earlier. 2337 */ 2338 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2339 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2340 return false; 2341 2342 return enable_pseudo_nmi; 2343 } 2344 2345 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2346 int scope) 2347 { 2348 /* 2349 * If we're not using priority masking then we won't be poking PMR_EL1, 2350 * and there's no need to relax synchronization of writes to it, and 2351 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2352 * that. 2353 * 2354 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2355 * feature, so will be detected earlier. 2356 */ 2357 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2358 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2359 return false; 2360 2361 /* 2362 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2363 * hint for interrupt distribution, a DSB is not necessary when 2364 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2365 * 2366 * Linux itself doesn't use 1:N distribution, so has no need to 2367 * set PMHE. The only reason to have it set is if EL3 requires it 2368 * (and we can't change it). 2369 */ 2370 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2371 } 2372 #endif 2373 2374 #ifdef CONFIG_ARM64_BTI 2375 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2376 { 2377 /* 2378 * Use of X16/X17 for tail-calls and trampolines that jump to 2379 * function entry points using BR is a requirement for 2380 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2381 * So, be strict and forbid other BRs using other registers to 2382 * jump onto a PACIxSP instruction: 2383 */ 2384 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2385 isb(); 2386 } 2387 #endif /* CONFIG_ARM64_BTI */ 2388 2389 #ifdef CONFIG_ARM64_MTE 2390 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2391 { 2392 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2393 2394 mte_cpu_setup(); 2395 2396 /* 2397 * Clear the tags in the zero page. This needs to be done via the 2398 * linear map which has the Tagged attribute. 2399 */ 2400 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2401 mte_clear_page_tags(lm_alias(empty_zero_page)); 2402 set_page_mte_tagged(ZERO_PAGE(0)); 2403 } 2404 2405 kasan_init_hw_tags_cpu(); 2406 } 2407 #endif /* CONFIG_ARM64_MTE */ 2408 2409 static void user_feature_fixup(void) 2410 { 2411 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2412 struct arm64_ftr_reg *regp; 2413 2414 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2415 if (regp) 2416 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2417 } 2418 2419 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2420 struct arm64_ftr_reg *regp; 2421 2422 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2423 if (regp) 2424 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2425 } 2426 } 2427 2428 static void elf_hwcap_fixup(void) 2429 { 2430 #ifdef CONFIG_COMPAT 2431 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2432 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2433 #endif /* CONFIG_COMPAT */ 2434 } 2435 2436 #ifdef CONFIG_KVM 2437 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2438 { 2439 return kvm_get_mode() == KVM_MODE_PROTECTED; 2440 } 2441 #endif /* CONFIG_KVM */ 2442 2443 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2444 { 2445 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2446 } 2447 2448 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2449 { 2450 set_pstate_dit(1); 2451 } 2452 2453 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2454 { 2455 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2456 } 2457 2458 #ifdef CONFIG_ARM64_POE 2459 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2460 { 2461 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2462 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2463 } 2464 #endif 2465 2466 #ifdef CONFIG_ARM64_GCS 2467 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2468 { 2469 /* GCSPR_EL0 is always readable */ 2470 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2471 } 2472 #endif 2473 2474 /* Internal helper functions to match cpu capability type */ 2475 static bool 2476 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2477 { 2478 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2479 } 2480 2481 static bool 2482 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2483 { 2484 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2485 } 2486 2487 static bool 2488 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2489 { 2490 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2491 } 2492 2493 static bool 2494 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2495 { 2496 if (!has_cpuid_feature(entry, scope)) 2497 return false; 2498 2499 /* Check firmware actually enabled MPAM on this cpu. */ 2500 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2501 } 2502 2503 static void 2504 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2505 { 2506 /* 2507 * Access by the kernel (at EL1) should use the reserved PARTID 2508 * which is configured unrestricted. This avoids priority-inversion 2509 * where latency sensitive tasks have to wait for a task that has 2510 * been throttled to release the lock. 2511 */ 2512 write_sysreg_s(0, SYS_MPAM1_EL1); 2513 } 2514 2515 static bool 2516 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2517 { 2518 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2519 2520 return idr & MPAMIDR_EL1_HAS_HCR; 2521 } 2522 2523 static const struct arm64_cpu_capabilities arm64_features[] = { 2524 { 2525 .capability = ARM64_ALWAYS_BOOT, 2526 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2527 .matches = has_always, 2528 }, 2529 { 2530 .capability = ARM64_ALWAYS_SYSTEM, 2531 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2532 .matches = has_always, 2533 }, 2534 { 2535 .desc = "GICv3 CPU interface", 2536 .capability = ARM64_HAS_GICV3_CPUIF, 2537 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2538 .matches = has_useable_gicv3_cpuif, 2539 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2540 }, 2541 { 2542 .desc = "Enhanced Counter Virtualization", 2543 .capability = ARM64_HAS_ECV, 2544 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2545 .matches = has_cpuid_feature, 2546 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2547 }, 2548 { 2549 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2550 .capability = ARM64_HAS_ECV_CNTPOFF, 2551 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2552 .matches = has_cpuid_feature, 2553 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2554 }, 2555 #ifdef CONFIG_ARM64_PAN 2556 { 2557 .desc = "Privileged Access Never", 2558 .capability = ARM64_HAS_PAN, 2559 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2560 .matches = has_cpuid_feature, 2561 .cpu_enable = cpu_enable_pan, 2562 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2563 }, 2564 #endif /* CONFIG_ARM64_PAN */ 2565 #ifdef CONFIG_ARM64_EPAN 2566 { 2567 .desc = "Enhanced Privileged Access Never", 2568 .capability = ARM64_HAS_EPAN, 2569 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2570 .matches = has_cpuid_feature, 2571 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2572 }, 2573 #endif /* CONFIG_ARM64_EPAN */ 2574 #ifdef CONFIG_ARM64_LSE_ATOMICS 2575 { 2576 .desc = "LSE atomic instructions", 2577 .capability = ARM64_HAS_LSE_ATOMICS, 2578 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2579 .matches = has_cpuid_feature, 2580 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2581 }, 2582 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2583 { 2584 .desc = "Virtualization Host Extensions", 2585 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2586 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2587 .matches = runs_at_el2, 2588 .cpu_enable = cpu_copy_el2regs, 2589 }, 2590 { 2591 .desc = "Nested Virtualization Support", 2592 .capability = ARM64_HAS_NESTED_VIRT, 2593 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2594 .matches = has_nested_virt_support, 2595 .match_list = (const struct arm64_cpu_capabilities []){ 2596 { 2597 .matches = has_cpuid_feature, 2598 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2599 }, 2600 { 2601 .matches = has_cpuid_feature, 2602 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2603 }, 2604 { /* Sentinel */ } 2605 }, 2606 }, 2607 { 2608 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2609 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2610 .matches = has_32bit_el0, 2611 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2612 }, 2613 #ifdef CONFIG_KVM 2614 { 2615 .desc = "32-bit EL1 Support", 2616 .capability = ARM64_HAS_32BIT_EL1, 2617 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2618 .matches = has_cpuid_feature, 2619 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2620 }, 2621 { 2622 .desc = "Protected KVM", 2623 .capability = ARM64_KVM_PROTECTED_MODE, 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .matches = is_kvm_protected_mode, 2626 }, 2627 { 2628 .desc = "HCRX_EL2 register", 2629 .capability = ARM64_HAS_HCX, 2630 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2631 .matches = has_cpuid_feature, 2632 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2633 }, 2634 #endif 2635 { 2636 .desc = "Kernel page table isolation (KPTI)", 2637 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2638 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2639 .cpu_enable = cpu_enable_kpti, 2640 .matches = unmap_kernel_at_el0, 2641 /* 2642 * The ID feature fields below are used to indicate that 2643 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2644 * more details. 2645 */ 2646 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2647 }, 2648 { 2649 .capability = ARM64_HAS_FPSIMD, 2650 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2651 .matches = has_cpuid_feature, 2652 .cpu_enable = cpu_enable_fpsimd, 2653 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2654 }, 2655 #ifdef CONFIG_ARM64_PMEM 2656 { 2657 .desc = "Data cache clean to Point of Persistence", 2658 .capability = ARM64_HAS_DCPOP, 2659 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2660 .matches = has_cpuid_feature, 2661 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2662 }, 2663 { 2664 .desc = "Data cache clean to Point of Deep Persistence", 2665 .capability = ARM64_HAS_DCPODP, 2666 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2667 .matches = has_cpuid_feature, 2668 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2669 }, 2670 #endif 2671 #ifdef CONFIG_ARM64_SVE 2672 { 2673 .desc = "Scalable Vector Extension", 2674 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2675 .capability = ARM64_SVE, 2676 .cpu_enable = cpu_enable_sve, 2677 .matches = has_cpuid_feature, 2678 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2679 }, 2680 #endif /* CONFIG_ARM64_SVE */ 2681 #ifdef CONFIG_ARM64_RAS_EXTN 2682 { 2683 .desc = "RAS Extension Support", 2684 .capability = ARM64_HAS_RAS_EXTN, 2685 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2686 .matches = has_cpuid_feature, 2687 .cpu_enable = cpu_clear_disr, 2688 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2689 }, 2690 #endif /* CONFIG_ARM64_RAS_EXTN */ 2691 #ifdef CONFIG_ARM64_AMU_EXTN 2692 { 2693 .desc = "Activity Monitors Unit (AMU)", 2694 .capability = ARM64_HAS_AMU_EXTN, 2695 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2696 .matches = has_amu, 2697 .cpu_enable = cpu_amu_enable, 2698 .cpus = &amu_cpus, 2699 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2700 }, 2701 #endif /* CONFIG_ARM64_AMU_EXTN */ 2702 { 2703 .desc = "Data cache clean to the PoU not required for I/D coherence", 2704 .capability = ARM64_HAS_CACHE_IDC, 2705 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2706 .matches = has_cache_idc, 2707 .cpu_enable = cpu_emulate_effective_ctr, 2708 }, 2709 { 2710 .desc = "Instruction cache invalidation not required for I/D coherence", 2711 .capability = ARM64_HAS_CACHE_DIC, 2712 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2713 .matches = has_cache_dic, 2714 }, 2715 { 2716 .desc = "Stage-2 Force Write-Back", 2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2718 .capability = ARM64_HAS_STAGE2_FWB, 2719 .matches = has_cpuid_feature, 2720 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2721 }, 2722 { 2723 .desc = "ARMv8.4 Translation Table Level", 2724 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2725 .capability = ARM64_HAS_ARMv8_4_TTL, 2726 .matches = has_cpuid_feature, 2727 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2728 }, 2729 { 2730 .desc = "TLB range maintenance instructions", 2731 .capability = ARM64_HAS_TLB_RANGE, 2732 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2733 .matches = has_cpuid_feature, 2734 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2735 }, 2736 #ifdef CONFIG_ARM64_HW_AFDBM 2737 { 2738 .desc = "Hardware dirty bit management", 2739 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2740 .capability = ARM64_HW_DBM, 2741 .matches = has_hw_dbm, 2742 .cpu_enable = cpu_enable_hw_dbm, 2743 .cpus = &dbm_cpus, 2744 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2745 }, 2746 #endif 2747 #ifdef CONFIG_ARM64_HAFT 2748 { 2749 .desc = "Hardware managed Access Flag for Table Descriptors", 2750 /* 2751 * Contrary to the page/block access flag, the table access flag 2752 * cannot be emulated in software (no access fault will occur). 2753 * Therefore this should be used only if it's supported system 2754 * wide. 2755 */ 2756 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2757 .capability = ARM64_HAFT, 2758 .matches = has_cpuid_feature, 2759 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2760 }, 2761 #endif 2762 { 2763 .desc = "CRC32 instructions", 2764 .capability = ARM64_HAS_CRC32, 2765 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2766 .matches = has_cpuid_feature, 2767 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2768 }, 2769 { 2770 .desc = "Speculative Store Bypassing Safe (SSBS)", 2771 .capability = ARM64_SSBS, 2772 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2773 .matches = has_cpuid_feature, 2774 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2775 }, 2776 #ifdef CONFIG_ARM64_CNP 2777 { 2778 .desc = "Common not Private translations", 2779 .capability = ARM64_HAS_CNP, 2780 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2781 .matches = has_useable_cnp, 2782 .cpu_enable = cpu_enable_cnp, 2783 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2784 }, 2785 #endif 2786 { 2787 .desc = "Speculation barrier (SB)", 2788 .capability = ARM64_HAS_SB, 2789 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2792 }, 2793 #ifdef CONFIG_ARM64_PTR_AUTH 2794 { 2795 .desc = "Address authentication (architected QARMA5 algorithm)", 2796 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2797 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2798 .matches = has_address_auth_cpucap, 2799 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2800 }, 2801 { 2802 .desc = "Address authentication (architected QARMA3 algorithm)", 2803 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2804 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2805 .matches = has_address_auth_cpucap, 2806 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2807 }, 2808 { 2809 .desc = "Address authentication (IMP DEF algorithm)", 2810 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2811 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2812 .matches = has_address_auth_cpucap, 2813 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2814 }, 2815 { 2816 .capability = ARM64_HAS_ADDRESS_AUTH, 2817 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2818 .matches = has_address_auth_metacap, 2819 }, 2820 { 2821 .desc = "Generic authentication (architected QARMA5 algorithm)", 2822 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2823 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2824 .matches = has_cpuid_feature, 2825 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2826 }, 2827 { 2828 .desc = "Generic authentication (architected QARMA3 algorithm)", 2829 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2831 .matches = has_cpuid_feature, 2832 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2833 }, 2834 { 2835 .desc = "Generic authentication (IMP DEF algorithm)", 2836 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2837 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2838 .matches = has_cpuid_feature, 2839 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2840 }, 2841 { 2842 .capability = ARM64_HAS_GENERIC_AUTH, 2843 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2844 .matches = has_generic_auth, 2845 }, 2846 #endif /* CONFIG_ARM64_PTR_AUTH */ 2847 #ifdef CONFIG_ARM64_PSEUDO_NMI 2848 { 2849 /* 2850 * Depends on having GICv3 2851 */ 2852 .desc = "IRQ priority masking", 2853 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2854 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2855 .matches = can_use_gic_priorities, 2856 }, 2857 { 2858 /* 2859 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2860 */ 2861 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2862 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2863 .matches = has_gic_prio_relaxed_sync, 2864 }, 2865 #endif 2866 #ifdef CONFIG_ARM64_E0PD 2867 { 2868 .desc = "E0PD", 2869 .capability = ARM64_HAS_E0PD, 2870 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2871 .cpu_enable = cpu_enable_e0pd, 2872 .matches = has_cpuid_feature, 2873 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2874 }, 2875 #endif 2876 { 2877 .desc = "Random Number Generator", 2878 .capability = ARM64_HAS_RNG, 2879 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2880 .matches = has_cpuid_feature, 2881 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2882 }, 2883 #ifdef CONFIG_ARM64_BTI 2884 { 2885 .desc = "Branch Target Identification", 2886 .capability = ARM64_BTI, 2887 #ifdef CONFIG_ARM64_BTI_KERNEL 2888 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2889 #else 2890 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2891 #endif 2892 .matches = has_cpuid_feature, 2893 .cpu_enable = bti_enable, 2894 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2895 }, 2896 #endif 2897 #ifdef CONFIG_ARM64_MTE 2898 { 2899 .desc = "Memory Tagging Extension", 2900 .capability = ARM64_MTE, 2901 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2902 .matches = has_cpuid_feature, 2903 .cpu_enable = cpu_enable_mte, 2904 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2905 }, 2906 { 2907 .desc = "Asymmetric MTE Tag Check Fault", 2908 .capability = ARM64_MTE_ASYMM, 2909 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2910 .matches = has_cpuid_feature, 2911 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2912 }, 2913 { 2914 .desc = "FAR on MTE Tag Check Fault", 2915 .capability = ARM64_MTE_FAR, 2916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2917 .matches = has_cpuid_feature, 2918 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2919 }, 2920 { 2921 .desc = "Store Only MTE Tag Check", 2922 .capability = ARM64_MTE_STORE_ONLY, 2923 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2924 .matches = has_cpuid_feature, 2925 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2926 }, 2927 #endif /* CONFIG_ARM64_MTE */ 2928 { 2929 .desc = "RCpc load-acquire (LDAPR)", 2930 .capability = ARM64_HAS_LDAPR, 2931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2932 .matches = has_cpuid_feature, 2933 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2934 }, 2935 { 2936 .desc = "Fine Grained Traps", 2937 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2938 .capability = ARM64_HAS_FGT, 2939 .matches = has_cpuid_feature, 2940 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2941 }, 2942 { 2943 .desc = "Fine Grained Traps 2", 2944 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2945 .capability = ARM64_HAS_FGT2, 2946 .matches = has_cpuid_feature, 2947 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2948 }, 2949 #ifdef CONFIG_ARM64_SME 2950 { 2951 .desc = "Scalable Matrix Extension", 2952 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2953 .capability = ARM64_SME, 2954 .matches = has_cpuid_feature, 2955 .cpu_enable = cpu_enable_sme, 2956 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2957 }, 2958 /* FA64 should be sorted after the base SME capability */ 2959 { 2960 .desc = "FA64", 2961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2962 .capability = ARM64_SME_FA64, 2963 .matches = has_cpuid_feature, 2964 .cpu_enable = cpu_enable_fa64, 2965 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2966 }, 2967 { 2968 .desc = "SME2", 2969 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2970 .capability = ARM64_SME2, 2971 .matches = has_cpuid_feature, 2972 .cpu_enable = cpu_enable_sme2, 2973 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2974 }, 2975 #endif /* CONFIG_ARM64_SME */ 2976 { 2977 .desc = "WFx with timeout", 2978 .capability = ARM64_HAS_WFXT, 2979 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2980 .matches = has_cpuid_feature, 2981 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2982 }, 2983 { 2984 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2985 .capability = ARM64_HAS_TIDCP1, 2986 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2987 .matches = has_cpuid_feature, 2988 .cpu_enable = cpu_trap_el0_impdef, 2989 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2990 }, 2991 { 2992 .desc = "Data independent timing control (DIT)", 2993 .capability = ARM64_HAS_DIT, 2994 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2995 .matches = has_cpuid_feature, 2996 .cpu_enable = cpu_enable_dit, 2997 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2998 }, 2999 { 3000 .desc = "Memory Copy and Memory Set instructions", 3001 .capability = ARM64_HAS_MOPS, 3002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3003 .matches = has_cpuid_feature, 3004 .cpu_enable = cpu_enable_mops, 3005 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3006 }, 3007 { 3008 .capability = ARM64_HAS_TCR2, 3009 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3010 .matches = has_cpuid_feature, 3011 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3012 }, 3013 { 3014 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3015 .capability = ARM64_HAS_S1PIE, 3016 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3017 .matches = has_cpuid_feature, 3018 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3019 }, 3020 { 3021 .desc = "VHE for hypervisor only", 3022 .capability = ARM64_KVM_HVHE, 3023 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3024 .matches = hvhe_possible, 3025 }, 3026 { 3027 .desc = "Enhanced Virtualization Traps", 3028 .capability = ARM64_HAS_EVT, 3029 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3030 .matches = has_cpuid_feature, 3031 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3032 }, 3033 { 3034 .desc = "BBM Level 2 without TLB conflict abort", 3035 .capability = ARM64_HAS_BBML2_NOABORT, 3036 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3037 .matches = has_bbml2_noabort, 3038 }, 3039 { 3040 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3041 .capability = ARM64_HAS_LPA2, 3042 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3043 .matches = has_lpa2, 3044 }, 3045 { 3046 .desc = "FPMR", 3047 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3048 .capability = ARM64_HAS_FPMR, 3049 .matches = has_cpuid_feature, 3050 .cpu_enable = cpu_enable_fpmr, 3051 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3052 }, 3053 #ifdef CONFIG_ARM64_VA_BITS_52 3054 { 3055 .capability = ARM64_HAS_VA52, 3056 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3057 .matches = has_cpuid_feature, 3058 #ifdef CONFIG_ARM64_64K_PAGES 3059 .desc = "52-bit Virtual Addressing (LVA)", 3060 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3061 #else 3062 .desc = "52-bit Virtual Addressing (LPA2)", 3063 #ifdef CONFIG_ARM64_4K_PAGES 3064 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3065 #else 3066 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3067 #endif 3068 #endif 3069 }, 3070 #endif 3071 { 3072 .desc = "Memory Partitioning And Monitoring", 3073 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3074 .capability = ARM64_MPAM, 3075 .matches = test_has_mpam, 3076 .cpu_enable = cpu_enable_mpam, 3077 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3078 }, 3079 { 3080 .desc = "Memory Partitioning And Monitoring Virtualisation", 3081 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3082 .capability = ARM64_MPAM_HCR, 3083 .matches = test_has_mpam_hcr, 3084 }, 3085 { 3086 .desc = "NV1", 3087 .capability = ARM64_HAS_HCR_NV1, 3088 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3089 .matches = has_nv1, 3090 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3091 }, 3092 #ifdef CONFIG_ARM64_POE 3093 { 3094 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3095 .capability = ARM64_HAS_S1POE, 3096 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3097 .matches = has_cpuid_feature, 3098 .cpu_enable = cpu_enable_poe, 3099 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3100 }, 3101 #endif 3102 #ifdef CONFIG_ARM64_GCS 3103 { 3104 .desc = "Guarded Control Stack (GCS)", 3105 .capability = ARM64_HAS_GCS, 3106 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3107 .cpu_enable = cpu_enable_gcs, 3108 .matches = has_cpuid_feature, 3109 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3110 }, 3111 #endif 3112 #ifdef CONFIG_HW_PERF_EVENTS 3113 { 3114 .desc = "PMUv3", 3115 .capability = ARM64_HAS_PMUV3, 3116 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3117 .matches = has_pmuv3, 3118 }, 3119 #endif 3120 { 3121 .desc = "SCTLR2", 3122 .capability = ARM64_HAS_SCTLR2, 3123 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3124 .matches = has_cpuid_feature, 3125 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3126 }, 3127 { 3128 .desc = "GICv5 CPU interface", 3129 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3130 .capability = ARM64_HAS_GICV5_CPUIF, 3131 .matches = has_cpuid_feature, 3132 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3133 }, 3134 {}, 3135 }; 3136 3137 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3138 .matches = has_user_cpuid_feature, \ 3139 ARM64_CPUID_FIELDS(reg, field, min_value) 3140 3141 #define __HWCAP_CAP(name, cap_type, cap) \ 3142 .desc = name, \ 3143 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3144 .hwcap_type = cap_type, \ 3145 .hwcap = cap, \ 3146 3147 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3148 { \ 3149 __HWCAP_CAP(#cap, cap_type, cap) \ 3150 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3151 } 3152 3153 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3154 { \ 3155 __HWCAP_CAP(#cap, cap_type, cap) \ 3156 .matches = cpucap_multi_entry_cap_matches, \ 3157 .match_list = list, \ 3158 } 3159 3160 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3161 { \ 3162 __HWCAP_CAP(#cap, cap_type, cap) \ 3163 .matches = match, \ 3164 } 3165 3166 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3167 { \ 3168 __HWCAP_CAP(#cap, cap_type, cap) \ 3169 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3170 .matches = match, \ 3171 } 3172 3173 #ifdef CONFIG_ARM64_PTR_AUTH 3174 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3175 { 3176 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3177 }, 3178 { 3179 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3180 }, 3181 { 3182 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3183 }, 3184 {}, 3185 }; 3186 3187 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3188 { 3189 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3190 }, 3191 { 3192 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3193 }, 3194 { 3195 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3196 }, 3197 {}, 3198 }; 3199 #endif 3200 3201 #ifdef CONFIG_ARM64_SVE 3202 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3203 { 3204 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3205 } 3206 #endif 3207 3208 #ifdef CONFIG_ARM64_SME 3209 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3210 { 3211 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3212 } 3213 #endif 3214 3215 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3216 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3217 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3218 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3219 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3220 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3221 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3222 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3223 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3224 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3225 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3226 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3227 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3228 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3229 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3230 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3231 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3232 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3233 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3234 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3235 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3236 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3237 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3238 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3239 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3240 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3241 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3242 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3243 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3244 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3245 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3246 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3247 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3248 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3249 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3250 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3251 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3252 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3253 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3254 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3255 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3256 #ifdef CONFIG_ARM64_SVE 3257 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3258 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3259 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3260 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3261 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3262 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3263 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3264 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3265 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3266 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3267 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3268 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3269 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3270 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3271 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3272 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3273 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3274 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3275 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3276 #endif 3277 #ifdef CONFIG_ARM64_GCS 3278 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3279 #endif 3280 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3281 #ifdef CONFIG_ARM64_BTI 3282 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3283 #endif 3284 #ifdef CONFIG_ARM64_PTR_AUTH 3285 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3286 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3287 #endif 3288 #ifdef CONFIG_ARM64_MTE 3289 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3290 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3291 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3292 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3293 #endif /* CONFIG_ARM64_MTE */ 3294 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3295 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3296 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3297 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3298 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3299 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3300 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3301 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3302 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3303 #ifdef CONFIG_ARM64_SME 3304 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3305 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3306 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3307 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3308 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3309 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3310 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3311 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3312 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3313 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3314 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3315 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3316 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3317 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3318 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3319 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3320 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3321 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3322 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3323 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3324 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3325 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3326 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3327 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3328 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3329 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3330 #endif /* CONFIG_ARM64_SME */ 3331 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3332 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3333 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3334 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3335 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3336 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3337 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3338 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3339 #ifdef CONFIG_ARM64_POE 3340 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3341 #endif 3342 {}, 3343 }; 3344 3345 #ifdef CONFIG_COMPAT 3346 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3347 { 3348 /* 3349 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3350 * in line with that of arm32 as in vfp_init(). We make sure that the 3351 * check is future proof, by making sure value is non-zero. 3352 */ 3353 u32 mvfr1; 3354 3355 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3356 if (scope == SCOPE_SYSTEM) 3357 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3358 else 3359 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3360 3361 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3362 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3363 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3364 } 3365 #endif 3366 3367 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3368 #ifdef CONFIG_COMPAT 3369 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3370 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3371 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3372 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3373 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3374 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3375 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3376 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3377 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3378 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3379 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3380 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3381 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3382 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3383 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3384 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3385 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3386 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3387 #endif 3388 {}, 3389 }; 3390 3391 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3392 { 3393 switch (cap->hwcap_type) { 3394 case CAP_HWCAP: 3395 cpu_set_feature(cap->hwcap); 3396 break; 3397 #ifdef CONFIG_COMPAT 3398 case CAP_COMPAT_HWCAP: 3399 compat_elf_hwcap |= (u32)cap->hwcap; 3400 break; 3401 case CAP_COMPAT_HWCAP2: 3402 compat_elf_hwcap2 |= (u32)cap->hwcap; 3403 break; 3404 #endif 3405 default: 3406 WARN_ON(1); 3407 break; 3408 } 3409 } 3410 3411 /* Check if we have a particular HWCAP enabled */ 3412 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3413 { 3414 bool rc; 3415 3416 switch (cap->hwcap_type) { 3417 case CAP_HWCAP: 3418 rc = cpu_have_feature(cap->hwcap); 3419 break; 3420 #ifdef CONFIG_COMPAT 3421 case CAP_COMPAT_HWCAP: 3422 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3423 break; 3424 case CAP_COMPAT_HWCAP2: 3425 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3426 break; 3427 #endif 3428 default: 3429 WARN_ON(1); 3430 rc = false; 3431 } 3432 3433 return rc; 3434 } 3435 3436 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3437 { 3438 /* We support emulation of accesses to CPU ID feature registers */ 3439 cpu_set_named_feature(CPUID); 3440 for (; hwcaps->matches; hwcaps++) 3441 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3442 cap_set_elf_hwcap(hwcaps); 3443 } 3444 3445 static void update_cpu_capabilities(u16 scope_mask) 3446 { 3447 int i; 3448 const struct arm64_cpu_capabilities *caps; 3449 3450 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3451 for (i = 0; i < ARM64_NCAPS; i++) { 3452 bool match_all = false; 3453 bool caps_set = false; 3454 bool boot_cpu = false; 3455 3456 caps = cpucap_ptrs[i]; 3457 if (!caps || !(caps->type & scope_mask)) 3458 continue; 3459 3460 match_all = cpucap_match_all_early_cpus(caps); 3461 caps_set = cpus_have_cap(caps->capability); 3462 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3463 3464 /* 3465 * Unless it's a match-all CPUs feature, avoid probing if 3466 * already detected. 3467 */ 3468 if (!match_all && caps_set) 3469 continue; 3470 3471 /* 3472 * A match-all CPUs capability is only set when probing the 3473 * boot CPU. It may be cleared subsequently if not detected on 3474 * secondary ones. 3475 */ 3476 if (match_all && !caps_set && !boot_cpu) 3477 continue; 3478 3479 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3480 if (match_all) 3481 __clear_bit(caps->capability, system_cpucaps); 3482 continue; 3483 } 3484 3485 /* 3486 * Match-all CPUs capabilities are logged later when the 3487 * system capabilities are finalised. 3488 */ 3489 if (!match_all && caps->desc && !caps->cpus) 3490 pr_info("detected: %s\n", caps->desc); 3491 3492 __set_bit(caps->capability, system_cpucaps); 3493 3494 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3495 set_bit(caps->capability, boot_cpucaps); 3496 } 3497 } 3498 3499 /* 3500 * Enable all the available capabilities on this CPU. The capabilities 3501 * with BOOT_CPU scope are handled separately and hence skipped here. 3502 */ 3503 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3504 { 3505 int i; 3506 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3507 3508 for_each_available_cap(i) { 3509 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3510 3511 if (WARN_ON(!cap)) 3512 continue; 3513 3514 if (!(cap->type & non_boot_scope)) 3515 continue; 3516 3517 if (cap->cpu_enable) 3518 cap->cpu_enable(cap); 3519 } 3520 return 0; 3521 } 3522 3523 /* 3524 * Run through the enabled capabilities and enable() it on all active 3525 * CPUs 3526 */ 3527 static void __init enable_cpu_capabilities(u16 scope_mask) 3528 { 3529 int i; 3530 const struct arm64_cpu_capabilities *caps; 3531 bool boot_scope; 3532 3533 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3534 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3535 3536 for (i = 0; i < ARM64_NCAPS; i++) { 3537 caps = cpucap_ptrs[i]; 3538 if (!caps || !(caps->type & scope_mask) || 3539 !cpus_have_cap(caps->capability)) 3540 continue; 3541 3542 if (boot_scope && caps->cpu_enable) 3543 /* 3544 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3545 * before any secondary CPU boots. Thus, each secondary 3546 * will enable the capability as appropriate via 3547 * check_local_cpu_capabilities(). The only exception is 3548 * the boot CPU, for which the capability must be 3549 * enabled here. This approach avoids costly 3550 * stop_machine() calls for this case. 3551 */ 3552 caps->cpu_enable(caps); 3553 } 3554 3555 /* 3556 * For all non-boot scope capabilities, use stop_machine() 3557 * as it schedules the work allowing us to modify PSTATE, 3558 * instead of on_each_cpu() which uses an IPI, giving us a 3559 * PSTATE that disappears when we return. 3560 */ 3561 if (!boot_scope) 3562 stop_machine(cpu_enable_non_boot_scope_capabilities, 3563 NULL, cpu_online_mask); 3564 } 3565 3566 /* 3567 * Run through the list of capabilities to check for conflicts. 3568 * If the system has already detected a capability, take necessary 3569 * action on this CPU. 3570 */ 3571 static void verify_local_cpu_caps(u16 scope_mask) 3572 { 3573 int i; 3574 bool cpu_has_cap, system_has_cap; 3575 const struct arm64_cpu_capabilities *caps; 3576 3577 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3578 3579 for (i = 0; i < ARM64_NCAPS; i++) { 3580 caps = cpucap_ptrs[i]; 3581 if (!caps || !(caps->type & scope_mask)) 3582 continue; 3583 3584 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3585 system_has_cap = cpus_have_cap(caps->capability); 3586 3587 if (system_has_cap) { 3588 /* 3589 * Check if the new CPU misses an advertised feature, 3590 * which is not safe to miss. 3591 */ 3592 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3593 break; 3594 /* 3595 * We have to issue cpu_enable() irrespective of 3596 * whether the CPU has it or not, as it is enabeld 3597 * system wide. It is upto the call back to take 3598 * appropriate action on this CPU. 3599 */ 3600 if (caps->cpu_enable) 3601 caps->cpu_enable(caps); 3602 } else { 3603 /* 3604 * Check if the CPU has this capability if it isn't 3605 * safe to have when the system doesn't. 3606 */ 3607 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3608 break; 3609 } 3610 } 3611 3612 if (i < ARM64_NCAPS) { 3613 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3614 smp_processor_id(), caps->capability, 3615 caps->desc, system_has_cap, cpu_has_cap); 3616 3617 if (cpucap_panic_on_conflict(caps)) 3618 cpu_panic_kernel(); 3619 else 3620 cpu_die_early(); 3621 } 3622 } 3623 3624 /* 3625 * Check for CPU features that are used in early boot 3626 * based on the Boot CPU value. 3627 */ 3628 static void check_early_cpu_features(void) 3629 { 3630 verify_cpu_asid_bits(); 3631 3632 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3633 } 3634 3635 static void 3636 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3637 { 3638 3639 for (; caps->matches; caps++) 3640 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3641 pr_crit("CPU%d: missing HWCAP: %s\n", 3642 smp_processor_id(), caps->desc); 3643 cpu_die_early(); 3644 } 3645 } 3646 3647 static void verify_local_elf_hwcaps(void) 3648 { 3649 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3650 3651 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3652 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3653 } 3654 3655 static void verify_sve_features(void) 3656 { 3657 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3658 3659 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3660 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3661 smp_processor_id()); 3662 cpu_die_early(); 3663 } 3664 3665 cpacr_restore(cpacr); 3666 } 3667 3668 static void verify_sme_features(void) 3669 { 3670 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3671 3672 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3673 pr_crit("CPU%d: SME: vector length support mismatch\n", 3674 smp_processor_id()); 3675 cpu_die_early(); 3676 } 3677 3678 cpacr_restore(cpacr); 3679 } 3680 3681 static void verify_hyp_capabilities(void) 3682 { 3683 u64 safe_mmfr1, mmfr0, mmfr1; 3684 int parange, ipa_max; 3685 unsigned int safe_vmid_bits, vmid_bits; 3686 3687 if (!IS_ENABLED(CONFIG_KVM)) 3688 return; 3689 3690 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3691 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3692 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3693 3694 /* Verify VMID bits */ 3695 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3696 vmid_bits = get_vmid_bits(mmfr1); 3697 if (vmid_bits < safe_vmid_bits) { 3698 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3699 cpu_die_early(); 3700 } 3701 3702 /* Verify IPA range */ 3703 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3704 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3705 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3706 if (ipa_max < get_kvm_ipa_limit()) { 3707 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3708 cpu_die_early(); 3709 } 3710 } 3711 3712 static void verify_mpam_capabilities(void) 3713 { 3714 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3715 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3716 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3717 3718 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3719 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3720 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3721 cpu_die_early(); 3722 } 3723 3724 cpu_idr = read_cpuid(MPAMIDR_EL1); 3725 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3726 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3727 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3728 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3729 cpu_die_early(); 3730 } 3731 3732 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3733 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3734 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3735 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3736 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3737 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3738 cpu_die_early(); 3739 } 3740 } 3741 3742 /* 3743 * Run through the enabled system capabilities and enable() it on this CPU. 3744 * The capabilities were decided based on the available CPUs at the boot time. 3745 * Any new CPU should match the system wide status of the capability. If the 3746 * new CPU doesn't have a capability which the system now has enabled, we 3747 * cannot do anything to fix it up and could cause unexpected failures. So 3748 * we park the CPU. 3749 */ 3750 static void verify_local_cpu_capabilities(void) 3751 { 3752 /* 3753 * The capabilities with SCOPE_BOOT_CPU are checked from 3754 * check_early_cpu_features(), as they need to be verified 3755 * on all secondary CPUs. 3756 */ 3757 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3758 verify_local_elf_hwcaps(); 3759 3760 if (system_supports_sve()) 3761 verify_sve_features(); 3762 3763 if (system_supports_sme()) 3764 verify_sme_features(); 3765 3766 if (is_hyp_mode_available()) 3767 verify_hyp_capabilities(); 3768 3769 if (system_supports_mpam()) 3770 verify_mpam_capabilities(); 3771 } 3772 3773 void check_local_cpu_capabilities(void) 3774 { 3775 /* 3776 * All secondary CPUs should conform to the early CPU features 3777 * in use by the kernel based on boot CPU. 3778 */ 3779 check_early_cpu_features(); 3780 3781 /* 3782 * If we haven't finalised the system capabilities, this CPU gets 3783 * a chance to update the errata work arounds and local features. 3784 * Otherwise, this CPU should verify that it has all the system 3785 * advertised capabilities. 3786 */ 3787 if (!system_capabilities_finalized()) 3788 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3789 else 3790 verify_local_cpu_capabilities(); 3791 } 3792 3793 bool this_cpu_has_cap(unsigned int n) 3794 { 3795 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3796 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3797 3798 if (cap) 3799 return cap->matches(cap, SCOPE_LOCAL_CPU); 3800 } 3801 3802 return false; 3803 } 3804 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3805 3806 /* 3807 * This helper function is used in a narrow window when, 3808 * - The system wide safe registers are set with all the SMP CPUs and, 3809 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3810 */ 3811 static bool __maybe_unused __system_matches_cap(unsigned int n) 3812 { 3813 if (n < ARM64_NCAPS) { 3814 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3815 3816 if (cap) 3817 return cap->matches(cap, SCOPE_SYSTEM); 3818 } 3819 return false; 3820 } 3821 3822 void cpu_set_feature(unsigned int num) 3823 { 3824 set_bit(num, elf_hwcap); 3825 } 3826 3827 bool cpu_have_feature(unsigned int num) 3828 { 3829 return test_bit(num, elf_hwcap); 3830 } 3831 EXPORT_SYMBOL_GPL(cpu_have_feature); 3832 3833 unsigned long cpu_get_elf_hwcap(void) 3834 { 3835 /* 3836 * We currently only populate the first 32 bits of AT_HWCAP. Please 3837 * note that for userspace compatibility we guarantee that bits 62 3838 * and 63 will always be returned as 0. 3839 */ 3840 return elf_hwcap[0]; 3841 } 3842 3843 unsigned long cpu_get_elf_hwcap2(void) 3844 { 3845 return elf_hwcap[1]; 3846 } 3847 3848 unsigned long cpu_get_elf_hwcap3(void) 3849 { 3850 return elf_hwcap[2]; 3851 } 3852 3853 static void __init setup_boot_cpu_capabilities(void) 3854 { 3855 kvm_arm_target_impl_cpu_init(); 3856 /* 3857 * The boot CPU's feature register values have been recorded. Detect 3858 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3859 * patch alternatives for the available boot cpucaps. 3860 */ 3861 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3862 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3863 apply_boot_alternatives(); 3864 } 3865 3866 void __init setup_boot_cpu_features(void) 3867 { 3868 /* 3869 * Initialize the indirect array of CPU capabilities pointers before we 3870 * handle the boot CPU. 3871 */ 3872 init_cpucap_indirect_list(); 3873 3874 /* 3875 * Detect broken pseudo-NMI. Must be called _before_ the call to 3876 * setup_boot_cpu_capabilities() since it interacts with 3877 * can_use_gic_priorities(). 3878 */ 3879 detect_system_supports_pseudo_nmi(); 3880 3881 setup_boot_cpu_capabilities(); 3882 } 3883 3884 static void __init setup_system_capabilities(void) 3885 { 3886 /* 3887 * The system-wide safe feature register values have been finalized. 3888 * Detect, enable, and patch alternatives for the available system 3889 * cpucaps. 3890 */ 3891 update_cpu_capabilities(SCOPE_SYSTEM); 3892 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3893 apply_alternatives_all(); 3894 3895 for (int i = 0; i < ARM64_NCAPS; i++) { 3896 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3897 3898 if (!caps || !caps->desc) 3899 continue; 3900 3901 /* 3902 * Log any cpucaps with a cpumask as these aren't logged by 3903 * update_cpu_capabilities(). 3904 */ 3905 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3906 pr_info("detected: %s on CPU%*pbl\n", 3907 caps->desc, cpumask_pr_args(caps->cpus)); 3908 3909 /* Log match-all CPUs capabilities */ 3910 if (cpucap_match_all_early_cpus(caps) && 3911 cpus_have_cap(caps->capability)) 3912 pr_info("detected: %s\n", caps->desc); 3913 } 3914 3915 /* 3916 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3917 */ 3918 if (system_uses_ttbr0_pan()) 3919 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3920 } 3921 3922 void __init setup_system_features(void) 3923 { 3924 setup_system_capabilities(); 3925 3926 kpti_install_ng_mappings(); 3927 3928 sve_setup(); 3929 sme_setup(); 3930 3931 /* 3932 * Check for sane CTR_EL0.CWG value. 3933 */ 3934 if (!cache_type_cwg()) 3935 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3936 ARCH_DMA_MINALIGN); 3937 } 3938 3939 void __init setup_user_features(void) 3940 { 3941 user_feature_fixup(); 3942 3943 setup_elf_hwcaps(arm64_elf_hwcaps); 3944 3945 if (system_supports_32bit_el0()) { 3946 setup_elf_hwcaps(compat_elf_hwcaps); 3947 elf_hwcap_fixup(); 3948 } 3949 3950 minsigstksz_setup(); 3951 } 3952 3953 static int enable_mismatched_32bit_el0(unsigned int cpu) 3954 { 3955 /* 3956 * The first 32-bit-capable CPU we detected and so can no longer 3957 * be offlined by userspace. -1 indicates we haven't yet onlined 3958 * a 32-bit-capable CPU. 3959 */ 3960 static int lucky_winner = -1; 3961 3962 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3963 bool cpu_32bit = false; 3964 3965 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3966 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3967 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3968 else 3969 cpu_32bit = true; 3970 } 3971 3972 if (cpu_32bit) { 3973 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3974 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3975 } 3976 3977 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3978 return 0; 3979 3980 if (lucky_winner >= 0) 3981 return 0; 3982 3983 /* 3984 * We've detected a mismatch. We need to keep one of our CPUs with 3985 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3986 * every CPU in the system for a 32-bit task. 3987 */ 3988 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3989 cpu_active_mask); 3990 get_cpu_device(lucky_winner)->offline_disabled = true; 3991 setup_elf_hwcaps(compat_elf_hwcaps); 3992 elf_hwcap_fixup(); 3993 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3994 cpu, lucky_winner); 3995 return 0; 3996 } 3997 3998 static int __init init_32bit_el0_mask(void) 3999 { 4000 if (!allow_mismatched_32bit_el0) 4001 return 0; 4002 4003 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4004 return -ENOMEM; 4005 4006 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4007 "arm64/mismatched_32bit_el0:online", 4008 enable_mismatched_32bit_el0, NULL); 4009 } 4010 subsys_initcall_sync(init_32bit_el0_mask); 4011 4012 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4013 { 4014 cpu_enable_swapper_cnp(); 4015 } 4016 4017 /* 4018 * We emulate only the following system register space. 4019 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4020 * See Table C5-6 System instruction encodings for System register accesses, 4021 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4022 */ 4023 static inline bool __attribute_const__ is_emulated(u32 id) 4024 { 4025 return (sys_reg_Op0(id) == 0x3 && 4026 sys_reg_CRn(id) == 0x0 && 4027 sys_reg_Op1(id) == 0x0 && 4028 (sys_reg_CRm(id) == 0 || 4029 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4030 } 4031 4032 /* 4033 * With CRm == 0, reg should be one of : 4034 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4035 */ 4036 static inline int emulate_id_reg(u32 id, u64 *valp) 4037 { 4038 switch (id) { 4039 case SYS_MIDR_EL1: 4040 *valp = read_cpuid_id(); 4041 break; 4042 case SYS_MPIDR_EL1: 4043 *valp = SYS_MPIDR_SAFE_VAL; 4044 break; 4045 case SYS_REVIDR_EL1: 4046 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4047 *valp = 0; 4048 break; 4049 default: 4050 return -EINVAL; 4051 } 4052 4053 return 0; 4054 } 4055 4056 static int emulate_sys_reg(u32 id, u64 *valp) 4057 { 4058 struct arm64_ftr_reg *regp; 4059 4060 if (!is_emulated(id)) 4061 return -EINVAL; 4062 4063 if (sys_reg_CRm(id) == 0) 4064 return emulate_id_reg(id, valp); 4065 4066 regp = get_arm64_ftr_reg_nowarn(id); 4067 if (regp) 4068 *valp = arm64_ftr_reg_user_value(regp); 4069 else 4070 /* 4071 * The untracked registers are either IMPLEMENTATION DEFINED 4072 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4073 */ 4074 *valp = 0; 4075 return 0; 4076 } 4077 4078 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4079 { 4080 int rc; 4081 u64 val; 4082 4083 rc = emulate_sys_reg(sys_reg, &val); 4084 if (!rc) { 4085 pt_regs_write_reg(regs, rt, val); 4086 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4087 } 4088 return rc; 4089 } 4090 4091 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4092 { 4093 u32 sys_reg, rt; 4094 4095 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4096 return false; 4097 4098 /* 4099 * sys_reg values are defined as used in mrs/msr instruction. 4100 * shift the imm value to get the encoding. 4101 */ 4102 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4103 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4104 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4105 } 4106 4107 enum mitigation_state arm64_get_meltdown_state(void) 4108 { 4109 if (__meltdown_safe) 4110 return SPECTRE_UNAFFECTED; 4111 4112 if (arm64_kernel_unmapped_at_el0()) 4113 return SPECTRE_MITIGATED; 4114 4115 return SPECTRE_VULNERABLE; 4116 } 4117 4118 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4119 char *buf) 4120 { 4121 switch (arm64_get_meltdown_state()) { 4122 case SPECTRE_UNAFFECTED: 4123 return sprintf(buf, "Not affected\n"); 4124 4125 case SPECTRE_MITIGATED: 4126 return sprintf(buf, "Mitigation: PTI\n"); 4127 4128 default: 4129 return sprintf(buf, "Vulnerable\n"); 4130 } 4131 } 4132