1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 121 /* 122 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 123 * ends up in the .bss section where it is initialized in early_map_kernel() 124 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 125 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 126 * may end up generating an incorrect idmap page table attributes. 127 */ 128 bool arm64_use_ng_mappings __read_mostly = false; 129 EXPORT_SYMBOL(arm64_use_ng_mappings); 130 131 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 132 133 /* 134 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 135 * support it? 136 */ 137 static bool __read_mostly allow_mismatched_32bit_el0; 138 139 /* 140 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 141 * seen at least one CPU capable of 32-bit EL0. 142 */ 143 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 144 145 /* 146 * Mask of CPUs supporting 32-bit EL0. 147 * Only valid if arm64_mismatched_32bit_el0 is enabled. 148 */ 149 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 150 151 void dump_cpu_features(void) 152 { 153 /* file-wide pr_fmt adds "CPU features: " prefix */ 154 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 155 } 156 157 #define __ARM64_MAX_POSITIVE(reg, field) \ 158 ((reg##_##field##_SIGNED ? \ 159 BIT(reg##_##field##_WIDTH - 1) : \ 160 BIT(reg##_##field##_WIDTH)) - 1) 161 162 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 163 164 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 165 .sys_reg = SYS_##reg, \ 166 .field_pos = reg##_##field##_SHIFT, \ 167 .field_width = reg##_##field##_WIDTH, \ 168 .sign = reg##_##field##_SIGNED, \ 169 .min_field_value = min_value, \ 170 .max_field_value = max_value, 171 172 /* 173 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 174 * an implicit maximum that depends on the sign-ess of the field. 175 * 176 * An unsigned field will be capped at all ones, while a signed field 177 * will be limited to the positive half only. 178 */ 179 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 180 __ARM64_CPUID_FIELDS(reg, field, \ 181 SYS_FIELD_VALUE(reg, field, min_value), \ 182 __ARM64_MAX_POSITIVE(reg, field)) 183 184 /* 185 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 186 * implicit minimal value to max_value. This should be used when 187 * matching a non-implemented property. 188 */ 189 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 190 __ARM64_CPUID_FIELDS(reg, field, \ 191 __ARM64_MIN_NEGATIVE(reg, field), \ 192 SYS_FIELD_VALUE(reg, field, max_value)) 193 194 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 { \ 196 .sign = SIGNED, \ 197 .visible = VISIBLE, \ 198 .strict = STRICT, \ 199 .type = TYPE, \ 200 .shift = SHIFT, \ 201 .width = WIDTH, \ 202 .safe_val = SAFE_VAL, \ 203 } 204 205 /* Define a feature with unsigned values */ 206 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 /* Define a feature with a signed value */ 210 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 211 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 212 213 #define ARM64_FTR_END \ 214 { \ 215 .width = 0, \ 216 } 217 218 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 219 220 static bool __system_matches_cap(unsigned int n); 221 222 /* 223 * NOTE: Any changes to the visibility of features should be kept in 224 * sync with the documentation of the CPU feature register ABI. 225 */ 226 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_ATS1A_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 277 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 286 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 290 ARM64_FTR_END, 291 }; 292 293 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 301 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 304 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 305 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 310 ARM64_FTR_END, 311 }; 312 313 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 316 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 317 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 325 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 326 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 327 ARM64_FTR_END, 328 }; 329 330 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 331 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 334 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 358 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 360 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 362 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 363 ARM64_FTR_END, 364 }; 365 366 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 408 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 410 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 412 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 414 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM2_SHIFT, 1, 0), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 427 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 428 ARM64_FTR_END, 429 }; 430 431 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 435 /* 436 * Page size not being supported at Stage-2 is not fatal. You 437 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 438 * your favourite nesting hypervisor. 439 * 440 * There is a small corner case where the hypervisor explicitly 441 * advertises a given granule size at Stage-2 (value 2) on some 442 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 443 * vCPUs. Although this is not forbidden by the architecture, it 444 * indicates that the hypervisor is being silly (or buggy). 445 * 446 * We make no effort to cope with this and pretend that if these 447 * fields are inconsistent across vCPUs, then it isn't worth 448 * trying to bring KVM up. 449 */ 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 453 /* 454 * We already refuse to boot CPUs that don't support our configured 455 * page size, so we can only detect mismatches for a page size other 456 * than the one we're currently using. Unfortunately, SoCs like this 457 * exist in the wild so, even though we don't like it, we'll have to go 458 * along with it and treat them as non-strict. 459 */ 460 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 461 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 463 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 465 /* Linux shouldn't care about secure memory */ 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 469 /* 470 * Differing PARange is fine as long as all peripherals and memory are mapped 471 * within the minimum PARange of all CPUs 472 */ 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 474 ARM64_FTR_END, 475 }; 476 477 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 515 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 516 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 520 ARM64_FTR_END, 521 }; 522 523 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 524 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 526 ARM64_FTR_END, 527 }; 528 529 static const struct arm64_ftr_bits ftr_ctr[] = { 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 536 /* 537 * Linux can handle differing I-cache policies. Userspace JITs will 538 * make use of *minLine. 539 * If we have differing I-cache policies, report it as the weakest - VIPT. 540 */ 541 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 542 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 543 ARM64_FTR_END, 544 }; 545 546 static struct arm64_ftr_override __ro_after_init no_override = { }; 547 548 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 549 .name = "SYS_CTR_EL0", 550 .ftr_bits = ftr_ctr, 551 .override = &no_override, 552 }; 553 554 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 555 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 560 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 563 ARM64_FTR_END, 564 }; 565 566 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 567 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 572 /* 573 * We can instantiate multiple PMU instances with different levels 574 * of support. 575 */ 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_mvfr0[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_mvfr1[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 602 ARM64_FTR_END, 603 }; 604 605 static const struct arm64_ftr_bits ftr_mvfr2[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_dczid[] = { 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 613 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_gmid[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 619 ARM64_FTR_END, 620 }; 621 622 static const struct arm64_ftr_bits ftr_id_isar0[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 630 ARM64_FTR_END, 631 }; 632 633 static const struct arm64_ftr_bits ftr_id_isar5[] = { 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 640 ARM64_FTR_END, 641 }; 642 643 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 651 652 /* 653 * SpecSEI = 1 indicates that the PE might generate an SError on an 654 * external abort on speculative read. It is safe to assume that an 655 * SError might be generated than it will not be. Hence it has been 656 * classified as FTR_HIGHER_SAFE. 657 */ 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 659 ARM64_FTR_END, 660 }; 661 662 static const struct arm64_ftr_bits ftr_id_isar4[] = { 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 676 ARM64_FTR_END, 677 }; 678 679 static const struct arm64_ftr_bits ftr_id_isar6[] = { 680 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 687 ARM64_FTR_END, 688 }; 689 690 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 697 ARM64_FTR_END, 698 }; 699 700 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 709 ARM64_FTR_END, 710 }; 711 712 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 713 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 715 ARM64_FTR_END, 716 }; 717 718 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 719 /* [31:28] TraceFilt */ 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 727 ARM64_FTR_END, 728 }; 729 730 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 731 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 732 ARM64_FTR_END, 733 }; 734 735 static const struct arm64_ftr_bits ftr_mpamidr[] = { 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 740 ARM64_FTR_END, 741 }; 742 743 /* 744 * Common ftr bits for a 32bit register with all hidden, strict 745 * attributes, with 4bit feature fields and a default safe value of 746 * 0. Covers the following 32bit registers: 747 * id_isar[1-3], id_mmfr[1-3] 748 */ 749 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 750 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 756 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 757 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 758 ARM64_FTR_END, 759 }; 760 761 /* Table for a single 32bit feature value */ 762 static const struct arm64_ftr_bits ftr_single32[] = { 763 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 764 ARM64_FTR_END, 765 }; 766 767 static const struct arm64_ftr_bits ftr_raz[] = { 768 ARM64_FTR_END, 769 }; 770 771 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 772 .sys_id = id, \ 773 .reg = &(struct arm64_ftr_reg){ \ 774 .name = id_str, \ 775 .override = (ovr), \ 776 .ftr_bits = &((table)[0]), \ 777 }} 778 779 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 780 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 781 782 #define ARM64_FTR_REG(id, table) \ 783 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 784 785 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 786 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 787 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 788 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 789 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 790 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 791 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 792 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 793 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 794 795 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 796 797 static const struct __ftr_reg_entry { 798 u32 sys_id; 799 struct arm64_ftr_reg *reg; 800 } arm64_ftr_regs[] = { 801 802 /* Op1 = 0, CRn = 0, CRm = 1 */ 803 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 804 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 805 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 806 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 807 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 808 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 809 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 810 811 /* Op1 = 0, CRn = 0, CRm = 2 */ 812 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 813 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 814 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 815 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 816 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 817 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 818 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 819 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 820 821 /* Op1 = 0, CRn = 0, CRm = 3 */ 822 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 823 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 824 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 825 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 826 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 827 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 828 829 /* Op1 = 0, CRn = 0, CRm = 4 */ 830 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 831 &id_aa64pfr0_override), 832 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 833 &id_aa64pfr1_override), 834 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 835 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 836 &id_aa64zfr0_override), 837 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 838 &id_aa64smfr0_override), 839 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 840 841 /* Op1 = 0, CRn = 0, CRm = 5 */ 842 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 843 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 844 845 /* Op1 = 0, CRn = 0, CRm = 6 */ 846 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 847 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 848 &id_aa64isar1_override), 849 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 850 &id_aa64isar2_override), 851 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 852 853 /* Op1 = 0, CRn = 0, CRm = 7 */ 854 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 855 &id_aa64mmfr0_override), 856 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 857 &id_aa64mmfr1_override), 858 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 859 &id_aa64mmfr2_override), 860 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 861 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 862 863 /* Op1 = 0, CRn = 10, CRm = 4 */ 864 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 865 866 /* Op1 = 1, CRn = 0, CRm = 0 */ 867 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 868 869 /* Op1 = 3, CRn = 0, CRm = 0 */ 870 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 871 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 872 873 /* Op1 = 3, CRn = 14, CRm = 0 */ 874 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 875 }; 876 877 static int search_cmp_ftr_reg(const void *id, const void *regp) 878 { 879 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 880 } 881 882 /* 883 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 884 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 885 * ascending order of sys_id, we use binary search to find a matching 886 * entry. 887 * 888 * returns - Upon success, matching ftr_reg entry for id. 889 * - NULL on failure. It is upto the caller to decide 890 * the impact of a failure. 891 */ 892 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 893 { 894 const struct __ftr_reg_entry *ret; 895 896 ret = bsearch((const void *)(unsigned long)sys_id, 897 arm64_ftr_regs, 898 ARRAY_SIZE(arm64_ftr_regs), 899 sizeof(arm64_ftr_regs[0]), 900 search_cmp_ftr_reg); 901 if (ret) 902 return ret->reg; 903 return NULL; 904 } 905 906 /* 907 * get_arm64_ftr_reg - Looks up a feature register entry using 908 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 909 * 910 * returns - Upon success, matching ftr_reg entry for id. 911 * - NULL on failure but with an WARN_ON(). 912 */ 913 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 914 { 915 struct arm64_ftr_reg *reg; 916 917 reg = get_arm64_ftr_reg_nowarn(sys_id); 918 919 /* 920 * Requesting a non-existent register search is an error. Warn 921 * and let the caller handle it. 922 */ 923 WARN_ON(!reg); 924 return reg; 925 } 926 927 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 928 s64 ftr_val) 929 { 930 u64 mask = arm64_ftr_mask(ftrp); 931 932 reg &= ~mask; 933 reg |= (ftr_val << ftrp->shift) & mask; 934 return reg; 935 } 936 937 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 938 s64 cur) 939 { 940 s64 ret = 0; 941 942 switch (ftrp->type) { 943 case FTR_EXACT: 944 ret = ftrp->safe_val; 945 break; 946 case FTR_LOWER_SAFE: 947 ret = min(new, cur); 948 break; 949 case FTR_HIGHER_OR_ZERO_SAFE: 950 if (!cur || !new) 951 break; 952 fallthrough; 953 case FTR_HIGHER_SAFE: 954 ret = max(new, cur); 955 break; 956 default: 957 BUG(); 958 } 959 960 return ret; 961 } 962 963 static void __init sort_ftr_regs(void) 964 { 965 unsigned int i; 966 967 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 968 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 969 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 970 unsigned int j = 0; 971 972 /* 973 * Features here must be sorted in descending order with respect 974 * to their shift values and should not overlap with each other. 975 */ 976 for (; ftr_bits->width != 0; ftr_bits++, j++) { 977 unsigned int width = ftr_reg->ftr_bits[j].width; 978 unsigned int shift = ftr_reg->ftr_bits[j].shift; 979 unsigned int prev_shift; 980 981 WARN((shift + width) > 64, 982 "%s has invalid feature at shift %d\n", 983 ftr_reg->name, shift); 984 985 /* 986 * Skip the first feature. There is nothing to 987 * compare against for now. 988 */ 989 if (j == 0) 990 continue; 991 992 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 993 WARN((shift + width) > prev_shift, 994 "%s has feature overlap at shift %d\n", 995 ftr_reg->name, shift); 996 } 997 998 /* 999 * Skip the first register. There is nothing to 1000 * compare against for now. 1001 */ 1002 if (i == 0) 1003 continue; 1004 /* 1005 * Registers here must be sorted in ascending order with respect 1006 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1007 * to work correctly. 1008 */ 1009 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1010 } 1011 } 1012 1013 /* 1014 * Initialise the CPU feature register from Boot CPU values. 1015 * Also initialises the strict_mask for the register. 1016 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1017 * RES0 for the system-wide value, and must strictly match. 1018 */ 1019 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1020 { 1021 u64 val = 0; 1022 u64 strict_mask = ~0x0ULL; 1023 u64 user_mask = 0; 1024 u64 valid_mask = 0; 1025 1026 const struct arm64_ftr_bits *ftrp; 1027 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1028 1029 if (!reg) 1030 return; 1031 1032 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1033 u64 ftr_mask = arm64_ftr_mask(ftrp); 1034 s64 ftr_new = arm64_ftr_value(ftrp, new); 1035 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1036 1037 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1038 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1039 char *str = NULL; 1040 1041 if (ftr_ovr != tmp) { 1042 /* Unsafe, remove the override */ 1043 reg->override->mask &= ~ftr_mask; 1044 reg->override->val &= ~ftr_mask; 1045 tmp = ftr_ovr; 1046 str = "ignoring override"; 1047 } else if (ftr_new != tmp) { 1048 /* Override was valid */ 1049 ftr_new = tmp; 1050 str = "forced"; 1051 } else { 1052 /* Override was the safe value */ 1053 str = "already set"; 1054 } 1055 1056 pr_warn("%s[%d:%d]: %s to %llx\n", 1057 reg->name, 1058 ftrp->shift + ftrp->width - 1, 1059 ftrp->shift, str, 1060 tmp & (BIT(ftrp->width) - 1)); 1061 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1062 reg->override->val &= ~ftr_mask; 1063 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1064 reg->name, 1065 ftrp->shift + ftrp->width - 1, 1066 ftrp->shift); 1067 } 1068 1069 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1070 1071 valid_mask |= ftr_mask; 1072 if (!ftrp->strict) 1073 strict_mask &= ~ftr_mask; 1074 if (ftrp->visible) 1075 user_mask |= ftr_mask; 1076 else 1077 reg->user_val = arm64_ftr_set_value(ftrp, 1078 reg->user_val, 1079 ftrp->safe_val); 1080 } 1081 1082 val &= valid_mask; 1083 1084 reg->sys_val = val; 1085 reg->strict_mask = strict_mask; 1086 reg->user_mask = user_mask; 1087 } 1088 1089 extern const struct arm64_cpu_capabilities arm64_errata[]; 1090 static const struct arm64_cpu_capabilities arm64_features[]; 1091 1092 static void __init 1093 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1094 { 1095 for (; caps->matches; caps++) { 1096 if (WARN(caps->capability >= ARM64_NCAPS, 1097 "Invalid capability %d\n", caps->capability)) 1098 continue; 1099 if (WARN(cpucap_ptrs[caps->capability], 1100 "Duplicate entry for capability %d\n", 1101 caps->capability)) 1102 continue; 1103 cpucap_ptrs[caps->capability] = caps; 1104 } 1105 } 1106 1107 static void __init init_cpucap_indirect_list(void) 1108 { 1109 init_cpucap_indirect_list_from_array(arm64_features); 1110 init_cpucap_indirect_list_from_array(arm64_errata); 1111 } 1112 1113 static void __init setup_boot_cpu_capabilities(void); 1114 1115 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1116 { 1117 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1118 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1119 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1120 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1121 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1122 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1123 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1124 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1125 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1126 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1127 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1128 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1129 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1130 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1131 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1132 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1133 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1134 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1135 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1136 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1137 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1138 } 1139 1140 #ifdef CONFIG_ARM64_PSEUDO_NMI 1141 static bool enable_pseudo_nmi; 1142 1143 static int __init early_enable_pseudo_nmi(char *p) 1144 { 1145 return kstrtobool(p, &enable_pseudo_nmi); 1146 } 1147 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1148 1149 static __init void detect_system_supports_pseudo_nmi(void) 1150 { 1151 struct device_node *np; 1152 1153 if (!enable_pseudo_nmi) 1154 return; 1155 1156 /* 1157 * Detect broken MediaTek firmware that doesn't properly save and 1158 * restore GIC priorities. 1159 */ 1160 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1161 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1162 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1163 enable_pseudo_nmi = false; 1164 } 1165 of_node_put(np); 1166 } 1167 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1168 static inline void detect_system_supports_pseudo_nmi(void) { } 1169 #endif 1170 1171 static bool detect_ftr_has_mpam(void) 1172 { 1173 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1174 u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1175 1176 return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); 1177 } 1178 1179 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1180 { 1181 /* Before we start using the tables, make sure it is sorted */ 1182 sort_ftr_regs(); 1183 1184 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1185 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1186 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1187 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1188 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1189 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1190 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1191 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1192 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1193 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1194 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1195 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1196 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1197 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1198 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1199 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1200 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1201 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1202 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1203 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1204 1205 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1206 init_32bit_cpu_features(&info->aarch32); 1207 1208 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1209 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1210 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1211 1212 vec_init_vq_map(ARM64_VEC_SVE); 1213 1214 cpacr_restore(cpacr); 1215 } 1216 1217 if (IS_ENABLED(CONFIG_ARM64_SME) && 1218 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1219 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1220 1221 vec_init_vq_map(ARM64_VEC_SME); 1222 1223 cpacr_restore(cpacr); 1224 } 1225 1226 if (detect_ftr_has_mpam()) { 1227 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1228 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1229 } 1230 1231 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1232 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1233 } 1234 1235 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1236 { 1237 const struct arm64_ftr_bits *ftrp; 1238 1239 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1240 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1241 s64 ftr_new = arm64_ftr_value(ftrp, new); 1242 1243 if (ftr_cur == ftr_new) 1244 continue; 1245 /* Find a safe value */ 1246 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1247 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1248 } 1249 1250 } 1251 1252 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1253 { 1254 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1255 1256 if (!regp) 1257 return 0; 1258 1259 update_cpu_ftr_reg(regp, val); 1260 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1261 return 0; 1262 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1263 regp->name, boot, cpu, val); 1264 return 1; 1265 } 1266 1267 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1268 { 1269 const struct arm64_ftr_bits *ftrp; 1270 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1271 1272 if (!regp) 1273 return; 1274 1275 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1276 if (ftrp->shift == field) { 1277 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1278 break; 1279 } 1280 } 1281 1282 /* Bogus field? */ 1283 WARN_ON(!ftrp->width); 1284 } 1285 1286 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1287 struct cpuinfo_arm64 *boot) 1288 { 1289 static bool boot_cpu_32bit_regs_overridden = false; 1290 1291 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1292 return; 1293 1294 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1295 return; 1296 1297 boot->aarch32 = info->aarch32; 1298 init_32bit_cpu_features(&boot->aarch32); 1299 boot_cpu_32bit_regs_overridden = true; 1300 } 1301 1302 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1303 struct cpuinfo_32bit *boot) 1304 { 1305 int taint = 0; 1306 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1307 1308 /* 1309 * If we don't have AArch32 at EL1, then relax the strictness of 1310 * EL1-dependent register fields to avoid spurious sanity check fails. 1311 */ 1312 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1313 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1314 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1315 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1316 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1317 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1318 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1319 } 1320 1321 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1322 info->reg_id_dfr0, boot->reg_id_dfr0); 1323 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1324 info->reg_id_dfr1, boot->reg_id_dfr1); 1325 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1326 info->reg_id_isar0, boot->reg_id_isar0); 1327 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1328 info->reg_id_isar1, boot->reg_id_isar1); 1329 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1330 info->reg_id_isar2, boot->reg_id_isar2); 1331 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1332 info->reg_id_isar3, boot->reg_id_isar3); 1333 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1334 info->reg_id_isar4, boot->reg_id_isar4); 1335 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1336 info->reg_id_isar5, boot->reg_id_isar5); 1337 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1338 info->reg_id_isar6, boot->reg_id_isar6); 1339 1340 /* 1341 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1342 * ACTLR formats could differ across CPUs and therefore would have to 1343 * be trapped for virtualization anyway. 1344 */ 1345 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1346 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1347 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1348 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1349 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1350 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1351 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1352 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1353 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1354 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1355 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1356 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1357 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1358 info->reg_id_pfr0, boot->reg_id_pfr0); 1359 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1360 info->reg_id_pfr1, boot->reg_id_pfr1); 1361 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1362 info->reg_id_pfr2, boot->reg_id_pfr2); 1363 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1364 info->reg_mvfr0, boot->reg_mvfr0); 1365 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1366 info->reg_mvfr1, boot->reg_mvfr1); 1367 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1368 info->reg_mvfr2, boot->reg_mvfr2); 1369 1370 return taint; 1371 } 1372 1373 /* 1374 * Update system wide CPU feature registers with the values from a 1375 * non-boot CPU. Also performs SANITY checks to make sure that there 1376 * aren't any insane variations from that of the boot CPU. 1377 */ 1378 void update_cpu_features(int cpu, 1379 struct cpuinfo_arm64 *info, 1380 struct cpuinfo_arm64 *boot) 1381 { 1382 int taint = 0; 1383 1384 /* 1385 * The kernel can handle differing I-cache policies, but otherwise 1386 * caches should look identical. Userspace JITs will make use of 1387 * *minLine. 1388 */ 1389 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1390 info->reg_ctr, boot->reg_ctr); 1391 1392 /* 1393 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1394 * could result in too much or too little memory being zeroed if a 1395 * process is preempted and migrated between CPUs. 1396 */ 1397 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1398 info->reg_dczid, boot->reg_dczid); 1399 1400 /* If different, timekeeping will be broken (especially with KVM) */ 1401 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1402 info->reg_cntfrq, boot->reg_cntfrq); 1403 1404 /* 1405 * The kernel uses self-hosted debug features and expects CPUs to 1406 * support identical debug features. We presently need CTX_CMPs, WRPs, 1407 * and BRPs to be identical. 1408 * ID_AA64DFR1 is currently RES0. 1409 */ 1410 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1411 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1412 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1413 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1414 /* 1415 * Even in big.LITTLE, processors should be identical instruction-set 1416 * wise. 1417 */ 1418 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1419 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1420 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1421 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1423 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1424 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1425 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1426 1427 /* 1428 * Differing PARange support is fine as long as all peripherals and 1429 * memory are mapped within the minimum PARange of all CPUs. 1430 * Linux should not care about secure memory. 1431 */ 1432 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1433 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1434 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1435 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1436 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1437 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1438 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1439 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1440 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1441 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1442 1443 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1444 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1445 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1446 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1447 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1448 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1449 1450 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1451 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1452 1453 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1454 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1455 1456 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1457 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1458 1459 /* Probe vector lengths */ 1460 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1461 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1462 if (!system_capabilities_finalized()) { 1463 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1464 1465 vec_update_vq_map(ARM64_VEC_SVE); 1466 1467 cpacr_restore(cpacr); 1468 } 1469 } 1470 1471 if (IS_ENABLED(CONFIG_ARM64_SME) && 1472 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1473 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1474 1475 /* Probe vector lengths */ 1476 if (!system_capabilities_finalized()) 1477 vec_update_vq_map(ARM64_VEC_SME); 1478 1479 cpacr_restore(cpacr); 1480 } 1481 1482 if (detect_ftr_has_mpam()) { 1483 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1484 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1485 info->reg_mpamidr, boot->reg_mpamidr); 1486 } 1487 1488 /* 1489 * The kernel uses the LDGM/STGM instructions and the number of tags 1490 * they read/write depends on the GMID_EL1.BS field. Check that the 1491 * value is the same on all CPUs. 1492 */ 1493 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1494 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1495 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1496 info->reg_gmid, boot->reg_gmid); 1497 } 1498 1499 /* 1500 * If we don't have AArch32 at all then skip the checks entirely 1501 * as the register values may be UNKNOWN and we're not going to be 1502 * using them for anything. 1503 * 1504 * This relies on a sanitised view of the AArch64 ID registers 1505 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1506 */ 1507 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1508 lazy_init_32bit_cpu_features(info, boot); 1509 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1510 &boot->aarch32); 1511 } 1512 1513 /* 1514 * Mismatched CPU features are a recipe for disaster. Don't even 1515 * pretend to support them. 1516 */ 1517 if (taint) { 1518 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1519 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1520 } 1521 } 1522 1523 u64 read_sanitised_ftr_reg(u32 id) 1524 { 1525 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1526 1527 if (!regp) 1528 return 0; 1529 return regp->sys_val; 1530 } 1531 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1532 1533 #define read_sysreg_case(r) \ 1534 case r: val = read_sysreg_s(r); break; 1535 1536 /* 1537 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1538 * Read the system register on the current CPU 1539 */ 1540 u64 __read_sysreg_by_encoding(u32 sys_id) 1541 { 1542 struct arm64_ftr_reg *regp; 1543 u64 val; 1544 1545 switch (sys_id) { 1546 read_sysreg_case(SYS_ID_PFR0_EL1); 1547 read_sysreg_case(SYS_ID_PFR1_EL1); 1548 read_sysreg_case(SYS_ID_PFR2_EL1); 1549 read_sysreg_case(SYS_ID_DFR0_EL1); 1550 read_sysreg_case(SYS_ID_DFR1_EL1); 1551 read_sysreg_case(SYS_ID_MMFR0_EL1); 1552 read_sysreg_case(SYS_ID_MMFR1_EL1); 1553 read_sysreg_case(SYS_ID_MMFR2_EL1); 1554 read_sysreg_case(SYS_ID_MMFR3_EL1); 1555 read_sysreg_case(SYS_ID_MMFR4_EL1); 1556 read_sysreg_case(SYS_ID_MMFR5_EL1); 1557 read_sysreg_case(SYS_ID_ISAR0_EL1); 1558 read_sysreg_case(SYS_ID_ISAR1_EL1); 1559 read_sysreg_case(SYS_ID_ISAR2_EL1); 1560 read_sysreg_case(SYS_ID_ISAR3_EL1); 1561 read_sysreg_case(SYS_ID_ISAR4_EL1); 1562 read_sysreg_case(SYS_ID_ISAR5_EL1); 1563 read_sysreg_case(SYS_ID_ISAR6_EL1); 1564 read_sysreg_case(SYS_MVFR0_EL1); 1565 read_sysreg_case(SYS_MVFR1_EL1); 1566 read_sysreg_case(SYS_MVFR2_EL1); 1567 1568 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1569 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1570 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1571 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1572 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1573 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1574 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1575 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1576 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1577 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1578 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1579 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1580 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1581 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1582 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1583 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1584 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1585 1586 read_sysreg_case(SYS_CNTFRQ_EL0); 1587 read_sysreg_case(SYS_CTR_EL0); 1588 read_sysreg_case(SYS_DCZID_EL0); 1589 1590 default: 1591 BUG(); 1592 return 0; 1593 } 1594 1595 regp = get_arm64_ftr_reg(sys_id); 1596 if (regp) { 1597 val &= ~regp->override->mask; 1598 val |= (regp->override->val & regp->override->mask); 1599 } 1600 1601 return val; 1602 } 1603 1604 #include <linux/irqchip/arm-gic-v3.h> 1605 1606 static bool 1607 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1608 { 1609 return true; 1610 } 1611 1612 static bool 1613 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1614 { 1615 int val, min, max; 1616 u64 tmp; 1617 1618 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1619 entry->field_width, 1620 entry->sign); 1621 1622 tmp = entry->min_field_value; 1623 tmp <<= entry->field_pos; 1624 1625 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1626 entry->field_width, 1627 entry->sign); 1628 1629 tmp = entry->max_field_value; 1630 tmp <<= entry->field_pos; 1631 1632 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1633 entry->field_width, 1634 entry->sign); 1635 1636 return val >= min && val <= max; 1637 } 1638 1639 static u64 1640 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1641 { 1642 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1643 if (scope == SCOPE_SYSTEM) 1644 return read_sanitised_ftr_reg(entry->sys_reg); 1645 else 1646 return __read_sysreg_by_encoding(entry->sys_reg); 1647 } 1648 1649 static bool 1650 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1651 { 1652 int mask; 1653 struct arm64_ftr_reg *regp; 1654 u64 val = read_scoped_sysreg(entry, scope); 1655 1656 regp = get_arm64_ftr_reg(entry->sys_reg); 1657 if (!regp) 1658 return false; 1659 1660 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1661 entry->field_pos, 1662 entry->field_width); 1663 if (!mask) 1664 return false; 1665 1666 return feature_matches(val, entry); 1667 } 1668 1669 static bool 1670 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1671 { 1672 u64 val = read_scoped_sysreg(entry, scope); 1673 return feature_matches(val, entry); 1674 } 1675 1676 const struct cpumask *system_32bit_el0_cpumask(void) 1677 { 1678 if (!system_supports_32bit_el0()) 1679 return cpu_none_mask; 1680 1681 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1682 return cpu_32bit_el0_mask; 1683 1684 return cpu_possible_mask; 1685 } 1686 1687 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1688 { 1689 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1690 } 1691 1692 static int __init parse_32bit_el0_param(char *str) 1693 { 1694 allow_mismatched_32bit_el0 = true; 1695 return 0; 1696 } 1697 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1698 1699 static ssize_t aarch32_el0_show(struct device *dev, 1700 struct device_attribute *attr, char *buf) 1701 { 1702 const struct cpumask *mask = system_32bit_el0_cpumask(); 1703 1704 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1705 } 1706 static const DEVICE_ATTR_RO(aarch32_el0); 1707 1708 static int __init aarch32_el0_sysfs_init(void) 1709 { 1710 struct device *dev_root; 1711 int ret = 0; 1712 1713 if (!allow_mismatched_32bit_el0) 1714 return 0; 1715 1716 dev_root = bus_get_dev_root(&cpu_subsys); 1717 if (dev_root) { 1718 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1719 put_device(dev_root); 1720 } 1721 return ret; 1722 } 1723 device_initcall(aarch32_el0_sysfs_init); 1724 1725 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1726 { 1727 if (!has_cpuid_feature(entry, scope)) 1728 return allow_mismatched_32bit_el0; 1729 1730 if (scope == SCOPE_SYSTEM) 1731 pr_info("detected: 32-bit EL0 Support\n"); 1732 1733 return true; 1734 } 1735 1736 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1737 { 1738 bool has_sre; 1739 1740 if (!has_cpuid_feature(entry, scope)) 1741 return false; 1742 1743 has_sre = gic_enable_sre(); 1744 if (!has_sre) 1745 pr_warn_once("%s present but disabled by higher exception level\n", 1746 entry->desc); 1747 1748 return has_sre; 1749 } 1750 1751 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1752 int scope) 1753 { 1754 u64 ctr; 1755 1756 if (scope == SCOPE_SYSTEM) 1757 ctr = arm64_ftr_reg_ctrel0.sys_val; 1758 else 1759 ctr = read_cpuid_effective_cachetype(); 1760 1761 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1762 } 1763 1764 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1765 { 1766 /* 1767 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1768 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1769 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1770 * value. 1771 */ 1772 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1773 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1774 } 1775 1776 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1777 int scope) 1778 { 1779 u64 ctr; 1780 1781 if (scope == SCOPE_SYSTEM) 1782 ctr = arm64_ftr_reg_ctrel0.sys_val; 1783 else 1784 ctr = read_cpuid_cachetype(); 1785 1786 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1787 } 1788 1789 static bool __maybe_unused 1790 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1791 { 1792 /* 1793 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1794 * may share TLB entries with a CPU stuck in the crashed 1795 * kernel. 1796 */ 1797 if (is_kdump_kernel()) 1798 return false; 1799 1800 if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) 1801 return false; 1802 1803 return has_cpuid_feature(entry, scope); 1804 } 1805 1806 static bool __meltdown_safe = true; 1807 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1808 1809 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1810 int scope) 1811 { 1812 /* List of CPUs that are not vulnerable and don't need KPTI */ 1813 static const struct midr_range kpti_safe_list[] = { 1814 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1815 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1816 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1817 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1818 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1819 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1820 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1821 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1822 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1823 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1824 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1825 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1826 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1827 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1828 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1829 { /* sentinel */ } 1830 }; 1831 char const *str = "kpti command line option"; 1832 bool meltdown_safe; 1833 1834 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1835 1836 /* Defer to CPU feature registers */ 1837 if (has_cpuid_feature(entry, scope)) 1838 meltdown_safe = true; 1839 1840 if (!meltdown_safe) 1841 __meltdown_safe = false; 1842 1843 /* 1844 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1845 * ThunderX leads to apparent I-cache corruption of kernel text, which 1846 * ends as well as you might imagine. Don't even try. We cannot rely 1847 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1848 * because cpucap detection order may change. However, since we know 1849 * affected CPUs are always in a homogeneous configuration, it is 1850 * safe to rely on this_cpu_has_cap() here. 1851 */ 1852 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1853 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1854 __kpti_forced = -1; 1855 } 1856 1857 /* Useful for KASLR robustness */ 1858 if (kaslr_enabled() && kaslr_requires_kpti()) { 1859 if (!__kpti_forced) { 1860 str = "KASLR"; 1861 __kpti_forced = 1; 1862 } 1863 } 1864 1865 if (cpu_mitigations_off() && !__kpti_forced) { 1866 str = "mitigations=off"; 1867 __kpti_forced = -1; 1868 } 1869 1870 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1871 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1872 return false; 1873 } 1874 1875 /* Forced? */ 1876 if (__kpti_forced) { 1877 pr_info_once("kernel page table isolation forced %s by %s\n", 1878 __kpti_forced > 0 ? "ON" : "OFF", str); 1879 return __kpti_forced > 0; 1880 } 1881 1882 return !meltdown_safe; 1883 } 1884 1885 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1886 { 1887 /* 1888 * Although the Apple M2 family appears to support NV1, the 1889 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1890 * that it doesn't support NV1 at all. 1891 */ 1892 static const struct midr_range nv1_ni_list[] = { 1893 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1894 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1895 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1896 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1897 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1898 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1899 {} 1900 }; 1901 1902 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1903 !(has_cpuid_feature(entry, scope) || 1904 is_midr_in_range_list(nv1_ni_list))); 1905 } 1906 1907 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1908 static bool has_lpa2_at_stage1(u64 mmfr0) 1909 { 1910 unsigned int tgran; 1911 1912 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1913 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1914 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1915 } 1916 1917 static bool has_lpa2_at_stage2(u64 mmfr0) 1918 { 1919 unsigned int tgran; 1920 1921 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1922 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1923 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1924 } 1925 1926 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1927 { 1928 u64 mmfr0; 1929 1930 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1931 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1932 } 1933 #else 1934 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1935 { 1936 return false; 1937 } 1938 #endif 1939 1940 #ifdef CONFIG_HW_PERF_EVENTS 1941 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1942 { 1943 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1944 unsigned int pmuver; 1945 1946 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1947 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1948 1949 return pmuv3_implemented(pmuver); 1950 } 1951 #endif 1952 1953 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1954 { 1955 if (__this_cpu_read(this_cpu_vector) == vectors) { 1956 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1957 1958 __this_cpu_write(this_cpu_vector, v); 1959 } 1960 1961 } 1962 1963 static int __init parse_kpti(char *str) 1964 { 1965 bool enabled; 1966 int ret = kstrtobool(str, &enabled); 1967 1968 if (ret) 1969 return ret; 1970 1971 __kpti_forced = enabled ? 1 : -1; 1972 return 0; 1973 } 1974 early_param("kpti", parse_kpti); 1975 1976 #ifdef CONFIG_ARM64_HW_AFDBM 1977 static struct cpumask dbm_cpus __read_mostly; 1978 1979 static inline void __cpu_enable_hw_dbm(void) 1980 { 1981 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1982 1983 write_sysreg(tcr, tcr_el1); 1984 isb(); 1985 local_flush_tlb_all(); 1986 } 1987 1988 static bool cpu_has_broken_dbm(void) 1989 { 1990 /* List of CPUs which have broken DBM support. */ 1991 static const struct midr_range cpus[] = { 1992 #ifdef CONFIG_ARM64_ERRATUM_1024718 1993 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1994 /* Kryo4xx Silver (rdpe => r1p0) */ 1995 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1996 #endif 1997 #ifdef CONFIG_ARM64_ERRATUM_2051678 1998 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1999 #endif 2000 {}, 2001 }; 2002 2003 return is_midr_in_range_list(cpus); 2004 } 2005 2006 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2007 { 2008 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2009 !cpu_has_broken_dbm(); 2010 } 2011 2012 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2013 { 2014 if (cpu_can_use_dbm(cap)) { 2015 __cpu_enable_hw_dbm(); 2016 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2017 } 2018 } 2019 2020 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2021 int __unused) 2022 { 2023 /* 2024 * DBM is a non-conflicting feature. i.e, the kernel can safely 2025 * run a mix of CPUs with and without the feature. So, we 2026 * unconditionally enable the capability to allow any late CPU 2027 * to use the feature. We only enable the control bits on the 2028 * CPU, if it is supported. 2029 */ 2030 2031 return true; 2032 } 2033 2034 #endif 2035 2036 #ifdef CONFIG_ARM64_AMU_EXTN 2037 2038 /* 2039 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2040 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2041 * information regarding all the events that it supports. When a CPU bit is 2042 * set in the cpumask, the user of this feature can only rely on the presence 2043 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2044 * counters are enabled or access to these counters is enabled by code 2045 * executed at higher exception levels (firmware). 2046 */ 2047 static struct cpumask amu_cpus __read_mostly; 2048 2049 bool cpu_has_amu_feat(int cpu) 2050 { 2051 return cpumask_test_cpu(cpu, &amu_cpus); 2052 } 2053 2054 int get_cpu_with_amu_feat(void) 2055 { 2056 return cpumask_any(&amu_cpus); 2057 } 2058 2059 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2060 { 2061 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2062 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2063 2064 /* 0 reference values signal broken/disabled counters */ 2065 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2066 update_freq_counters_refs(); 2067 } 2068 } 2069 2070 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2071 int __unused) 2072 { 2073 /* 2074 * The AMU extension is a non-conflicting feature: the kernel can 2075 * safely run a mix of CPUs with and without support for the 2076 * activity monitors extension. Therefore, unconditionally enable 2077 * the capability to allow any late CPU to use the feature. 2078 * 2079 * With this feature unconditionally enabled, the cpu_enable 2080 * function will be called for all CPUs that match the criteria, 2081 * including secondary and hotplugged, marking this feature as 2082 * present on that respective CPU. The enable function will also 2083 * print a detection message. 2084 */ 2085 2086 return true; 2087 } 2088 #else 2089 int get_cpu_with_amu_feat(void) 2090 { 2091 return nr_cpu_ids; 2092 } 2093 #endif 2094 2095 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2096 { 2097 return is_kernel_in_hyp_mode(); 2098 } 2099 2100 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2101 { 2102 /* 2103 * Copy register values that aren't redirected by hardware. 2104 * 2105 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2106 * this value to tpidr_el2 before we patch the code. Once we've done 2107 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2108 * do anything here. 2109 */ 2110 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2111 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2112 } 2113 2114 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2115 int scope) 2116 { 2117 if (kvm_get_mode() != KVM_MODE_NV) 2118 return false; 2119 2120 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2121 pr_warn("unavailable: %s\n", cap->desc); 2122 return false; 2123 } 2124 2125 return true; 2126 } 2127 2128 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2129 int __unused) 2130 { 2131 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2132 } 2133 2134 bool cpu_supports_bbml3(void) 2135 { 2136 /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ 2137 static const struct midr_range supports_bbml3_list[] = { 2138 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2139 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2140 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2141 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2142 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2143 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2144 MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), 2145 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 2146 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 2147 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 2148 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 2149 MIDR_ALL_VERSIONS(MIDR_C1_NANO), 2150 MIDR_ALL_VERSIONS(MIDR_C1_PRO), 2151 /* Erratum 3683289 fixed in r1p1 */ 2152 MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), 2153 MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), 2154 {} 2155 }; 2156 u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); 2157 2158 if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) 2159 return true; 2160 2161 return is_midr_in_range_list(supports_bbml3_list); 2162 } 2163 2164 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) 2165 { 2166 return cpu_supports_bbml3(); 2167 } 2168 2169 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2170 { 2171 /* 2172 * We modify PSTATE. This won't work from irq context as the PSTATE 2173 * is discarded once we return from the exception. 2174 */ 2175 WARN_ON_ONCE(in_interrupt()); 2176 2177 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2178 set_pstate_pan(1); 2179 } 2180 2181 #ifdef CONFIG_ARM64_RAS_EXTN 2182 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2183 { 2184 /* Firmware may have left a deferred SError in this register. */ 2185 write_sysreg_s(0, SYS_DISR_EL1); 2186 } 2187 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2188 { 2189 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2190 { 2191 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2192 }, 2193 { 2194 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2195 }, 2196 { 2197 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2198 }, 2199 }; 2200 2201 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2202 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2203 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2204 } 2205 #endif /* CONFIG_ARM64_RAS_EXTN */ 2206 2207 #ifdef CONFIG_ARM64_PTR_AUTH 2208 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2209 { 2210 int boot_val, sec_val; 2211 2212 /* We don't expect to be called with SCOPE_SYSTEM */ 2213 WARN_ON(scope == SCOPE_SYSTEM); 2214 /* 2215 * The ptr-auth feature levels are not intercompatible with lower 2216 * levels. Hence we must match ptr-auth feature level of the secondary 2217 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2218 * from the sanitised register whereas direct register read is done for 2219 * the secondary CPUs. 2220 * The sanitised feature state is guaranteed to match that of the 2221 * boot CPU as a mismatched secondary CPU is parked before it gets 2222 * a chance to update the state, with the capability. 2223 */ 2224 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2225 entry->field_pos, entry->sign); 2226 if (scope & SCOPE_BOOT_CPU) 2227 return boot_val >= entry->min_field_value; 2228 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2229 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2230 entry->field_pos, entry->sign); 2231 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2232 } 2233 2234 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2235 int scope) 2236 { 2237 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2238 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2239 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2240 2241 return apa || apa3 || api; 2242 } 2243 2244 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2245 int __unused) 2246 { 2247 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2248 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2249 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2250 2251 return gpa || gpa3 || gpi; 2252 } 2253 #endif /* CONFIG_ARM64_PTR_AUTH */ 2254 2255 #ifdef CONFIG_ARM64_E0PD 2256 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2257 { 2258 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2259 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2260 } 2261 #endif /* CONFIG_ARM64_E0PD */ 2262 2263 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2264 { 2265 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2266 } 2267 2268 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2269 { 2270 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2271 } 2272 2273 #ifdef CONFIG_ARM64_PSEUDO_NMI 2274 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2275 int scope) 2276 { 2277 /* 2278 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2279 * feature, so will be detected earlier. 2280 */ 2281 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2282 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2283 return false; 2284 2285 return enable_pseudo_nmi; 2286 } 2287 2288 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2289 int scope) 2290 { 2291 /* 2292 * If we're not using priority masking then we won't be poking PMR_EL1, 2293 * and there's no need to relax synchronization of writes to it, and 2294 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2295 * that. 2296 * 2297 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2298 * feature, so will be detected earlier. 2299 */ 2300 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2301 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2302 return false; 2303 2304 /* 2305 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2306 * hint for interrupt distribution, a DSB is not necessary when 2307 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2308 * 2309 * Linux itself doesn't use 1:N distribution, so has no need to 2310 * set PMHE. The only reason to have it set is if EL3 requires it 2311 * (and we can't change it). 2312 */ 2313 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2314 } 2315 #endif 2316 2317 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2318 int scope) 2319 { 2320 static const struct midr_range has_vgic_v3[] = { 2321 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2322 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2323 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2324 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2325 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2326 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2327 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2328 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2329 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2330 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2331 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2332 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2333 {}, 2334 }; 2335 struct arm_smccc_res res = {}; 2336 2337 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2338 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2339 if (!is_hyp_mode_available()) 2340 return false; 2341 2342 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2343 return true; 2344 2345 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2346 !is_midr_in_range_list(has_vgic_v3)) 2347 return false; 2348 2349 /* 2350 * pKVM prevents late onlining of CPUs. This means that whatever 2351 * state the capability is in after deprivilege cannot be affected 2352 * by a new CPU booting -- this is garanteed to be a CPU we have 2353 * already seen, and the cap is therefore unchanged. 2354 */ 2355 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2356 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2357 2358 if (is_kernel_in_hyp_mode()) 2359 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2360 else 2361 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2362 2363 if (res.a0 == HVC_STUB_ERR) 2364 return false; 2365 2366 return res.a1 & ICH_VTR_EL2_TDS; 2367 } 2368 2369 #ifdef CONFIG_ARM64_BTI 2370 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2371 { 2372 /* 2373 * Use of X16/X17 for tail-calls and trampolines that jump to 2374 * function entry points using BR is a requirement for 2375 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2376 * So, be strict and forbid other BRs using other registers to 2377 * jump onto a PACIxSP instruction: 2378 */ 2379 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2380 isb(); 2381 } 2382 #endif /* CONFIG_ARM64_BTI */ 2383 2384 #ifdef CONFIG_ARM64_MTE 2385 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2386 { 2387 static bool cleared_zero_page = false; 2388 2389 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2390 2391 mte_cpu_setup(); 2392 2393 /* 2394 * Clear the tags in the zero page. This needs to be done via the 2395 * linear map which has the Tagged attribute. Since this page is 2396 * always mapped as pte_special(), set_pte_at() will not attempt to 2397 * clear the tags or set PG_mte_tagged. 2398 */ 2399 if (!cleared_zero_page) { 2400 cleared_zero_page = true; 2401 mte_clear_page_tags(lm_alias(empty_zero_page)); 2402 } 2403 2404 kasan_init_hw_tags_cpu(); 2405 } 2406 #endif /* CONFIG_ARM64_MTE */ 2407 2408 static void user_feature_fixup(void) 2409 { 2410 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2411 struct arm64_ftr_reg *regp; 2412 2413 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2414 if (regp) 2415 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2416 } 2417 2418 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2419 struct arm64_ftr_reg *regp; 2420 2421 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2422 if (regp) 2423 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2424 } 2425 } 2426 2427 static void elf_hwcap_fixup(void) 2428 { 2429 #ifdef CONFIG_COMPAT 2430 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2431 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2432 #endif /* CONFIG_COMPAT */ 2433 } 2434 2435 #ifdef CONFIG_KVM 2436 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2437 { 2438 return kvm_get_mode() == KVM_MODE_PROTECTED; 2439 } 2440 #endif /* CONFIG_KVM */ 2441 2442 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2443 { 2444 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2445 } 2446 2447 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2448 { 2449 set_pstate_dit(1); 2450 } 2451 2452 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2453 { 2454 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2455 } 2456 2457 #ifdef CONFIG_ARM64_POE 2458 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2459 { 2460 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2461 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2462 } 2463 #endif 2464 2465 #ifdef CONFIG_ARM64_GCS 2466 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2467 { 2468 /* GCSPR_EL0 is always readable */ 2469 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2470 } 2471 #endif 2472 2473 /* Internal helper functions to match cpu capability type */ 2474 static bool 2475 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2476 { 2477 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2478 } 2479 2480 static bool 2481 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2482 { 2483 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2484 } 2485 2486 static bool 2487 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2488 { 2489 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2490 } 2491 2492 static bool 2493 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2494 { 2495 if (!detect_ftr_has_mpam()) 2496 return false; 2497 2498 /* Check firmware actually enabled MPAM on this cpu. */ 2499 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2500 } 2501 2502 static void 2503 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2504 { 2505 int cpu = smp_processor_id(); 2506 u64 regval = 0; 2507 2508 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2509 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2510 2511 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2512 if (cpus_have_cap(ARM64_SME)) 2513 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2514 isb(); 2515 2516 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2517 write_sysreg_s(regval, SYS_MPAM0_EL1); 2518 } 2519 2520 static bool 2521 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2522 { 2523 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2524 2525 return idr & MPAMIDR_EL1_HAS_HCR; 2526 } 2527 2528 static bool 2529 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2530 { 2531 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2532 return false; 2533 2534 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2535 } 2536 2537 static const struct arm64_cpu_capabilities arm64_features[] = { 2538 { 2539 .capability = ARM64_ALWAYS_BOOT, 2540 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2541 .matches = has_always, 2542 }, 2543 { 2544 .capability = ARM64_ALWAYS_SYSTEM, 2545 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2546 .matches = has_always, 2547 }, 2548 { 2549 .desc = "GICv3 CPU interface", 2550 .capability = ARM64_HAS_GICV3_CPUIF, 2551 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2552 .matches = has_useable_gicv3_cpuif, 2553 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2554 }, 2555 { 2556 .desc = "Enhanced Counter Virtualization", 2557 .capability = ARM64_HAS_ECV, 2558 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2559 .matches = has_cpuid_feature, 2560 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2561 }, 2562 { 2563 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2564 .capability = ARM64_HAS_ECV_CNTPOFF, 2565 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2566 .matches = has_cpuid_feature, 2567 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2568 }, 2569 { 2570 .desc = "Privileged Access Never", 2571 .capability = ARM64_HAS_PAN, 2572 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2573 .matches = has_cpuid_feature, 2574 .cpu_enable = cpu_enable_pan, 2575 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2576 }, 2577 #ifdef CONFIG_ARM64_EPAN 2578 { 2579 .desc = "Enhanced Privileged Access Never", 2580 .capability = ARM64_HAS_EPAN, 2581 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2582 .matches = has_cpuid_feature, 2583 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2584 }, 2585 #endif /* CONFIG_ARM64_EPAN */ 2586 { 2587 .desc = "LSE atomic instructions", 2588 .capability = ARM64_HAS_LSE_ATOMICS, 2589 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2590 .matches = has_cpuid_feature, 2591 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2592 }, 2593 { 2594 .desc = "Virtualization Host Extensions", 2595 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2596 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2597 .matches = runs_at_el2, 2598 .cpu_enable = cpu_copy_el2regs, 2599 }, 2600 { 2601 .desc = "Nested Virtualization Support", 2602 .capability = ARM64_HAS_NESTED_VIRT, 2603 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2604 .matches = has_nested_virt_support, 2605 .match_list = (const struct arm64_cpu_capabilities []){ 2606 { 2607 .matches = has_cpuid_feature, 2608 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2609 }, 2610 { 2611 .matches = has_cpuid_feature, 2612 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2613 }, 2614 { /* Sentinel */ } 2615 }, 2616 }, 2617 { 2618 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2619 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2620 .matches = has_32bit_el0, 2621 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2622 }, 2623 #ifdef CONFIG_KVM 2624 { 2625 .desc = "32-bit EL1 Support", 2626 .capability = ARM64_HAS_32BIT_EL1, 2627 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2628 .matches = has_cpuid_feature, 2629 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2630 }, 2631 { 2632 .desc = "Protected KVM", 2633 .capability = ARM64_KVM_PROTECTED_MODE, 2634 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2635 .matches = is_kvm_protected_mode, 2636 }, 2637 { 2638 .desc = "HCRX_EL2 register", 2639 .capability = ARM64_HAS_HCX, 2640 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2641 .matches = has_cpuid_feature, 2642 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2643 }, 2644 #endif 2645 { 2646 .desc = "Kernel page table isolation (KPTI)", 2647 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2648 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2649 .cpu_enable = cpu_enable_kpti, 2650 .matches = unmap_kernel_at_el0, 2651 /* 2652 * The ID feature fields below are used to indicate that 2653 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2654 * more details. 2655 */ 2656 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2657 }, 2658 { 2659 .capability = ARM64_HAS_FPSIMD, 2660 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2661 .matches = has_cpuid_feature, 2662 .cpu_enable = cpu_enable_fpsimd, 2663 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2664 }, 2665 #ifdef CONFIG_ARM64_PMEM 2666 { 2667 .desc = "Data cache clean to Point of Persistence", 2668 .capability = ARM64_HAS_DCPOP, 2669 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2670 .matches = has_cpuid_feature, 2671 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2672 }, 2673 { 2674 .desc = "Data cache clean to Point of Deep Persistence", 2675 .capability = ARM64_HAS_DCPODP, 2676 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2677 .matches = has_cpuid_feature, 2678 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2679 }, 2680 #endif 2681 #ifdef CONFIG_ARM64_SVE 2682 { 2683 .desc = "Scalable Vector Extension", 2684 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2685 .capability = ARM64_SVE, 2686 .cpu_enable = cpu_enable_sve, 2687 .matches = has_cpuid_feature, 2688 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2689 }, 2690 #endif /* CONFIG_ARM64_SVE */ 2691 #ifdef CONFIG_ARM64_RAS_EXTN 2692 { 2693 .desc = "RAS Extension Support", 2694 .capability = ARM64_HAS_RAS_EXTN, 2695 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2696 .matches = has_cpuid_feature, 2697 .cpu_enable = cpu_clear_disr, 2698 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2699 }, 2700 { 2701 .desc = "RASv1p1 Extension Support", 2702 .capability = ARM64_HAS_RASV1P1_EXTN, 2703 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2704 .matches = has_rasv1p1, 2705 }, 2706 #endif /* CONFIG_ARM64_RAS_EXTN */ 2707 #ifdef CONFIG_ARM64_AMU_EXTN 2708 { 2709 .desc = "Activity Monitors Unit (AMU)", 2710 .capability = ARM64_HAS_AMU_EXTN, 2711 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2712 .matches = has_amu, 2713 .cpu_enable = cpu_amu_enable, 2714 .cpus = &amu_cpus, 2715 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2716 }, 2717 #endif /* CONFIG_ARM64_AMU_EXTN */ 2718 { 2719 .desc = "Data cache clean to the PoU not required for I/D coherence", 2720 .capability = ARM64_HAS_CACHE_IDC, 2721 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2722 .matches = has_cache_idc, 2723 .cpu_enable = cpu_emulate_effective_ctr, 2724 }, 2725 { 2726 .desc = "Instruction cache invalidation not required for I/D coherence", 2727 .capability = ARM64_HAS_CACHE_DIC, 2728 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2729 .matches = has_cache_dic, 2730 }, 2731 { 2732 .desc = "Stage-2 Force Write-Back", 2733 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2734 .capability = ARM64_HAS_STAGE2_FWB, 2735 .matches = has_cpuid_feature, 2736 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2737 }, 2738 { 2739 .desc = "ARMv8.4 Translation Table Level", 2740 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2741 .capability = ARM64_HAS_ARMv8_4_TTL, 2742 .matches = has_cpuid_feature, 2743 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2744 }, 2745 { 2746 .desc = "TLB range maintenance instructions", 2747 .capability = ARM64_HAS_TLB_RANGE, 2748 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2749 .matches = has_cpuid_feature, 2750 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2751 }, 2752 #ifdef CONFIG_ARM64_HW_AFDBM 2753 { 2754 .desc = "Hardware dirty bit management", 2755 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2756 .capability = ARM64_HW_DBM, 2757 .matches = has_hw_dbm, 2758 .cpu_enable = cpu_enable_hw_dbm, 2759 .cpus = &dbm_cpus, 2760 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2761 }, 2762 #endif 2763 #ifdef CONFIG_ARM64_HAFT 2764 { 2765 .desc = "Hardware managed Access Flag for Table Descriptors", 2766 /* 2767 * Contrary to the page/block access flag, the table access flag 2768 * cannot be emulated in software (no access fault will occur). 2769 * Therefore this should be used only if it's supported system 2770 * wide. 2771 */ 2772 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2773 .capability = ARM64_HAFT, 2774 .matches = has_cpuid_feature, 2775 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2776 }, 2777 #endif 2778 { 2779 .desc = "CRC32 instructions", 2780 .capability = ARM64_HAS_CRC32, 2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2782 .matches = has_cpuid_feature, 2783 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2784 }, 2785 { 2786 .desc = "Speculative Store Bypassing Safe (SSBS)", 2787 .capability = ARM64_SSBS, 2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2789 .matches = has_cpuid_feature, 2790 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2791 }, 2792 #ifdef CONFIG_ARM64_CNP 2793 { 2794 .desc = "Common not Private translations", 2795 .capability = ARM64_HAS_CNP, 2796 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2797 .matches = has_useable_cnp, 2798 .cpu_enable = cpu_enable_cnp, 2799 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2800 }, 2801 #endif 2802 { 2803 .desc = "Speculation barrier (SB)", 2804 .capability = ARM64_HAS_SB, 2805 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2806 .matches = has_cpuid_feature, 2807 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2808 }, 2809 #ifdef CONFIG_ARM64_PTR_AUTH 2810 { 2811 .desc = "Address authentication (architected QARMA5 algorithm)", 2812 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2813 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2814 .matches = has_address_auth_cpucap, 2815 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2816 }, 2817 { 2818 .desc = "Address authentication (architected QARMA3 algorithm)", 2819 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2820 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2821 .matches = has_address_auth_cpucap, 2822 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2823 }, 2824 { 2825 .desc = "Address authentication (IMP DEF algorithm)", 2826 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2827 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2828 .matches = has_address_auth_cpucap, 2829 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2830 }, 2831 { 2832 .capability = ARM64_HAS_ADDRESS_AUTH, 2833 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2834 .matches = has_address_auth_metacap, 2835 }, 2836 { 2837 .desc = "Generic authentication (architected QARMA5 algorithm)", 2838 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2839 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2840 .matches = has_cpuid_feature, 2841 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2842 }, 2843 { 2844 .desc = "Generic authentication (architected QARMA3 algorithm)", 2845 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2846 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2847 .matches = has_cpuid_feature, 2848 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2849 }, 2850 { 2851 .desc = "Generic authentication (IMP DEF algorithm)", 2852 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2853 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2854 .matches = has_cpuid_feature, 2855 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2856 }, 2857 { 2858 .capability = ARM64_HAS_GENERIC_AUTH, 2859 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2860 .matches = has_generic_auth, 2861 }, 2862 #endif /* CONFIG_ARM64_PTR_AUTH */ 2863 #ifdef CONFIG_ARM64_PSEUDO_NMI 2864 { 2865 /* 2866 * Depends on having GICv3 2867 */ 2868 .desc = "IRQ priority masking", 2869 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2870 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2871 .matches = can_use_gic_priorities, 2872 }, 2873 { 2874 /* 2875 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2876 */ 2877 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2878 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2879 .matches = has_gic_prio_relaxed_sync, 2880 }, 2881 #endif 2882 { 2883 /* 2884 * Depends on having GICv3 2885 */ 2886 .desc = "ICV_DIR_EL1 trapping", 2887 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2888 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2889 .matches = can_trap_icv_dir_el1, 2890 }, 2891 #ifdef CONFIG_ARM64_E0PD 2892 { 2893 .desc = "E0PD", 2894 .capability = ARM64_HAS_E0PD, 2895 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2896 .cpu_enable = cpu_enable_e0pd, 2897 .matches = has_cpuid_feature, 2898 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2899 }, 2900 #endif 2901 { 2902 .desc = "Random Number Generator", 2903 .capability = ARM64_HAS_RNG, 2904 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2905 .matches = has_cpuid_feature, 2906 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2907 }, 2908 #ifdef CONFIG_ARM64_BTI 2909 { 2910 .desc = "Branch Target Identification", 2911 .capability = ARM64_BTI, 2912 #ifdef CONFIG_ARM64_BTI_KERNEL 2913 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2914 #else 2915 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2916 #endif 2917 .matches = has_cpuid_feature, 2918 .cpu_enable = bti_enable, 2919 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2920 }, 2921 #endif 2922 #ifdef CONFIG_ARM64_MTE 2923 { 2924 .desc = "Memory Tagging Extension", 2925 .capability = ARM64_MTE, 2926 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2927 .matches = has_cpuid_feature, 2928 .cpu_enable = cpu_enable_mte, 2929 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2930 }, 2931 { 2932 .desc = "Asymmetric MTE Tag Check Fault", 2933 .capability = ARM64_MTE_ASYMM, 2934 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2935 .matches = has_cpuid_feature, 2936 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2937 }, 2938 { 2939 .desc = "FAR on MTE Tag Check Fault", 2940 .capability = ARM64_MTE_FAR, 2941 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2942 .matches = has_cpuid_feature, 2943 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2944 }, 2945 { 2946 .desc = "Store Only MTE Tag Check", 2947 .capability = ARM64_MTE_STORE_ONLY, 2948 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2949 .matches = has_cpuid_feature, 2950 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2951 }, 2952 #endif /* CONFIG_ARM64_MTE */ 2953 { 2954 .desc = "RCpc load-acquire (LDAPR)", 2955 .capability = ARM64_HAS_LDAPR, 2956 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2957 .matches = has_cpuid_feature, 2958 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2959 }, 2960 { 2961 .desc = "Fine Grained Traps", 2962 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2963 .capability = ARM64_HAS_FGT, 2964 .matches = has_cpuid_feature, 2965 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2966 }, 2967 { 2968 .desc = "Fine Grained Traps 2", 2969 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2970 .capability = ARM64_HAS_FGT2, 2971 .matches = has_cpuid_feature, 2972 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2973 }, 2974 #ifdef CONFIG_ARM64_SME 2975 { 2976 .desc = "Scalable Matrix Extension", 2977 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2978 .capability = ARM64_SME, 2979 .matches = has_cpuid_feature, 2980 .cpu_enable = cpu_enable_sme, 2981 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2982 }, 2983 /* FA64 should be sorted after the base SME capability */ 2984 { 2985 .desc = "FA64", 2986 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2987 .capability = ARM64_SME_FA64, 2988 .matches = has_cpuid_feature, 2989 .cpu_enable = cpu_enable_fa64, 2990 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2991 }, 2992 { 2993 .desc = "SME2", 2994 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2995 .capability = ARM64_SME2, 2996 .matches = has_cpuid_feature, 2997 .cpu_enable = cpu_enable_sme2, 2998 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2999 }, 3000 #endif /* CONFIG_ARM64_SME */ 3001 { 3002 .desc = "WFx with timeout", 3003 .capability = ARM64_HAS_WFXT, 3004 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3005 .matches = has_cpuid_feature, 3006 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 3007 }, 3008 { 3009 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 3010 .capability = ARM64_HAS_TIDCP1, 3011 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3012 .matches = has_cpuid_feature, 3013 .cpu_enable = cpu_trap_el0_impdef, 3014 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3015 }, 3016 { 3017 .desc = "Data independent timing control (DIT)", 3018 .capability = ARM64_HAS_DIT, 3019 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3020 .matches = has_cpuid_feature, 3021 .cpu_enable = cpu_enable_dit, 3022 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3023 }, 3024 { 3025 .desc = "Memory Copy and Memory Set instructions", 3026 .capability = ARM64_HAS_MOPS, 3027 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3028 .matches = has_cpuid_feature, 3029 .cpu_enable = cpu_enable_mops, 3030 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3031 }, 3032 { 3033 .capability = ARM64_HAS_TCR2, 3034 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3035 .matches = has_cpuid_feature, 3036 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3037 }, 3038 { 3039 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3040 .capability = ARM64_HAS_S1PIE, 3041 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3042 .matches = has_cpuid_feature, 3043 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3044 }, 3045 { 3046 .desc = "VHE for hypervisor only", 3047 .capability = ARM64_KVM_HVHE, 3048 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3049 .matches = hvhe_possible, 3050 }, 3051 { 3052 .desc = "Enhanced Virtualization Traps", 3053 .capability = ARM64_HAS_EVT, 3054 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3055 .matches = has_cpuid_feature, 3056 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3057 }, 3058 { 3059 .desc = "BBM Level 3", 3060 .capability = ARM64_HAS_BBML3, 3061 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3062 .matches = has_bbml3, 3063 }, 3064 { 3065 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3066 .capability = ARM64_HAS_LPA2, 3067 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3068 .matches = has_lpa2, 3069 }, 3070 { 3071 .desc = "FPMR", 3072 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3073 .capability = ARM64_HAS_FPMR, 3074 .matches = has_cpuid_feature, 3075 .cpu_enable = cpu_enable_fpmr, 3076 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3077 }, 3078 #ifdef CONFIG_ARM64_VA_BITS_52 3079 { 3080 .capability = ARM64_HAS_VA52, 3081 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3082 .matches = has_cpuid_feature, 3083 #ifdef CONFIG_ARM64_64K_PAGES 3084 .desc = "52-bit Virtual Addressing (LVA)", 3085 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3086 #else 3087 .desc = "52-bit Virtual Addressing (LPA2)", 3088 #ifdef CONFIG_ARM64_4K_PAGES 3089 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3090 #else 3091 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3092 #endif 3093 #endif 3094 }, 3095 #endif 3096 { 3097 .desc = "Memory Partitioning And Monitoring", 3098 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3099 .capability = ARM64_MPAM, 3100 .matches = test_has_mpam, 3101 .cpu_enable = cpu_enable_mpam, 3102 }, 3103 { 3104 .desc = "Memory Partitioning And Monitoring Virtualisation", 3105 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3106 .capability = ARM64_MPAM_HCR, 3107 .matches = test_has_mpam_hcr, 3108 }, 3109 { 3110 .desc = "NV1", 3111 .capability = ARM64_HAS_HCR_NV1, 3112 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3113 .matches = has_nv1, 3114 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3115 }, 3116 #ifdef CONFIG_ARM64_POE 3117 { 3118 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3119 .capability = ARM64_HAS_S1POE, 3120 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3121 .matches = has_cpuid_feature, 3122 .cpu_enable = cpu_enable_poe, 3123 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3124 }, 3125 #endif 3126 #ifdef CONFIG_ARM64_GCS 3127 { 3128 .desc = "Guarded Control Stack (GCS)", 3129 .capability = ARM64_HAS_GCS, 3130 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3131 .cpu_enable = cpu_enable_gcs, 3132 .matches = has_cpuid_feature, 3133 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3134 }, 3135 #endif 3136 #ifdef CONFIG_HW_PERF_EVENTS 3137 { 3138 .desc = "PMUv3", 3139 .capability = ARM64_HAS_PMUV3, 3140 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3141 .matches = has_pmuv3, 3142 }, 3143 #endif 3144 { 3145 .desc = "SCTLR2", 3146 .capability = ARM64_HAS_SCTLR2, 3147 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3148 .matches = has_cpuid_feature, 3149 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3150 }, 3151 { 3152 .desc = "GICv5 CPU interface", 3153 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3154 .capability = ARM64_HAS_GICV5_CPUIF, 3155 .matches = has_cpuid_feature, 3156 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3157 }, 3158 { 3159 .desc = "GICv5 Legacy vCPU interface", 3160 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3161 .capability = ARM64_HAS_GICV5_LEGACY, 3162 .matches = test_has_gicv5_legacy, 3163 }, 3164 { 3165 .desc = "XNX", 3166 .capability = ARM64_HAS_XNX, 3167 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3168 .matches = has_cpuid_feature, 3169 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3170 }, 3171 { 3172 .desc = "LS64", 3173 .capability = ARM64_HAS_LS64, 3174 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3175 .matches = has_cpuid_feature, 3176 .cpu_enable = cpu_enable_ls64, 3177 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3178 }, 3179 { 3180 .desc = "LS64_V", 3181 .capability = ARM64_HAS_LS64_V, 3182 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3183 .matches = has_cpuid_feature, 3184 .cpu_enable = cpu_enable_ls64_v, 3185 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3186 }, 3187 #ifdef CONFIG_ARM64_LSUI 3188 { 3189 .desc = "Unprivileged Load Store Instructions (LSUI)", 3190 .capability = ARM64_HAS_LSUI, 3191 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3192 .matches = has_cpuid_feature, 3193 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3194 }, 3195 #endif 3196 {}, 3197 }; 3198 3199 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3200 .matches = has_user_cpuid_feature, \ 3201 ARM64_CPUID_FIELDS(reg, field, min_value) 3202 3203 #define __HWCAP_CAP(name, cap_type, cap) \ 3204 .desc = name, \ 3205 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3206 .hwcap_type = cap_type, \ 3207 .hwcap = cap, \ 3208 3209 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3210 { \ 3211 __HWCAP_CAP(#cap, cap_type, cap) \ 3212 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3213 } 3214 3215 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3216 { \ 3217 __HWCAP_CAP(#cap, cap_type, cap) \ 3218 .matches = cpucap_multi_entry_cap_matches, \ 3219 .match_list = list, \ 3220 } 3221 3222 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3223 { \ 3224 __HWCAP_CAP(#cap, cap_type, cap) \ 3225 .matches = match, \ 3226 } 3227 3228 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3229 { \ 3230 __HWCAP_CAP(#cap, cap_type, cap) \ 3231 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3232 .matches = match, \ 3233 } 3234 3235 #ifdef CONFIG_ARM64_PTR_AUTH 3236 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3237 { 3238 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3239 }, 3240 { 3241 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3242 }, 3243 { 3244 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3245 }, 3246 {}, 3247 }; 3248 3249 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3250 { 3251 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3252 }, 3253 { 3254 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3255 }, 3256 { 3257 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3258 }, 3259 {}, 3260 }; 3261 #endif 3262 3263 #ifdef CONFIG_ARM64_SVE 3264 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3265 { 3266 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3267 } 3268 #endif 3269 3270 #ifdef CONFIG_ARM64_SME 3271 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3272 { 3273 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3274 } 3275 #endif 3276 3277 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3278 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3279 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3280 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3281 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3282 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3283 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3284 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3285 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3286 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3287 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3288 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3289 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3290 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3291 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3292 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F32DOT), 3293 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32MM), 3294 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3295 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3296 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3297 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3298 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3299 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3300 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3301 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3302 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3303 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3304 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3305 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3306 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3307 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3308 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3309 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3310 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3311 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3312 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3313 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3314 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3315 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3316 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3317 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3318 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3319 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3320 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3321 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3322 #ifdef CONFIG_ARM64_SVE 3323 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_SVE_LUT6), 3324 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3325 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_HWCAP, KERNEL_HWCAP_SVE2P3), 3326 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3327 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3328 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3329 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3330 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3331 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3332 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3333 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3334 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3335 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_HWCAP, KERNEL_HWCAP_SVE_B16MM), 3336 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3337 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3338 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3339 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3340 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3341 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3342 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3343 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3344 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3345 #endif 3346 #ifdef CONFIG_ARM64_GCS 3347 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3348 #endif 3349 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3350 #ifdef CONFIG_ARM64_BTI 3351 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3352 #endif 3353 #ifdef CONFIG_ARM64_PTR_AUTH 3354 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3355 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3356 #endif 3357 #ifdef CONFIG_ARM64_MTE 3358 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3359 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3360 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3361 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3362 #endif /* CONFIG_ARM64_MTE */ 3363 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3364 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3365 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3366 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3367 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3368 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3369 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3370 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3371 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3372 #ifdef CONFIG_ARM64_SME 3373 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3374 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3375 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUT6), 3376 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3377 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP_HWCAP, KERNEL_HWCAP_SME2P3), 3378 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3379 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3380 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3381 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3382 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3383 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3384 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3385 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3386 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3387 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3388 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3389 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3390 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3391 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3392 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3393 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3394 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3395 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3396 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3397 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3398 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3399 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3400 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3401 #endif /* CONFIG_ARM64_SME */ 3402 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3403 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3404 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3405 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3406 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3407 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3408 HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), 3409 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3410 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3411 #ifdef CONFIG_ARM64_POE 3412 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3413 #endif 3414 {}, 3415 }; 3416 3417 #ifdef CONFIG_COMPAT 3418 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3419 { 3420 /* 3421 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3422 * in line with that of arm32 as in vfp_init(). We make sure that the 3423 * check is future proof, by making sure value is non-zero. 3424 */ 3425 u32 mvfr1; 3426 3427 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3428 if (scope == SCOPE_SYSTEM) 3429 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3430 else 3431 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3432 3433 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3434 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3435 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3436 } 3437 #endif 3438 3439 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3440 #ifdef CONFIG_COMPAT 3441 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3442 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3443 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3444 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3445 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3446 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3447 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3448 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3449 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3450 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3451 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3452 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3453 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3454 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3455 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3456 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3457 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3458 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3459 #endif 3460 {}, 3461 }; 3462 3463 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3464 { 3465 switch (cap->hwcap_type) { 3466 case CAP_HWCAP: 3467 cpu_set_feature(cap->hwcap); 3468 break; 3469 #ifdef CONFIG_COMPAT 3470 case CAP_COMPAT_HWCAP: 3471 compat_elf_hwcap |= (u32)cap->hwcap; 3472 break; 3473 case CAP_COMPAT_HWCAP2: 3474 compat_elf_hwcap2 |= (u32)cap->hwcap; 3475 break; 3476 #endif 3477 default: 3478 WARN_ON(1); 3479 break; 3480 } 3481 } 3482 3483 /* Check if we have a particular HWCAP enabled */ 3484 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3485 { 3486 bool rc; 3487 3488 switch (cap->hwcap_type) { 3489 case CAP_HWCAP: 3490 rc = cpu_have_feature(cap->hwcap); 3491 break; 3492 #ifdef CONFIG_COMPAT 3493 case CAP_COMPAT_HWCAP: 3494 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3495 break; 3496 case CAP_COMPAT_HWCAP2: 3497 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3498 break; 3499 #endif 3500 default: 3501 WARN_ON(1); 3502 rc = false; 3503 } 3504 3505 return rc; 3506 } 3507 3508 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3509 { 3510 /* We support emulation of accesses to CPU ID feature registers */ 3511 cpu_set_named_feature(CPUID); 3512 for (; hwcaps->matches; hwcaps++) 3513 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3514 cap_set_elf_hwcap(hwcaps); 3515 } 3516 3517 static void update_cpu_capabilities(u16 scope_mask) 3518 { 3519 int i; 3520 const struct arm64_cpu_capabilities *caps; 3521 3522 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3523 for (i = 0; i < ARM64_NCAPS; i++) { 3524 bool match_all = false; 3525 bool caps_set = false; 3526 bool boot_cpu = false; 3527 3528 caps = cpucap_ptrs[i]; 3529 if (!caps || !(caps->type & scope_mask)) 3530 continue; 3531 3532 match_all = cpucap_match_all_early_cpus(caps); 3533 caps_set = cpus_have_cap(caps->capability); 3534 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3535 3536 /* 3537 * Unless it's a match-all CPUs feature, avoid probing if 3538 * already detected. 3539 */ 3540 if (!match_all && caps_set) 3541 continue; 3542 3543 /* 3544 * A match-all CPUs capability is only set when probing the 3545 * boot CPU. It may be cleared subsequently if not detected on 3546 * secondary ones. 3547 */ 3548 if (match_all && !caps_set && !boot_cpu) 3549 continue; 3550 3551 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3552 if (match_all) 3553 __clear_bit(caps->capability, system_cpucaps); 3554 continue; 3555 } 3556 3557 /* 3558 * Match-all CPUs capabilities are logged later when the 3559 * system capabilities are finalised. 3560 */ 3561 if (!match_all && caps->desc && !caps->cpus) 3562 pr_info("detected: %s\n", caps->desc); 3563 3564 __set_bit(caps->capability, system_cpucaps); 3565 3566 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3567 set_bit(caps->capability, boot_cpucaps); 3568 } 3569 } 3570 3571 /* 3572 * Enable all the available capabilities on this CPU. The capabilities 3573 * with BOOT_CPU scope are handled separately and hence skipped here. 3574 */ 3575 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3576 { 3577 int i; 3578 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3579 3580 for_each_available_cap(i) { 3581 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3582 3583 if (WARN_ON(!cap)) 3584 continue; 3585 3586 if (!(cap->type & non_boot_scope)) 3587 continue; 3588 3589 if (cap->cpu_enable) 3590 cap->cpu_enable(cap); 3591 } 3592 return 0; 3593 } 3594 3595 /* 3596 * Run through the enabled capabilities and enable() it on all active 3597 * CPUs 3598 */ 3599 static void __init enable_cpu_capabilities(u16 scope_mask) 3600 { 3601 int i; 3602 const struct arm64_cpu_capabilities *caps; 3603 bool boot_scope; 3604 3605 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3606 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3607 3608 for (i = 0; i < ARM64_NCAPS; i++) { 3609 caps = cpucap_ptrs[i]; 3610 if (!caps || !(caps->type & scope_mask) || 3611 !cpus_have_cap(caps->capability)) 3612 continue; 3613 3614 if (boot_scope && caps->cpu_enable) 3615 /* 3616 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3617 * before any secondary CPU boots. Thus, each secondary 3618 * will enable the capability as appropriate via 3619 * check_local_cpu_capabilities(). The only exception is 3620 * the boot CPU, for which the capability must be 3621 * enabled here. This approach avoids costly 3622 * stop_machine() calls for this case. 3623 */ 3624 caps->cpu_enable(caps); 3625 } 3626 3627 /* 3628 * For all non-boot scope capabilities, use stop_machine() 3629 * as it schedules the work allowing us to modify PSTATE, 3630 * instead of on_each_cpu() which uses an IPI, giving us a 3631 * PSTATE that disappears when we return. 3632 */ 3633 if (!boot_scope) 3634 stop_machine(cpu_enable_non_boot_scope_capabilities, 3635 NULL, cpu_online_mask); 3636 } 3637 3638 /* 3639 * Run through the list of capabilities to check for conflicts. 3640 * If the system has already detected a capability, take necessary 3641 * action on this CPU. 3642 */ 3643 static void verify_local_cpu_caps(u16 scope_mask) 3644 { 3645 int i; 3646 bool cpu_has_cap, system_has_cap; 3647 const struct arm64_cpu_capabilities *caps; 3648 3649 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3650 3651 for (i = 0; i < ARM64_NCAPS; i++) { 3652 caps = cpucap_ptrs[i]; 3653 if (!caps || !(caps->type & scope_mask)) 3654 continue; 3655 3656 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3657 system_has_cap = cpus_have_cap(caps->capability); 3658 3659 if (system_has_cap) { 3660 /* 3661 * Check if the new CPU misses an advertised feature, 3662 * which is not safe to miss. 3663 */ 3664 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3665 break; 3666 /* 3667 * We have to issue cpu_enable() irrespective of 3668 * whether the CPU has it or not, as it is enabeld 3669 * system wide. It is upto the call back to take 3670 * appropriate action on this CPU. 3671 */ 3672 if (caps->cpu_enable) 3673 caps->cpu_enable(caps); 3674 } else { 3675 /* 3676 * Check if the CPU has this capability if it isn't 3677 * safe to have when the system doesn't. 3678 */ 3679 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3680 break; 3681 } 3682 } 3683 3684 if (i < ARM64_NCAPS) { 3685 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3686 smp_processor_id(), caps->capability, 3687 caps->desc, system_has_cap, cpu_has_cap); 3688 3689 if (cpucap_panic_on_conflict(caps)) 3690 cpu_panic_kernel(); 3691 else 3692 cpu_die_early(); 3693 } 3694 } 3695 3696 /* 3697 * Check for CPU features that are used in early boot 3698 * based on the Boot CPU value. 3699 */ 3700 static void check_early_cpu_features(void) 3701 { 3702 verify_cpu_asid_bits(); 3703 3704 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3705 } 3706 3707 static void 3708 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3709 { 3710 3711 for (; caps->matches; caps++) 3712 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3713 pr_crit("CPU%d: missing HWCAP: %s\n", 3714 smp_processor_id(), caps->desc); 3715 cpu_die_early(); 3716 } 3717 } 3718 3719 static void verify_local_elf_hwcaps(void) 3720 { 3721 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3722 3723 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3724 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3725 } 3726 3727 static void verify_sve_features(void) 3728 { 3729 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3730 3731 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3732 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3733 smp_processor_id()); 3734 cpu_die_early(); 3735 } 3736 3737 cpacr_restore(cpacr); 3738 } 3739 3740 static void verify_sme_features(void) 3741 { 3742 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3743 3744 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3745 pr_crit("CPU%d: SME: vector length support mismatch\n", 3746 smp_processor_id()); 3747 cpu_die_early(); 3748 } 3749 3750 cpacr_restore(cpacr); 3751 } 3752 3753 static void verify_hyp_capabilities(void) 3754 { 3755 u64 safe_mmfr1, mmfr0, mmfr1; 3756 int parange, ipa_max; 3757 unsigned int safe_vmid_bits, vmid_bits; 3758 3759 if (!IS_ENABLED(CONFIG_KVM)) 3760 return; 3761 3762 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3763 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3764 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3765 3766 /* Verify VMID bits */ 3767 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3768 vmid_bits = get_vmid_bits(mmfr1); 3769 if (vmid_bits < safe_vmid_bits) { 3770 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3771 cpu_die_early(); 3772 } 3773 3774 /* Verify IPA range */ 3775 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3776 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3777 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3778 if (ipa_max < get_kvm_ipa_limit()) { 3779 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3780 cpu_die_early(); 3781 } 3782 } 3783 3784 static void verify_mpam_capabilities(void) 3785 { 3786 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3787 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3788 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3789 3790 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3791 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3792 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3793 cpu_die_early(); 3794 } 3795 3796 cpu_idr = read_cpuid(MPAMIDR_EL1); 3797 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3798 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3799 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3800 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3801 cpu_die_early(); 3802 } 3803 3804 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3805 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3806 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3807 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3808 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3809 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3810 cpu_die_early(); 3811 } 3812 } 3813 3814 /* 3815 * Run through the enabled system capabilities and enable() it on this CPU. 3816 * The capabilities were decided based on the available CPUs at the boot time. 3817 * Any new CPU should match the system wide status of the capability. If the 3818 * new CPU doesn't have a capability which the system now has enabled, we 3819 * cannot do anything to fix it up and could cause unexpected failures. So 3820 * we park the CPU. 3821 */ 3822 static void verify_local_cpu_capabilities(void) 3823 { 3824 /* 3825 * The capabilities with SCOPE_BOOT_CPU are checked from 3826 * check_early_cpu_features(), as they need to be verified 3827 * on all secondary CPUs. 3828 */ 3829 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3830 verify_local_elf_hwcaps(); 3831 3832 if (system_supports_sve()) 3833 verify_sve_features(); 3834 3835 if (system_supports_sme()) 3836 verify_sme_features(); 3837 3838 if (is_hyp_mode_available()) 3839 verify_hyp_capabilities(); 3840 3841 if (system_supports_mpam()) 3842 verify_mpam_capabilities(); 3843 } 3844 3845 void check_local_cpu_capabilities(void) 3846 { 3847 /* 3848 * All secondary CPUs should conform to the early CPU features 3849 * in use by the kernel based on boot CPU. 3850 */ 3851 check_early_cpu_features(); 3852 3853 /* 3854 * If we haven't finalised the system capabilities, this CPU gets 3855 * a chance to update the errata work arounds and local features. 3856 * Otherwise, this CPU should verify that it has all the system 3857 * advertised capabilities. 3858 */ 3859 if (!system_capabilities_finalized()) 3860 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3861 else 3862 verify_local_cpu_capabilities(); 3863 } 3864 3865 bool this_cpu_has_cap(unsigned int n) 3866 { 3867 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3868 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3869 3870 if (cap) 3871 return cap->matches(cap, SCOPE_LOCAL_CPU); 3872 } 3873 3874 return false; 3875 } 3876 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3877 3878 /* 3879 * This helper function is used in a narrow window when, 3880 * - The system wide safe registers are set with all the SMP CPUs and, 3881 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3882 */ 3883 static bool __maybe_unused __system_matches_cap(unsigned int n) 3884 { 3885 if (n < ARM64_NCAPS) { 3886 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3887 3888 if (cap) 3889 return cap->matches(cap, SCOPE_SYSTEM); 3890 } 3891 return false; 3892 } 3893 3894 void cpu_set_feature(unsigned int num) 3895 { 3896 set_bit(num, elf_hwcap); 3897 } 3898 3899 bool cpu_have_feature(unsigned int num) 3900 { 3901 return test_bit(num, elf_hwcap); 3902 } 3903 EXPORT_SYMBOL_GPL(cpu_have_feature); 3904 3905 unsigned long cpu_get_elf_hwcap(void) 3906 { 3907 /* 3908 * We currently only populate the first 32 bits of AT_HWCAP. Please 3909 * note that for userspace compatibility we guarantee that bits 62 3910 * and 63 will always be returned as 0. 3911 */ 3912 return elf_hwcap[0]; 3913 } 3914 3915 unsigned long cpu_get_elf_hwcap2(void) 3916 { 3917 return elf_hwcap[1]; 3918 } 3919 3920 unsigned long cpu_get_elf_hwcap3(void) 3921 { 3922 return elf_hwcap[2]; 3923 } 3924 3925 static void __init setup_boot_cpu_capabilities(void) 3926 { 3927 kvm_arm_target_impl_cpu_init(); 3928 /* 3929 * The boot CPU's feature register values have been recorded. Detect 3930 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3931 * patch alternatives for the available boot cpucaps. 3932 */ 3933 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3934 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3935 apply_boot_alternatives(); 3936 } 3937 3938 void __init setup_boot_cpu_features(void) 3939 { 3940 /* 3941 * Initialize the indirect array of CPU capabilities pointers before we 3942 * handle the boot CPU. 3943 */ 3944 init_cpucap_indirect_list(); 3945 3946 /* 3947 * Detect broken pseudo-NMI. Must be called _before_ the call to 3948 * setup_boot_cpu_capabilities() since it interacts with 3949 * can_use_gic_priorities(). 3950 */ 3951 detect_system_supports_pseudo_nmi(); 3952 3953 setup_boot_cpu_capabilities(); 3954 } 3955 3956 static void __init setup_system_capabilities(void) 3957 { 3958 /* 3959 * The system-wide safe feature register values have been finalized. 3960 * Detect, enable, and patch alternatives for the available system 3961 * cpucaps. 3962 */ 3963 update_cpu_capabilities(SCOPE_SYSTEM); 3964 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3965 apply_alternatives_all(); 3966 3967 for (int i = 0; i < ARM64_NCAPS; i++) { 3968 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3969 3970 if (!caps || !caps->desc) 3971 continue; 3972 3973 /* 3974 * Log any cpucaps with a cpumask as these aren't logged by 3975 * update_cpu_capabilities(). 3976 */ 3977 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3978 pr_info("detected: %s on CPU%*pbl\n", 3979 caps->desc, cpumask_pr_args(caps->cpus)); 3980 3981 /* Log match-all CPUs capabilities */ 3982 if (cpucap_match_all_early_cpus(caps) && 3983 cpus_have_cap(caps->capability)) 3984 pr_info("detected: %s\n", caps->desc); 3985 } 3986 3987 /* 3988 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3989 */ 3990 if (system_uses_ttbr0_pan()) 3991 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3992 3993 /* 3994 * Report Spectre mitigations status. 3995 */ 3996 spectre_print_disabled_mitigations(); 3997 } 3998 3999 void __init setup_system_features(void) 4000 { 4001 setup_system_capabilities(); 4002 4003 linear_map_maybe_split_to_ptes(); 4004 kpti_install_ng_mappings(); 4005 4006 sve_setup(); 4007 sme_setup(); 4008 4009 /* 4010 * Check for sane CTR_EL0.CWG value. 4011 */ 4012 if (!cache_type_cwg()) 4013 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4014 ARCH_DMA_MINALIGN); 4015 } 4016 4017 void __init setup_user_features(void) 4018 { 4019 user_feature_fixup(); 4020 4021 setup_elf_hwcaps(arm64_elf_hwcaps); 4022 4023 if (system_supports_32bit_el0()) { 4024 setup_elf_hwcaps(compat_elf_hwcaps); 4025 elf_hwcap_fixup(); 4026 } 4027 4028 minsigstksz_setup(); 4029 } 4030 4031 static int enable_mismatched_32bit_el0(unsigned int cpu) 4032 { 4033 /* 4034 * The first 32-bit-capable CPU we detected and so can no longer 4035 * be offlined by userspace. -1 indicates we haven't yet onlined 4036 * a 32-bit-capable CPU. 4037 */ 4038 static int lucky_winner = -1; 4039 4040 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4041 bool cpu_32bit = false; 4042 4043 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4044 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4045 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4046 else 4047 cpu_32bit = true; 4048 } 4049 4050 if (cpu_32bit) { 4051 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4052 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4053 } 4054 4055 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4056 return 0; 4057 4058 if (lucky_winner >= 0) 4059 return 0; 4060 4061 /* 4062 * We've detected a mismatch. We need to keep one of our CPUs with 4063 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4064 * every CPU in the system for a 32-bit task. 4065 */ 4066 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4067 cpu_active_mask); 4068 dev_set_offline_disabled(get_cpu_device(lucky_winner)); 4069 setup_elf_hwcaps(compat_elf_hwcaps); 4070 elf_hwcap_fixup(); 4071 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4072 cpu, lucky_winner); 4073 return 0; 4074 } 4075 4076 static int __init init_32bit_el0_mask(void) 4077 { 4078 if (!allow_mismatched_32bit_el0) 4079 return 0; 4080 4081 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4082 return -ENOMEM; 4083 4084 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4085 "arm64/mismatched_32bit_el0:online", 4086 enable_mismatched_32bit_el0, NULL); 4087 } 4088 subsys_initcall_sync(init_32bit_el0_mask); 4089 4090 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4091 { 4092 cpu_enable_swapper_cnp(); 4093 } 4094 4095 /* 4096 * We emulate only the following system register space. 4097 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4098 * See Table C5-6 System instruction encodings for System register accesses, 4099 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4100 */ 4101 static inline bool __attribute_const__ is_emulated(u32 id) 4102 { 4103 return (sys_reg_Op0(id) == 0x3 && 4104 sys_reg_CRn(id) == 0x0 && 4105 sys_reg_Op1(id) == 0x0 && 4106 (sys_reg_CRm(id) == 0 || 4107 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4108 } 4109 4110 /* 4111 * With CRm == 0, reg should be one of : 4112 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4113 */ 4114 static inline int emulate_id_reg(u32 id, u64 *valp) 4115 { 4116 switch (id) { 4117 case SYS_MIDR_EL1: 4118 *valp = read_cpuid_id(); 4119 break; 4120 case SYS_MPIDR_EL1: 4121 *valp = SYS_MPIDR_SAFE_VAL; 4122 break; 4123 case SYS_REVIDR_EL1: 4124 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4125 *valp = 0; 4126 break; 4127 default: 4128 return -EINVAL; 4129 } 4130 4131 return 0; 4132 } 4133 4134 static int emulate_sys_reg(u32 id, u64 *valp) 4135 { 4136 struct arm64_ftr_reg *regp; 4137 4138 if (!is_emulated(id)) 4139 return -EINVAL; 4140 4141 if (sys_reg_CRm(id) == 0) 4142 return emulate_id_reg(id, valp); 4143 4144 regp = get_arm64_ftr_reg_nowarn(id); 4145 if (regp) 4146 *valp = arm64_ftr_reg_user_value(regp); 4147 else 4148 /* 4149 * The untracked registers are either IMPLEMENTATION DEFINED 4150 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4151 */ 4152 *valp = 0; 4153 return 0; 4154 } 4155 4156 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4157 { 4158 int rc; 4159 u64 val; 4160 4161 rc = emulate_sys_reg(sys_reg, &val); 4162 if (!rc) { 4163 pt_regs_write_reg(regs, rt, val); 4164 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4165 } 4166 return rc; 4167 } 4168 4169 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4170 { 4171 u32 sys_reg, rt; 4172 4173 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4174 return false; 4175 4176 /* 4177 * sys_reg values are defined as used in mrs/msr instruction. 4178 * shift the imm value to get the encoding. 4179 */ 4180 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4181 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4182 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4183 } 4184 4185 enum mitigation_state arm64_get_meltdown_state(void) 4186 { 4187 if (__meltdown_safe) 4188 return SPECTRE_UNAFFECTED; 4189 4190 if (arm64_kernel_unmapped_at_el0()) 4191 return SPECTRE_MITIGATED; 4192 4193 return SPECTRE_VULNERABLE; 4194 } 4195 4196 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4197 char *buf) 4198 { 4199 switch (arm64_get_meltdown_state()) { 4200 case SPECTRE_UNAFFECTED: 4201 return sprintf(buf, "Not affected\n"); 4202 4203 case SPECTRE_MITIGATED: 4204 return sprintf(buf, "Mitigation: PTI\n"); 4205 4206 default: 4207 return sprintf(buf, "Vulnerable\n"); 4208 } 4209 } 4210