1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 unsigned int compat_elf_hwcap3 __read_mostly; 107 #endif 108 109 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 110 EXPORT_SYMBOL(system_cpucaps); 111 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 112 113 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 114 115 bool arm64_use_ng_mappings = false; 116 EXPORT_SYMBOL(arm64_use_ng_mappings); 117 118 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 119 120 /* 121 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 122 * support it? 123 */ 124 static bool __read_mostly allow_mismatched_32bit_el0; 125 126 /* 127 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 128 * seen at least one CPU capable of 32-bit EL0. 129 */ 130 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 131 132 /* 133 * Mask of CPUs supporting 32-bit EL0. 134 * Only valid if arm64_mismatched_32bit_el0 is enabled. 135 */ 136 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 137 138 void dump_cpu_features(void) 139 { 140 /* file-wide pr_fmt adds "CPU features: " prefix */ 141 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 142 } 143 144 #define __ARM64_MAX_POSITIVE(reg, field) \ 145 ((reg##_##field##_SIGNED ? \ 146 BIT(reg##_##field##_WIDTH - 1) : \ 147 BIT(reg##_##field##_WIDTH)) - 1) 148 149 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 150 151 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 152 .sys_reg = SYS_##reg, \ 153 .field_pos = reg##_##field##_SHIFT, \ 154 .field_width = reg##_##field##_WIDTH, \ 155 .sign = reg##_##field##_SIGNED, \ 156 .min_field_value = min_value, \ 157 .max_field_value = max_value, 158 159 /* 160 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 161 * an implicit maximum that depends on the sign-ess of the field. 162 * 163 * An unsigned field will be capped at all ones, while a signed field 164 * will be limited to the positive half only. 165 */ 166 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 167 __ARM64_CPUID_FIELDS(reg, field, \ 168 SYS_FIELD_VALUE(reg, field, min_value), \ 169 __ARM64_MAX_POSITIVE(reg, field)) 170 171 /* 172 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 173 * implicit minimal value to max_value. This should be used when 174 * matching a non-implemented property. 175 */ 176 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 177 __ARM64_CPUID_FIELDS(reg, field, \ 178 __ARM64_MIN_NEGATIVE(reg, field), \ 179 SYS_FIELD_VALUE(reg, field, max_value)) 180 181 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 182 { \ 183 .sign = SIGNED, \ 184 .visible = VISIBLE, \ 185 .strict = STRICT, \ 186 .type = TYPE, \ 187 .shift = SHIFT, \ 188 .width = WIDTH, \ 189 .safe_val = SAFE_VAL, \ 190 } 191 192 /* Define a feature with unsigned values */ 193 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 194 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 195 196 /* Define a feature with a signed value */ 197 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 198 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 199 200 #define ARM64_FTR_END \ 201 { \ 202 .width = 0, \ 203 } 204 205 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 206 207 static bool __system_matches_cap(unsigned int n); 208 209 /* 210 * NOTE: Any changes to the visibility of features should be kept in 211 * sync with the documentation of the CPU feature register ABI. 212 */ 213 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 228 ARM64_FTR_END, 229 }; 230 231 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 251 ARM64_FTR_END, 252 }; 253 254 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 272 ARM64_FTR_END, 273 }; 274 275 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 286 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 287 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 292 ARM64_FTR_END, 293 }; 294 295 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 297 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 303 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 304 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 306 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 307 ARM64_FTR_END, 308 }; 309 310 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 311 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 312 ARM64_FTR_END, 313 }; 314 315 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 336 ARM64_FTR_END, 337 }; 338 339 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 343 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 345 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 376 ARM64_FTR_END, 377 }; 378 379 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 386 ARM64_FTR_END, 387 }; 388 389 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 390 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 393 /* 394 * Page size not being supported at Stage-2 is not fatal. You 395 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 396 * your favourite nesting hypervisor. 397 * 398 * There is a small corner case where the hypervisor explicitly 399 * advertises a given granule size at Stage-2 (value 2) on some 400 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 401 * vCPUs. Although this is not forbidden by the architecture, it 402 * indicates that the hypervisor is being silly (or buggy). 403 * 404 * We make no effort to cope with this and pretend that if these 405 * fields are inconsistent across vCPUs, then it isn't worth 406 * trying to bring KVM up. 407 */ 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 411 /* 412 * We already refuse to boot CPUs that don't support our configured 413 * page size, so we can only detect mismatches for a page size other 414 * than the one we're currently using. Unfortunately, SoCs like this 415 * exist in the wild so, even though we don't like it, we'll have to go 416 * along with it and treat them as non-strict. 417 */ 418 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 421 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 423 /* Linux shouldn't care about secure memory */ 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 427 /* 428 * Differing PARange is fine as long as all peripherals and memory are mapped 429 * within the minimum PARange of all CPUs 430 */ 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 432 ARM64_FTR_END, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 450 ARM64_FTR_END, 451 }; 452 453 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 469 ARM64_FTR_END, 470 }; 471 472 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 473 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 474 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 481 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_ctr[] = { 486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 492 /* 493 * Linux can handle differing I-cache policies. Userspace JITs will 494 * make use of *minLine. 495 * If we have differing I-cache policies, report it as the weakest - VIPT. 496 */ 497 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 498 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static struct arm64_ftr_override __ro_after_init no_override = { }; 503 504 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 505 .name = "SYS_CTR_EL0", 506 .ftr_bits = ftr_ctr, 507 .override = &no_override, 508 }; 509 510 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 511 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 516 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 523 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 528 /* 529 * We can instantiate multiple PMU instances with different levels 530 * of support. 531 */ 532 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 534 ARM64_FTR_END, 535 }; 536 537 static const struct arm64_ftr_bits ftr_mvfr0[] = { 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 546 ARM64_FTR_END, 547 }; 548 549 static const struct arm64_ftr_bits ftr_mvfr1[] = { 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 558 ARM64_FTR_END, 559 }; 560 561 static const struct arm64_ftr_bits ftr_mvfr2[] = { 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_dczid[] = { 568 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 569 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 570 ARM64_FTR_END, 571 }; 572 573 static const struct arm64_ftr_bits ftr_gmid[] = { 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_id_isar0[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 586 ARM64_FTR_END, 587 }; 588 589 static const struct arm64_ftr_bits ftr_id_isar5[] = { 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 607 608 /* 609 * SpecSEI = 1 indicates that the PE might generate an SError on an 610 * external abort on speculative read. It is safe to assume that an 611 * SError might be generated than it will not be. Hence it has been 612 * classified as FTR_HIGHER_SAFE. 613 */ 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 615 ARM64_FTR_END, 616 }; 617 618 static const struct arm64_ftr_bits ftr_id_isar4[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 627 ARM64_FTR_END, 628 }; 629 630 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_isar6[] = { 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 643 ARM64_FTR_END, 644 }; 645 646 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 653 ARM64_FTR_END, 654 }; 655 656 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 665 ARM64_FTR_END, 666 }; 667 668 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 675 /* [31:28] TraceFilt */ 676 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 687 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 688 ARM64_FTR_END, 689 }; 690 691 /* 692 * Common ftr bits for a 32bit register with all hidden, strict 693 * attributes, with 4bit feature fields and a default safe value of 694 * 0. Covers the following 32bit registers: 695 * id_isar[1-3], id_mmfr[1-3] 696 */ 697 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 706 ARM64_FTR_END, 707 }; 708 709 /* Table for a single 32bit feature value */ 710 static const struct arm64_ftr_bits ftr_single32[] = { 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 712 ARM64_FTR_END, 713 }; 714 715 static const struct arm64_ftr_bits ftr_raz[] = { 716 ARM64_FTR_END, 717 }; 718 719 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 720 .sys_id = id, \ 721 .reg = &(struct arm64_ftr_reg){ \ 722 .name = id_str, \ 723 .override = (ovr), \ 724 .ftr_bits = &((table)[0]), \ 725 }} 726 727 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 728 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 729 730 #define ARM64_FTR_REG(id, table) \ 731 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 732 733 struct arm64_ftr_override id_aa64mmfr0_override; 734 struct arm64_ftr_override id_aa64mmfr1_override; 735 struct arm64_ftr_override id_aa64mmfr2_override; 736 struct arm64_ftr_override id_aa64pfr0_override; 737 struct arm64_ftr_override id_aa64pfr1_override; 738 struct arm64_ftr_override id_aa64zfr0_override; 739 struct arm64_ftr_override id_aa64smfr0_override; 740 struct arm64_ftr_override id_aa64isar1_override; 741 struct arm64_ftr_override id_aa64isar2_override; 742 743 struct arm64_ftr_override arm64_sw_feature_override; 744 745 static const struct __ftr_reg_entry { 746 u32 sys_id; 747 struct arm64_ftr_reg *reg; 748 } arm64_ftr_regs[] = { 749 750 /* Op1 = 0, CRn = 0, CRm = 1 */ 751 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 752 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 753 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 754 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 755 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 756 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 757 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 758 759 /* Op1 = 0, CRn = 0, CRm = 2 */ 760 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 761 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 762 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 763 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 764 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 765 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 766 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 767 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 768 769 /* Op1 = 0, CRn = 0, CRm = 3 */ 770 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 771 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 772 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 773 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 774 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 775 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 776 777 /* Op1 = 0, CRn = 0, CRm = 4 */ 778 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 779 &id_aa64pfr0_override), 780 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 781 &id_aa64pfr1_override), 782 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 783 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 784 &id_aa64zfr0_override), 785 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 786 &id_aa64smfr0_override), 787 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 788 789 /* Op1 = 0, CRn = 0, CRm = 5 */ 790 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 791 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 792 793 /* Op1 = 0, CRn = 0, CRm = 6 */ 794 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 795 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 796 &id_aa64isar1_override), 797 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 798 &id_aa64isar2_override), 799 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 800 801 /* Op1 = 0, CRn = 0, CRm = 7 */ 802 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 803 &id_aa64mmfr0_override), 804 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 805 &id_aa64mmfr1_override), 806 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 807 &id_aa64mmfr2_override), 808 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 809 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 810 811 /* Op1 = 1, CRn = 0, CRm = 0 */ 812 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 813 814 /* Op1 = 3, CRn = 0, CRm = 0 */ 815 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 816 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 817 818 /* Op1 = 3, CRn = 14, CRm = 0 */ 819 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 820 }; 821 822 static int search_cmp_ftr_reg(const void *id, const void *regp) 823 { 824 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 825 } 826 827 /* 828 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 829 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 830 * ascending order of sys_id, we use binary search to find a matching 831 * entry. 832 * 833 * returns - Upon success, matching ftr_reg entry for id. 834 * - NULL on failure. It is upto the caller to decide 835 * the impact of a failure. 836 */ 837 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 838 { 839 const struct __ftr_reg_entry *ret; 840 841 ret = bsearch((const void *)(unsigned long)sys_id, 842 arm64_ftr_regs, 843 ARRAY_SIZE(arm64_ftr_regs), 844 sizeof(arm64_ftr_regs[0]), 845 search_cmp_ftr_reg); 846 if (ret) 847 return ret->reg; 848 return NULL; 849 } 850 851 /* 852 * get_arm64_ftr_reg - Looks up a feature register entry using 853 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 854 * 855 * returns - Upon success, matching ftr_reg entry for id. 856 * - NULL on failure but with an WARN_ON(). 857 */ 858 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 859 { 860 struct arm64_ftr_reg *reg; 861 862 reg = get_arm64_ftr_reg_nowarn(sys_id); 863 864 /* 865 * Requesting a non-existent register search is an error. Warn 866 * and let the caller handle it. 867 */ 868 WARN_ON(!reg); 869 return reg; 870 } 871 872 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 873 s64 ftr_val) 874 { 875 u64 mask = arm64_ftr_mask(ftrp); 876 877 reg &= ~mask; 878 reg |= (ftr_val << ftrp->shift) & mask; 879 return reg; 880 } 881 882 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 883 s64 cur) 884 { 885 s64 ret = 0; 886 887 switch (ftrp->type) { 888 case FTR_EXACT: 889 ret = ftrp->safe_val; 890 break; 891 case FTR_LOWER_SAFE: 892 ret = min(new, cur); 893 break; 894 case FTR_HIGHER_OR_ZERO_SAFE: 895 if (!cur || !new) 896 break; 897 fallthrough; 898 case FTR_HIGHER_SAFE: 899 ret = max(new, cur); 900 break; 901 default: 902 BUG(); 903 } 904 905 return ret; 906 } 907 908 static void __init sort_ftr_regs(void) 909 { 910 unsigned int i; 911 912 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 913 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 914 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 915 unsigned int j = 0; 916 917 /* 918 * Features here must be sorted in descending order with respect 919 * to their shift values and should not overlap with each other. 920 */ 921 for (; ftr_bits->width != 0; ftr_bits++, j++) { 922 unsigned int width = ftr_reg->ftr_bits[j].width; 923 unsigned int shift = ftr_reg->ftr_bits[j].shift; 924 unsigned int prev_shift; 925 926 WARN((shift + width) > 64, 927 "%s has invalid feature at shift %d\n", 928 ftr_reg->name, shift); 929 930 /* 931 * Skip the first feature. There is nothing to 932 * compare against for now. 933 */ 934 if (j == 0) 935 continue; 936 937 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 938 WARN((shift + width) > prev_shift, 939 "%s has feature overlap at shift %d\n", 940 ftr_reg->name, shift); 941 } 942 943 /* 944 * Skip the first register. There is nothing to 945 * compare against for now. 946 */ 947 if (i == 0) 948 continue; 949 /* 950 * Registers here must be sorted in ascending order with respect 951 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 952 * to work correctly. 953 */ 954 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 955 } 956 } 957 958 /* 959 * Initialise the CPU feature register from Boot CPU values. 960 * Also initiliases the strict_mask for the register. 961 * Any bits that are not covered by an arm64_ftr_bits entry are considered 962 * RES0 for the system-wide value, and must strictly match. 963 */ 964 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 965 { 966 u64 val = 0; 967 u64 strict_mask = ~0x0ULL; 968 u64 user_mask = 0; 969 u64 valid_mask = 0; 970 971 const struct arm64_ftr_bits *ftrp; 972 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 973 974 if (!reg) 975 return; 976 977 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 978 u64 ftr_mask = arm64_ftr_mask(ftrp); 979 s64 ftr_new = arm64_ftr_value(ftrp, new); 980 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 981 982 if ((ftr_mask & reg->override->mask) == ftr_mask) { 983 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 984 char *str = NULL; 985 986 if (ftr_ovr != tmp) { 987 /* Unsafe, remove the override */ 988 reg->override->mask &= ~ftr_mask; 989 reg->override->val &= ~ftr_mask; 990 tmp = ftr_ovr; 991 str = "ignoring override"; 992 } else if (ftr_new != tmp) { 993 /* Override was valid */ 994 ftr_new = tmp; 995 str = "forced"; 996 } else if (ftr_ovr == tmp) { 997 /* Override was the safe value */ 998 str = "already set"; 999 } 1000 1001 if (str) 1002 pr_warn("%s[%d:%d]: %s to %llx\n", 1003 reg->name, 1004 ftrp->shift + ftrp->width - 1, 1005 ftrp->shift, str, 1006 tmp & (BIT(ftrp->width) - 1)); 1007 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1008 reg->override->val &= ~ftr_mask; 1009 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1010 reg->name, 1011 ftrp->shift + ftrp->width - 1, 1012 ftrp->shift); 1013 } 1014 1015 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1016 1017 valid_mask |= ftr_mask; 1018 if (!ftrp->strict) 1019 strict_mask &= ~ftr_mask; 1020 if (ftrp->visible) 1021 user_mask |= ftr_mask; 1022 else 1023 reg->user_val = arm64_ftr_set_value(ftrp, 1024 reg->user_val, 1025 ftrp->safe_val); 1026 } 1027 1028 val &= valid_mask; 1029 1030 reg->sys_val = val; 1031 reg->strict_mask = strict_mask; 1032 reg->user_mask = user_mask; 1033 } 1034 1035 extern const struct arm64_cpu_capabilities arm64_errata[]; 1036 static const struct arm64_cpu_capabilities arm64_features[]; 1037 1038 static void __init 1039 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1040 { 1041 for (; caps->matches; caps++) { 1042 if (WARN(caps->capability >= ARM64_NCAPS, 1043 "Invalid capability %d\n", caps->capability)) 1044 continue; 1045 if (WARN(cpucap_ptrs[caps->capability], 1046 "Duplicate entry for capability %d\n", 1047 caps->capability)) 1048 continue; 1049 cpucap_ptrs[caps->capability] = caps; 1050 } 1051 } 1052 1053 static void __init init_cpucap_indirect_list(void) 1054 { 1055 init_cpucap_indirect_list_from_array(arm64_features); 1056 init_cpucap_indirect_list_from_array(arm64_errata); 1057 } 1058 1059 static void __init setup_boot_cpu_capabilities(void); 1060 1061 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1062 { 1063 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1064 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1065 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1066 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1067 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1068 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1069 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1070 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1071 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1072 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1073 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1074 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1075 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1076 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1077 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1078 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1079 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1080 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1081 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1082 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1083 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1084 } 1085 1086 #ifdef CONFIG_ARM64_PSEUDO_NMI 1087 static bool enable_pseudo_nmi; 1088 1089 static int __init early_enable_pseudo_nmi(char *p) 1090 { 1091 return kstrtobool(p, &enable_pseudo_nmi); 1092 } 1093 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1094 1095 static __init void detect_system_supports_pseudo_nmi(void) 1096 { 1097 struct device_node *np; 1098 1099 if (!enable_pseudo_nmi) 1100 return; 1101 1102 /* 1103 * Detect broken MediaTek firmware that doesn't properly save and 1104 * restore GIC priorities. 1105 */ 1106 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1107 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1108 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1109 enable_pseudo_nmi = false; 1110 } 1111 of_node_put(np); 1112 } 1113 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1114 static inline void detect_system_supports_pseudo_nmi(void) { } 1115 #endif 1116 1117 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1118 { 1119 /* Before we start using the tables, make sure it is sorted */ 1120 sort_ftr_regs(); 1121 1122 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1123 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1124 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1125 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1126 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1127 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1128 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1129 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1130 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1131 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1132 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1133 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1134 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1135 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1136 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1137 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1138 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1139 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1140 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1141 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1142 1143 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1144 init_32bit_cpu_features(&info->aarch32); 1145 1146 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1147 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1148 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1149 1150 vec_init_vq_map(ARM64_VEC_SVE); 1151 1152 cpacr_restore(cpacr); 1153 } 1154 1155 if (IS_ENABLED(CONFIG_ARM64_SME) && 1156 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1157 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1158 1159 /* 1160 * We mask out SMPS since even if the hardware 1161 * supports priorities the kernel does not at present 1162 * and we block access to them. 1163 */ 1164 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1165 vec_init_vq_map(ARM64_VEC_SME); 1166 1167 cpacr_restore(cpacr); 1168 } 1169 1170 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1171 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1172 } 1173 1174 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1175 { 1176 const struct arm64_ftr_bits *ftrp; 1177 1178 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1179 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1180 s64 ftr_new = arm64_ftr_value(ftrp, new); 1181 1182 if (ftr_cur == ftr_new) 1183 continue; 1184 /* Find a safe value */ 1185 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1186 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1187 } 1188 1189 } 1190 1191 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1192 { 1193 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1194 1195 if (!regp) 1196 return 0; 1197 1198 update_cpu_ftr_reg(regp, val); 1199 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1200 return 0; 1201 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1202 regp->name, boot, cpu, val); 1203 return 1; 1204 } 1205 1206 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1207 { 1208 const struct arm64_ftr_bits *ftrp; 1209 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1210 1211 if (!regp) 1212 return; 1213 1214 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1215 if (ftrp->shift == field) { 1216 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1217 break; 1218 } 1219 } 1220 1221 /* Bogus field? */ 1222 WARN_ON(!ftrp->width); 1223 } 1224 1225 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1226 struct cpuinfo_arm64 *boot) 1227 { 1228 static bool boot_cpu_32bit_regs_overridden = false; 1229 1230 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1231 return; 1232 1233 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1234 return; 1235 1236 boot->aarch32 = info->aarch32; 1237 init_32bit_cpu_features(&boot->aarch32); 1238 boot_cpu_32bit_regs_overridden = true; 1239 } 1240 1241 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1242 struct cpuinfo_32bit *boot) 1243 { 1244 int taint = 0; 1245 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1246 1247 /* 1248 * If we don't have AArch32 at EL1, then relax the strictness of 1249 * EL1-dependent register fields to avoid spurious sanity check fails. 1250 */ 1251 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1252 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1253 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1254 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1255 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1256 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1257 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1258 } 1259 1260 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1261 info->reg_id_dfr0, boot->reg_id_dfr0); 1262 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1263 info->reg_id_dfr1, boot->reg_id_dfr1); 1264 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1265 info->reg_id_isar0, boot->reg_id_isar0); 1266 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1267 info->reg_id_isar1, boot->reg_id_isar1); 1268 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1269 info->reg_id_isar2, boot->reg_id_isar2); 1270 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1271 info->reg_id_isar3, boot->reg_id_isar3); 1272 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1273 info->reg_id_isar4, boot->reg_id_isar4); 1274 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1275 info->reg_id_isar5, boot->reg_id_isar5); 1276 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1277 info->reg_id_isar6, boot->reg_id_isar6); 1278 1279 /* 1280 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1281 * ACTLR formats could differ across CPUs and therefore would have to 1282 * be trapped for virtualization anyway. 1283 */ 1284 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1285 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1286 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1287 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1288 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1289 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1290 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1291 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1292 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1293 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1294 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1295 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1296 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1297 info->reg_id_pfr0, boot->reg_id_pfr0); 1298 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1299 info->reg_id_pfr1, boot->reg_id_pfr1); 1300 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1301 info->reg_id_pfr2, boot->reg_id_pfr2); 1302 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1303 info->reg_mvfr0, boot->reg_mvfr0); 1304 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1305 info->reg_mvfr1, boot->reg_mvfr1); 1306 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1307 info->reg_mvfr2, boot->reg_mvfr2); 1308 1309 return taint; 1310 } 1311 1312 /* 1313 * Update system wide CPU feature registers with the values from a 1314 * non-boot CPU. Also performs SANITY checks to make sure that there 1315 * aren't any insane variations from that of the boot CPU. 1316 */ 1317 void update_cpu_features(int cpu, 1318 struct cpuinfo_arm64 *info, 1319 struct cpuinfo_arm64 *boot) 1320 { 1321 int taint = 0; 1322 1323 /* 1324 * The kernel can handle differing I-cache policies, but otherwise 1325 * caches should look identical. Userspace JITs will make use of 1326 * *minLine. 1327 */ 1328 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1329 info->reg_ctr, boot->reg_ctr); 1330 1331 /* 1332 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1333 * could result in too much or too little memory being zeroed if a 1334 * process is preempted and migrated between CPUs. 1335 */ 1336 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1337 info->reg_dczid, boot->reg_dczid); 1338 1339 /* If different, timekeeping will be broken (especially with KVM) */ 1340 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1341 info->reg_cntfrq, boot->reg_cntfrq); 1342 1343 /* 1344 * The kernel uses self-hosted debug features and expects CPUs to 1345 * support identical debug features. We presently need CTX_CMPs, WRPs, 1346 * and BRPs to be identical. 1347 * ID_AA64DFR1 is currently RES0. 1348 */ 1349 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1350 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1351 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1352 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1353 /* 1354 * Even in big.LITTLE, processors should be identical instruction-set 1355 * wise. 1356 */ 1357 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1358 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1359 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1360 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1361 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1362 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1363 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1364 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1365 1366 /* 1367 * Differing PARange support is fine as long as all peripherals and 1368 * memory are mapped within the minimum PARange of all CPUs. 1369 * Linux should not care about secure memory. 1370 */ 1371 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1372 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1373 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1374 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1375 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1376 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1377 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1378 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1379 1380 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1381 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1382 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1383 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1384 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1385 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1386 1387 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1388 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1389 1390 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1391 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1392 1393 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1394 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1395 1396 /* Probe vector lengths */ 1397 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1398 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1399 if (!system_capabilities_finalized()) { 1400 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1401 1402 vec_update_vq_map(ARM64_VEC_SVE); 1403 1404 cpacr_restore(cpacr); 1405 } 1406 } 1407 1408 if (IS_ENABLED(CONFIG_ARM64_SME) && 1409 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1410 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1411 1412 /* 1413 * We mask out SMPS since even if the hardware 1414 * supports priorities the kernel does not at present 1415 * and we block access to them. 1416 */ 1417 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1418 1419 /* Probe vector lengths */ 1420 if (!system_capabilities_finalized()) 1421 vec_update_vq_map(ARM64_VEC_SME); 1422 1423 cpacr_restore(cpacr); 1424 } 1425 1426 /* 1427 * The kernel uses the LDGM/STGM instructions and the number of tags 1428 * they read/write depends on the GMID_EL1.BS field. Check that the 1429 * value is the same on all CPUs. 1430 */ 1431 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1432 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1433 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1434 info->reg_gmid, boot->reg_gmid); 1435 } 1436 1437 /* 1438 * If we don't have AArch32 at all then skip the checks entirely 1439 * as the register values may be UNKNOWN and we're not going to be 1440 * using them for anything. 1441 * 1442 * This relies on a sanitised view of the AArch64 ID registers 1443 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1444 */ 1445 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1446 lazy_init_32bit_cpu_features(info, boot); 1447 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1448 &boot->aarch32); 1449 } 1450 1451 /* 1452 * Mismatched CPU features are a recipe for disaster. Don't even 1453 * pretend to support them. 1454 */ 1455 if (taint) { 1456 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1457 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1458 } 1459 } 1460 1461 u64 read_sanitised_ftr_reg(u32 id) 1462 { 1463 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1464 1465 if (!regp) 1466 return 0; 1467 return regp->sys_val; 1468 } 1469 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1470 1471 #define read_sysreg_case(r) \ 1472 case r: val = read_sysreg_s(r); break; 1473 1474 /* 1475 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1476 * Read the system register on the current CPU 1477 */ 1478 u64 __read_sysreg_by_encoding(u32 sys_id) 1479 { 1480 struct arm64_ftr_reg *regp; 1481 u64 val; 1482 1483 switch (sys_id) { 1484 read_sysreg_case(SYS_ID_PFR0_EL1); 1485 read_sysreg_case(SYS_ID_PFR1_EL1); 1486 read_sysreg_case(SYS_ID_PFR2_EL1); 1487 read_sysreg_case(SYS_ID_DFR0_EL1); 1488 read_sysreg_case(SYS_ID_DFR1_EL1); 1489 read_sysreg_case(SYS_ID_MMFR0_EL1); 1490 read_sysreg_case(SYS_ID_MMFR1_EL1); 1491 read_sysreg_case(SYS_ID_MMFR2_EL1); 1492 read_sysreg_case(SYS_ID_MMFR3_EL1); 1493 read_sysreg_case(SYS_ID_MMFR4_EL1); 1494 read_sysreg_case(SYS_ID_MMFR5_EL1); 1495 read_sysreg_case(SYS_ID_ISAR0_EL1); 1496 read_sysreg_case(SYS_ID_ISAR1_EL1); 1497 read_sysreg_case(SYS_ID_ISAR2_EL1); 1498 read_sysreg_case(SYS_ID_ISAR3_EL1); 1499 read_sysreg_case(SYS_ID_ISAR4_EL1); 1500 read_sysreg_case(SYS_ID_ISAR5_EL1); 1501 read_sysreg_case(SYS_ID_ISAR6_EL1); 1502 read_sysreg_case(SYS_MVFR0_EL1); 1503 read_sysreg_case(SYS_MVFR1_EL1); 1504 read_sysreg_case(SYS_MVFR2_EL1); 1505 1506 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1507 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1508 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1509 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1510 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1511 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1512 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1513 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1514 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1515 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1516 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1517 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1518 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1519 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1520 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1521 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1522 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1523 1524 read_sysreg_case(SYS_CNTFRQ_EL0); 1525 read_sysreg_case(SYS_CTR_EL0); 1526 read_sysreg_case(SYS_DCZID_EL0); 1527 1528 default: 1529 BUG(); 1530 return 0; 1531 } 1532 1533 regp = get_arm64_ftr_reg(sys_id); 1534 if (regp) { 1535 val &= ~regp->override->mask; 1536 val |= (regp->override->val & regp->override->mask); 1537 } 1538 1539 return val; 1540 } 1541 1542 #include <linux/irqchip/arm-gic-v3.h> 1543 1544 static bool 1545 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1546 { 1547 return true; 1548 } 1549 1550 static bool 1551 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1552 { 1553 int val, min, max; 1554 u64 tmp; 1555 1556 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1557 entry->field_width, 1558 entry->sign); 1559 1560 tmp = entry->min_field_value; 1561 tmp <<= entry->field_pos; 1562 1563 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1564 entry->field_width, 1565 entry->sign); 1566 1567 tmp = entry->max_field_value; 1568 tmp <<= entry->field_pos; 1569 1570 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1571 entry->field_width, 1572 entry->sign); 1573 1574 return val >= min && val <= max; 1575 } 1576 1577 static u64 1578 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1579 { 1580 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1581 if (scope == SCOPE_SYSTEM) 1582 return read_sanitised_ftr_reg(entry->sys_reg); 1583 else 1584 return __read_sysreg_by_encoding(entry->sys_reg); 1585 } 1586 1587 static bool 1588 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1589 { 1590 int mask; 1591 struct arm64_ftr_reg *regp; 1592 u64 val = read_scoped_sysreg(entry, scope); 1593 1594 regp = get_arm64_ftr_reg(entry->sys_reg); 1595 if (!regp) 1596 return false; 1597 1598 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1599 entry->field_pos, 1600 entry->field_width); 1601 if (!mask) 1602 return false; 1603 1604 return feature_matches(val, entry); 1605 } 1606 1607 static bool 1608 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1609 { 1610 u64 val = read_scoped_sysreg(entry, scope); 1611 return feature_matches(val, entry); 1612 } 1613 1614 const struct cpumask *system_32bit_el0_cpumask(void) 1615 { 1616 if (!system_supports_32bit_el0()) 1617 return cpu_none_mask; 1618 1619 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1620 return cpu_32bit_el0_mask; 1621 1622 return cpu_possible_mask; 1623 } 1624 1625 static int __init parse_32bit_el0_param(char *str) 1626 { 1627 allow_mismatched_32bit_el0 = true; 1628 return 0; 1629 } 1630 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1631 1632 static ssize_t aarch32_el0_show(struct device *dev, 1633 struct device_attribute *attr, char *buf) 1634 { 1635 const struct cpumask *mask = system_32bit_el0_cpumask(); 1636 1637 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1638 } 1639 static const DEVICE_ATTR_RO(aarch32_el0); 1640 1641 static int __init aarch32_el0_sysfs_init(void) 1642 { 1643 struct device *dev_root; 1644 int ret = 0; 1645 1646 if (!allow_mismatched_32bit_el0) 1647 return 0; 1648 1649 dev_root = bus_get_dev_root(&cpu_subsys); 1650 if (dev_root) { 1651 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1652 put_device(dev_root); 1653 } 1654 return ret; 1655 } 1656 device_initcall(aarch32_el0_sysfs_init); 1657 1658 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1659 { 1660 if (!has_cpuid_feature(entry, scope)) 1661 return allow_mismatched_32bit_el0; 1662 1663 if (scope == SCOPE_SYSTEM) 1664 pr_info("detected: 32-bit EL0 Support\n"); 1665 1666 return true; 1667 } 1668 1669 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1670 { 1671 bool has_sre; 1672 1673 if (!has_cpuid_feature(entry, scope)) 1674 return false; 1675 1676 has_sre = gic_enable_sre(); 1677 if (!has_sre) 1678 pr_warn_once("%s present but disabled by higher exception level\n", 1679 entry->desc); 1680 1681 return has_sre; 1682 } 1683 1684 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1685 int scope) 1686 { 1687 u64 ctr; 1688 1689 if (scope == SCOPE_SYSTEM) 1690 ctr = arm64_ftr_reg_ctrel0.sys_val; 1691 else 1692 ctr = read_cpuid_effective_cachetype(); 1693 1694 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1695 } 1696 1697 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1698 { 1699 /* 1700 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1701 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1702 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1703 * value. 1704 */ 1705 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1706 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1707 } 1708 1709 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1710 int scope) 1711 { 1712 u64 ctr; 1713 1714 if (scope == SCOPE_SYSTEM) 1715 ctr = arm64_ftr_reg_ctrel0.sys_val; 1716 else 1717 ctr = read_cpuid_cachetype(); 1718 1719 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1720 } 1721 1722 static bool __maybe_unused 1723 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1724 { 1725 /* 1726 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1727 * may share TLB entries with a CPU stuck in the crashed 1728 * kernel. 1729 */ 1730 if (is_kdump_kernel()) 1731 return false; 1732 1733 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1734 return false; 1735 1736 return has_cpuid_feature(entry, scope); 1737 } 1738 1739 static bool __meltdown_safe = true; 1740 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1741 1742 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1743 int scope) 1744 { 1745 /* List of CPUs that are not vulnerable and don't need KPTI */ 1746 static const struct midr_range kpti_safe_list[] = { 1747 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1748 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1749 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1750 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1751 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1752 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1753 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1754 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1755 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1756 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1757 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1758 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1759 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1760 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1761 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1762 { /* sentinel */ } 1763 }; 1764 char const *str = "kpti command line option"; 1765 bool meltdown_safe; 1766 1767 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1768 1769 /* Defer to CPU feature registers */ 1770 if (has_cpuid_feature(entry, scope)) 1771 meltdown_safe = true; 1772 1773 if (!meltdown_safe) 1774 __meltdown_safe = false; 1775 1776 /* 1777 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1778 * ThunderX leads to apparent I-cache corruption of kernel text, which 1779 * ends as well as you might imagine. Don't even try. We cannot rely 1780 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1781 * because cpucap detection order may change. However, since we know 1782 * affected CPUs are always in a homogeneous configuration, it is 1783 * safe to rely on this_cpu_has_cap() here. 1784 */ 1785 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1786 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1787 __kpti_forced = -1; 1788 } 1789 1790 /* Useful for KASLR robustness */ 1791 if (kaslr_enabled() && kaslr_requires_kpti()) { 1792 if (!__kpti_forced) { 1793 str = "KASLR"; 1794 __kpti_forced = 1; 1795 } 1796 } 1797 1798 if (cpu_mitigations_off() && !__kpti_forced) { 1799 str = "mitigations=off"; 1800 __kpti_forced = -1; 1801 } 1802 1803 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1804 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1805 return false; 1806 } 1807 1808 /* Forced? */ 1809 if (__kpti_forced) { 1810 pr_info_once("kernel page table isolation forced %s by %s\n", 1811 __kpti_forced > 0 ? "ON" : "OFF", str); 1812 return __kpti_forced > 0; 1813 } 1814 1815 return !meltdown_safe; 1816 } 1817 1818 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1819 { 1820 /* 1821 * Although the Apple M2 family appears to support NV1, the 1822 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1823 * that it doesn't support NV1 at all. 1824 */ 1825 static const struct midr_range nv1_ni_list[] = { 1826 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1827 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1828 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1829 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1830 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1831 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1832 {} 1833 }; 1834 1835 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1836 !(has_cpuid_feature(entry, scope) || 1837 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1838 } 1839 1840 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1841 static bool has_lpa2_at_stage1(u64 mmfr0) 1842 { 1843 unsigned int tgran; 1844 1845 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1846 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1847 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1848 } 1849 1850 static bool has_lpa2_at_stage2(u64 mmfr0) 1851 { 1852 unsigned int tgran; 1853 1854 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1855 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1856 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1857 } 1858 1859 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1860 { 1861 u64 mmfr0; 1862 1863 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1864 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1865 } 1866 #else 1867 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1868 { 1869 return false; 1870 } 1871 #endif 1872 1873 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1874 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1875 1876 extern 1877 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1878 phys_addr_t size, pgprot_t prot, 1879 phys_addr_t (*pgtable_alloc)(int), int flags); 1880 1881 static phys_addr_t __initdata kpti_ng_temp_alloc; 1882 1883 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1884 { 1885 kpti_ng_temp_alloc -= PAGE_SIZE; 1886 return kpti_ng_temp_alloc; 1887 } 1888 1889 static int __init __kpti_install_ng_mappings(void *__unused) 1890 { 1891 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1892 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1893 kpti_remap_fn *remap_fn; 1894 1895 int cpu = smp_processor_id(); 1896 int levels = CONFIG_PGTABLE_LEVELS; 1897 int order = order_base_2(levels); 1898 u64 kpti_ng_temp_pgd_pa = 0; 1899 pgd_t *kpti_ng_temp_pgd; 1900 u64 alloc = 0; 1901 1902 if (levels == 5 && !pgtable_l5_enabled()) 1903 levels = 4; 1904 else if (levels == 4 && !pgtable_l4_enabled()) 1905 levels = 3; 1906 1907 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1908 1909 if (!cpu) { 1910 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1911 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1912 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1913 1914 // 1915 // Create a minimal page table hierarchy that permits us to map 1916 // the swapper page tables temporarily as we traverse them. 1917 // 1918 // The physical pages are laid out as follows: 1919 // 1920 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1921 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1922 // +--------+-\-------+-\------ +-\------ +-///--------+ 1923 // ^ 1924 // The first page is mapped into this hierarchy at a PMD_SHIFT 1925 // aligned virtual address, so that we can manipulate the PTE 1926 // level entries while the mapping is active. The first entry 1927 // covers the PTE[] page itself, the remaining entries are free 1928 // to be used as a ad-hoc fixmap. 1929 // 1930 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1931 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1932 kpti_ng_pgd_alloc, 0); 1933 } 1934 1935 cpu_install_idmap(); 1936 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1937 cpu_uninstall_idmap(); 1938 1939 if (!cpu) { 1940 free_pages(alloc, order); 1941 arm64_use_ng_mappings = true; 1942 } 1943 1944 return 0; 1945 } 1946 1947 static void __init kpti_install_ng_mappings(void) 1948 { 1949 /* Check whether KPTI is going to be used */ 1950 if (!arm64_kernel_unmapped_at_el0()) 1951 return; 1952 1953 /* 1954 * We don't need to rewrite the page-tables if either we've done 1955 * it already or we have KASLR enabled and therefore have not 1956 * created any global mappings at all. 1957 */ 1958 if (arm64_use_ng_mappings) 1959 return; 1960 1961 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1962 } 1963 1964 #else 1965 static inline void kpti_install_ng_mappings(void) 1966 { 1967 } 1968 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1969 1970 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1971 { 1972 if (__this_cpu_read(this_cpu_vector) == vectors) { 1973 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1974 1975 __this_cpu_write(this_cpu_vector, v); 1976 } 1977 1978 } 1979 1980 static int __init parse_kpti(char *str) 1981 { 1982 bool enabled; 1983 int ret = kstrtobool(str, &enabled); 1984 1985 if (ret) 1986 return ret; 1987 1988 __kpti_forced = enabled ? 1 : -1; 1989 return 0; 1990 } 1991 early_param("kpti", parse_kpti); 1992 1993 #ifdef CONFIG_ARM64_HW_AFDBM 1994 static struct cpumask dbm_cpus __read_mostly; 1995 1996 static inline void __cpu_enable_hw_dbm(void) 1997 { 1998 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1999 2000 write_sysreg(tcr, tcr_el1); 2001 isb(); 2002 local_flush_tlb_all(); 2003 } 2004 2005 static bool cpu_has_broken_dbm(void) 2006 { 2007 /* List of CPUs which have broken DBM support. */ 2008 static const struct midr_range cpus[] = { 2009 #ifdef CONFIG_ARM64_ERRATUM_1024718 2010 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2011 /* Kryo4xx Silver (rdpe => r1p0) */ 2012 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2013 #endif 2014 #ifdef CONFIG_ARM64_ERRATUM_2051678 2015 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2016 #endif 2017 {}, 2018 }; 2019 2020 return is_midr_in_range_list(read_cpuid_id(), cpus); 2021 } 2022 2023 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2024 { 2025 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2026 !cpu_has_broken_dbm(); 2027 } 2028 2029 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2030 { 2031 if (cpu_can_use_dbm(cap)) { 2032 __cpu_enable_hw_dbm(); 2033 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2034 } 2035 } 2036 2037 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2038 int __unused) 2039 { 2040 /* 2041 * DBM is a non-conflicting feature. i.e, the kernel can safely 2042 * run a mix of CPUs with and without the feature. So, we 2043 * unconditionally enable the capability to allow any late CPU 2044 * to use the feature. We only enable the control bits on the 2045 * CPU, if it is supported. 2046 */ 2047 2048 return true; 2049 } 2050 2051 #endif 2052 2053 #ifdef CONFIG_ARM64_AMU_EXTN 2054 2055 /* 2056 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2057 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2058 * information regarding all the events that it supports. When a CPU bit is 2059 * set in the cpumask, the user of this feature can only rely on the presence 2060 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2061 * counters are enabled or access to these counters is enabled by code 2062 * executed at higher exception levels (firmware). 2063 */ 2064 static struct cpumask amu_cpus __read_mostly; 2065 2066 bool cpu_has_amu_feat(int cpu) 2067 { 2068 return cpumask_test_cpu(cpu, &amu_cpus); 2069 } 2070 2071 int get_cpu_with_amu_feat(void) 2072 { 2073 return cpumask_any(&amu_cpus); 2074 } 2075 2076 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2077 { 2078 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2079 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2080 2081 /* 0 reference values signal broken/disabled counters */ 2082 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2083 update_freq_counters_refs(); 2084 } 2085 } 2086 2087 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2088 int __unused) 2089 { 2090 /* 2091 * The AMU extension is a non-conflicting feature: the kernel can 2092 * safely run a mix of CPUs with and without support for the 2093 * activity monitors extension. Therefore, unconditionally enable 2094 * the capability to allow any late CPU to use the feature. 2095 * 2096 * With this feature unconditionally enabled, the cpu_enable 2097 * function will be called for all CPUs that match the criteria, 2098 * including secondary and hotplugged, marking this feature as 2099 * present on that respective CPU. The enable function will also 2100 * print a detection message. 2101 */ 2102 2103 return true; 2104 } 2105 #else 2106 int get_cpu_with_amu_feat(void) 2107 { 2108 return nr_cpu_ids; 2109 } 2110 #endif 2111 2112 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2113 { 2114 return is_kernel_in_hyp_mode(); 2115 } 2116 2117 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2118 { 2119 /* 2120 * Copy register values that aren't redirected by hardware. 2121 * 2122 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2123 * this value to tpidr_el2 before we patch the code. Once we've done 2124 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2125 * do anything here. 2126 */ 2127 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2128 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2129 } 2130 2131 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2132 int scope) 2133 { 2134 if (kvm_get_mode() != KVM_MODE_NV) 2135 return false; 2136 2137 if (!has_cpuid_feature(cap, scope)) { 2138 pr_warn("unavailable: %s\n", cap->desc); 2139 return false; 2140 } 2141 2142 return true; 2143 } 2144 2145 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2146 int __unused) 2147 { 2148 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2149 } 2150 2151 #ifdef CONFIG_ARM64_PAN 2152 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2153 { 2154 /* 2155 * We modify PSTATE. This won't work from irq context as the PSTATE 2156 * is discarded once we return from the exception. 2157 */ 2158 WARN_ON_ONCE(in_interrupt()); 2159 2160 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2161 set_pstate_pan(1); 2162 } 2163 #endif /* CONFIG_ARM64_PAN */ 2164 2165 #ifdef CONFIG_ARM64_RAS_EXTN 2166 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2167 { 2168 /* Firmware may have left a deferred SError in this register. */ 2169 write_sysreg_s(0, SYS_DISR_EL1); 2170 } 2171 #endif /* CONFIG_ARM64_RAS_EXTN */ 2172 2173 #ifdef CONFIG_ARM64_PTR_AUTH 2174 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2175 { 2176 int boot_val, sec_val; 2177 2178 /* We don't expect to be called with SCOPE_SYSTEM */ 2179 WARN_ON(scope == SCOPE_SYSTEM); 2180 /* 2181 * The ptr-auth feature levels are not intercompatible with lower 2182 * levels. Hence we must match ptr-auth feature level of the secondary 2183 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2184 * from the sanitised register whereas direct register read is done for 2185 * the secondary CPUs. 2186 * The sanitised feature state is guaranteed to match that of the 2187 * boot CPU as a mismatched secondary CPU is parked before it gets 2188 * a chance to update the state, with the capability. 2189 */ 2190 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2191 entry->field_pos, entry->sign); 2192 if (scope & SCOPE_BOOT_CPU) 2193 return boot_val >= entry->min_field_value; 2194 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2195 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2196 entry->field_pos, entry->sign); 2197 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2198 } 2199 2200 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2201 int scope) 2202 { 2203 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2204 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2205 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2206 2207 return apa || apa3 || api; 2208 } 2209 2210 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2211 int __unused) 2212 { 2213 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2214 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2215 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2216 2217 return gpa || gpa3 || gpi; 2218 } 2219 #endif /* CONFIG_ARM64_PTR_AUTH */ 2220 2221 #ifdef CONFIG_ARM64_E0PD 2222 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2223 { 2224 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2225 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2226 } 2227 #endif /* CONFIG_ARM64_E0PD */ 2228 2229 #ifdef CONFIG_ARM64_PSEUDO_NMI 2230 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2231 int scope) 2232 { 2233 /* 2234 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2235 * feature, so will be detected earlier. 2236 */ 2237 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2238 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2239 return false; 2240 2241 return enable_pseudo_nmi; 2242 } 2243 2244 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2245 int scope) 2246 { 2247 /* 2248 * If we're not using priority masking then we won't be poking PMR_EL1, 2249 * and there's no need to relax synchronization of writes to it, and 2250 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2251 * that. 2252 * 2253 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2254 * feature, so will be detected earlier. 2255 */ 2256 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2257 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2258 return false; 2259 2260 /* 2261 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2262 * hint for interrupt distribution, a DSB is not necessary when 2263 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2264 * 2265 * Linux itself doesn't use 1:N distribution, so has no need to 2266 * set PMHE. The only reason to have it set is if EL3 requires it 2267 * (and we can't change it). 2268 */ 2269 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2270 } 2271 #endif 2272 2273 #ifdef CONFIG_ARM64_BTI 2274 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2275 { 2276 /* 2277 * Use of X16/X17 for tail-calls and trampolines that jump to 2278 * function entry points using BR is a requirement for 2279 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2280 * So, be strict and forbid other BRs using other registers to 2281 * jump onto a PACIxSP instruction: 2282 */ 2283 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2284 isb(); 2285 } 2286 #endif /* CONFIG_ARM64_BTI */ 2287 2288 #ifdef CONFIG_ARM64_MTE 2289 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2290 { 2291 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2292 2293 mte_cpu_setup(); 2294 2295 /* 2296 * Clear the tags in the zero page. This needs to be done via the 2297 * linear map which has the Tagged attribute. 2298 */ 2299 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2300 mte_clear_page_tags(lm_alias(empty_zero_page)); 2301 set_page_mte_tagged(ZERO_PAGE(0)); 2302 } 2303 2304 kasan_init_hw_tags_cpu(); 2305 } 2306 #endif /* CONFIG_ARM64_MTE */ 2307 2308 static void user_feature_fixup(void) 2309 { 2310 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2311 struct arm64_ftr_reg *regp; 2312 2313 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2314 if (regp) 2315 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2316 } 2317 2318 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2319 struct arm64_ftr_reg *regp; 2320 2321 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2322 if (regp) 2323 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2324 } 2325 } 2326 2327 static void elf_hwcap_fixup(void) 2328 { 2329 #ifdef CONFIG_COMPAT 2330 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2331 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2332 #endif /* CONFIG_COMPAT */ 2333 } 2334 2335 #ifdef CONFIG_KVM 2336 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2337 { 2338 return kvm_get_mode() == KVM_MODE_PROTECTED; 2339 } 2340 #endif /* CONFIG_KVM */ 2341 2342 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2343 { 2344 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2345 } 2346 2347 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2348 { 2349 set_pstate_dit(1); 2350 } 2351 2352 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2353 { 2354 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2355 } 2356 2357 #ifdef CONFIG_ARM64_POE 2358 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2359 { 2360 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); 2361 sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); 2362 } 2363 #endif 2364 2365 #ifdef CONFIG_ARM64_GCS 2366 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2367 { 2368 /* GCSPR_EL0 is always readable */ 2369 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2370 } 2371 #endif 2372 2373 /* Internal helper functions to match cpu capability type */ 2374 static bool 2375 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2376 { 2377 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2378 } 2379 2380 static bool 2381 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2382 { 2383 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2384 } 2385 2386 static bool 2387 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2388 { 2389 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2390 } 2391 2392 static const struct arm64_cpu_capabilities arm64_features[] = { 2393 { 2394 .capability = ARM64_ALWAYS_BOOT, 2395 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2396 .matches = has_always, 2397 }, 2398 { 2399 .capability = ARM64_ALWAYS_SYSTEM, 2400 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2401 .matches = has_always, 2402 }, 2403 { 2404 .desc = "GIC system register CPU interface", 2405 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2406 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2407 .matches = has_useable_gicv3_cpuif, 2408 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2409 }, 2410 { 2411 .desc = "Enhanced Counter Virtualization", 2412 .capability = ARM64_HAS_ECV, 2413 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2414 .matches = has_cpuid_feature, 2415 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2416 }, 2417 { 2418 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2419 .capability = ARM64_HAS_ECV_CNTPOFF, 2420 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2421 .matches = has_cpuid_feature, 2422 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2423 }, 2424 #ifdef CONFIG_ARM64_PAN 2425 { 2426 .desc = "Privileged Access Never", 2427 .capability = ARM64_HAS_PAN, 2428 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2429 .matches = has_cpuid_feature, 2430 .cpu_enable = cpu_enable_pan, 2431 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2432 }, 2433 #endif /* CONFIG_ARM64_PAN */ 2434 #ifdef CONFIG_ARM64_EPAN 2435 { 2436 .desc = "Enhanced Privileged Access Never", 2437 .capability = ARM64_HAS_EPAN, 2438 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2439 .matches = has_cpuid_feature, 2440 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2441 }, 2442 #endif /* CONFIG_ARM64_EPAN */ 2443 #ifdef CONFIG_ARM64_LSE_ATOMICS 2444 { 2445 .desc = "LSE atomic instructions", 2446 .capability = ARM64_HAS_LSE_ATOMICS, 2447 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2448 .matches = has_cpuid_feature, 2449 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2450 }, 2451 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2452 { 2453 .desc = "Virtualization Host Extensions", 2454 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2455 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2456 .matches = runs_at_el2, 2457 .cpu_enable = cpu_copy_el2regs, 2458 }, 2459 { 2460 .desc = "Nested Virtualization Support", 2461 .capability = ARM64_HAS_NESTED_VIRT, 2462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2463 .matches = has_nested_virt_support, 2464 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2465 }, 2466 { 2467 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2468 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2469 .matches = has_32bit_el0, 2470 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2471 }, 2472 #ifdef CONFIG_KVM 2473 { 2474 .desc = "32-bit EL1 Support", 2475 .capability = ARM64_HAS_32BIT_EL1, 2476 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2477 .matches = has_cpuid_feature, 2478 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2479 }, 2480 { 2481 .desc = "Protected KVM", 2482 .capability = ARM64_KVM_PROTECTED_MODE, 2483 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2484 .matches = is_kvm_protected_mode, 2485 }, 2486 { 2487 .desc = "HCRX_EL2 register", 2488 .capability = ARM64_HAS_HCX, 2489 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2490 .matches = has_cpuid_feature, 2491 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2492 }, 2493 #endif 2494 { 2495 .desc = "Kernel page table isolation (KPTI)", 2496 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2497 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2498 .cpu_enable = cpu_enable_kpti, 2499 .matches = unmap_kernel_at_el0, 2500 /* 2501 * The ID feature fields below are used to indicate that 2502 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2503 * more details. 2504 */ 2505 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2506 }, 2507 { 2508 .capability = ARM64_HAS_FPSIMD, 2509 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2510 .matches = has_cpuid_feature, 2511 .cpu_enable = cpu_enable_fpsimd, 2512 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2513 }, 2514 #ifdef CONFIG_ARM64_PMEM 2515 { 2516 .desc = "Data cache clean to Point of Persistence", 2517 .capability = ARM64_HAS_DCPOP, 2518 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2519 .matches = has_cpuid_feature, 2520 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2521 }, 2522 { 2523 .desc = "Data cache clean to Point of Deep Persistence", 2524 .capability = ARM64_HAS_DCPODP, 2525 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2526 .matches = has_cpuid_feature, 2527 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2528 }, 2529 #endif 2530 #ifdef CONFIG_ARM64_SVE 2531 { 2532 .desc = "Scalable Vector Extension", 2533 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2534 .capability = ARM64_SVE, 2535 .cpu_enable = cpu_enable_sve, 2536 .matches = has_cpuid_feature, 2537 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2538 }, 2539 #endif /* CONFIG_ARM64_SVE */ 2540 #ifdef CONFIG_ARM64_RAS_EXTN 2541 { 2542 .desc = "RAS Extension Support", 2543 .capability = ARM64_HAS_RAS_EXTN, 2544 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2545 .matches = has_cpuid_feature, 2546 .cpu_enable = cpu_clear_disr, 2547 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2548 }, 2549 #endif /* CONFIG_ARM64_RAS_EXTN */ 2550 #ifdef CONFIG_ARM64_AMU_EXTN 2551 { 2552 .desc = "Activity Monitors Unit (AMU)", 2553 .capability = ARM64_HAS_AMU_EXTN, 2554 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2555 .matches = has_amu, 2556 .cpu_enable = cpu_amu_enable, 2557 .cpus = &amu_cpus, 2558 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2559 }, 2560 #endif /* CONFIG_ARM64_AMU_EXTN */ 2561 { 2562 .desc = "Data cache clean to the PoU not required for I/D coherence", 2563 .capability = ARM64_HAS_CACHE_IDC, 2564 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2565 .matches = has_cache_idc, 2566 .cpu_enable = cpu_emulate_effective_ctr, 2567 }, 2568 { 2569 .desc = "Instruction cache invalidation not required for I/D coherence", 2570 .capability = ARM64_HAS_CACHE_DIC, 2571 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2572 .matches = has_cache_dic, 2573 }, 2574 { 2575 .desc = "Stage-2 Force Write-Back", 2576 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2577 .capability = ARM64_HAS_STAGE2_FWB, 2578 .matches = has_cpuid_feature, 2579 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2580 }, 2581 { 2582 .desc = "ARMv8.4 Translation Table Level", 2583 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2584 .capability = ARM64_HAS_ARMv8_4_TTL, 2585 .matches = has_cpuid_feature, 2586 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2587 }, 2588 { 2589 .desc = "TLB range maintenance instructions", 2590 .capability = ARM64_HAS_TLB_RANGE, 2591 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2592 .matches = has_cpuid_feature, 2593 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2594 }, 2595 #ifdef CONFIG_ARM64_HW_AFDBM 2596 { 2597 .desc = "Hardware dirty bit management", 2598 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2599 .capability = ARM64_HW_DBM, 2600 .matches = has_hw_dbm, 2601 .cpu_enable = cpu_enable_hw_dbm, 2602 .cpus = &dbm_cpus, 2603 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2604 }, 2605 #endif 2606 #ifdef CONFIG_ARM64_HAFT 2607 { 2608 .desc = "Hardware managed Access Flag for Table Descriptors", 2609 /* 2610 * Contrary to the page/block access flag, the table access flag 2611 * cannot be emulated in software (no access fault will occur). 2612 * Therefore this should be used only if it's supported system 2613 * wide. 2614 */ 2615 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2616 .capability = ARM64_HAFT, 2617 .matches = has_cpuid_feature, 2618 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2619 }, 2620 #endif 2621 { 2622 .desc = "CRC32 instructions", 2623 .capability = ARM64_HAS_CRC32, 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .matches = has_cpuid_feature, 2626 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2627 }, 2628 { 2629 .desc = "Speculative Store Bypassing Safe (SSBS)", 2630 .capability = ARM64_SSBS, 2631 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2632 .matches = has_cpuid_feature, 2633 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2634 }, 2635 #ifdef CONFIG_ARM64_CNP 2636 { 2637 .desc = "Common not Private translations", 2638 .capability = ARM64_HAS_CNP, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = has_useable_cnp, 2641 .cpu_enable = cpu_enable_cnp, 2642 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2643 }, 2644 #endif 2645 { 2646 .desc = "Speculation barrier (SB)", 2647 .capability = ARM64_HAS_SB, 2648 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2649 .matches = has_cpuid_feature, 2650 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2651 }, 2652 #ifdef CONFIG_ARM64_PTR_AUTH 2653 { 2654 .desc = "Address authentication (architected QARMA5 algorithm)", 2655 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2656 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2657 .matches = has_address_auth_cpucap, 2658 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2659 }, 2660 { 2661 .desc = "Address authentication (architected QARMA3 algorithm)", 2662 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2663 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2664 .matches = has_address_auth_cpucap, 2665 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2666 }, 2667 { 2668 .desc = "Address authentication (IMP DEF algorithm)", 2669 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2670 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2671 .matches = has_address_auth_cpucap, 2672 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2673 }, 2674 { 2675 .capability = ARM64_HAS_ADDRESS_AUTH, 2676 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2677 .matches = has_address_auth_metacap, 2678 }, 2679 { 2680 .desc = "Generic authentication (architected QARMA5 algorithm)", 2681 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2682 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2683 .matches = has_cpuid_feature, 2684 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2685 }, 2686 { 2687 .desc = "Generic authentication (architected QARMA3 algorithm)", 2688 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2689 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2690 .matches = has_cpuid_feature, 2691 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2692 }, 2693 { 2694 .desc = "Generic authentication (IMP DEF algorithm)", 2695 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2696 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2697 .matches = has_cpuid_feature, 2698 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2699 }, 2700 { 2701 .capability = ARM64_HAS_GENERIC_AUTH, 2702 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2703 .matches = has_generic_auth, 2704 }, 2705 #endif /* CONFIG_ARM64_PTR_AUTH */ 2706 #ifdef CONFIG_ARM64_PSEUDO_NMI 2707 { 2708 /* 2709 * Depends on having GICv3 2710 */ 2711 .desc = "IRQ priority masking", 2712 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2713 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2714 .matches = can_use_gic_priorities, 2715 }, 2716 { 2717 /* 2718 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2719 */ 2720 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2721 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2722 .matches = has_gic_prio_relaxed_sync, 2723 }, 2724 #endif 2725 #ifdef CONFIG_ARM64_E0PD 2726 { 2727 .desc = "E0PD", 2728 .capability = ARM64_HAS_E0PD, 2729 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2730 .cpu_enable = cpu_enable_e0pd, 2731 .matches = has_cpuid_feature, 2732 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2733 }, 2734 #endif 2735 { 2736 .desc = "Random Number Generator", 2737 .capability = ARM64_HAS_RNG, 2738 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2739 .matches = has_cpuid_feature, 2740 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2741 }, 2742 #ifdef CONFIG_ARM64_BTI 2743 { 2744 .desc = "Branch Target Identification", 2745 .capability = ARM64_BTI, 2746 #ifdef CONFIG_ARM64_BTI_KERNEL 2747 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2748 #else 2749 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2750 #endif 2751 .matches = has_cpuid_feature, 2752 .cpu_enable = bti_enable, 2753 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2754 }, 2755 #endif 2756 #ifdef CONFIG_ARM64_MTE 2757 { 2758 .desc = "Memory Tagging Extension", 2759 .capability = ARM64_MTE, 2760 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2761 .matches = has_cpuid_feature, 2762 .cpu_enable = cpu_enable_mte, 2763 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2764 }, 2765 { 2766 .desc = "Asymmetric MTE Tag Check Fault", 2767 .capability = ARM64_MTE_ASYMM, 2768 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2769 .matches = has_cpuid_feature, 2770 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2771 }, 2772 #endif /* CONFIG_ARM64_MTE */ 2773 { 2774 .desc = "RCpc load-acquire (LDAPR)", 2775 .capability = ARM64_HAS_LDAPR, 2776 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2777 .matches = has_cpuid_feature, 2778 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2779 }, 2780 { 2781 .desc = "Fine Grained Traps", 2782 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2783 .capability = ARM64_HAS_FGT, 2784 .matches = has_cpuid_feature, 2785 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2786 }, 2787 #ifdef CONFIG_ARM64_SME 2788 { 2789 .desc = "Scalable Matrix Extension", 2790 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2791 .capability = ARM64_SME, 2792 .matches = has_cpuid_feature, 2793 .cpu_enable = cpu_enable_sme, 2794 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2795 }, 2796 /* FA64 should be sorted after the base SME capability */ 2797 { 2798 .desc = "FA64", 2799 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2800 .capability = ARM64_SME_FA64, 2801 .matches = has_cpuid_feature, 2802 .cpu_enable = cpu_enable_fa64, 2803 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2804 }, 2805 { 2806 .desc = "SME2", 2807 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2808 .capability = ARM64_SME2, 2809 .matches = has_cpuid_feature, 2810 .cpu_enable = cpu_enable_sme2, 2811 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2812 }, 2813 #endif /* CONFIG_ARM64_SME */ 2814 { 2815 .desc = "WFx with timeout", 2816 .capability = ARM64_HAS_WFXT, 2817 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2818 .matches = has_cpuid_feature, 2819 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2820 }, 2821 { 2822 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2823 .capability = ARM64_HAS_TIDCP1, 2824 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2825 .matches = has_cpuid_feature, 2826 .cpu_enable = cpu_trap_el0_impdef, 2827 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2828 }, 2829 { 2830 .desc = "Data independent timing control (DIT)", 2831 .capability = ARM64_HAS_DIT, 2832 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2833 .matches = has_cpuid_feature, 2834 .cpu_enable = cpu_enable_dit, 2835 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2836 }, 2837 { 2838 .desc = "Memory Copy and Memory Set instructions", 2839 .capability = ARM64_HAS_MOPS, 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .matches = has_cpuid_feature, 2842 .cpu_enable = cpu_enable_mops, 2843 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2844 }, 2845 { 2846 .capability = ARM64_HAS_TCR2, 2847 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2848 .matches = has_cpuid_feature, 2849 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2850 }, 2851 { 2852 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2853 .capability = ARM64_HAS_S1PIE, 2854 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2855 .matches = has_cpuid_feature, 2856 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2857 }, 2858 { 2859 .desc = "VHE for hypervisor only", 2860 .capability = ARM64_KVM_HVHE, 2861 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2862 .matches = hvhe_possible, 2863 }, 2864 { 2865 .desc = "Enhanced Virtualization Traps", 2866 .capability = ARM64_HAS_EVT, 2867 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2868 .matches = has_cpuid_feature, 2869 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2870 }, 2871 { 2872 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2873 .capability = ARM64_HAS_LPA2, 2874 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2875 .matches = has_lpa2, 2876 }, 2877 { 2878 .desc = "FPMR", 2879 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2880 .capability = ARM64_HAS_FPMR, 2881 .matches = has_cpuid_feature, 2882 .cpu_enable = cpu_enable_fpmr, 2883 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2884 }, 2885 #ifdef CONFIG_ARM64_VA_BITS_52 2886 { 2887 .capability = ARM64_HAS_VA52, 2888 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2889 .matches = has_cpuid_feature, 2890 #ifdef CONFIG_ARM64_64K_PAGES 2891 .desc = "52-bit Virtual Addressing (LVA)", 2892 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2893 #else 2894 .desc = "52-bit Virtual Addressing (LPA2)", 2895 #ifdef CONFIG_ARM64_4K_PAGES 2896 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2897 #else 2898 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2899 #endif 2900 #endif 2901 }, 2902 #endif 2903 { 2904 .desc = "NV1", 2905 .capability = ARM64_HAS_HCR_NV1, 2906 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2907 .matches = has_nv1, 2908 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2909 }, 2910 #ifdef CONFIG_ARM64_POE 2911 { 2912 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2913 .capability = ARM64_HAS_S1POE, 2914 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2915 .matches = has_cpuid_feature, 2916 .cpu_enable = cpu_enable_poe, 2917 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2918 }, 2919 #endif 2920 #ifdef CONFIG_ARM64_GCS 2921 { 2922 .desc = "Guarded Control Stack (GCS)", 2923 .capability = ARM64_HAS_GCS, 2924 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2925 .cpu_enable = cpu_enable_gcs, 2926 .matches = has_cpuid_feature, 2927 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 2928 }, 2929 #endif 2930 {}, 2931 }; 2932 2933 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2934 .matches = has_user_cpuid_feature, \ 2935 ARM64_CPUID_FIELDS(reg, field, min_value) 2936 2937 #define __HWCAP_CAP(name, cap_type, cap) \ 2938 .desc = name, \ 2939 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2940 .hwcap_type = cap_type, \ 2941 .hwcap = cap, \ 2942 2943 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 2944 { \ 2945 __HWCAP_CAP(#cap, cap_type, cap) \ 2946 HWCAP_CPUID_MATCH(reg, field, min_value) \ 2947 } 2948 2949 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2950 { \ 2951 __HWCAP_CAP(#cap, cap_type, cap) \ 2952 .matches = cpucap_multi_entry_cap_matches, \ 2953 .match_list = list, \ 2954 } 2955 2956 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2957 { \ 2958 __HWCAP_CAP(#cap, cap_type, cap) \ 2959 .matches = match, \ 2960 } 2961 2962 #ifdef CONFIG_ARM64_PTR_AUTH 2963 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2964 { 2965 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 2966 }, 2967 { 2968 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 2969 }, 2970 { 2971 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 2972 }, 2973 {}, 2974 }; 2975 2976 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2977 { 2978 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 2979 }, 2980 { 2981 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 2982 }, 2983 { 2984 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 2985 }, 2986 {}, 2987 }; 2988 #endif 2989 2990 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2991 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2992 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 2993 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2994 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2995 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2996 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2997 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2998 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 2999 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3000 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3001 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3002 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3003 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3004 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3005 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3006 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3007 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3008 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3009 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3010 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3011 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3012 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3013 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3014 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3015 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3016 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3017 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3018 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3019 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3020 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3021 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3022 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3023 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3024 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3025 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3026 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3027 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3028 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3029 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3030 #ifdef CONFIG_ARM64_SVE 3031 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3032 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3033 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3034 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3035 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3036 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3037 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3038 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3039 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3040 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3041 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3042 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3043 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3044 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3045 #endif 3046 #ifdef CONFIG_ARM64_GCS 3047 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3048 #endif 3049 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3050 #ifdef CONFIG_ARM64_BTI 3051 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3052 #endif 3053 #ifdef CONFIG_ARM64_PTR_AUTH 3054 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3055 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3056 #endif 3057 #ifdef CONFIG_ARM64_MTE 3058 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3059 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3060 #endif /* CONFIG_ARM64_MTE */ 3061 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3062 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3063 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3064 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3065 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3066 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3067 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3068 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3069 #ifdef CONFIG_ARM64_SME 3070 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3071 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3072 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3073 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3074 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3075 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3076 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3077 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3078 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3079 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3080 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3081 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3082 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3083 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3084 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3085 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3086 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3087 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3088 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3089 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3090 #endif /* CONFIG_ARM64_SME */ 3091 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3092 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3093 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3094 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3095 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3096 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3097 #ifdef CONFIG_ARM64_POE 3098 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3099 #endif 3100 {}, 3101 }; 3102 3103 #ifdef CONFIG_COMPAT 3104 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3105 { 3106 /* 3107 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3108 * in line with that of arm32 as in vfp_init(). We make sure that the 3109 * check is future proof, by making sure value is non-zero. 3110 */ 3111 u32 mvfr1; 3112 3113 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3114 if (scope == SCOPE_SYSTEM) 3115 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3116 else 3117 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3118 3119 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3120 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3121 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3122 } 3123 #endif 3124 3125 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3126 #ifdef CONFIG_COMPAT 3127 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3128 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3129 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3130 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3131 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3132 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3133 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3134 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3135 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3136 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3137 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3138 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3139 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3140 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3141 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3142 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3143 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3144 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3145 #endif 3146 {}, 3147 }; 3148 3149 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3150 { 3151 switch (cap->hwcap_type) { 3152 case CAP_HWCAP: 3153 cpu_set_feature(cap->hwcap); 3154 break; 3155 #ifdef CONFIG_COMPAT 3156 case CAP_COMPAT_HWCAP: 3157 compat_elf_hwcap |= (u32)cap->hwcap; 3158 break; 3159 case CAP_COMPAT_HWCAP2: 3160 compat_elf_hwcap2 |= (u32)cap->hwcap; 3161 break; 3162 #endif 3163 default: 3164 WARN_ON(1); 3165 break; 3166 } 3167 } 3168 3169 /* Check if we have a particular HWCAP enabled */ 3170 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3171 { 3172 bool rc; 3173 3174 switch (cap->hwcap_type) { 3175 case CAP_HWCAP: 3176 rc = cpu_have_feature(cap->hwcap); 3177 break; 3178 #ifdef CONFIG_COMPAT 3179 case CAP_COMPAT_HWCAP: 3180 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3181 break; 3182 case CAP_COMPAT_HWCAP2: 3183 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3184 break; 3185 #endif 3186 default: 3187 WARN_ON(1); 3188 rc = false; 3189 } 3190 3191 return rc; 3192 } 3193 3194 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3195 { 3196 /* We support emulation of accesses to CPU ID feature registers */ 3197 cpu_set_named_feature(CPUID); 3198 for (; hwcaps->matches; hwcaps++) 3199 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3200 cap_set_elf_hwcap(hwcaps); 3201 } 3202 3203 static void update_cpu_capabilities(u16 scope_mask) 3204 { 3205 int i; 3206 const struct arm64_cpu_capabilities *caps; 3207 3208 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3209 for (i = 0; i < ARM64_NCAPS; i++) { 3210 caps = cpucap_ptrs[i]; 3211 if (!caps || !(caps->type & scope_mask) || 3212 cpus_have_cap(caps->capability) || 3213 !caps->matches(caps, cpucap_default_scope(caps))) 3214 continue; 3215 3216 if (caps->desc && !caps->cpus) 3217 pr_info("detected: %s\n", caps->desc); 3218 3219 __set_bit(caps->capability, system_cpucaps); 3220 3221 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3222 set_bit(caps->capability, boot_cpucaps); 3223 } 3224 } 3225 3226 /* 3227 * Enable all the available capabilities on this CPU. The capabilities 3228 * with BOOT_CPU scope are handled separately and hence skipped here. 3229 */ 3230 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3231 { 3232 int i; 3233 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3234 3235 for_each_available_cap(i) { 3236 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3237 3238 if (WARN_ON(!cap)) 3239 continue; 3240 3241 if (!(cap->type & non_boot_scope)) 3242 continue; 3243 3244 if (cap->cpu_enable) 3245 cap->cpu_enable(cap); 3246 } 3247 return 0; 3248 } 3249 3250 /* 3251 * Run through the enabled capabilities and enable() it on all active 3252 * CPUs 3253 */ 3254 static void __init enable_cpu_capabilities(u16 scope_mask) 3255 { 3256 int i; 3257 const struct arm64_cpu_capabilities *caps; 3258 bool boot_scope; 3259 3260 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3261 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3262 3263 for (i = 0; i < ARM64_NCAPS; i++) { 3264 caps = cpucap_ptrs[i]; 3265 if (!caps || !(caps->type & scope_mask) || 3266 !cpus_have_cap(caps->capability)) 3267 continue; 3268 3269 if (boot_scope && caps->cpu_enable) 3270 /* 3271 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3272 * before any secondary CPU boots. Thus, each secondary 3273 * will enable the capability as appropriate via 3274 * check_local_cpu_capabilities(). The only exception is 3275 * the boot CPU, for which the capability must be 3276 * enabled here. This approach avoids costly 3277 * stop_machine() calls for this case. 3278 */ 3279 caps->cpu_enable(caps); 3280 } 3281 3282 /* 3283 * For all non-boot scope capabilities, use stop_machine() 3284 * as it schedules the work allowing us to modify PSTATE, 3285 * instead of on_each_cpu() which uses an IPI, giving us a 3286 * PSTATE that disappears when we return. 3287 */ 3288 if (!boot_scope) 3289 stop_machine(cpu_enable_non_boot_scope_capabilities, 3290 NULL, cpu_online_mask); 3291 } 3292 3293 /* 3294 * Run through the list of capabilities to check for conflicts. 3295 * If the system has already detected a capability, take necessary 3296 * action on this CPU. 3297 */ 3298 static void verify_local_cpu_caps(u16 scope_mask) 3299 { 3300 int i; 3301 bool cpu_has_cap, system_has_cap; 3302 const struct arm64_cpu_capabilities *caps; 3303 3304 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3305 3306 for (i = 0; i < ARM64_NCAPS; i++) { 3307 caps = cpucap_ptrs[i]; 3308 if (!caps || !(caps->type & scope_mask)) 3309 continue; 3310 3311 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3312 system_has_cap = cpus_have_cap(caps->capability); 3313 3314 if (system_has_cap) { 3315 /* 3316 * Check if the new CPU misses an advertised feature, 3317 * which is not safe to miss. 3318 */ 3319 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3320 break; 3321 /* 3322 * We have to issue cpu_enable() irrespective of 3323 * whether the CPU has it or not, as it is enabeld 3324 * system wide. It is upto the call back to take 3325 * appropriate action on this CPU. 3326 */ 3327 if (caps->cpu_enable) 3328 caps->cpu_enable(caps); 3329 } else { 3330 /* 3331 * Check if the CPU has this capability if it isn't 3332 * safe to have when the system doesn't. 3333 */ 3334 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3335 break; 3336 } 3337 } 3338 3339 if (i < ARM64_NCAPS) { 3340 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3341 smp_processor_id(), caps->capability, 3342 caps->desc, system_has_cap, cpu_has_cap); 3343 3344 if (cpucap_panic_on_conflict(caps)) 3345 cpu_panic_kernel(); 3346 else 3347 cpu_die_early(); 3348 } 3349 } 3350 3351 /* 3352 * Check for CPU features that are used in early boot 3353 * based on the Boot CPU value. 3354 */ 3355 static void check_early_cpu_features(void) 3356 { 3357 verify_cpu_asid_bits(); 3358 3359 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3360 } 3361 3362 static void 3363 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3364 { 3365 3366 for (; caps->matches; caps++) 3367 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3368 pr_crit("CPU%d: missing HWCAP: %s\n", 3369 smp_processor_id(), caps->desc); 3370 cpu_die_early(); 3371 } 3372 } 3373 3374 static void verify_local_elf_hwcaps(void) 3375 { 3376 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3377 3378 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3379 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3380 } 3381 3382 static void verify_sve_features(void) 3383 { 3384 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3385 3386 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3387 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3388 smp_processor_id()); 3389 cpu_die_early(); 3390 } 3391 3392 cpacr_restore(cpacr); 3393 } 3394 3395 static void verify_sme_features(void) 3396 { 3397 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3398 3399 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3400 pr_crit("CPU%d: SME: vector length support mismatch\n", 3401 smp_processor_id()); 3402 cpu_die_early(); 3403 } 3404 3405 cpacr_restore(cpacr); 3406 } 3407 3408 static void verify_hyp_capabilities(void) 3409 { 3410 u64 safe_mmfr1, mmfr0, mmfr1; 3411 int parange, ipa_max; 3412 unsigned int safe_vmid_bits, vmid_bits; 3413 3414 if (!IS_ENABLED(CONFIG_KVM)) 3415 return; 3416 3417 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3418 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3419 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3420 3421 /* Verify VMID bits */ 3422 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3423 vmid_bits = get_vmid_bits(mmfr1); 3424 if (vmid_bits < safe_vmid_bits) { 3425 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3426 cpu_die_early(); 3427 } 3428 3429 /* Verify IPA range */ 3430 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3431 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3432 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3433 if (ipa_max < get_kvm_ipa_limit()) { 3434 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3435 cpu_die_early(); 3436 } 3437 } 3438 3439 /* 3440 * Run through the enabled system capabilities and enable() it on this CPU. 3441 * The capabilities were decided based on the available CPUs at the boot time. 3442 * Any new CPU should match the system wide status of the capability. If the 3443 * new CPU doesn't have a capability which the system now has enabled, we 3444 * cannot do anything to fix it up and could cause unexpected failures. So 3445 * we park the CPU. 3446 */ 3447 static void verify_local_cpu_capabilities(void) 3448 { 3449 /* 3450 * The capabilities with SCOPE_BOOT_CPU are checked from 3451 * check_early_cpu_features(), as they need to be verified 3452 * on all secondary CPUs. 3453 */ 3454 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3455 verify_local_elf_hwcaps(); 3456 3457 if (system_supports_sve()) 3458 verify_sve_features(); 3459 3460 if (system_supports_sme()) 3461 verify_sme_features(); 3462 3463 if (is_hyp_mode_available()) 3464 verify_hyp_capabilities(); 3465 } 3466 3467 void check_local_cpu_capabilities(void) 3468 { 3469 /* 3470 * All secondary CPUs should conform to the early CPU features 3471 * in use by the kernel based on boot CPU. 3472 */ 3473 check_early_cpu_features(); 3474 3475 /* 3476 * If we haven't finalised the system capabilities, this CPU gets 3477 * a chance to update the errata work arounds and local features. 3478 * Otherwise, this CPU should verify that it has all the system 3479 * advertised capabilities. 3480 */ 3481 if (!system_capabilities_finalized()) 3482 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3483 else 3484 verify_local_cpu_capabilities(); 3485 } 3486 3487 bool this_cpu_has_cap(unsigned int n) 3488 { 3489 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3490 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3491 3492 if (cap) 3493 return cap->matches(cap, SCOPE_LOCAL_CPU); 3494 } 3495 3496 return false; 3497 } 3498 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3499 3500 /* 3501 * This helper function is used in a narrow window when, 3502 * - The system wide safe registers are set with all the SMP CPUs and, 3503 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3504 */ 3505 static bool __maybe_unused __system_matches_cap(unsigned int n) 3506 { 3507 if (n < ARM64_NCAPS) { 3508 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3509 3510 if (cap) 3511 return cap->matches(cap, SCOPE_SYSTEM); 3512 } 3513 return false; 3514 } 3515 3516 void cpu_set_feature(unsigned int num) 3517 { 3518 set_bit(num, elf_hwcap); 3519 } 3520 3521 bool cpu_have_feature(unsigned int num) 3522 { 3523 return test_bit(num, elf_hwcap); 3524 } 3525 EXPORT_SYMBOL_GPL(cpu_have_feature); 3526 3527 unsigned long cpu_get_elf_hwcap(void) 3528 { 3529 /* 3530 * We currently only populate the first 32 bits of AT_HWCAP. Please 3531 * note that for userspace compatibility we guarantee that bits 62 3532 * and 63 will always be returned as 0. 3533 */ 3534 return elf_hwcap[0]; 3535 } 3536 3537 unsigned long cpu_get_elf_hwcap2(void) 3538 { 3539 return elf_hwcap[1]; 3540 } 3541 3542 unsigned long cpu_get_elf_hwcap3(void) 3543 { 3544 return elf_hwcap[2]; 3545 } 3546 3547 static void __init setup_boot_cpu_capabilities(void) 3548 { 3549 /* 3550 * The boot CPU's feature register values have been recorded. Detect 3551 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3552 * patch alternatives for the available boot cpucaps. 3553 */ 3554 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3555 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3556 apply_boot_alternatives(); 3557 } 3558 3559 void __init setup_boot_cpu_features(void) 3560 { 3561 /* 3562 * Initialize the indirect array of CPU capabilities pointers before we 3563 * handle the boot CPU. 3564 */ 3565 init_cpucap_indirect_list(); 3566 3567 /* 3568 * Detect broken pseudo-NMI. Must be called _before_ the call to 3569 * setup_boot_cpu_capabilities() since it interacts with 3570 * can_use_gic_priorities(). 3571 */ 3572 detect_system_supports_pseudo_nmi(); 3573 3574 setup_boot_cpu_capabilities(); 3575 } 3576 3577 static void __init setup_system_capabilities(void) 3578 { 3579 /* 3580 * The system-wide safe feature register values have been finalized. 3581 * Detect, enable, and patch alternatives for the available system 3582 * cpucaps. 3583 */ 3584 update_cpu_capabilities(SCOPE_SYSTEM); 3585 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3586 apply_alternatives_all(); 3587 3588 /* 3589 * Log any cpucaps with a cpumask as these aren't logged by 3590 * update_cpu_capabilities(). 3591 */ 3592 for (int i = 0; i < ARM64_NCAPS; i++) { 3593 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3594 3595 if (caps && caps->cpus && caps->desc && 3596 cpumask_any(caps->cpus) < nr_cpu_ids) 3597 pr_info("detected: %s on CPU%*pbl\n", 3598 caps->desc, cpumask_pr_args(caps->cpus)); 3599 } 3600 3601 /* 3602 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3603 */ 3604 if (system_uses_ttbr0_pan()) 3605 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3606 } 3607 3608 void __init setup_system_features(void) 3609 { 3610 setup_system_capabilities(); 3611 3612 kpti_install_ng_mappings(); 3613 3614 sve_setup(); 3615 sme_setup(); 3616 3617 /* 3618 * Check for sane CTR_EL0.CWG value. 3619 */ 3620 if (!cache_type_cwg()) 3621 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3622 ARCH_DMA_MINALIGN); 3623 } 3624 3625 void __init setup_user_features(void) 3626 { 3627 user_feature_fixup(); 3628 3629 setup_elf_hwcaps(arm64_elf_hwcaps); 3630 3631 if (system_supports_32bit_el0()) { 3632 setup_elf_hwcaps(compat_elf_hwcaps); 3633 elf_hwcap_fixup(); 3634 } 3635 3636 minsigstksz_setup(); 3637 } 3638 3639 static int enable_mismatched_32bit_el0(unsigned int cpu) 3640 { 3641 /* 3642 * The first 32-bit-capable CPU we detected and so can no longer 3643 * be offlined by userspace. -1 indicates we haven't yet onlined 3644 * a 32-bit-capable CPU. 3645 */ 3646 static int lucky_winner = -1; 3647 3648 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3649 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3650 3651 if (cpu_32bit) { 3652 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3653 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3654 } 3655 3656 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3657 return 0; 3658 3659 if (lucky_winner >= 0) 3660 return 0; 3661 3662 /* 3663 * We've detected a mismatch. We need to keep one of our CPUs with 3664 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3665 * every CPU in the system for a 32-bit task. 3666 */ 3667 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3668 cpu_active_mask); 3669 get_cpu_device(lucky_winner)->offline_disabled = true; 3670 setup_elf_hwcaps(compat_elf_hwcaps); 3671 elf_hwcap_fixup(); 3672 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3673 cpu, lucky_winner); 3674 return 0; 3675 } 3676 3677 static int __init init_32bit_el0_mask(void) 3678 { 3679 if (!allow_mismatched_32bit_el0) 3680 return 0; 3681 3682 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3683 return -ENOMEM; 3684 3685 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3686 "arm64/mismatched_32bit_el0:online", 3687 enable_mismatched_32bit_el0, NULL); 3688 } 3689 subsys_initcall_sync(init_32bit_el0_mask); 3690 3691 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3692 { 3693 cpu_enable_swapper_cnp(); 3694 } 3695 3696 /* 3697 * We emulate only the following system register space. 3698 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3699 * See Table C5-6 System instruction encodings for System register accesses, 3700 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3701 */ 3702 static inline bool __attribute_const__ is_emulated(u32 id) 3703 { 3704 return (sys_reg_Op0(id) == 0x3 && 3705 sys_reg_CRn(id) == 0x0 && 3706 sys_reg_Op1(id) == 0x0 && 3707 (sys_reg_CRm(id) == 0 || 3708 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3709 } 3710 3711 /* 3712 * With CRm == 0, reg should be one of : 3713 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3714 */ 3715 static inline int emulate_id_reg(u32 id, u64 *valp) 3716 { 3717 switch (id) { 3718 case SYS_MIDR_EL1: 3719 *valp = read_cpuid_id(); 3720 break; 3721 case SYS_MPIDR_EL1: 3722 *valp = SYS_MPIDR_SAFE_VAL; 3723 break; 3724 case SYS_REVIDR_EL1: 3725 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3726 *valp = 0; 3727 break; 3728 default: 3729 return -EINVAL; 3730 } 3731 3732 return 0; 3733 } 3734 3735 static int emulate_sys_reg(u32 id, u64 *valp) 3736 { 3737 struct arm64_ftr_reg *regp; 3738 3739 if (!is_emulated(id)) 3740 return -EINVAL; 3741 3742 if (sys_reg_CRm(id) == 0) 3743 return emulate_id_reg(id, valp); 3744 3745 regp = get_arm64_ftr_reg_nowarn(id); 3746 if (regp) 3747 *valp = arm64_ftr_reg_user_value(regp); 3748 else 3749 /* 3750 * The untracked registers are either IMPLEMENTATION DEFINED 3751 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3752 */ 3753 *valp = 0; 3754 return 0; 3755 } 3756 3757 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3758 { 3759 int rc; 3760 u64 val; 3761 3762 rc = emulate_sys_reg(sys_reg, &val); 3763 if (!rc) { 3764 pt_regs_write_reg(regs, rt, val); 3765 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3766 } 3767 return rc; 3768 } 3769 3770 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3771 { 3772 u32 sys_reg, rt; 3773 3774 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3775 return false; 3776 3777 /* 3778 * sys_reg values are defined as used in mrs/msr instruction. 3779 * shift the imm value to get the encoding. 3780 */ 3781 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3782 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3783 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3784 } 3785 3786 enum mitigation_state arm64_get_meltdown_state(void) 3787 { 3788 if (__meltdown_safe) 3789 return SPECTRE_UNAFFECTED; 3790 3791 if (arm64_kernel_unmapped_at_el0()) 3792 return SPECTRE_MITIGATED; 3793 3794 return SPECTRE_VULNERABLE; 3795 } 3796 3797 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3798 char *buf) 3799 { 3800 switch (arm64_get_meltdown_state()) { 3801 case SPECTRE_UNAFFECTED: 3802 return sprintf(buf, "Not affected\n"); 3803 3804 case SPECTRE_MITIGATED: 3805 return sprintf(buf, "Mitigation: PTI\n"); 3806 3807 default: 3808 return sprintf(buf, "Vulnerable\n"); 3809 } 3810 } 3811