1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/hypervisor.h> 90 #include <asm/processor.h> 91 #include <asm/smp.h> 92 #include <asm/sysreg.h> 93 #include <asm/traps.h> 94 #include <asm/vectors.h> 95 #include <asm/virt.h> 96 97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 99 100 #ifdef CONFIG_COMPAT 101 #define COMPAT_ELF_HWCAP_DEFAULT \ 102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 105 COMPAT_HWCAP_LPAE) 106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 107 unsigned int compat_elf_hwcap2 __read_mostly; 108 unsigned int compat_elf_hwcap3 __read_mostly; 109 #endif 110 111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 112 EXPORT_SYMBOL(system_cpucaps); 113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 114 115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 116 117 /* 118 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 119 * ends up in the .bss section where it is initialized in early_map_kernel() 120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 122 * may end up generating an incorrect idmap page table attributes. 123 */ 124 bool arm64_use_ng_mappings __read_mostly = false; 125 EXPORT_SYMBOL(arm64_use_ng_mappings); 126 127 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 128 129 /* 130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 131 * support it? 132 */ 133 static bool __read_mostly allow_mismatched_32bit_el0; 134 135 /* 136 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 137 * seen at least one CPU capable of 32-bit EL0. 138 */ 139 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 140 141 /* 142 * Mask of CPUs supporting 32-bit EL0. 143 * Only valid if arm64_mismatched_32bit_el0 is enabled. 144 */ 145 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 151 } 152 153 #define __ARM64_MAX_POSITIVE(reg, field) \ 154 ((reg##_##field##_SIGNED ? \ 155 BIT(reg##_##field##_WIDTH - 1) : \ 156 BIT(reg##_##field##_WIDTH)) - 1) 157 158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 159 160 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 161 .sys_reg = SYS_##reg, \ 162 .field_pos = reg##_##field##_SHIFT, \ 163 .field_width = reg##_##field##_WIDTH, \ 164 .sign = reg##_##field##_SIGNED, \ 165 .min_field_value = min_value, \ 166 .max_field_value = max_value, 167 168 /* 169 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 170 * an implicit maximum that depends on the sign-ess of the field. 171 * 172 * An unsigned field will be capped at all ones, while a signed field 173 * will be limited to the positive half only. 174 */ 175 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 176 __ARM64_CPUID_FIELDS(reg, field, \ 177 SYS_FIELD_VALUE(reg, field, min_value), \ 178 __ARM64_MAX_POSITIVE(reg, field)) 179 180 /* 181 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 182 * implicit minimal value to max_value. This should be used when 183 * matching a non-implemented property. 184 */ 185 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 186 __ARM64_CPUID_FIELDS(reg, field, \ 187 __ARM64_MIN_NEGATIVE(reg, field), \ 188 SYS_FIELD_VALUE(reg, field, max_value)) 189 190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 191 { \ 192 .sign = SIGNED, \ 193 .visible = VISIBLE, \ 194 .strict = STRICT, \ 195 .type = TYPE, \ 196 .shift = SHIFT, \ 197 .width = WIDTH, \ 198 .safe_val = SAFE_VAL, \ 199 } 200 201 /* Define a feature with unsigned values */ 202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 204 205 /* Define a feature with a signed value */ 206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 #define ARM64_FTR_END \ 210 { \ 211 .width = 0, \ 212 } 213 214 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 215 216 static bool __system_matches_cap(unsigned int n); 217 218 /* 219 * NOTE: Any changes to the visibility of features should be kept in 220 * sync with the documentation of the CPU feature register ABI. 221 */ 222 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 237 ARM64_FTR_END, 238 }; 239 240 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 276 ARM64_FTR_END, 277 }; 278 279 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 296 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 297 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 308 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 314 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 315 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 318 ARM64_FTR_END, 319 }; 320 321 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 322 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 325 ARM64_FTR_END, 326 }; 327 328 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 329 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 330 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 332 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 353 ARM64_FTR_END, 354 }; 355 356 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 358 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 360 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 403 ARM64_FTR_END, 404 }; 405 406 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 421 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 422 /* 423 * Page size not being supported at Stage-2 is not fatal. You 424 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 425 * your favourite nesting hypervisor. 426 * 427 * There is a small corner case where the hypervisor explicitly 428 * advertises a given granule size at Stage-2 (value 2) on some 429 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 430 * vCPUs. Although this is not forbidden by the architecture, it 431 * indicates that the hypervisor is being silly (or buggy). 432 * 433 * We make no effort to cope with this and pretend that if these 434 * fields are inconsistent across vCPUs, then it isn't worth 435 * trying to bring KVM up. 436 */ 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 440 /* 441 * We already refuse to boot CPUs that don't support our configured 442 * page size, so we can only detect mismatches for a page size other 443 * than the one we're currently using. Unfortunately, SoCs like this 444 * exist in the wild so, even though we don't like it, we'll have to go 445 * along with it and treat them as non-strict. 446 */ 447 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 448 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 450 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 452 /* Linux shouldn't care about secure memory */ 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 456 /* 457 * Differing PARange is fine as long as all peripherals and memory are mapped 458 * within the minimum PARange of all CPUs 459 */ 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 461 ARM64_FTR_END, 462 }; 463 464 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 479 ARM64_FTR_END, 480 }; 481 482 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 498 ARM64_FTR_END, 499 }; 500 501 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 502 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 503 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 506 ARM64_FTR_END, 507 }; 508 509 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 510 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 512 ARM64_FTR_END, 513 }; 514 515 static const struct arm64_ftr_bits ftr_ctr[] = { 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 521 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 522 /* 523 * Linux can handle differing I-cache policies. Userspace JITs will 524 * make use of *minLine. 525 * If we have differing I-cache policies, report it as the weakest - VIPT. 526 */ 527 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 528 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 529 ARM64_FTR_END, 530 }; 531 532 static struct arm64_ftr_override __ro_after_init no_override = { }; 533 534 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 535 .name = "SYS_CTR_EL0", 536 .ftr_bits = ftr_ctr, 537 .override = &no_override, 538 }; 539 540 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 541 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 546 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 549 ARM64_FTR_END, 550 }; 551 552 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 553 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 558 /* 559 * We can instantiate multiple PMU instances with different levels 560 * of support. 561 */ 562 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_mvfr0[] = { 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 576 ARM64_FTR_END, 577 }; 578 579 static const struct arm64_ftr_bits ftr_mvfr1[] = { 580 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 588 ARM64_FTR_END, 589 }; 590 591 static const struct arm64_ftr_bits ftr_mvfr2[] = { 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 594 ARM64_FTR_END, 595 }; 596 597 static const struct arm64_ftr_bits ftr_dczid[] = { 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 600 ARM64_FTR_END, 601 }; 602 603 static const struct arm64_ftr_bits ftr_gmid[] = { 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 605 ARM64_FTR_END, 606 }; 607 608 static const struct arm64_ftr_bits ftr_id_isar0[] = { 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 616 ARM64_FTR_END, 617 }; 618 619 static const struct arm64_ftr_bits ftr_id_isar5[] = { 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 626 ARM64_FTR_END, 627 }; 628 629 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 637 638 /* 639 * SpecSEI = 1 indicates that the PE might generate an SError on an 640 * external abort on speculative read. It is safe to assume that an 641 * SError might be generated than it will not be. Hence it has been 642 * classified as FTR_HIGHER_SAFE. 643 */ 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 645 ARM64_FTR_END, 646 }; 647 648 static const struct arm64_ftr_bits ftr_id_isar4[] = { 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 657 ARM64_FTR_END, 658 }; 659 660 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 662 ARM64_FTR_END, 663 }; 664 665 static const struct arm64_ftr_bits ftr_id_isar6[] = { 666 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 673 ARM64_FTR_END, 674 }; 675 676 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 695 ARM64_FTR_END, 696 }; 697 698 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 699 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 701 ARM64_FTR_END, 702 }; 703 704 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 705 /* [31:28] TraceFilt */ 706 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 713 ARM64_FTR_END, 714 }; 715 716 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 717 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 718 ARM64_FTR_END, 719 }; 720 721 static const struct arm64_ftr_bits ftr_mpamidr[] = { 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 726 ARM64_FTR_END, 727 }; 728 729 /* 730 * Common ftr bits for a 32bit register with all hidden, strict 731 * attributes, with 4bit feature fields and a default safe value of 732 * 0. Covers the following 32bit registers: 733 * id_isar[1-3], id_mmfr[1-3] 734 */ 735 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 744 ARM64_FTR_END, 745 }; 746 747 /* Table for a single 32bit feature value */ 748 static const struct arm64_ftr_bits ftr_single32[] = { 749 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 750 ARM64_FTR_END, 751 }; 752 753 static const struct arm64_ftr_bits ftr_raz[] = { 754 ARM64_FTR_END, 755 }; 756 757 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 758 .sys_id = id, \ 759 .reg = &(struct arm64_ftr_reg){ \ 760 .name = id_str, \ 761 .override = (ovr), \ 762 .ftr_bits = &((table)[0]), \ 763 }} 764 765 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 766 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 767 768 #define ARM64_FTR_REG(id, table) \ 769 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 770 771 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 772 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 773 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 774 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 775 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 776 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 777 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 778 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 779 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 780 781 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 782 783 static const struct __ftr_reg_entry { 784 u32 sys_id; 785 struct arm64_ftr_reg *reg; 786 } arm64_ftr_regs[] = { 787 788 /* Op1 = 0, CRn = 0, CRm = 1 */ 789 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 790 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 791 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 792 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 793 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 794 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 795 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 796 797 /* Op1 = 0, CRn = 0, CRm = 2 */ 798 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 799 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 801 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 802 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 803 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 804 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 805 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 806 807 /* Op1 = 0, CRn = 0, CRm = 3 */ 808 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 809 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 810 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 811 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 812 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 813 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 814 815 /* Op1 = 0, CRn = 0, CRm = 4 */ 816 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 817 &id_aa64pfr0_override), 818 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 819 &id_aa64pfr1_override), 820 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 821 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 822 &id_aa64zfr0_override), 823 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 824 &id_aa64smfr0_override), 825 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 826 827 /* Op1 = 0, CRn = 0, CRm = 5 */ 828 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 829 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 830 831 /* Op1 = 0, CRn = 0, CRm = 6 */ 832 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 834 &id_aa64isar1_override), 835 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 836 &id_aa64isar2_override), 837 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 838 839 /* Op1 = 0, CRn = 0, CRm = 7 */ 840 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 841 &id_aa64mmfr0_override), 842 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 843 &id_aa64mmfr1_override), 844 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 845 &id_aa64mmfr2_override), 846 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 847 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 848 849 /* Op1 = 0, CRn = 10, CRm = 4 */ 850 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 851 852 /* Op1 = 1, CRn = 0, CRm = 0 */ 853 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 854 855 /* Op1 = 3, CRn = 0, CRm = 0 */ 856 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 857 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 858 859 /* Op1 = 3, CRn = 14, CRm = 0 */ 860 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 861 }; 862 863 static int search_cmp_ftr_reg(const void *id, const void *regp) 864 { 865 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 866 } 867 868 /* 869 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 870 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 871 * ascending order of sys_id, we use binary search to find a matching 872 * entry. 873 * 874 * returns - Upon success, matching ftr_reg entry for id. 875 * - NULL on failure. It is upto the caller to decide 876 * the impact of a failure. 877 */ 878 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 879 { 880 const struct __ftr_reg_entry *ret; 881 882 ret = bsearch((const void *)(unsigned long)sys_id, 883 arm64_ftr_regs, 884 ARRAY_SIZE(arm64_ftr_regs), 885 sizeof(arm64_ftr_regs[0]), 886 search_cmp_ftr_reg); 887 if (ret) 888 return ret->reg; 889 return NULL; 890 } 891 892 /* 893 * get_arm64_ftr_reg - Looks up a feature register entry using 894 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 895 * 896 * returns - Upon success, matching ftr_reg entry for id. 897 * - NULL on failure but with an WARN_ON(). 898 */ 899 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 900 { 901 struct arm64_ftr_reg *reg; 902 903 reg = get_arm64_ftr_reg_nowarn(sys_id); 904 905 /* 906 * Requesting a non-existent register search is an error. Warn 907 * and let the caller handle it. 908 */ 909 WARN_ON(!reg); 910 return reg; 911 } 912 913 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 914 s64 ftr_val) 915 { 916 u64 mask = arm64_ftr_mask(ftrp); 917 918 reg &= ~mask; 919 reg |= (ftr_val << ftrp->shift) & mask; 920 return reg; 921 } 922 923 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 924 s64 cur) 925 { 926 s64 ret = 0; 927 928 switch (ftrp->type) { 929 case FTR_EXACT: 930 ret = ftrp->safe_val; 931 break; 932 case FTR_LOWER_SAFE: 933 ret = min(new, cur); 934 break; 935 case FTR_HIGHER_OR_ZERO_SAFE: 936 if (!cur || !new) 937 break; 938 fallthrough; 939 case FTR_HIGHER_SAFE: 940 ret = max(new, cur); 941 break; 942 default: 943 BUG(); 944 } 945 946 return ret; 947 } 948 949 static void __init sort_ftr_regs(void) 950 { 951 unsigned int i; 952 953 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 954 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 955 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 956 unsigned int j = 0; 957 958 /* 959 * Features here must be sorted in descending order with respect 960 * to their shift values and should not overlap with each other. 961 */ 962 for (; ftr_bits->width != 0; ftr_bits++, j++) { 963 unsigned int width = ftr_reg->ftr_bits[j].width; 964 unsigned int shift = ftr_reg->ftr_bits[j].shift; 965 unsigned int prev_shift; 966 967 WARN((shift + width) > 64, 968 "%s has invalid feature at shift %d\n", 969 ftr_reg->name, shift); 970 971 /* 972 * Skip the first feature. There is nothing to 973 * compare against for now. 974 */ 975 if (j == 0) 976 continue; 977 978 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 979 WARN((shift + width) > prev_shift, 980 "%s has feature overlap at shift %d\n", 981 ftr_reg->name, shift); 982 } 983 984 /* 985 * Skip the first register. There is nothing to 986 * compare against for now. 987 */ 988 if (i == 0) 989 continue; 990 /* 991 * Registers here must be sorted in ascending order with respect 992 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 993 * to work correctly. 994 */ 995 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 996 } 997 } 998 999 /* 1000 * Initialise the CPU feature register from Boot CPU values. 1001 * Also initiliases the strict_mask for the register. 1002 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1003 * RES0 for the system-wide value, and must strictly match. 1004 */ 1005 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1006 { 1007 u64 val = 0; 1008 u64 strict_mask = ~0x0ULL; 1009 u64 user_mask = 0; 1010 u64 valid_mask = 0; 1011 1012 const struct arm64_ftr_bits *ftrp; 1013 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1014 1015 if (!reg) 1016 return; 1017 1018 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1019 u64 ftr_mask = arm64_ftr_mask(ftrp); 1020 s64 ftr_new = arm64_ftr_value(ftrp, new); 1021 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1022 1023 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1024 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1025 char *str = NULL; 1026 1027 if (ftr_ovr != tmp) { 1028 /* Unsafe, remove the override */ 1029 reg->override->mask &= ~ftr_mask; 1030 reg->override->val &= ~ftr_mask; 1031 tmp = ftr_ovr; 1032 str = "ignoring override"; 1033 } else if (ftr_new != tmp) { 1034 /* Override was valid */ 1035 ftr_new = tmp; 1036 str = "forced"; 1037 } else { 1038 /* Override was the safe value */ 1039 str = "already set"; 1040 } 1041 1042 pr_warn("%s[%d:%d]: %s to %llx\n", 1043 reg->name, 1044 ftrp->shift + ftrp->width - 1, 1045 ftrp->shift, str, 1046 tmp & (BIT(ftrp->width) - 1)); 1047 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1048 reg->override->val &= ~ftr_mask; 1049 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1050 reg->name, 1051 ftrp->shift + ftrp->width - 1, 1052 ftrp->shift); 1053 } 1054 1055 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1056 1057 valid_mask |= ftr_mask; 1058 if (!ftrp->strict) 1059 strict_mask &= ~ftr_mask; 1060 if (ftrp->visible) 1061 user_mask |= ftr_mask; 1062 else 1063 reg->user_val = arm64_ftr_set_value(ftrp, 1064 reg->user_val, 1065 ftrp->safe_val); 1066 } 1067 1068 val &= valid_mask; 1069 1070 reg->sys_val = val; 1071 reg->strict_mask = strict_mask; 1072 reg->user_mask = user_mask; 1073 } 1074 1075 extern const struct arm64_cpu_capabilities arm64_errata[]; 1076 static const struct arm64_cpu_capabilities arm64_features[]; 1077 1078 static void __init 1079 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1080 { 1081 for (; caps->matches; caps++) { 1082 if (WARN(caps->capability >= ARM64_NCAPS, 1083 "Invalid capability %d\n", caps->capability)) 1084 continue; 1085 if (WARN(cpucap_ptrs[caps->capability], 1086 "Duplicate entry for capability %d\n", 1087 caps->capability)) 1088 continue; 1089 cpucap_ptrs[caps->capability] = caps; 1090 } 1091 } 1092 1093 static void __init init_cpucap_indirect_list(void) 1094 { 1095 init_cpucap_indirect_list_from_array(arm64_features); 1096 init_cpucap_indirect_list_from_array(arm64_errata); 1097 } 1098 1099 static void __init setup_boot_cpu_capabilities(void); 1100 1101 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1102 { 1103 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1104 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1105 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1106 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1107 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1108 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1109 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1110 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1111 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1112 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1113 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1114 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1115 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1116 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1117 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1118 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1119 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1120 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1121 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1122 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1123 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1124 } 1125 1126 #ifdef CONFIG_ARM64_PSEUDO_NMI 1127 static bool enable_pseudo_nmi; 1128 1129 static int __init early_enable_pseudo_nmi(char *p) 1130 { 1131 return kstrtobool(p, &enable_pseudo_nmi); 1132 } 1133 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1134 1135 static __init void detect_system_supports_pseudo_nmi(void) 1136 { 1137 struct device_node *np; 1138 1139 if (!enable_pseudo_nmi) 1140 return; 1141 1142 /* 1143 * Detect broken MediaTek firmware that doesn't properly save and 1144 * restore GIC priorities. 1145 */ 1146 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1147 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1148 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1149 enable_pseudo_nmi = false; 1150 } 1151 of_node_put(np); 1152 } 1153 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1154 static inline void detect_system_supports_pseudo_nmi(void) { } 1155 #endif 1156 1157 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1158 { 1159 /* Before we start using the tables, make sure it is sorted */ 1160 sort_ftr_regs(); 1161 1162 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1163 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1164 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1165 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1166 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1167 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1168 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1169 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1170 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1171 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1172 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1173 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1174 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1175 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1176 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1177 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1178 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1179 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1180 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1181 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1182 1183 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1184 init_32bit_cpu_features(&info->aarch32); 1185 1186 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1187 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1188 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1189 1190 vec_init_vq_map(ARM64_VEC_SVE); 1191 1192 cpacr_restore(cpacr); 1193 } 1194 1195 if (IS_ENABLED(CONFIG_ARM64_SME) && 1196 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1197 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1198 1199 vec_init_vq_map(ARM64_VEC_SME); 1200 1201 cpacr_restore(cpacr); 1202 } 1203 1204 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1205 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1206 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1207 } 1208 1209 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1210 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1211 } 1212 1213 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1214 { 1215 const struct arm64_ftr_bits *ftrp; 1216 1217 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1218 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1219 s64 ftr_new = arm64_ftr_value(ftrp, new); 1220 1221 if (ftr_cur == ftr_new) 1222 continue; 1223 /* Find a safe value */ 1224 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1225 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1226 } 1227 1228 } 1229 1230 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1231 { 1232 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1233 1234 if (!regp) 1235 return 0; 1236 1237 update_cpu_ftr_reg(regp, val); 1238 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1239 return 0; 1240 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1241 regp->name, boot, cpu, val); 1242 return 1; 1243 } 1244 1245 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1246 { 1247 const struct arm64_ftr_bits *ftrp; 1248 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1249 1250 if (!regp) 1251 return; 1252 1253 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1254 if (ftrp->shift == field) { 1255 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1256 break; 1257 } 1258 } 1259 1260 /* Bogus field? */ 1261 WARN_ON(!ftrp->width); 1262 } 1263 1264 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1265 struct cpuinfo_arm64 *boot) 1266 { 1267 static bool boot_cpu_32bit_regs_overridden = false; 1268 1269 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1270 return; 1271 1272 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1273 return; 1274 1275 boot->aarch32 = info->aarch32; 1276 init_32bit_cpu_features(&boot->aarch32); 1277 boot_cpu_32bit_regs_overridden = true; 1278 } 1279 1280 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1281 struct cpuinfo_32bit *boot) 1282 { 1283 int taint = 0; 1284 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1285 1286 /* 1287 * If we don't have AArch32 at EL1, then relax the strictness of 1288 * EL1-dependent register fields to avoid spurious sanity check fails. 1289 */ 1290 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1291 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1292 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1293 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1294 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1295 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1296 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1297 } 1298 1299 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1300 info->reg_id_dfr0, boot->reg_id_dfr0); 1301 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1302 info->reg_id_dfr1, boot->reg_id_dfr1); 1303 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1304 info->reg_id_isar0, boot->reg_id_isar0); 1305 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1306 info->reg_id_isar1, boot->reg_id_isar1); 1307 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1308 info->reg_id_isar2, boot->reg_id_isar2); 1309 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1310 info->reg_id_isar3, boot->reg_id_isar3); 1311 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1312 info->reg_id_isar4, boot->reg_id_isar4); 1313 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1314 info->reg_id_isar5, boot->reg_id_isar5); 1315 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1316 info->reg_id_isar6, boot->reg_id_isar6); 1317 1318 /* 1319 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1320 * ACTLR formats could differ across CPUs and therefore would have to 1321 * be trapped for virtualization anyway. 1322 */ 1323 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1324 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1325 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1326 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1327 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1328 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1329 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1330 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1331 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1332 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1333 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1334 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1335 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1336 info->reg_id_pfr0, boot->reg_id_pfr0); 1337 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1338 info->reg_id_pfr1, boot->reg_id_pfr1); 1339 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1340 info->reg_id_pfr2, boot->reg_id_pfr2); 1341 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1342 info->reg_mvfr0, boot->reg_mvfr0); 1343 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1344 info->reg_mvfr1, boot->reg_mvfr1); 1345 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1346 info->reg_mvfr2, boot->reg_mvfr2); 1347 1348 return taint; 1349 } 1350 1351 /* 1352 * Update system wide CPU feature registers with the values from a 1353 * non-boot CPU. Also performs SANITY checks to make sure that there 1354 * aren't any insane variations from that of the boot CPU. 1355 */ 1356 void update_cpu_features(int cpu, 1357 struct cpuinfo_arm64 *info, 1358 struct cpuinfo_arm64 *boot) 1359 { 1360 int taint = 0; 1361 1362 /* 1363 * The kernel can handle differing I-cache policies, but otherwise 1364 * caches should look identical. Userspace JITs will make use of 1365 * *minLine. 1366 */ 1367 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1368 info->reg_ctr, boot->reg_ctr); 1369 1370 /* 1371 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1372 * could result in too much or too little memory being zeroed if a 1373 * process is preempted and migrated between CPUs. 1374 */ 1375 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1376 info->reg_dczid, boot->reg_dczid); 1377 1378 /* If different, timekeeping will be broken (especially with KVM) */ 1379 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1380 info->reg_cntfrq, boot->reg_cntfrq); 1381 1382 /* 1383 * The kernel uses self-hosted debug features and expects CPUs to 1384 * support identical debug features. We presently need CTX_CMPs, WRPs, 1385 * and BRPs to be identical. 1386 * ID_AA64DFR1 is currently RES0. 1387 */ 1388 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1389 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1390 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1391 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1392 /* 1393 * Even in big.LITTLE, processors should be identical instruction-set 1394 * wise. 1395 */ 1396 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1397 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1398 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1399 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1400 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1401 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1402 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1403 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1404 1405 /* 1406 * Differing PARange support is fine as long as all peripherals and 1407 * memory are mapped within the minimum PARange of all CPUs. 1408 * Linux should not care about secure memory. 1409 */ 1410 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1411 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1412 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1413 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1414 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1415 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1416 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1417 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1418 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1419 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1420 1421 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1422 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1423 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1424 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1425 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1426 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1427 1428 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1429 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1430 1431 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1432 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1433 1434 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1435 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1436 1437 /* Probe vector lengths */ 1438 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1439 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1440 if (!system_capabilities_finalized()) { 1441 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1442 1443 vec_update_vq_map(ARM64_VEC_SVE); 1444 1445 cpacr_restore(cpacr); 1446 } 1447 } 1448 1449 if (IS_ENABLED(CONFIG_ARM64_SME) && 1450 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1451 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1452 1453 /* Probe vector lengths */ 1454 if (!system_capabilities_finalized()) 1455 vec_update_vq_map(ARM64_VEC_SME); 1456 1457 cpacr_restore(cpacr); 1458 } 1459 1460 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1461 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1462 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1463 info->reg_mpamidr, boot->reg_mpamidr); 1464 } 1465 1466 /* 1467 * The kernel uses the LDGM/STGM instructions and the number of tags 1468 * they read/write depends on the GMID_EL1.BS field. Check that the 1469 * value is the same on all CPUs. 1470 */ 1471 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1472 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1473 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1474 info->reg_gmid, boot->reg_gmid); 1475 } 1476 1477 /* 1478 * If we don't have AArch32 at all then skip the checks entirely 1479 * as the register values may be UNKNOWN and we're not going to be 1480 * using them for anything. 1481 * 1482 * This relies on a sanitised view of the AArch64 ID registers 1483 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1484 */ 1485 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1486 lazy_init_32bit_cpu_features(info, boot); 1487 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1488 &boot->aarch32); 1489 } 1490 1491 /* 1492 * Mismatched CPU features are a recipe for disaster. Don't even 1493 * pretend to support them. 1494 */ 1495 if (taint) { 1496 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1497 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1498 } 1499 } 1500 1501 u64 read_sanitised_ftr_reg(u32 id) 1502 { 1503 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1504 1505 if (!regp) 1506 return 0; 1507 return regp->sys_val; 1508 } 1509 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1510 1511 #define read_sysreg_case(r) \ 1512 case r: val = read_sysreg_s(r); break; 1513 1514 /* 1515 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1516 * Read the system register on the current CPU 1517 */ 1518 u64 __read_sysreg_by_encoding(u32 sys_id) 1519 { 1520 struct arm64_ftr_reg *regp; 1521 u64 val; 1522 1523 switch (sys_id) { 1524 read_sysreg_case(SYS_ID_PFR0_EL1); 1525 read_sysreg_case(SYS_ID_PFR1_EL1); 1526 read_sysreg_case(SYS_ID_PFR2_EL1); 1527 read_sysreg_case(SYS_ID_DFR0_EL1); 1528 read_sysreg_case(SYS_ID_DFR1_EL1); 1529 read_sysreg_case(SYS_ID_MMFR0_EL1); 1530 read_sysreg_case(SYS_ID_MMFR1_EL1); 1531 read_sysreg_case(SYS_ID_MMFR2_EL1); 1532 read_sysreg_case(SYS_ID_MMFR3_EL1); 1533 read_sysreg_case(SYS_ID_MMFR4_EL1); 1534 read_sysreg_case(SYS_ID_MMFR5_EL1); 1535 read_sysreg_case(SYS_ID_ISAR0_EL1); 1536 read_sysreg_case(SYS_ID_ISAR1_EL1); 1537 read_sysreg_case(SYS_ID_ISAR2_EL1); 1538 read_sysreg_case(SYS_ID_ISAR3_EL1); 1539 read_sysreg_case(SYS_ID_ISAR4_EL1); 1540 read_sysreg_case(SYS_ID_ISAR5_EL1); 1541 read_sysreg_case(SYS_ID_ISAR6_EL1); 1542 read_sysreg_case(SYS_MVFR0_EL1); 1543 read_sysreg_case(SYS_MVFR1_EL1); 1544 read_sysreg_case(SYS_MVFR2_EL1); 1545 1546 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1547 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1548 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1549 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1550 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1551 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1552 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1553 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1554 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1556 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1557 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1558 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1559 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1560 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1561 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1562 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1563 1564 read_sysreg_case(SYS_CNTFRQ_EL0); 1565 read_sysreg_case(SYS_CTR_EL0); 1566 read_sysreg_case(SYS_DCZID_EL0); 1567 1568 default: 1569 BUG(); 1570 return 0; 1571 } 1572 1573 regp = get_arm64_ftr_reg(sys_id); 1574 if (regp) { 1575 val &= ~regp->override->mask; 1576 val |= (regp->override->val & regp->override->mask); 1577 } 1578 1579 return val; 1580 } 1581 1582 #include <linux/irqchip/arm-gic-v3.h> 1583 1584 static bool 1585 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1586 { 1587 return true; 1588 } 1589 1590 static bool 1591 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1592 { 1593 int val, min, max; 1594 u64 tmp; 1595 1596 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1597 entry->field_width, 1598 entry->sign); 1599 1600 tmp = entry->min_field_value; 1601 tmp <<= entry->field_pos; 1602 1603 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1604 entry->field_width, 1605 entry->sign); 1606 1607 tmp = entry->max_field_value; 1608 tmp <<= entry->field_pos; 1609 1610 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1611 entry->field_width, 1612 entry->sign); 1613 1614 return val >= min && val <= max; 1615 } 1616 1617 static u64 1618 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1619 { 1620 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1621 if (scope == SCOPE_SYSTEM) 1622 return read_sanitised_ftr_reg(entry->sys_reg); 1623 else 1624 return __read_sysreg_by_encoding(entry->sys_reg); 1625 } 1626 1627 static bool 1628 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1629 { 1630 int mask; 1631 struct arm64_ftr_reg *regp; 1632 u64 val = read_scoped_sysreg(entry, scope); 1633 1634 regp = get_arm64_ftr_reg(entry->sys_reg); 1635 if (!regp) 1636 return false; 1637 1638 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1639 entry->field_pos, 1640 entry->field_width); 1641 if (!mask) 1642 return false; 1643 1644 return feature_matches(val, entry); 1645 } 1646 1647 static bool 1648 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1649 { 1650 u64 val = read_scoped_sysreg(entry, scope); 1651 return feature_matches(val, entry); 1652 } 1653 1654 const struct cpumask *system_32bit_el0_cpumask(void) 1655 { 1656 if (!system_supports_32bit_el0()) 1657 return cpu_none_mask; 1658 1659 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1660 return cpu_32bit_el0_mask; 1661 1662 return cpu_possible_mask; 1663 } 1664 1665 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1666 { 1667 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1668 } 1669 1670 static int __init parse_32bit_el0_param(char *str) 1671 { 1672 allow_mismatched_32bit_el0 = true; 1673 return 0; 1674 } 1675 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1676 1677 static ssize_t aarch32_el0_show(struct device *dev, 1678 struct device_attribute *attr, char *buf) 1679 { 1680 const struct cpumask *mask = system_32bit_el0_cpumask(); 1681 1682 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1683 } 1684 static const DEVICE_ATTR_RO(aarch32_el0); 1685 1686 static int __init aarch32_el0_sysfs_init(void) 1687 { 1688 struct device *dev_root; 1689 int ret = 0; 1690 1691 if (!allow_mismatched_32bit_el0) 1692 return 0; 1693 1694 dev_root = bus_get_dev_root(&cpu_subsys); 1695 if (dev_root) { 1696 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1697 put_device(dev_root); 1698 } 1699 return ret; 1700 } 1701 device_initcall(aarch32_el0_sysfs_init); 1702 1703 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1704 { 1705 if (!has_cpuid_feature(entry, scope)) 1706 return allow_mismatched_32bit_el0; 1707 1708 if (scope == SCOPE_SYSTEM) 1709 pr_info("detected: 32-bit EL0 Support\n"); 1710 1711 return true; 1712 } 1713 1714 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1715 { 1716 bool has_sre; 1717 1718 if (!has_cpuid_feature(entry, scope)) 1719 return false; 1720 1721 has_sre = gic_enable_sre(); 1722 if (!has_sre) 1723 pr_warn_once("%s present but disabled by higher exception level\n", 1724 entry->desc); 1725 1726 return has_sre; 1727 } 1728 1729 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1730 int scope) 1731 { 1732 u64 ctr; 1733 1734 if (scope == SCOPE_SYSTEM) 1735 ctr = arm64_ftr_reg_ctrel0.sys_val; 1736 else 1737 ctr = read_cpuid_effective_cachetype(); 1738 1739 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1740 } 1741 1742 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1743 { 1744 /* 1745 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1746 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1747 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1748 * value. 1749 */ 1750 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1751 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1752 } 1753 1754 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1755 int scope) 1756 { 1757 u64 ctr; 1758 1759 if (scope == SCOPE_SYSTEM) 1760 ctr = arm64_ftr_reg_ctrel0.sys_val; 1761 else 1762 ctr = read_cpuid_cachetype(); 1763 1764 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1765 } 1766 1767 static bool __maybe_unused 1768 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1769 { 1770 /* 1771 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1772 * may share TLB entries with a CPU stuck in the crashed 1773 * kernel. 1774 */ 1775 if (is_kdump_kernel()) 1776 return false; 1777 1778 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1779 return false; 1780 1781 return has_cpuid_feature(entry, scope); 1782 } 1783 1784 static bool __meltdown_safe = true; 1785 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1786 1787 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1788 int scope) 1789 { 1790 /* List of CPUs that are not vulnerable and don't need KPTI */ 1791 static const struct midr_range kpti_safe_list[] = { 1792 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1793 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1794 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1795 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1796 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1797 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1798 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1799 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1800 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1801 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1802 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1803 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1804 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1805 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1806 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1807 { /* sentinel */ } 1808 }; 1809 char const *str = "kpti command line option"; 1810 bool meltdown_safe; 1811 1812 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1813 1814 /* Defer to CPU feature registers */ 1815 if (has_cpuid_feature(entry, scope)) 1816 meltdown_safe = true; 1817 1818 if (!meltdown_safe) 1819 __meltdown_safe = false; 1820 1821 /* 1822 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1823 * ThunderX leads to apparent I-cache corruption of kernel text, which 1824 * ends as well as you might imagine. Don't even try. We cannot rely 1825 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1826 * because cpucap detection order may change. However, since we know 1827 * affected CPUs are always in a homogeneous configuration, it is 1828 * safe to rely on this_cpu_has_cap() here. 1829 */ 1830 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1831 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1832 __kpti_forced = -1; 1833 } 1834 1835 /* Useful for KASLR robustness */ 1836 if (kaslr_enabled() && kaslr_requires_kpti()) { 1837 if (!__kpti_forced) { 1838 str = "KASLR"; 1839 __kpti_forced = 1; 1840 } 1841 } 1842 1843 if (cpu_mitigations_off() && !__kpti_forced) { 1844 str = "mitigations=off"; 1845 __kpti_forced = -1; 1846 } 1847 1848 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1849 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1850 return false; 1851 } 1852 1853 /* Forced? */ 1854 if (__kpti_forced) { 1855 pr_info_once("kernel page table isolation forced %s by %s\n", 1856 __kpti_forced > 0 ? "ON" : "OFF", str); 1857 return __kpti_forced > 0; 1858 } 1859 1860 return !meltdown_safe; 1861 } 1862 1863 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1864 { 1865 /* 1866 * Although the Apple M2 family appears to support NV1, the 1867 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1868 * that it doesn't support NV1 at all. 1869 */ 1870 static const struct midr_range nv1_ni_list[] = { 1871 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1872 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1873 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1874 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1875 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1876 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1877 {} 1878 }; 1879 1880 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1881 !(has_cpuid_feature(entry, scope) || 1882 is_midr_in_range_list(nv1_ni_list))); 1883 } 1884 1885 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1886 static bool has_lpa2_at_stage1(u64 mmfr0) 1887 { 1888 unsigned int tgran; 1889 1890 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1891 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1892 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1893 } 1894 1895 static bool has_lpa2_at_stage2(u64 mmfr0) 1896 { 1897 unsigned int tgran; 1898 1899 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1900 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1901 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1902 } 1903 1904 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1905 { 1906 u64 mmfr0; 1907 1908 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1909 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1910 } 1911 #else 1912 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1913 { 1914 return false; 1915 } 1916 #endif 1917 1918 #ifdef CONFIG_HW_PERF_EVENTS 1919 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1920 { 1921 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1922 unsigned int pmuver; 1923 1924 /* 1925 * PMUVer follows the standard ID scheme for an unsigned field with the 1926 * exception of 0xF (IMP_DEF) which is treated specially and implies 1927 * FEAT_PMUv3 is not implemented. 1928 * 1929 * See DDI0487L.a D24.1.3.2 for more details. 1930 */ 1931 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1932 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1933 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1934 return false; 1935 1936 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1937 } 1938 #endif 1939 1940 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1941 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1942 1943 extern 1944 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1945 phys_addr_t size, pgprot_t prot, 1946 phys_addr_t (*pgtable_alloc)(int), int flags); 1947 1948 static phys_addr_t __initdata kpti_ng_temp_alloc; 1949 1950 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1951 { 1952 kpti_ng_temp_alloc -= PAGE_SIZE; 1953 return kpti_ng_temp_alloc; 1954 } 1955 1956 static int __init __kpti_install_ng_mappings(void *__unused) 1957 { 1958 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1959 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1960 kpti_remap_fn *remap_fn; 1961 1962 int cpu = smp_processor_id(); 1963 int levels = CONFIG_PGTABLE_LEVELS; 1964 int order = order_base_2(levels); 1965 u64 kpti_ng_temp_pgd_pa = 0; 1966 pgd_t *kpti_ng_temp_pgd; 1967 u64 alloc = 0; 1968 1969 if (levels == 5 && !pgtable_l5_enabled()) 1970 levels = 4; 1971 else if (levels == 4 && !pgtable_l4_enabled()) 1972 levels = 3; 1973 1974 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1975 1976 if (!cpu) { 1977 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1978 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1979 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1980 1981 // 1982 // Create a minimal page table hierarchy that permits us to map 1983 // the swapper page tables temporarily as we traverse them. 1984 // 1985 // The physical pages are laid out as follows: 1986 // 1987 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1988 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1989 // +--------+-\-------+-\------ +-\------ +-///--------+ 1990 // ^ 1991 // The first page is mapped into this hierarchy at a PMD_SHIFT 1992 // aligned virtual address, so that we can manipulate the PTE 1993 // level entries while the mapping is active. The first entry 1994 // covers the PTE[] page itself, the remaining entries are free 1995 // to be used as a ad-hoc fixmap. 1996 // 1997 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1998 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1999 kpti_ng_pgd_alloc, 0); 2000 } 2001 2002 cpu_install_idmap(); 2003 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 2004 cpu_uninstall_idmap(); 2005 2006 if (!cpu) { 2007 free_pages(alloc, order); 2008 arm64_use_ng_mappings = true; 2009 } 2010 2011 return 0; 2012 } 2013 2014 static void __init kpti_install_ng_mappings(void) 2015 { 2016 /* Check whether KPTI is going to be used */ 2017 if (!arm64_kernel_unmapped_at_el0()) 2018 return; 2019 2020 /* 2021 * We don't need to rewrite the page-tables if either we've done 2022 * it already or we have KASLR enabled and therefore have not 2023 * created any global mappings at all. 2024 */ 2025 if (arm64_use_ng_mappings) 2026 return; 2027 2028 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 2029 } 2030 2031 #else 2032 static inline void kpti_install_ng_mappings(void) 2033 { 2034 } 2035 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 2036 2037 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 2038 { 2039 if (__this_cpu_read(this_cpu_vector) == vectors) { 2040 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2041 2042 __this_cpu_write(this_cpu_vector, v); 2043 } 2044 2045 } 2046 2047 static int __init parse_kpti(char *str) 2048 { 2049 bool enabled; 2050 int ret = kstrtobool(str, &enabled); 2051 2052 if (ret) 2053 return ret; 2054 2055 __kpti_forced = enabled ? 1 : -1; 2056 return 0; 2057 } 2058 early_param("kpti", parse_kpti); 2059 2060 #ifdef CONFIG_ARM64_HW_AFDBM 2061 static struct cpumask dbm_cpus __read_mostly; 2062 2063 static inline void __cpu_enable_hw_dbm(void) 2064 { 2065 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2066 2067 write_sysreg(tcr, tcr_el1); 2068 isb(); 2069 local_flush_tlb_all(); 2070 } 2071 2072 static bool cpu_has_broken_dbm(void) 2073 { 2074 /* List of CPUs which have broken DBM support. */ 2075 static const struct midr_range cpus[] = { 2076 #ifdef CONFIG_ARM64_ERRATUM_1024718 2077 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2078 /* Kryo4xx Silver (rdpe => r1p0) */ 2079 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2080 #endif 2081 #ifdef CONFIG_ARM64_ERRATUM_2051678 2082 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2083 #endif 2084 {}, 2085 }; 2086 2087 return is_midr_in_range_list(cpus); 2088 } 2089 2090 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2091 { 2092 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2093 !cpu_has_broken_dbm(); 2094 } 2095 2096 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2097 { 2098 if (cpu_can_use_dbm(cap)) { 2099 __cpu_enable_hw_dbm(); 2100 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2101 } 2102 } 2103 2104 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2105 int __unused) 2106 { 2107 /* 2108 * DBM is a non-conflicting feature. i.e, the kernel can safely 2109 * run a mix of CPUs with and without the feature. So, we 2110 * unconditionally enable the capability to allow any late CPU 2111 * to use the feature. We only enable the control bits on the 2112 * CPU, if it is supported. 2113 */ 2114 2115 return true; 2116 } 2117 2118 #endif 2119 2120 #ifdef CONFIG_ARM64_AMU_EXTN 2121 2122 /* 2123 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2124 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2125 * information regarding all the events that it supports. When a CPU bit is 2126 * set in the cpumask, the user of this feature can only rely on the presence 2127 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2128 * counters are enabled or access to these counters is enabled by code 2129 * executed at higher exception levels (firmware). 2130 */ 2131 static struct cpumask amu_cpus __read_mostly; 2132 2133 bool cpu_has_amu_feat(int cpu) 2134 { 2135 return cpumask_test_cpu(cpu, &amu_cpus); 2136 } 2137 2138 int get_cpu_with_amu_feat(void) 2139 { 2140 return cpumask_any(&amu_cpus); 2141 } 2142 2143 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2144 { 2145 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2146 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2147 2148 /* 0 reference values signal broken/disabled counters */ 2149 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2150 update_freq_counters_refs(); 2151 } 2152 } 2153 2154 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2155 int __unused) 2156 { 2157 /* 2158 * The AMU extension is a non-conflicting feature: the kernel can 2159 * safely run a mix of CPUs with and without support for the 2160 * activity monitors extension. Therefore, unconditionally enable 2161 * the capability to allow any late CPU to use the feature. 2162 * 2163 * With this feature unconditionally enabled, the cpu_enable 2164 * function will be called for all CPUs that match the criteria, 2165 * including secondary and hotplugged, marking this feature as 2166 * present on that respective CPU. The enable function will also 2167 * print a detection message. 2168 */ 2169 2170 return true; 2171 } 2172 #else 2173 int get_cpu_with_amu_feat(void) 2174 { 2175 return nr_cpu_ids; 2176 } 2177 #endif 2178 2179 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2180 { 2181 return is_kernel_in_hyp_mode(); 2182 } 2183 2184 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2185 { 2186 /* 2187 * Copy register values that aren't redirected by hardware. 2188 * 2189 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2190 * this value to tpidr_el2 before we patch the code. Once we've done 2191 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2192 * do anything here. 2193 */ 2194 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2195 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2196 } 2197 2198 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2199 int scope) 2200 { 2201 if (kvm_get_mode() != KVM_MODE_NV) 2202 return false; 2203 2204 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2205 pr_warn("unavailable: %s\n", cap->desc); 2206 return false; 2207 } 2208 2209 return true; 2210 } 2211 2212 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2213 int __unused) 2214 { 2215 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2216 } 2217 2218 #ifdef CONFIG_ARM64_PAN 2219 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2220 { 2221 /* 2222 * We modify PSTATE. This won't work from irq context as the PSTATE 2223 * is discarded once we return from the exception. 2224 */ 2225 WARN_ON_ONCE(in_interrupt()); 2226 2227 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2228 set_pstate_pan(1); 2229 } 2230 #endif /* CONFIG_ARM64_PAN */ 2231 2232 #ifdef CONFIG_ARM64_RAS_EXTN 2233 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2234 { 2235 /* Firmware may have left a deferred SError in this register. */ 2236 write_sysreg_s(0, SYS_DISR_EL1); 2237 } 2238 #endif /* CONFIG_ARM64_RAS_EXTN */ 2239 2240 #ifdef CONFIG_ARM64_PTR_AUTH 2241 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2242 { 2243 int boot_val, sec_val; 2244 2245 /* We don't expect to be called with SCOPE_SYSTEM */ 2246 WARN_ON(scope == SCOPE_SYSTEM); 2247 /* 2248 * The ptr-auth feature levels are not intercompatible with lower 2249 * levels. Hence we must match ptr-auth feature level of the secondary 2250 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2251 * from the sanitised register whereas direct register read is done for 2252 * the secondary CPUs. 2253 * The sanitised feature state is guaranteed to match that of the 2254 * boot CPU as a mismatched secondary CPU is parked before it gets 2255 * a chance to update the state, with the capability. 2256 */ 2257 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2258 entry->field_pos, entry->sign); 2259 if (scope & SCOPE_BOOT_CPU) 2260 return boot_val >= entry->min_field_value; 2261 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2262 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2263 entry->field_pos, entry->sign); 2264 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2265 } 2266 2267 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2268 int scope) 2269 { 2270 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2271 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2272 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2273 2274 return apa || apa3 || api; 2275 } 2276 2277 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2278 int __unused) 2279 { 2280 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2281 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2282 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2283 2284 return gpa || gpa3 || gpi; 2285 } 2286 #endif /* CONFIG_ARM64_PTR_AUTH */ 2287 2288 #ifdef CONFIG_ARM64_E0PD 2289 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2290 { 2291 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2292 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2293 } 2294 #endif /* CONFIG_ARM64_E0PD */ 2295 2296 #ifdef CONFIG_ARM64_PSEUDO_NMI 2297 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2298 int scope) 2299 { 2300 /* 2301 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2302 * feature, so will be detected earlier. 2303 */ 2304 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2305 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2306 return false; 2307 2308 return enable_pseudo_nmi; 2309 } 2310 2311 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2312 int scope) 2313 { 2314 /* 2315 * If we're not using priority masking then we won't be poking PMR_EL1, 2316 * and there's no need to relax synchronization of writes to it, and 2317 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2318 * that. 2319 * 2320 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2321 * feature, so will be detected earlier. 2322 */ 2323 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2324 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2325 return false; 2326 2327 /* 2328 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2329 * hint for interrupt distribution, a DSB is not necessary when 2330 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2331 * 2332 * Linux itself doesn't use 1:N distribution, so has no need to 2333 * set PMHE. The only reason to have it set is if EL3 requires it 2334 * (and we can't change it). 2335 */ 2336 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2337 } 2338 #endif 2339 2340 #ifdef CONFIG_ARM64_BTI 2341 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2342 { 2343 /* 2344 * Use of X16/X17 for tail-calls and trampolines that jump to 2345 * function entry points using BR is a requirement for 2346 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2347 * So, be strict and forbid other BRs using other registers to 2348 * jump onto a PACIxSP instruction: 2349 */ 2350 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2351 isb(); 2352 } 2353 #endif /* CONFIG_ARM64_BTI */ 2354 2355 #ifdef CONFIG_ARM64_MTE 2356 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2357 { 2358 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2359 2360 mte_cpu_setup(); 2361 2362 /* 2363 * Clear the tags in the zero page. This needs to be done via the 2364 * linear map which has the Tagged attribute. 2365 */ 2366 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2367 mte_clear_page_tags(lm_alias(empty_zero_page)); 2368 set_page_mte_tagged(ZERO_PAGE(0)); 2369 } 2370 2371 kasan_init_hw_tags_cpu(); 2372 } 2373 #endif /* CONFIG_ARM64_MTE */ 2374 2375 static void user_feature_fixup(void) 2376 { 2377 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2378 struct arm64_ftr_reg *regp; 2379 2380 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2381 if (regp) 2382 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2383 } 2384 2385 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2386 struct arm64_ftr_reg *regp; 2387 2388 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2389 if (regp) 2390 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2391 } 2392 } 2393 2394 static void elf_hwcap_fixup(void) 2395 { 2396 #ifdef CONFIG_COMPAT 2397 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2398 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2399 #endif /* CONFIG_COMPAT */ 2400 } 2401 2402 #ifdef CONFIG_KVM 2403 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2404 { 2405 return kvm_get_mode() == KVM_MODE_PROTECTED; 2406 } 2407 #endif /* CONFIG_KVM */ 2408 2409 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2410 { 2411 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2412 } 2413 2414 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2415 { 2416 set_pstate_dit(1); 2417 } 2418 2419 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2420 { 2421 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2422 } 2423 2424 #ifdef CONFIG_ARM64_POE 2425 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2426 { 2427 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2428 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2429 } 2430 #endif 2431 2432 #ifdef CONFIG_ARM64_GCS 2433 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2434 { 2435 /* GCSPR_EL0 is always readable */ 2436 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2437 } 2438 #endif 2439 2440 /* Internal helper functions to match cpu capability type */ 2441 static bool 2442 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2443 { 2444 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2445 } 2446 2447 static bool 2448 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2449 { 2450 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2451 } 2452 2453 static bool 2454 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2455 { 2456 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2457 } 2458 2459 static bool 2460 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2461 { 2462 if (!has_cpuid_feature(entry, scope)) 2463 return false; 2464 2465 /* Check firmware actually enabled MPAM on this cpu. */ 2466 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2467 } 2468 2469 static void 2470 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2471 { 2472 /* 2473 * Access by the kernel (at EL1) should use the reserved PARTID 2474 * which is configured unrestricted. This avoids priority-inversion 2475 * where latency sensitive tasks have to wait for a task that has 2476 * been throttled to release the lock. 2477 */ 2478 write_sysreg_s(0, SYS_MPAM1_EL1); 2479 } 2480 2481 static bool 2482 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2483 { 2484 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2485 2486 return idr & MPAMIDR_EL1_HAS_HCR; 2487 } 2488 2489 static const struct arm64_cpu_capabilities arm64_features[] = { 2490 { 2491 .capability = ARM64_ALWAYS_BOOT, 2492 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2493 .matches = has_always, 2494 }, 2495 { 2496 .capability = ARM64_ALWAYS_SYSTEM, 2497 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2498 .matches = has_always, 2499 }, 2500 { 2501 .desc = "GIC system register CPU interface", 2502 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2503 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2504 .matches = has_useable_gicv3_cpuif, 2505 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2506 }, 2507 { 2508 .desc = "Enhanced Counter Virtualization", 2509 .capability = ARM64_HAS_ECV, 2510 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2511 .matches = has_cpuid_feature, 2512 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2513 }, 2514 { 2515 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2516 .capability = ARM64_HAS_ECV_CNTPOFF, 2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2518 .matches = has_cpuid_feature, 2519 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2520 }, 2521 #ifdef CONFIG_ARM64_PAN 2522 { 2523 .desc = "Privileged Access Never", 2524 .capability = ARM64_HAS_PAN, 2525 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2526 .matches = has_cpuid_feature, 2527 .cpu_enable = cpu_enable_pan, 2528 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2529 }, 2530 #endif /* CONFIG_ARM64_PAN */ 2531 #ifdef CONFIG_ARM64_EPAN 2532 { 2533 .desc = "Enhanced Privileged Access Never", 2534 .capability = ARM64_HAS_EPAN, 2535 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2536 .matches = has_cpuid_feature, 2537 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2538 }, 2539 #endif /* CONFIG_ARM64_EPAN */ 2540 #ifdef CONFIG_ARM64_LSE_ATOMICS 2541 { 2542 .desc = "LSE atomic instructions", 2543 .capability = ARM64_HAS_LSE_ATOMICS, 2544 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2545 .matches = has_cpuid_feature, 2546 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2547 }, 2548 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2549 { 2550 .desc = "Virtualization Host Extensions", 2551 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2552 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2553 .matches = runs_at_el2, 2554 .cpu_enable = cpu_copy_el2regs, 2555 }, 2556 { 2557 .desc = "Nested Virtualization Support", 2558 .capability = ARM64_HAS_NESTED_VIRT, 2559 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2560 .matches = has_nested_virt_support, 2561 .match_list = (const struct arm64_cpu_capabilities []){ 2562 { 2563 .matches = has_cpuid_feature, 2564 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2565 }, 2566 { 2567 .matches = has_cpuid_feature, 2568 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2569 }, 2570 { /* Sentinel */ } 2571 }, 2572 }, 2573 { 2574 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2576 .matches = has_32bit_el0, 2577 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2578 }, 2579 #ifdef CONFIG_KVM 2580 { 2581 .desc = "32-bit EL1 Support", 2582 .capability = ARM64_HAS_32BIT_EL1, 2583 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2584 .matches = has_cpuid_feature, 2585 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2586 }, 2587 { 2588 .desc = "Protected KVM", 2589 .capability = ARM64_KVM_PROTECTED_MODE, 2590 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2591 .matches = is_kvm_protected_mode, 2592 }, 2593 { 2594 .desc = "HCRX_EL2 register", 2595 .capability = ARM64_HAS_HCX, 2596 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2597 .matches = has_cpuid_feature, 2598 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2599 }, 2600 #endif 2601 { 2602 .desc = "Kernel page table isolation (KPTI)", 2603 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2604 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2605 .cpu_enable = cpu_enable_kpti, 2606 .matches = unmap_kernel_at_el0, 2607 /* 2608 * The ID feature fields below are used to indicate that 2609 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2610 * more details. 2611 */ 2612 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2613 }, 2614 { 2615 .capability = ARM64_HAS_FPSIMD, 2616 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2617 .matches = has_cpuid_feature, 2618 .cpu_enable = cpu_enable_fpsimd, 2619 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2620 }, 2621 #ifdef CONFIG_ARM64_PMEM 2622 { 2623 .desc = "Data cache clean to Point of Persistence", 2624 .capability = ARM64_HAS_DCPOP, 2625 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2626 .matches = has_cpuid_feature, 2627 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2628 }, 2629 { 2630 .desc = "Data cache clean to Point of Deep Persistence", 2631 .capability = ARM64_HAS_DCPODP, 2632 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2633 .matches = has_cpuid_feature, 2634 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2635 }, 2636 #endif 2637 #ifdef CONFIG_ARM64_SVE 2638 { 2639 .desc = "Scalable Vector Extension", 2640 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2641 .capability = ARM64_SVE, 2642 .cpu_enable = cpu_enable_sve, 2643 .matches = has_cpuid_feature, 2644 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2645 }, 2646 #endif /* CONFIG_ARM64_SVE */ 2647 #ifdef CONFIG_ARM64_RAS_EXTN 2648 { 2649 .desc = "RAS Extension Support", 2650 .capability = ARM64_HAS_RAS_EXTN, 2651 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2652 .matches = has_cpuid_feature, 2653 .cpu_enable = cpu_clear_disr, 2654 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2655 }, 2656 #endif /* CONFIG_ARM64_RAS_EXTN */ 2657 #ifdef CONFIG_ARM64_AMU_EXTN 2658 { 2659 .desc = "Activity Monitors Unit (AMU)", 2660 .capability = ARM64_HAS_AMU_EXTN, 2661 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2662 .matches = has_amu, 2663 .cpu_enable = cpu_amu_enable, 2664 .cpus = &amu_cpus, 2665 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2666 }, 2667 #endif /* CONFIG_ARM64_AMU_EXTN */ 2668 { 2669 .desc = "Data cache clean to the PoU not required for I/D coherence", 2670 .capability = ARM64_HAS_CACHE_IDC, 2671 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2672 .matches = has_cache_idc, 2673 .cpu_enable = cpu_emulate_effective_ctr, 2674 }, 2675 { 2676 .desc = "Instruction cache invalidation not required for I/D coherence", 2677 .capability = ARM64_HAS_CACHE_DIC, 2678 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2679 .matches = has_cache_dic, 2680 }, 2681 { 2682 .desc = "Stage-2 Force Write-Back", 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .capability = ARM64_HAS_STAGE2_FWB, 2685 .matches = has_cpuid_feature, 2686 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2687 }, 2688 { 2689 .desc = "ARMv8.4 Translation Table Level", 2690 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2691 .capability = ARM64_HAS_ARMv8_4_TTL, 2692 .matches = has_cpuid_feature, 2693 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2694 }, 2695 { 2696 .desc = "TLB range maintenance instructions", 2697 .capability = ARM64_HAS_TLB_RANGE, 2698 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2699 .matches = has_cpuid_feature, 2700 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2701 }, 2702 #ifdef CONFIG_ARM64_HW_AFDBM 2703 { 2704 .desc = "Hardware dirty bit management", 2705 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2706 .capability = ARM64_HW_DBM, 2707 .matches = has_hw_dbm, 2708 .cpu_enable = cpu_enable_hw_dbm, 2709 .cpus = &dbm_cpus, 2710 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2711 }, 2712 #endif 2713 #ifdef CONFIG_ARM64_HAFT 2714 { 2715 .desc = "Hardware managed Access Flag for Table Descriptors", 2716 /* 2717 * Contrary to the page/block access flag, the table access flag 2718 * cannot be emulated in software (no access fault will occur). 2719 * Therefore this should be used only if it's supported system 2720 * wide. 2721 */ 2722 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2723 .capability = ARM64_HAFT, 2724 .matches = has_cpuid_feature, 2725 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2726 }, 2727 #endif 2728 { 2729 .desc = "CRC32 instructions", 2730 .capability = ARM64_HAS_CRC32, 2731 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2732 .matches = has_cpuid_feature, 2733 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2734 }, 2735 { 2736 .desc = "Speculative Store Bypassing Safe (SSBS)", 2737 .capability = ARM64_SSBS, 2738 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2739 .matches = has_cpuid_feature, 2740 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2741 }, 2742 #ifdef CONFIG_ARM64_CNP 2743 { 2744 .desc = "Common not Private translations", 2745 .capability = ARM64_HAS_CNP, 2746 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2747 .matches = has_useable_cnp, 2748 .cpu_enable = cpu_enable_cnp, 2749 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2750 }, 2751 #endif 2752 { 2753 .desc = "Speculation barrier (SB)", 2754 .capability = ARM64_HAS_SB, 2755 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2756 .matches = has_cpuid_feature, 2757 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2758 }, 2759 #ifdef CONFIG_ARM64_PTR_AUTH 2760 { 2761 .desc = "Address authentication (architected QARMA5 algorithm)", 2762 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2763 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2764 .matches = has_address_auth_cpucap, 2765 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2766 }, 2767 { 2768 .desc = "Address authentication (architected QARMA3 algorithm)", 2769 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2770 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2771 .matches = has_address_auth_cpucap, 2772 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2773 }, 2774 { 2775 .desc = "Address authentication (IMP DEF algorithm)", 2776 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2777 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2778 .matches = has_address_auth_cpucap, 2779 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2780 }, 2781 { 2782 .capability = ARM64_HAS_ADDRESS_AUTH, 2783 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2784 .matches = has_address_auth_metacap, 2785 }, 2786 { 2787 .desc = "Generic authentication (architected QARMA5 algorithm)", 2788 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2789 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2792 }, 2793 { 2794 .desc = "Generic authentication (architected QARMA3 algorithm)", 2795 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2796 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2797 .matches = has_cpuid_feature, 2798 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2799 }, 2800 { 2801 .desc = "Generic authentication (IMP DEF algorithm)", 2802 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2803 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2804 .matches = has_cpuid_feature, 2805 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2806 }, 2807 { 2808 .capability = ARM64_HAS_GENERIC_AUTH, 2809 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2810 .matches = has_generic_auth, 2811 }, 2812 #endif /* CONFIG_ARM64_PTR_AUTH */ 2813 #ifdef CONFIG_ARM64_PSEUDO_NMI 2814 { 2815 /* 2816 * Depends on having GICv3 2817 */ 2818 .desc = "IRQ priority masking", 2819 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2820 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2821 .matches = can_use_gic_priorities, 2822 }, 2823 { 2824 /* 2825 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2826 */ 2827 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2828 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2829 .matches = has_gic_prio_relaxed_sync, 2830 }, 2831 #endif 2832 #ifdef CONFIG_ARM64_E0PD 2833 { 2834 .desc = "E0PD", 2835 .capability = ARM64_HAS_E0PD, 2836 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2837 .cpu_enable = cpu_enable_e0pd, 2838 .matches = has_cpuid_feature, 2839 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2840 }, 2841 #endif 2842 { 2843 .desc = "Random Number Generator", 2844 .capability = ARM64_HAS_RNG, 2845 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2846 .matches = has_cpuid_feature, 2847 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2848 }, 2849 #ifdef CONFIG_ARM64_BTI 2850 { 2851 .desc = "Branch Target Identification", 2852 .capability = ARM64_BTI, 2853 #ifdef CONFIG_ARM64_BTI_KERNEL 2854 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2855 #else 2856 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2857 #endif 2858 .matches = has_cpuid_feature, 2859 .cpu_enable = bti_enable, 2860 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2861 }, 2862 #endif 2863 #ifdef CONFIG_ARM64_MTE 2864 { 2865 .desc = "Memory Tagging Extension", 2866 .capability = ARM64_MTE, 2867 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2868 .matches = has_cpuid_feature, 2869 .cpu_enable = cpu_enable_mte, 2870 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2871 }, 2872 { 2873 .desc = "Asymmetric MTE Tag Check Fault", 2874 .capability = ARM64_MTE_ASYMM, 2875 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2876 .matches = has_cpuid_feature, 2877 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2878 }, 2879 { 2880 .desc = "FAR on MTE Tag Check Fault", 2881 .capability = ARM64_MTE_FAR, 2882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2883 .matches = has_cpuid_feature, 2884 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2885 }, 2886 { 2887 .desc = "Store Only MTE Tag Check", 2888 .capability = ARM64_MTE_STORE_ONLY, 2889 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2890 .matches = has_cpuid_feature, 2891 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2892 }, 2893 #endif /* CONFIG_ARM64_MTE */ 2894 { 2895 .desc = "RCpc load-acquire (LDAPR)", 2896 .capability = ARM64_HAS_LDAPR, 2897 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2898 .matches = has_cpuid_feature, 2899 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2900 }, 2901 { 2902 .desc = "Fine Grained Traps", 2903 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2904 .capability = ARM64_HAS_FGT, 2905 .matches = has_cpuid_feature, 2906 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2907 }, 2908 { 2909 .desc = "Fine Grained Traps 2", 2910 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2911 .capability = ARM64_HAS_FGT2, 2912 .matches = has_cpuid_feature, 2913 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2914 }, 2915 #ifdef CONFIG_ARM64_SME 2916 { 2917 .desc = "Scalable Matrix Extension", 2918 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2919 .capability = ARM64_SME, 2920 .matches = has_cpuid_feature, 2921 .cpu_enable = cpu_enable_sme, 2922 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2923 }, 2924 /* FA64 should be sorted after the base SME capability */ 2925 { 2926 .desc = "FA64", 2927 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2928 .capability = ARM64_SME_FA64, 2929 .matches = has_cpuid_feature, 2930 .cpu_enable = cpu_enable_fa64, 2931 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2932 }, 2933 { 2934 .desc = "SME2", 2935 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2936 .capability = ARM64_SME2, 2937 .matches = has_cpuid_feature, 2938 .cpu_enable = cpu_enable_sme2, 2939 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2940 }, 2941 #endif /* CONFIG_ARM64_SME */ 2942 { 2943 .desc = "WFx with timeout", 2944 .capability = ARM64_HAS_WFXT, 2945 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2946 .matches = has_cpuid_feature, 2947 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2948 }, 2949 { 2950 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2951 .capability = ARM64_HAS_TIDCP1, 2952 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2953 .matches = has_cpuid_feature, 2954 .cpu_enable = cpu_trap_el0_impdef, 2955 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2956 }, 2957 { 2958 .desc = "Data independent timing control (DIT)", 2959 .capability = ARM64_HAS_DIT, 2960 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2961 .matches = has_cpuid_feature, 2962 .cpu_enable = cpu_enable_dit, 2963 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2964 }, 2965 { 2966 .desc = "Memory Copy and Memory Set instructions", 2967 .capability = ARM64_HAS_MOPS, 2968 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2969 .matches = has_cpuid_feature, 2970 .cpu_enable = cpu_enable_mops, 2971 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2972 }, 2973 { 2974 .capability = ARM64_HAS_TCR2, 2975 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2976 .matches = has_cpuid_feature, 2977 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2978 }, 2979 { 2980 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2981 .capability = ARM64_HAS_S1PIE, 2982 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2983 .matches = has_cpuid_feature, 2984 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2985 }, 2986 { 2987 .desc = "VHE for hypervisor only", 2988 .capability = ARM64_KVM_HVHE, 2989 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2990 .matches = hvhe_possible, 2991 }, 2992 { 2993 .desc = "Enhanced Virtualization Traps", 2994 .capability = ARM64_HAS_EVT, 2995 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2996 .matches = has_cpuid_feature, 2997 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2998 }, 2999 { 3000 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3001 .capability = ARM64_HAS_LPA2, 3002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3003 .matches = has_lpa2, 3004 }, 3005 { 3006 .desc = "FPMR", 3007 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3008 .capability = ARM64_HAS_FPMR, 3009 .matches = has_cpuid_feature, 3010 .cpu_enable = cpu_enable_fpmr, 3011 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3012 }, 3013 #ifdef CONFIG_ARM64_VA_BITS_52 3014 { 3015 .capability = ARM64_HAS_VA52, 3016 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3017 .matches = has_cpuid_feature, 3018 #ifdef CONFIG_ARM64_64K_PAGES 3019 .desc = "52-bit Virtual Addressing (LVA)", 3020 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3021 #else 3022 .desc = "52-bit Virtual Addressing (LPA2)", 3023 #ifdef CONFIG_ARM64_4K_PAGES 3024 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3025 #else 3026 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3027 #endif 3028 #endif 3029 }, 3030 #endif 3031 { 3032 .desc = "Memory Partitioning And Monitoring", 3033 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3034 .capability = ARM64_MPAM, 3035 .matches = test_has_mpam, 3036 .cpu_enable = cpu_enable_mpam, 3037 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3038 }, 3039 { 3040 .desc = "Memory Partitioning And Monitoring Virtualisation", 3041 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3042 .capability = ARM64_MPAM_HCR, 3043 .matches = test_has_mpam_hcr, 3044 }, 3045 { 3046 .desc = "NV1", 3047 .capability = ARM64_HAS_HCR_NV1, 3048 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3049 .matches = has_nv1, 3050 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3051 }, 3052 #ifdef CONFIG_ARM64_POE 3053 { 3054 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3055 .capability = ARM64_HAS_S1POE, 3056 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3057 .matches = has_cpuid_feature, 3058 .cpu_enable = cpu_enable_poe, 3059 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3060 }, 3061 #endif 3062 #ifdef CONFIG_ARM64_GCS 3063 { 3064 .desc = "Guarded Control Stack (GCS)", 3065 .capability = ARM64_HAS_GCS, 3066 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3067 .cpu_enable = cpu_enable_gcs, 3068 .matches = has_cpuid_feature, 3069 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3070 }, 3071 #endif 3072 #ifdef CONFIG_HW_PERF_EVENTS 3073 { 3074 .desc = "PMUv3", 3075 .capability = ARM64_HAS_PMUV3, 3076 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3077 .matches = has_pmuv3, 3078 }, 3079 #endif 3080 {}, 3081 }; 3082 3083 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3084 .matches = has_user_cpuid_feature, \ 3085 ARM64_CPUID_FIELDS(reg, field, min_value) 3086 3087 #define __HWCAP_CAP(name, cap_type, cap) \ 3088 .desc = name, \ 3089 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3090 .hwcap_type = cap_type, \ 3091 .hwcap = cap, \ 3092 3093 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3094 { \ 3095 __HWCAP_CAP(#cap, cap_type, cap) \ 3096 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3097 } 3098 3099 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3100 { \ 3101 __HWCAP_CAP(#cap, cap_type, cap) \ 3102 .matches = cpucap_multi_entry_cap_matches, \ 3103 .match_list = list, \ 3104 } 3105 3106 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3107 { \ 3108 __HWCAP_CAP(#cap, cap_type, cap) \ 3109 .matches = match, \ 3110 } 3111 3112 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3113 { \ 3114 __HWCAP_CAP(#cap, cap_type, cap) \ 3115 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3116 .matches = match, \ 3117 } 3118 3119 #ifdef CONFIG_ARM64_PTR_AUTH 3120 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3121 { 3122 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3123 }, 3124 { 3125 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3126 }, 3127 { 3128 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3129 }, 3130 {}, 3131 }; 3132 3133 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3134 { 3135 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3136 }, 3137 { 3138 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3139 }, 3140 { 3141 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3142 }, 3143 {}, 3144 }; 3145 #endif 3146 3147 #ifdef CONFIG_ARM64_SVE 3148 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3149 { 3150 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3151 } 3152 #endif 3153 3154 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3155 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3156 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3157 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3158 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3159 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3160 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3161 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3162 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3163 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3164 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3165 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3166 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3167 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3168 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3169 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3170 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3171 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3172 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3173 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3174 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3175 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3176 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3177 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3178 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3179 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3180 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3181 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3182 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3183 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3184 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3185 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3186 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3187 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3188 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3189 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3190 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3191 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3192 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3193 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3194 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3195 #ifdef CONFIG_ARM64_SVE 3196 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3197 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3198 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3199 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3200 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3201 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3202 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3203 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3204 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3205 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3206 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3207 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3208 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3209 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3210 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3211 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3212 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3213 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3214 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3215 #endif 3216 #ifdef CONFIG_ARM64_GCS 3217 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3218 #endif 3219 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3220 #ifdef CONFIG_ARM64_BTI 3221 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3222 #endif 3223 #ifdef CONFIG_ARM64_PTR_AUTH 3224 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3225 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3226 #endif 3227 #ifdef CONFIG_ARM64_MTE 3228 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3229 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3230 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3231 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3232 #endif /* CONFIG_ARM64_MTE */ 3233 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3234 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3235 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3236 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3237 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3238 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3239 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3240 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3241 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3242 #ifdef CONFIG_ARM64_SME 3243 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3244 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3245 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3246 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3247 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3248 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3249 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3250 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3251 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3252 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3253 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3254 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3255 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3256 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3257 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3258 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3259 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3260 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3261 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3262 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3263 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3264 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3265 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3266 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3267 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3268 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3269 #endif /* CONFIG_ARM64_SME */ 3270 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3271 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3272 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3273 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3274 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3275 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3276 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3277 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3278 #ifdef CONFIG_ARM64_POE 3279 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3280 #endif 3281 {}, 3282 }; 3283 3284 #ifdef CONFIG_COMPAT 3285 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3286 { 3287 /* 3288 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3289 * in line with that of arm32 as in vfp_init(). We make sure that the 3290 * check is future proof, by making sure value is non-zero. 3291 */ 3292 u32 mvfr1; 3293 3294 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3295 if (scope == SCOPE_SYSTEM) 3296 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3297 else 3298 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3299 3300 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3301 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3302 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3303 } 3304 #endif 3305 3306 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3307 #ifdef CONFIG_COMPAT 3308 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3309 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3310 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3311 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3312 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3313 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3314 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3315 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3316 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3317 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3318 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3319 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3320 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3321 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3322 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3323 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3324 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3325 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3326 #endif 3327 {}, 3328 }; 3329 3330 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3331 { 3332 switch (cap->hwcap_type) { 3333 case CAP_HWCAP: 3334 cpu_set_feature(cap->hwcap); 3335 break; 3336 #ifdef CONFIG_COMPAT 3337 case CAP_COMPAT_HWCAP: 3338 compat_elf_hwcap |= (u32)cap->hwcap; 3339 break; 3340 case CAP_COMPAT_HWCAP2: 3341 compat_elf_hwcap2 |= (u32)cap->hwcap; 3342 break; 3343 #endif 3344 default: 3345 WARN_ON(1); 3346 break; 3347 } 3348 } 3349 3350 /* Check if we have a particular HWCAP enabled */ 3351 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3352 { 3353 bool rc; 3354 3355 switch (cap->hwcap_type) { 3356 case CAP_HWCAP: 3357 rc = cpu_have_feature(cap->hwcap); 3358 break; 3359 #ifdef CONFIG_COMPAT 3360 case CAP_COMPAT_HWCAP: 3361 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3362 break; 3363 case CAP_COMPAT_HWCAP2: 3364 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3365 break; 3366 #endif 3367 default: 3368 WARN_ON(1); 3369 rc = false; 3370 } 3371 3372 return rc; 3373 } 3374 3375 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3376 { 3377 /* We support emulation of accesses to CPU ID feature registers */ 3378 cpu_set_named_feature(CPUID); 3379 for (; hwcaps->matches; hwcaps++) 3380 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3381 cap_set_elf_hwcap(hwcaps); 3382 } 3383 3384 static void update_cpu_capabilities(u16 scope_mask) 3385 { 3386 int i; 3387 const struct arm64_cpu_capabilities *caps; 3388 3389 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3390 for (i = 0; i < ARM64_NCAPS; i++) { 3391 caps = cpucap_ptrs[i]; 3392 if (!caps || !(caps->type & scope_mask) || 3393 cpus_have_cap(caps->capability) || 3394 !caps->matches(caps, cpucap_default_scope(caps))) 3395 continue; 3396 3397 if (caps->desc && !caps->cpus) 3398 pr_info("detected: %s\n", caps->desc); 3399 3400 __set_bit(caps->capability, system_cpucaps); 3401 3402 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3403 set_bit(caps->capability, boot_cpucaps); 3404 } 3405 } 3406 3407 /* 3408 * Enable all the available capabilities on this CPU. The capabilities 3409 * with BOOT_CPU scope are handled separately and hence skipped here. 3410 */ 3411 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3412 { 3413 int i; 3414 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3415 3416 for_each_available_cap(i) { 3417 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3418 3419 if (WARN_ON(!cap)) 3420 continue; 3421 3422 if (!(cap->type & non_boot_scope)) 3423 continue; 3424 3425 if (cap->cpu_enable) 3426 cap->cpu_enable(cap); 3427 } 3428 return 0; 3429 } 3430 3431 /* 3432 * Run through the enabled capabilities and enable() it on all active 3433 * CPUs 3434 */ 3435 static void __init enable_cpu_capabilities(u16 scope_mask) 3436 { 3437 int i; 3438 const struct arm64_cpu_capabilities *caps; 3439 bool boot_scope; 3440 3441 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3442 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3443 3444 for (i = 0; i < ARM64_NCAPS; i++) { 3445 caps = cpucap_ptrs[i]; 3446 if (!caps || !(caps->type & scope_mask) || 3447 !cpus_have_cap(caps->capability)) 3448 continue; 3449 3450 if (boot_scope && caps->cpu_enable) 3451 /* 3452 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3453 * before any secondary CPU boots. Thus, each secondary 3454 * will enable the capability as appropriate via 3455 * check_local_cpu_capabilities(). The only exception is 3456 * the boot CPU, for which the capability must be 3457 * enabled here. This approach avoids costly 3458 * stop_machine() calls for this case. 3459 */ 3460 caps->cpu_enable(caps); 3461 } 3462 3463 /* 3464 * For all non-boot scope capabilities, use stop_machine() 3465 * as it schedules the work allowing us to modify PSTATE, 3466 * instead of on_each_cpu() which uses an IPI, giving us a 3467 * PSTATE that disappears when we return. 3468 */ 3469 if (!boot_scope) 3470 stop_machine(cpu_enable_non_boot_scope_capabilities, 3471 NULL, cpu_online_mask); 3472 } 3473 3474 /* 3475 * Run through the list of capabilities to check for conflicts. 3476 * If the system has already detected a capability, take necessary 3477 * action on this CPU. 3478 */ 3479 static void verify_local_cpu_caps(u16 scope_mask) 3480 { 3481 int i; 3482 bool cpu_has_cap, system_has_cap; 3483 const struct arm64_cpu_capabilities *caps; 3484 3485 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3486 3487 for (i = 0; i < ARM64_NCAPS; i++) { 3488 caps = cpucap_ptrs[i]; 3489 if (!caps || !(caps->type & scope_mask)) 3490 continue; 3491 3492 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3493 system_has_cap = cpus_have_cap(caps->capability); 3494 3495 if (system_has_cap) { 3496 /* 3497 * Check if the new CPU misses an advertised feature, 3498 * which is not safe to miss. 3499 */ 3500 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3501 break; 3502 /* 3503 * We have to issue cpu_enable() irrespective of 3504 * whether the CPU has it or not, as it is enabeld 3505 * system wide. It is upto the call back to take 3506 * appropriate action on this CPU. 3507 */ 3508 if (caps->cpu_enable) 3509 caps->cpu_enable(caps); 3510 } else { 3511 /* 3512 * Check if the CPU has this capability if it isn't 3513 * safe to have when the system doesn't. 3514 */ 3515 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3516 break; 3517 } 3518 } 3519 3520 if (i < ARM64_NCAPS) { 3521 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3522 smp_processor_id(), caps->capability, 3523 caps->desc, system_has_cap, cpu_has_cap); 3524 3525 if (cpucap_panic_on_conflict(caps)) 3526 cpu_panic_kernel(); 3527 else 3528 cpu_die_early(); 3529 } 3530 } 3531 3532 /* 3533 * Check for CPU features that are used in early boot 3534 * based on the Boot CPU value. 3535 */ 3536 static void check_early_cpu_features(void) 3537 { 3538 verify_cpu_asid_bits(); 3539 3540 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3541 } 3542 3543 static void 3544 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3545 { 3546 3547 for (; caps->matches; caps++) 3548 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3549 pr_crit("CPU%d: missing HWCAP: %s\n", 3550 smp_processor_id(), caps->desc); 3551 cpu_die_early(); 3552 } 3553 } 3554 3555 static void verify_local_elf_hwcaps(void) 3556 { 3557 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3558 3559 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3560 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3561 } 3562 3563 static void verify_sve_features(void) 3564 { 3565 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3566 3567 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3568 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3569 smp_processor_id()); 3570 cpu_die_early(); 3571 } 3572 3573 cpacr_restore(cpacr); 3574 } 3575 3576 static void verify_sme_features(void) 3577 { 3578 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3579 3580 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3581 pr_crit("CPU%d: SME: vector length support mismatch\n", 3582 smp_processor_id()); 3583 cpu_die_early(); 3584 } 3585 3586 cpacr_restore(cpacr); 3587 } 3588 3589 static void verify_hyp_capabilities(void) 3590 { 3591 u64 safe_mmfr1, mmfr0, mmfr1; 3592 int parange, ipa_max; 3593 unsigned int safe_vmid_bits, vmid_bits; 3594 3595 if (!IS_ENABLED(CONFIG_KVM)) 3596 return; 3597 3598 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3599 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3600 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3601 3602 /* Verify VMID bits */ 3603 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3604 vmid_bits = get_vmid_bits(mmfr1); 3605 if (vmid_bits < safe_vmid_bits) { 3606 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3607 cpu_die_early(); 3608 } 3609 3610 /* Verify IPA range */ 3611 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3612 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3613 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3614 if (ipa_max < get_kvm_ipa_limit()) { 3615 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3616 cpu_die_early(); 3617 } 3618 } 3619 3620 static void verify_mpam_capabilities(void) 3621 { 3622 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3623 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3624 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3625 3626 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3627 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3628 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3629 cpu_die_early(); 3630 } 3631 3632 cpu_idr = read_cpuid(MPAMIDR_EL1); 3633 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3634 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3635 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3636 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3637 cpu_die_early(); 3638 } 3639 3640 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3641 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3642 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3643 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3644 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3645 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3646 cpu_die_early(); 3647 } 3648 } 3649 3650 /* 3651 * Run through the enabled system capabilities and enable() it on this CPU. 3652 * The capabilities were decided based on the available CPUs at the boot time. 3653 * Any new CPU should match the system wide status of the capability. If the 3654 * new CPU doesn't have a capability which the system now has enabled, we 3655 * cannot do anything to fix it up and could cause unexpected failures. So 3656 * we park the CPU. 3657 */ 3658 static void verify_local_cpu_capabilities(void) 3659 { 3660 /* 3661 * The capabilities with SCOPE_BOOT_CPU are checked from 3662 * check_early_cpu_features(), as they need to be verified 3663 * on all secondary CPUs. 3664 */ 3665 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3666 verify_local_elf_hwcaps(); 3667 3668 if (system_supports_sve()) 3669 verify_sve_features(); 3670 3671 if (system_supports_sme()) 3672 verify_sme_features(); 3673 3674 if (is_hyp_mode_available()) 3675 verify_hyp_capabilities(); 3676 3677 if (system_supports_mpam()) 3678 verify_mpam_capabilities(); 3679 } 3680 3681 void check_local_cpu_capabilities(void) 3682 { 3683 /* 3684 * All secondary CPUs should conform to the early CPU features 3685 * in use by the kernel based on boot CPU. 3686 */ 3687 check_early_cpu_features(); 3688 3689 /* 3690 * If we haven't finalised the system capabilities, this CPU gets 3691 * a chance to update the errata work arounds and local features. 3692 * Otherwise, this CPU should verify that it has all the system 3693 * advertised capabilities. 3694 */ 3695 if (!system_capabilities_finalized()) 3696 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3697 else 3698 verify_local_cpu_capabilities(); 3699 } 3700 3701 bool this_cpu_has_cap(unsigned int n) 3702 { 3703 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3704 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3705 3706 if (cap) 3707 return cap->matches(cap, SCOPE_LOCAL_CPU); 3708 } 3709 3710 return false; 3711 } 3712 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3713 3714 /* 3715 * This helper function is used in a narrow window when, 3716 * - The system wide safe registers are set with all the SMP CPUs and, 3717 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3718 */ 3719 static bool __maybe_unused __system_matches_cap(unsigned int n) 3720 { 3721 if (n < ARM64_NCAPS) { 3722 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3723 3724 if (cap) 3725 return cap->matches(cap, SCOPE_SYSTEM); 3726 } 3727 return false; 3728 } 3729 3730 void cpu_set_feature(unsigned int num) 3731 { 3732 set_bit(num, elf_hwcap); 3733 } 3734 3735 bool cpu_have_feature(unsigned int num) 3736 { 3737 return test_bit(num, elf_hwcap); 3738 } 3739 EXPORT_SYMBOL_GPL(cpu_have_feature); 3740 3741 unsigned long cpu_get_elf_hwcap(void) 3742 { 3743 /* 3744 * We currently only populate the first 32 bits of AT_HWCAP. Please 3745 * note that for userspace compatibility we guarantee that bits 62 3746 * and 63 will always be returned as 0. 3747 */ 3748 return elf_hwcap[0]; 3749 } 3750 3751 unsigned long cpu_get_elf_hwcap2(void) 3752 { 3753 return elf_hwcap[1]; 3754 } 3755 3756 unsigned long cpu_get_elf_hwcap3(void) 3757 { 3758 return elf_hwcap[2]; 3759 } 3760 3761 static void __init setup_boot_cpu_capabilities(void) 3762 { 3763 kvm_arm_target_impl_cpu_init(); 3764 /* 3765 * The boot CPU's feature register values have been recorded. Detect 3766 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3767 * patch alternatives for the available boot cpucaps. 3768 */ 3769 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3770 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3771 apply_boot_alternatives(); 3772 } 3773 3774 void __init setup_boot_cpu_features(void) 3775 { 3776 /* 3777 * Initialize the indirect array of CPU capabilities pointers before we 3778 * handle the boot CPU. 3779 */ 3780 init_cpucap_indirect_list(); 3781 3782 /* 3783 * Detect broken pseudo-NMI. Must be called _before_ the call to 3784 * setup_boot_cpu_capabilities() since it interacts with 3785 * can_use_gic_priorities(). 3786 */ 3787 detect_system_supports_pseudo_nmi(); 3788 3789 setup_boot_cpu_capabilities(); 3790 } 3791 3792 static void __init setup_system_capabilities(void) 3793 { 3794 /* 3795 * The system-wide safe feature register values have been finalized. 3796 * Detect, enable, and patch alternatives for the available system 3797 * cpucaps. 3798 */ 3799 update_cpu_capabilities(SCOPE_SYSTEM); 3800 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3801 apply_alternatives_all(); 3802 3803 /* 3804 * Log any cpucaps with a cpumask as these aren't logged by 3805 * update_cpu_capabilities(). 3806 */ 3807 for (int i = 0; i < ARM64_NCAPS; i++) { 3808 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3809 3810 if (caps && caps->cpus && caps->desc && 3811 cpumask_any(caps->cpus) < nr_cpu_ids) 3812 pr_info("detected: %s on CPU%*pbl\n", 3813 caps->desc, cpumask_pr_args(caps->cpus)); 3814 } 3815 3816 /* 3817 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3818 */ 3819 if (system_uses_ttbr0_pan()) 3820 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3821 } 3822 3823 void __init setup_system_features(void) 3824 { 3825 setup_system_capabilities(); 3826 3827 kpti_install_ng_mappings(); 3828 3829 sve_setup(); 3830 sme_setup(); 3831 3832 /* 3833 * Check for sane CTR_EL0.CWG value. 3834 */ 3835 if (!cache_type_cwg()) 3836 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3837 ARCH_DMA_MINALIGN); 3838 } 3839 3840 void __init setup_user_features(void) 3841 { 3842 user_feature_fixup(); 3843 3844 setup_elf_hwcaps(arm64_elf_hwcaps); 3845 3846 if (system_supports_32bit_el0()) { 3847 setup_elf_hwcaps(compat_elf_hwcaps); 3848 elf_hwcap_fixup(); 3849 } 3850 3851 minsigstksz_setup(); 3852 } 3853 3854 static int enable_mismatched_32bit_el0(unsigned int cpu) 3855 { 3856 /* 3857 * The first 32-bit-capable CPU we detected and so can no longer 3858 * be offlined by userspace. -1 indicates we haven't yet onlined 3859 * a 32-bit-capable CPU. 3860 */ 3861 static int lucky_winner = -1; 3862 3863 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3864 bool cpu_32bit = false; 3865 3866 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3867 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3868 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3869 else 3870 cpu_32bit = true; 3871 } 3872 3873 if (cpu_32bit) { 3874 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3875 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3876 } 3877 3878 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3879 return 0; 3880 3881 if (lucky_winner >= 0) 3882 return 0; 3883 3884 /* 3885 * We've detected a mismatch. We need to keep one of our CPUs with 3886 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3887 * every CPU in the system for a 32-bit task. 3888 */ 3889 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3890 cpu_active_mask); 3891 get_cpu_device(lucky_winner)->offline_disabled = true; 3892 setup_elf_hwcaps(compat_elf_hwcaps); 3893 elf_hwcap_fixup(); 3894 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3895 cpu, lucky_winner); 3896 return 0; 3897 } 3898 3899 static int __init init_32bit_el0_mask(void) 3900 { 3901 if (!allow_mismatched_32bit_el0) 3902 return 0; 3903 3904 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3905 return -ENOMEM; 3906 3907 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3908 "arm64/mismatched_32bit_el0:online", 3909 enable_mismatched_32bit_el0, NULL); 3910 } 3911 subsys_initcall_sync(init_32bit_el0_mask); 3912 3913 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3914 { 3915 cpu_enable_swapper_cnp(); 3916 } 3917 3918 /* 3919 * We emulate only the following system register space. 3920 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3921 * See Table C5-6 System instruction encodings for System register accesses, 3922 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3923 */ 3924 static inline bool __attribute_const__ is_emulated(u32 id) 3925 { 3926 return (sys_reg_Op0(id) == 0x3 && 3927 sys_reg_CRn(id) == 0x0 && 3928 sys_reg_Op1(id) == 0x0 && 3929 (sys_reg_CRm(id) == 0 || 3930 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3931 } 3932 3933 /* 3934 * With CRm == 0, reg should be one of : 3935 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3936 */ 3937 static inline int emulate_id_reg(u32 id, u64 *valp) 3938 { 3939 switch (id) { 3940 case SYS_MIDR_EL1: 3941 *valp = read_cpuid_id(); 3942 break; 3943 case SYS_MPIDR_EL1: 3944 *valp = SYS_MPIDR_SAFE_VAL; 3945 break; 3946 case SYS_REVIDR_EL1: 3947 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3948 *valp = 0; 3949 break; 3950 default: 3951 return -EINVAL; 3952 } 3953 3954 return 0; 3955 } 3956 3957 static int emulate_sys_reg(u32 id, u64 *valp) 3958 { 3959 struct arm64_ftr_reg *regp; 3960 3961 if (!is_emulated(id)) 3962 return -EINVAL; 3963 3964 if (sys_reg_CRm(id) == 0) 3965 return emulate_id_reg(id, valp); 3966 3967 regp = get_arm64_ftr_reg_nowarn(id); 3968 if (regp) 3969 *valp = arm64_ftr_reg_user_value(regp); 3970 else 3971 /* 3972 * The untracked registers are either IMPLEMENTATION DEFINED 3973 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3974 */ 3975 *valp = 0; 3976 return 0; 3977 } 3978 3979 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3980 { 3981 int rc; 3982 u64 val; 3983 3984 rc = emulate_sys_reg(sys_reg, &val); 3985 if (!rc) { 3986 pt_regs_write_reg(regs, rt, val); 3987 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3988 } 3989 return rc; 3990 } 3991 3992 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3993 { 3994 u32 sys_reg, rt; 3995 3996 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3997 return false; 3998 3999 /* 4000 * sys_reg values are defined as used in mrs/msr instruction. 4001 * shift the imm value to get the encoding. 4002 */ 4003 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4004 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4005 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4006 } 4007 4008 enum mitigation_state arm64_get_meltdown_state(void) 4009 { 4010 if (__meltdown_safe) 4011 return SPECTRE_UNAFFECTED; 4012 4013 if (arm64_kernel_unmapped_at_el0()) 4014 return SPECTRE_MITIGATED; 4015 4016 return SPECTRE_VULNERABLE; 4017 } 4018 4019 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4020 char *buf) 4021 { 4022 switch (arm64_get_meltdown_state()) { 4023 case SPECTRE_UNAFFECTED: 4024 return sprintf(buf, "Not affected\n"); 4025 4026 case SPECTRE_MITIGATED: 4027 return sprintf(buf, "Mitigation: PTI\n"); 4028 4029 default: 4030 return sprintf(buf, "Vulnerable\n"); 4031 } 4032 } 4033