1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu.h> 88 #include <asm/mmu_context.h> 89 #include <asm/mte.h> 90 #include <asm/hypervisor.h> 91 #include <asm/processor.h> 92 #include <asm/smp.h> 93 #include <asm/sysreg.h> 94 #include <asm/traps.h> 95 #include <asm/vectors.h> 96 #include <asm/virt.h> 97 98 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 99 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 100 101 #ifdef CONFIG_COMPAT 102 #define COMPAT_ELF_HWCAP_DEFAULT \ 103 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 104 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 105 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 106 COMPAT_HWCAP_LPAE) 107 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 108 unsigned int compat_elf_hwcap2 __read_mostly; 109 unsigned int compat_elf_hwcap3 __read_mostly; 110 #endif 111 112 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 113 EXPORT_SYMBOL(system_cpucaps); 114 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 115 116 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 117 118 /* 119 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 120 * ends up in the .bss section where it is initialized in early_map_kernel() 121 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 122 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 123 * may end up generating an incorrect idmap page table attributes. 124 */ 125 bool arm64_use_ng_mappings __read_mostly = false; 126 EXPORT_SYMBOL(arm64_use_ng_mappings); 127 128 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 129 130 /* 131 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 132 * support it? 133 */ 134 static bool __read_mostly allow_mismatched_32bit_el0; 135 136 /* 137 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 138 * seen at least one CPU capable of 32-bit EL0. 139 */ 140 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 141 142 /* 143 * Mask of CPUs supporting 32-bit EL0. 144 * Only valid if arm64_mismatched_32bit_el0 is enabled. 145 */ 146 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 147 148 void dump_cpu_features(void) 149 { 150 /* file-wide pr_fmt adds "CPU features: " prefix */ 151 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 152 } 153 154 #define __ARM64_MAX_POSITIVE(reg, field) \ 155 ((reg##_##field##_SIGNED ? \ 156 BIT(reg##_##field##_WIDTH - 1) : \ 157 BIT(reg##_##field##_WIDTH)) - 1) 158 159 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 160 161 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 162 .sys_reg = SYS_##reg, \ 163 .field_pos = reg##_##field##_SHIFT, \ 164 .field_width = reg##_##field##_WIDTH, \ 165 .sign = reg##_##field##_SIGNED, \ 166 .min_field_value = min_value, \ 167 .max_field_value = max_value, 168 169 /* 170 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 171 * an implicit maximum that depends on the sign-ess of the field. 172 * 173 * An unsigned field will be capped at all ones, while a signed field 174 * will be limited to the positive half only. 175 */ 176 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 177 __ARM64_CPUID_FIELDS(reg, field, \ 178 SYS_FIELD_VALUE(reg, field, min_value), \ 179 __ARM64_MAX_POSITIVE(reg, field)) 180 181 /* 182 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 183 * implicit minimal value to max_value. This should be used when 184 * matching a non-implemented property. 185 */ 186 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 187 __ARM64_CPUID_FIELDS(reg, field, \ 188 __ARM64_MIN_NEGATIVE(reg, field), \ 189 SYS_FIELD_VALUE(reg, field, max_value)) 190 191 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 192 { \ 193 .sign = SIGNED, \ 194 .visible = VISIBLE, \ 195 .strict = STRICT, \ 196 .type = TYPE, \ 197 .shift = SHIFT, \ 198 .width = WIDTH, \ 199 .safe_val = SAFE_VAL, \ 200 } 201 202 /* Define a feature with unsigned values */ 203 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 204 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 205 206 /* Define a feature with a signed value */ 207 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 208 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 209 210 #define ARM64_FTR_END \ 211 { \ 212 .width = 0, \ 213 } 214 215 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 216 217 static bool __system_matches_cap(unsigned int n); 218 219 /* 220 * NOTE: Any changes to the visibility of features should be kept in 221 * sync with the documentation of the CPU feature register ABI. 222 */ 223 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 238 ARM64_FTR_END, 239 }; 240 241 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 250 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 252 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 257 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 259 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 261 ARM64_FTR_END, 262 }; 263 264 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 272 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 277 ARM64_FTR_END, 278 }; 279 280 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 284 ARM64_FTR_END, 285 }; 286 287 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 295 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 298 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 299 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 304 ARM64_FTR_END, 305 }; 306 307 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 310 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 311 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 313 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 318 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 319 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 320 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 321 ARM64_FTR_END, 322 }; 323 324 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 325 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 327 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 328 ARM64_FTR_END, 329 }; 330 331 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 353 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 355 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 356 ARM64_FTR_END, 357 }; 358 359 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 403 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 405 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 406 ARM64_FTR_END, 407 }; 408 409 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 414 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 415 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 418 ARM64_FTR_END, 419 }; 420 421 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 425 /* 426 * Page size not being supported at Stage-2 is not fatal. You 427 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 428 * your favourite nesting hypervisor. 429 * 430 * There is a small corner case where the hypervisor explicitly 431 * advertises a given granule size at Stage-2 (value 2) on some 432 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 433 * vCPUs. Although this is not forbidden by the architecture, it 434 * indicates that the hypervisor is being silly (or buggy). 435 * 436 * We make no effort to cope with this and pretend that if these 437 * fields are inconsistent across vCPUs, then it isn't worth 438 * trying to bring KVM up. 439 */ 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 443 /* 444 * We already refuse to boot CPUs that don't support our configured 445 * page size, so we can only detect mismatches for a page size other 446 * than the one we're currently using. Unfortunately, SoCs like this 447 * exist in the wild so, even though we don't like it, we'll have to go 448 * along with it and treat them as non-strict. 449 */ 450 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 451 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 453 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 455 /* Linux shouldn't care about secure memory */ 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 459 /* 460 * Differing PARange is fine as long as all peripherals and memory are mapped 461 * within the minimum PARange of all CPUs 462 */ 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 464 ARM64_FTR_END, 465 }; 466 467 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 501 ARM64_FTR_END, 502 }; 503 504 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 505 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 506 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 514 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static const struct arm64_ftr_bits ftr_ctr[] = { 520 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 521 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 522 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 523 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 526 /* 527 * Linux can handle differing I-cache policies. Userspace JITs will 528 * make use of *minLine. 529 * If we have differing I-cache policies, report it as the weakest - VIPT. 530 */ 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 533 ARM64_FTR_END, 534 }; 535 536 static struct arm64_ftr_override __ro_after_init no_override = { }; 537 538 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 539 .name = "SYS_CTR_EL0", 540 .ftr_bits = ftr_ctr, 541 .override = &no_override, 542 }; 543 544 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 545 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 548 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 549 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 553 ARM64_FTR_END, 554 }; 555 556 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 557 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 562 /* 563 * We can instantiate multiple PMU instances with different levels 564 * of support. 565 */ 566 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 568 ARM64_FTR_END, 569 }; 570 571 static const struct arm64_ftr_bits ftr_mvfr0[] = { 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 578 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 580 ARM64_FTR_END, 581 }; 582 583 static const struct arm64_ftr_bits ftr_mvfr1[] = { 584 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 592 ARM64_FTR_END, 593 }; 594 595 static const struct arm64_ftr_bits ftr_mvfr2[] = { 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 598 ARM64_FTR_END, 599 }; 600 601 static const struct arm64_ftr_bits ftr_dczid[] = { 602 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 603 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 604 ARM64_FTR_END, 605 }; 606 607 static const struct arm64_ftr_bits ftr_gmid[] = { 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 609 ARM64_FTR_END, 610 }; 611 612 static const struct arm64_ftr_bits ftr_id_isar0[] = { 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 615 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 616 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 620 ARM64_FTR_END, 621 }; 622 623 static const struct arm64_ftr_bits ftr_id_isar5[] = { 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 630 ARM64_FTR_END, 631 }; 632 633 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 641 642 /* 643 * SpecSEI = 1 indicates that the PE might generate an SError on an 644 * external abort on speculative read. It is safe to assume that an 645 * SError might be generated than it will not be. Hence it has been 646 * classified as FTR_HIGHER_SAFE. 647 */ 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 649 ARM64_FTR_END, 650 }; 651 652 static const struct arm64_ftr_bits ftr_id_isar4[] = { 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 661 ARM64_FTR_END, 662 }; 663 664 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 666 ARM64_FTR_END, 667 }; 668 669 static const struct arm64_ftr_bits ftr_id_isar6[] = { 670 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 672 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 673 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 674 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 677 ARM64_FTR_END, 678 }; 679 680 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 687 ARM64_FTR_END, 688 }; 689 690 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 699 ARM64_FTR_END, 700 }; 701 702 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 703 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 705 ARM64_FTR_END, 706 }; 707 708 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 709 /* [31:28] TraceFilt */ 710 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 715 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 716 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 717 ARM64_FTR_END, 718 }; 719 720 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 721 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 722 ARM64_FTR_END, 723 }; 724 725 static const struct arm64_ftr_bits ftr_mpamidr[] = { 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 730 ARM64_FTR_END, 731 }; 732 733 /* 734 * Common ftr bits for a 32bit register with all hidden, strict 735 * attributes, with 4bit feature fields and a default safe value of 736 * 0. Covers the following 32bit registers: 737 * id_isar[1-3], id_mmfr[1-3] 738 */ 739 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 743 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 744 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 745 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 746 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 748 ARM64_FTR_END, 749 }; 750 751 /* Table for a single 32bit feature value */ 752 static const struct arm64_ftr_bits ftr_single32[] = { 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 754 ARM64_FTR_END, 755 }; 756 757 static const struct arm64_ftr_bits ftr_raz[] = { 758 ARM64_FTR_END, 759 }; 760 761 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 762 .sys_id = id, \ 763 .reg = &(struct arm64_ftr_reg){ \ 764 .name = id_str, \ 765 .override = (ovr), \ 766 .ftr_bits = &((table)[0]), \ 767 }} 768 769 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 770 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 771 772 #define ARM64_FTR_REG(id, table) \ 773 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 774 775 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 776 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 777 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 778 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 779 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 780 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 781 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 782 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 783 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 784 785 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 786 787 static const struct __ftr_reg_entry { 788 u32 sys_id; 789 struct arm64_ftr_reg *reg; 790 } arm64_ftr_regs[] = { 791 792 /* Op1 = 0, CRn = 0, CRm = 1 */ 793 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 794 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 795 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 796 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 797 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 798 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 799 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 800 801 /* Op1 = 0, CRn = 0, CRm = 2 */ 802 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 803 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 804 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 805 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 806 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 807 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 808 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 809 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 810 811 /* Op1 = 0, CRn = 0, CRm = 3 */ 812 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 813 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 814 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 815 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 816 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 817 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 818 819 /* Op1 = 0, CRn = 0, CRm = 4 */ 820 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 821 &id_aa64pfr0_override), 822 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 823 &id_aa64pfr1_override), 824 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 825 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 826 &id_aa64zfr0_override), 827 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 828 &id_aa64smfr0_override), 829 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 830 831 /* Op1 = 0, CRn = 0, CRm = 5 */ 832 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 833 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 834 835 /* Op1 = 0, CRn = 0, CRm = 6 */ 836 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 837 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 838 &id_aa64isar1_override), 839 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 840 &id_aa64isar2_override), 841 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 842 843 /* Op1 = 0, CRn = 0, CRm = 7 */ 844 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 845 &id_aa64mmfr0_override), 846 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 847 &id_aa64mmfr1_override), 848 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 849 &id_aa64mmfr2_override), 850 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 851 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 852 853 /* Op1 = 0, CRn = 10, CRm = 4 */ 854 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 855 856 /* Op1 = 1, CRn = 0, CRm = 0 */ 857 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 858 859 /* Op1 = 3, CRn = 0, CRm = 0 */ 860 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 861 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 862 863 /* Op1 = 3, CRn = 14, CRm = 0 */ 864 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 865 }; 866 867 static int search_cmp_ftr_reg(const void *id, const void *regp) 868 { 869 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 870 } 871 872 /* 873 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 874 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 875 * ascending order of sys_id, we use binary search to find a matching 876 * entry. 877 * 878 * returns - Upon success, matching ftr_reg entry for id. 879 * - NULL on failure. It is upto the caller to decide 880 * the impact of a failure. 881 */ 882 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 883 { 884 const struct __ftr_reg_entry *ret; 885 886 ret = bsearch((const void *)(unsigned long)sys_id, 887 arm64_ftr_regs, 888 ARRAY_SIZE(arm64_ftr_regs), 889 sizeof(arm64_ftr_regs[0]), 890 search_cmp_ftr_reg); 891 if (ret) 892 return ret->reg; 893 return NULL; 894 } 895 896 /* 897 * get_arm64_ftr_reg - Looks up a feature register entry using 898 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 899 * 900 * returns - Upon success, matching ftr_reg entry for id. 901 * - NULL on failure but with an WARN_ON(). 902 */ 903 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 904 { 905 struct arm64_ftr_reg *reg; 906 907 reg = get_arm64_ftr_reg_nowarn(sys_id); 908 909 /* 910 * Requesting a non-existent register search is an error. Warn 911 * and let the caller handle it. 912 */ 913 WARN_ON(!reg); 914 return reg; 915 } 916 917 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 918 s64 ftr_val) 919 { 920 u64 mask = arm64_ftr_mask(ftrp); 921 922 reg &= ~mask; 923 reg |= (ftr_val << ftrp->shift) & mask; 924 return reg; 925 } 926 927 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 928 s64 cur) 929 { 930 s64 ret = 0; 931 932 switch (ftrp->type) { 933 case FTR_EXACT: 934 ret = ftrp->safe_val; 935 break; 936 case FTR_LOWER_SAFE: 937 ret = min(new, cur); 938 break; 939 case FTR_HIGHER_OR_ZERO_SAFE: 940 if (!cur || !new) 941 break; 942 fallthrough; 943 case FTR_HIGHER_SAFE: 944 ret = max(new, cur); 945 break; 946 default: 947 BUG(); 948 } 949 950 return ret; 951 } 952 953 static void __init sort_ftr_regs(void) 954 { 955 unsigned int i; 956 957 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 958 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 959 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 960 unsigned int j = 0; 961 962 /* 963 * Features here must be sorted in descending order with respect 964 * to their shift values and should not overlap with each other. 965 */ 966 for (; ftr_bits->width != 0; ftr_bits++, j++) { 967 unsigned int width = ftr_reg->ftr_bits[j].width; 968 unsigned int shift = ftr_reg->ftr_bits[j].shift; 969 unsigned int prev_shift; 970 971 WARN((shift + width) > 64, 972 "%s has invalid feature at shift %d\n", 973 ftr_reg->name, shift); 974 975 /* 976 * Skip the first feature. There is nothing to 977 * compare against for now. 978 */ 979 if (j == 0) 980 continue; 981 982 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 983 WARN((shift + width) > prev_shift, 984 "%s has feature overlap at shift %d\n", 985 ftr_reg->name, shift); 986 } 987 988 /* 989 * Skip the first register. There is nothing to 990 * compare against for now. 991 */ 992 if (i == 0) 993 continue; 994 /* 995 * Registers here must be sorted in ascending order with respect 996 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 997 * to work correctly. 998 */ 999 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1000 } 1001 } 1002 1003 /* 1004 * Initialise the CPU feature register from Boot CPU values. 1005 * Also initiliases the strict_mask for the register. 1006 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1007 * RES0 for the system-wide value, and must strictly match. 1008 */ 1009 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1010 { 1011 u64 val = 0; 1012 u64 strict_mask = ~0x0ULL; 1013 u64 user_mask = 0; 1014 u64 valid_mask = 0; 1015 1016 const struct arm64_ftr_bits *ftrp; 1017 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1018 1019 if (!reg) 1020 return; 1021 1022 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1023 u64 ftr_mask = arm64_ftr_mask(ftrp); 1024 s64 ftr_new = arm64_ftr_value(ftrp, new); 1025 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1026 1027 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1028 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1029 char *str = NULL; 1030 1031 if (ftr_ovr != tmp) { 1032 /* Unsafe, remove the override */ 1033 reg->override->mask &= ~ftr_mask; 1034 reg->override->val &= ~ftr_mask; 1035 tmp = ftr_ovr; 1036 str = "ignoring override"; 1037 } else if (ftr_new != tmp) { 1038 /* Override was valid */ 1039 ftr_new = tmp; 1040 str = "forced"; 1041 } else { 1042 /* Override was the safe value */ 1043 str = "already set"; 1044 } 1045 1046 pr_warn("%s[%d:%d]: %s to %llx\n", 1047 reg->name, 1048 ftrp->shift + ftrp->width - 1, 1049 ftrp->shift, str, 1050 tmp & (BIT(ftrp->width) - 1)); 1051 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1052 reg->override->val &= ~ftr_mask; 1053 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1054 reg->name, 1055 ftrp->shift + ftrp->width - 1, 1056 ftrp->shift); 1057 } 1058 1059 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1060 1061 valid_mask |= ftr_mask; 1062 if (!ftrp->strict) 1063 strict_mask &= ~ftr_mask; 1064 if (ftrp->visible) 1065 user_mask |= ftr_mask; 1066 else 1067 reg->user_val = arm64_ftr_set_value(ftrp, 1068 reg->user_val, 1069 ftrp->safe_val); 1070 } 1071 1072 val &= valid_mask; 1073 1074 reg->sys_val = val; 1075 reg->strict_mask = strict_mask; 1076 reg->user_mask = user_mask; 1077 } 1078 1079 extern const struct arm64_cpu_capabilities arm64_errata[]; 1080 static const struct arm64_cpu_capabilities arm64_features[]; 1081 1082 static void __init 1083 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1084 { 1085 for (; caps->matches; caps++) { 1086 if (WARN(caps->capability >= ARM64_NCAPS, 1087 "Invalid capability %d\n", caps->capability)) 1088 continue; 1089 if (WARN(cpucap_ptrs[caps->capability], 1090 "Duplicate entry for capability %d\n", 1091 caps->capability)) 1092 continue; 1093 cpucap_ptrs[caps->capability] = caps; 1094 } 1095 } 1096 1097 static void __init init_cpucap_indirect_list(void) 1098 { 1099 init_cpucap_indirect_list_from_array(arm64_features); 1100 init_cpucap_indirect_list_from_array(arm64_errata); 1101 } 1102 1103 static void __init setup_boot_cpu_capabilities(void); 1104 1105 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1106 { 1107 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1108 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1109 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1110 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1111 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1112 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1113 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1114 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1115 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1116 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1117 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1118 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1119 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1120 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1121 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1122 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1123 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1124 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1125 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1126 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1127 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1128 } 1129 1130 #ifdef CONFIG_ARM64_PSEUDO_NMI 1131 static bool enable_pseudo_nmi; 1132 1133 static int __init early_enable_pseudo_nmi(char *p) 1134 { 1135 return kstrtobool(p, &enable_pseudo_nmi); 1136 } 1137 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1138 1139 static __init void detect_system_supports_pseudo_nmi(void) 1140 { 1141 struct device_node *np; 1142 1143 if (!enable_pseudo_nmi) 1144 return; 1145 1146 /* 1147 * Detect broken MediaTek firmware that doesn't properly save and 1148 * restore GIC priorities. 1149 */ 1150 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1151 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1152 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1153 enable_pseudo_nmi = false; 1154 } 1155 of_node_put(np); 1156 } 1157 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1158 static inline void detect_system_supports_pseudo_nmi(void) { } 1159 #endif 1160 1161 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1162 { 1163 /* Before we start using the tables, make sure it is sorted */ 1164 sort_ftr_regs(); 1165 1166 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1167 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1168 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1169 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1170 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1171 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1172 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1173 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1174 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1175 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1176 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1177 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1178 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1179 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1180 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1181 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1182 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1183 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1184 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1185 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1186 1187 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1188 init_32bit_cpu_features(&info->aarch32); 1189 1190 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1191 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1192 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1193 1194 vec_init_vq_map(ARM64_VEC_SVE); 1195 1196 cpacr_restore(cpacr); 1197 } 1198 1199 if (IS_ENABLED(CONFIG_ARM64_SME) && 1200 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1201 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1202 1203 vec_init_vq_map(ARM64_VEC_SME); 1204 1205 cpacr_restore(cpacr); 1206 } 1207 1208 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1209 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1210 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1211 } 1212 1213 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1214 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1215 } 1216 1217 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1218 { 1219 const struct arm64_ftr_bits *ftrp; 1220 1221 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1222 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1223 s64 ftr_new = arm64_ftr_value(ftrp, new); 1224 1225 if (ftr_cur == ftr_new) 1226 continue; 1227 /* Find a safe value */ 1228 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1229 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1230 } 1231 1232 } 1233 1234 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1235 { 1236 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1237 1238 if (!regp) 1239 return 0; 1240 1241 update_cpu_ftr_reg(regp, val); 1242 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1243 return 0; 1244 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1245 regp->name, boot, cpu, val); 1246 return 1; 1247 } 1248 1249 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1250 { 1251 const struct arm64_ftr_bits *ftrp; 1252 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1253 1254 if (!regp) 1255 return; 1256 1257 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1258 if (ftrp->shift == field) { 1259 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1260 break; 1261 } 1262 } 1263 1264 /* Bogus field? */ 1265 WARN_ON(!ftrp->width); 1266 } 1267 1268 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1269 struct cpuinfo_arm64 *boot) 1270 { 1271 static bool boot_cpu_32bit_regs_overridden = false; 1272 1273 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1274 return; 1275 1276 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1277 return; 1278 1279 boot->aarch32 = info->aarch32; 1280 init_32bit_cpu_features(&boot->aarch32); 1281 boot_cpu_32bit_regs_overridden = true; 1282 } 1283 1284 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1285 struct cpuinfo_32bit *boot) 1286 { 1287 int taint = 0; 1288 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1289 1290 /* 1291 * If we don't have AArch32 at EL1, then relax the strictness of 1292 * EL1-dependent register fields to avoid spurious sanity check fails. 1293 */ 1294 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1295 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1296 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1297 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1298 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1299 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1300 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1301 } 1302 1303 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1304 info->reg_id_dfr0, boot->reg_id_dfr0); 1305 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1306 info->reg_id_dfr1, boot->reg_id_dfr1); 1307 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1308 info->reg_id_isar0, boot->reg_id_isar0); 1309 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1310 info->reg_id_isar1, boot->reg_id_isar1); 1311 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1312 info->reg_id_isar2, boot->reg_id_isar2); 1313 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1314 info->reg_id_isar3, boot->reg_id_isar3); 1315 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1316 info->reg_id_isar4, boot->reg_id_isar4); 1317 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1318 info->reg_id_isar5, boot->reg_id_isar5); 1319 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1320 info->reg_id_isar6, boot->reg_id_isar6); 1321 1322 /* 1323 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1324 * ACTLR formats could differ across CPUs and therefore would have to 1325 * be trapped for virtualization anyway. 1326 */ 1327 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1328 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1329 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1330 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1331 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1332 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1333 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1334 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1335 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1336 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1337 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1338 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1339 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1340 info->reg_id_pfr0, boot->reg_id_pfr0); 1341 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1342 info->reg_id_pfr1, boot->reg_id_pfr1); 1343 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1344 info->reg_id_pfr2, boot->reg_id_pfr2); 1345 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1346 info->reg_mvfr0, boot->reg_mvfr0); 1347 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1348 info->reg_mvfr1, boot->reg_mvfr1); 1349 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1350 info->reg_mvfr2, boot->reg_mvfr2); 1351 1352 return taint; 1353 } 1354 1355 /* 1356 * Update system wide CPU feature registers with the values from a 1357 * non-boot CPU. Also performs SANITY checks to make sure that there 1358 * aren't any insane variations from that of the boot CPU. 1359 */ 1360 void update_cpu_features(int cpu, 1361 struct cpuinfo_arm64 *info, 1362 struct cpuinfo_arm64 *boot) 1363 { 1364 int taint = 0; 1365 1366 /* 1367 * The kernel can handle differing I-cache policies, but otherwise 1368 * caches should look identical. Userspace JITs will make use of 1369 * *minLine. 1370 */ 1371 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1372 info->reg_ctr, boot->reg_ctr); 1373 1374 /* 1375 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1376 * could result in too much or too little memory being zeroed if a 1377 * process is preempted and migrated between CPUs. 1378 */ 1379 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1380 info->reg_dczid, boot->reg_dczid); 1381 1382 /* If different, timekeeping will be broken (especially with KVM) */ 1383 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1384 info->reg_cntfrq, boot->reg_cntfrq); 1385 1386 /* 1387 * The kernel uses self-hosted debug features and expects CPUs to 1388 * support identical debug features. We presently need CTX_CMPs, WRPs, 1389 * and BRPs to be identical. 1390 * ID_AA64DFR1 is currently RES0. 1391 */ 1392 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1393 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1394 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1395 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1396 /* 1397 * Even in big.LITTLE, processors should be identical instruction-set 1398 * wise. 1399 */ 1400 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1401 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1402 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1403 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1404 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1405 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1406 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1407 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1408 1409 /* 1410 * Differing PARange support is fine as long as all peripherals and 1411 * memory are mapped within the minimum PARange of all CPUs. 1412 * Linux should not care about secure memory. 1413 */ 1414 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1415 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1416 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1417 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1418 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1419 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1420 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1421 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1423 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1424 1425 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1426 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1427 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1428 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1429 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1430 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1431 1432 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1433 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1434 1435 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1436 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1437 1438 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1439 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1440 1441 /* Probe vector lengths */ 1442 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1443 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1444 if (!system_capabilities_finalized()) { 1445 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1446 1447 vec_update_vq_map(ARM64_VEC_SVE); 1448 1449 cpacr_restore(cpacr); 1450 } 1451 } 1452 1453 if (IS_ENABLED(CONFIG_ARM64_SME) && 1454 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1455 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1456 1457 /* Probe vector lengths */ 1458 if (!system_capabilities_finalized()) 1459 vec_update_vq_map(ARM64_VEC_SME); 1460 1461 cpacr_restore(cpacr); 1462 } 1463 1464 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1465 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1466 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1467 info->reg_mpamidr, boot->reg_mpamidr); 1468 } 1469 1470 /* 1471 * The kernel uses the LDGM/STGM instructions and the number of tags 1472 * they read/write depends on the GMID_EL1.BS field. Check that the 1473 * value is the same on all CPUs. 1474 */ 1475 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1476 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1477 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1478 info->reg_gmid, boot->reg_gmid); 1479 } 1480 1481 /* 1482 * If we don't have AArch32 at all then skip the checks entirely 1483 * as the register values may be UNKNOWN and we're not going to be 1484 * using them for anything. 1485 * 1486 * This relies on a sanitised view of the AArch64 ID registers 1487 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1488 */ 1489 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1490 lazy_init_32bit_cpu_features(info, boot); 1491 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1492 &boot->aarch32); 1493 } 1494 1495 /* 1496 * Mismatched CPU features are a recipe for disaster. Don't even 1497 * pretend to support them. 1498 */ 1499 if (taint) { 1500 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1501 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1502 } 1503 } 1504 1505 u64 read_sanitised_ftr_reg(u32 id) 1506 { 1507 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1508 1509 if (!regp) 1510 return 0; 1511 return regp->sys_val; 1512 } 1513 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1514 1515 #define read_sysreg_case(r) \ 1516 case r: val = read_sysreg_s(r); break; 1517 1518 /* 1519 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1520 * Read the system register on the current CPU 1521 */ 1522 u64 __read_sysreg_by_encoding(u32 sys_id) 1523 { 1524 struct arm64_ftr_reg *regp; 1525 u64 val; 1526 1527 switch (sys_id) { 1528 read_sysreg_case(SYS_ID_PFR0_EL1); 1529 read_sysreg_case(SYS_ID_PFR1_EL1); 1530 read_sysreg_case(SYS_ID_PFR2_EL1); 1531 read_sysreg_case(SYS_ID_DFR0_EL1); 1532 read_sysreg_case(SYS_ID_DFR1_EL1); 1533 read_sysreg_case(SYS_ID_MMFR0_EL1); 1534 read_sysreg_case(SYS_ID_MMFR1_EL1); 1535 read_sysreg_case(SYS_ID_MMFR2_EL1); 1536 read_sysreg_case(SYS_ID_MMFR3_EL1); 1537 read_sysreg_case(SYS_ID_MMFR4_EL1); 1538 read_sysreg_case(SYS_ID_MMFR5_EL1); 1539 read_sysreg_case(SYS_ID_ISAR0_EL1); 1540 read_sysreg_case(SYS_ID_ISAR1_EL1); 1541 read_sysreg_case(SYS_ID_ISAR2_EL1); 1542 read_sysreg_case(SYS_ID_ISAR3_EL1); 1543 read_sysreg_case(SYS_ID_ISAR4_EL1); 1544 read_sysreg_case(SYS_ID_ISAR5_EL1); 1545 read_sysreg_case(SYS_ID_ISAR6_EL1); 1546 read_sysreg_case(SYS_MVFR0_EL1); 1547 read_sysreg_case(SYS_MVFR1_EL1); 1548 read_sysreg_case(SYS_MVFR2_EL1); 1549 1550 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1551 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1552 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1553 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1554 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1556 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1557 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1558 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1559 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1560 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1561 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1562 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1563 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1564 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1565 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1566 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1567 1568 read_sysreg_case(SYS_CNTFRQ_EL0); 1569 read_sysreg_case(SYS_CTR_EL0); 1570 read_sysreg_case(SYS_DCZID_EL0); 1571 1572 default: 1573 BUG(); 1574 return 0; 1575 } 1576 1577 regp = get_arm64_ftr_reg(sys_id); 1578 if (regp) { 1579 val &= ~regp->override->mask; 1580 val |= (regp->override->val & regp->override->mask); 1581 } 1582 1583 return val; 1584 } 1585 1586 #include <linux/irqchip/arm-gic-v3.h> 1587 1588 static bool 1589 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1590 { 1591 return true; 1592 } 1593 1594 static bool 1595 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1596 { 1597 int val, min, max; 1598 u64 tmp; 1599 1600 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1601 entry->field_width, 1602 entry->sign); 1603 1604 tmp = entry->min_field_value; 1605 tmp <<= entry->field_pos; 1606 1607 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1608 entry->field_width, 1609 entry->sign); 1610 1611 tmp = entry->max_field_value; 1612 tmp <<= entry->field_pos; 1613 1614 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1615 entry->field_width, 1616 entry->sign); 1617 1618 return val >= min && val <= max; 1619 } 1620 1621 static u64 1622 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1623 { 1624 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1625 if (scope == SCOPE_SYSTEM) 1626 return read_sanitised_ftr_reg(entry->sys_reg); 1627 else 1628 return __read_sysreg_by_encoding(entry->sys_reg); 1629 } 1630 1631 static bool 1632 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1633 { 1634 int mask; 1635 struct arm64_ftr_reg *regp; 1636 u64 val = read_scoped_sysreg(entry, scope); 1637 1638 regp = get_arm64_ftr_reg(entry->sys_reg); 1639 if (!regp) 1640 return false; 1641 1642 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1643 entry->field_pos, 1644 entry->field_width); 1645 if (!mask) 1646 return false; 1647 1648 return feature_matches(val, entry); 1649 } 1650 1651 static bool 1652 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1653 { 1654 u64 val = read_scoped_sysreg(entry, scope); 1655 return feature_matches(val, entry); 1656 } 1657 1658 const struct cpumask *system_32bit_el0_cpumask(void) 1659 { 1660 if (!system_supports_32bit_el0()) 1661 return cpu_none_mask; 1662 1663 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1664 return cpu_32bit_el0_mask; 1665 1666 return cpu_possible_mask; 1667 } 1668 1669 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1670 { 1671 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1672 } 1673 1674 static int __init parse_32bit_el0_param(char *str) 1675 { 1676 allow_mismatched_32bit_el0 = true; 1677 return 0; 1678 } 1679 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1680 1681 static ssize_t aarch32_el0_show(struct device *dev, 1682 struct device_attribute *attr, char *buf) 1683 { 1684 const struct cpumask *mask = system_32bit_el0_cpumask(); 1685 1686 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1687 } 1688 static const DEVICE_ATTR_RO(aarch32_el0); 1689 1690 static int __init aarch32_el0_sysfs_init(void) 1691 { 1692 struct device *dev_root; 1693 int ret = 0; 1694 1695 if (!allow_mismatched_32bit_el0) 1696 return 0; 1697 1698 dev_root = bus_get_dev_root(&cpu_subsys); 1699 if (dev_root) { 1700 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1701 put_device(dev_root); 1702 } 1703 return ret; 1704 } 1705 device_initcall(aarch32_el0_sysfs_init); 1706 1707 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1708 { 1709 if (!has_cpuid_feature(entry, scope)) 1710 return allow_mismatched_32bit_el0; 1711 1712 if (scope == SCOPE_SYSTEM) 1713 pr_info("detected: 32-bit EL0 Support\n"); 1714 1715 return true; 1716 } 1717 1718 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1719 { 1720 bool has_sre; 1721 1722 if (!has_cpuid_feature(entry, scope)) 1723 return false; 1724 1725 has_sre = gic_enable_sre(); 1726 if (!has_sre) 1727 pr_warn_once("%s present but disabled by higher exception level\n", 1728 entry->desc); 1729 1730 return has_sre; 1731 } 1732 1733 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1734 int scope) 1735 { 1736 u64 ctr; 1737 1738 if (scope == SCOPE_SYSTEM) 1739 ctr = arm64_ftr_reg_ctrel0.sys_val; 1740 else 1741 ctr = read_cpuid_effective_cachetype(); 1742 1743 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1744 } 1745 1746 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1747 { 1748 /* 1749 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1750 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1751 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1752 * value. 1753 */ 1754 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1755 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1756 } 1757 1758 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1759 int scope) 1760 { 1761 u64 ctr; 1762 1763 if (scope == SCOPE_SYSTEM) 1764 ctr = arm64_ftr_reg_ctrel0.sys_val; 1765 else 1766 ctr = read_cpuid_cachetype(); 1767 1768 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1769 } 1770 1771 static bool __maybe_unused 1772 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1773 { 1774 /* 1775 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1776 * may share TLB entries with a CPU stuck in the crashed 1777 * kernel. 1778 */ 1779 if (is_kdump_kernel()) 1780 return false; 1781 1782 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1783 return false; 1784 1785 return has_cpuid_feature(entry, scope); 1786 } 1787 1788 static bool __meltdown_safe = true; 1789 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1790 1791 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1792 int scope) 1793 { 1794 /* List of CPUs that are not vulnerable and don't need KPTI */ 1795 static const struct midr_range kpti_safe_list[] = { 1796 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1797 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1798 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1799 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1800 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1801 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1802 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1803 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1804 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1805 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1806 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1807 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1808 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1809 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1810 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1811 { /* sentinel */ } 1812 }; 1813 char const *str = "kpti command line option"; 1814 bool meltdown_safe; 1815 1816 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1817 1818 /* Defer to CPU feature registers */ 1819 if (has_cpuid_feature(entry, scope)) 1820 meltdown_safe = true; 1821 1822 if (!meltdown_safe) 1823 __meltdown_safe = false; 1824 1825 /* 1826 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1827 * ThunderX leads to apparent I-cache corruption of kernel text, which 1828 * ends as well as you might imagine. Don't even try. We cannot rely 1829 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1830 * because cpucap detection order may change. However, since we know 1831 * affected CPUs are always in a homogeneous configuration, it is 1832 * safe to rely on this_cpu_has_cap() here. 1833 */ 1834 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1835 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1836 __kpti_forced = -1; 1837 } 1838 1839 /* Useful for KASLR robustness */ 1840 if (kaslr_enabled() && kaslr_requires_kpti()) { 1841 if (!__kpti_forced) { 1842 str = "KASLR"; 1843 __kpti_forced = 1; 1844 } 1845 } 1846 1847 if (cpu_mitigations_off() && !__kpti_forced) { 1848 str = "mitigations=off"; 1849 __kpti_forced = -1; 1850 } 1851 1852 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1853 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1854 return false; 1855 } 1856 1857 /* Forced? */ 1858 if (__kpti_forced) { 1859 pr_info_once("kernel page table isolation forced %s by %s\n", 1860 __kpti_forced > 0 ? "ON" : "OFF", str); 1861 return __kpti_forced > 0; 1862 } 1863 1864 return !meltdown_safe; 1865 } 1866 1867 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1868 { 1869 /* 1870 * Although the Apple M2 family appears to support NV1, the 1871 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1872 * that it doesn't support NV1 at all. 1873 */ 1874 static const struct midr_range nv1_ni_list[] = { 1875 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1876 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1877 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1878 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1879 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1880 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1881 {} 1882 }; 1883 1884 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1885 !(has_cpuid_feature(entry, scope) || 1886 is_midr_in_range_list(nv1_ni_list))); 1887 } 1888 1889 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1890 static bool has_lpa2_at_stage1(u64 mmfr0) 1891 { 1892 unsigned int tgran; 1893 1894 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1895 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1896 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1897 } 1898 1899 static bool has_lpa2_at_stage2(u64 mmfr0) 1900 { 1901 unsigned int tgran; 1902 1903 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1904 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1905 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1906 } 1907 1908 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1909 { 1910 u64 mmfr0; 1911 1912 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1913 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1914 } 1915 #else 1916 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1917 { 1918 return false; 1919 } 1920 #endif 1921 1922 #ifdef CONFIG_HW_PERF_EVENTS 1923 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1924 { 1925 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1926 unsigned int pmuver; 1927 1928 /* 1929 * PMUVer follows the standard ID scheme for an unsigned field with the 1930 * exception of 0xF (IMP_DEF) which is treated specially and implies 1931 * FEAT_PMUv3 is not implemented. 1932 * 1933 * See DDI0487L.a D24.1.3.2 for more details. 1934 */ 1935 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1936 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1937 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1938 return false; 1939 1940 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1941 } 1942 #endif 1943 1944 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1945 { 1946 if (__this_cpu_read(this_cpu_vector) == vectors) { 1947 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1948 1949 __this_cpu_write(this_cpu_vector, v); 1950 } 1951 1952 } 1953 1954 static int __init parse_kpti(char *str) 1955 { 1956 bool enabled; 1957 int ret = kstrtobool(str, &enabled); 1958 1959 if (ret) 1960 return ret; 1961 1962 __kpti_forced = enabled ? 1 : -1; 1963 return 0; 1964 } 1965 early_param("kpti", parse_kpti); 1966 1967 #ifdef CONFIG_ARM64_HW_AFDBM 1968 static struct cpumask dbm_cpus __read_mostly; 1969 1970 static inline void __cpu_enable_hw_dbm(void) 1971 { 1972 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1973 1974 write_sysreg(tcr, tcr_el1); 1975 isb(); 1976 local_flush_tlb_all(); 1977 } 1978 1979 static bool cpu_has_broken_dbm(void) 1980 { 1981 /* List of CPUs which have broken DBM support. */ 1982 static const struct midr_range cpus[] = { 1983 #ifdef CONFIG_ARM64_ERRATUM_1024718 1984 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1985 /* Kryo4xx Silver (rdpe => r1p0) */ 1986 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1987 #endif 1988 #ifdef CONFIG_ARM64_ERRATUM_2051678 1989 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1990 #endif 1991 {}, 1992 }; 1993 1994 return is_midr_in_range_list(cpus); 1995 } 1996 1997 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1998 { 1999 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2000 !cpu_has_broken_dbm(); 2001 } 2002 2003 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2004 { 2005 if (cpu_can_use_dbm(cap)) { 2006 __cpu_enable_hw_dbm(); 2007 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2008 } 2009 } 2010 2011 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2012 int __unused) 2013 { 2014 /* 2015 * DBM is a non-conflicting feature. i.e, the kernel can safely 2016 * run a mix of CPUs with and without the feature. So, we 2017 * unconditionally enable the capability to allow any late CPU 2018 * to use the feature. We only enable the control bits on the 2019 * CPU, if it is supported. 2020 */ 2021 2022 return true; 2023 } 2024 2025 #endif 2026 2027 #ifdef CONFIG_ARM64_AMU_EXTN 2028 2029 /* 2030 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2031 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2032 * information regarding all the events that it supports. When a CPU bit is 2033 * set in the cpumask, the user of this feature can only rely on the presence 2034 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2035 * counters are enabled or access to these counters is enabled by code 2036 * executed at higher exception levels (firmware). 2037 */ 2038 static struct cpumask amu_cpus __read_mostly; 2039 2040 bool cpu_has_amu_feat(int cpu) 2041 { 2042 return cpumask_test_cpu(cpu, &amu_cpus); 2043 } 2044 2045 int get_cpu_with_amu_feat(void) 2046 { 2047 return cpumask_any(&amu_cpus); 2048 } 2049 2050 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2051 { 2052 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2053 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2054 2055 /* 0 reference values signal broken/disabled counters */ 2056 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2057 update_freq_counters_refs(); 2058 } 2059 } 2060 2061 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2062 int __unused) 2063 { 2064 /* 2065 * The AMU extension is a non-conflicting feature: the kernel can 2066 * safely run a mix of CPUs with and without support for the 2067 * activity monitors extension. Therefore, unconditionally enable 2068 * the capability to allow any late CPU to use the feature. 2069 * 2070 * With this feature unconditionally enabled, the cpu_enable 2071 * function will be called for all CPUs that match the criteria, 2072 * including secondary and hotplugged, marking this feature as 2073 * present on that respective CPU. The enable function will also 2074 * print a detection message. 2075 */ 2076 2077 return true; 2078 } 2079 #else 2080 int get_cpu_with_amu_feat(void) 2081 { 2082 return nr_cpu_ids; 2083 } 2084 #endif 2085 2086 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2087 { 2088 return is_kernel_in_hyp_mode(); 2089 } 2090 2091 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2092 { 2093 /* 2094 * Copy register values that aren't redirected by hardware. 2095 * 2096 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2097 * this value to tpidr_el2 before we patch the code. Once we've done 2098 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2099 * do anything here. 2100 */ 2101 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2102 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2103 } 2104 2105 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2106 int scope) 2107 { 2108 if (kvm_get_mode() != KVM_MODE_NV) 2109 return false; 2110 2111 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2112 pr_warn("unavailable: %s\n", cap->desc); 2113 return false; 2114 } 2115 2116 return true; 2117 } 2118 2119 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2120 int __unused) 2121 { 2122 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2123 } 2124 2125 bool cpu_supports_bbml2_noabort(void) 2126 { 2127 /* 2128 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2129 * as possible. This list is therefore an allow-list of known-good 2130 * implementations that both support BBML2 and additionally, fulfill the 2131 * extra constraint of never generating TLB conflict aborts when using 2132 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2133 * kernel contexts difficult to prove safe against recursive aborts). 2134 * 2135 * Note that implementations can only be considered "known-good" if their 2136 * implementors attest to the fact that the implementation never raises 2137 * TLB conflict aborts for BBML2 mapping granularity changes. 2138 */ 2139 static const struct midr_range supports_bbml2_noabort_list[] = { 2140 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2141 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2142 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2143 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2144 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2145 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2146 {} 2147 }; 2148 2149 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2150 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2151 return false; 2152 2153 /* 2154 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2155 * about whether the MIDR check passes. 2156 */ 2157 2158 return true; 2159 } 2160 2161 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2162 { 2163 return cpu_supports_bbml2_noabort(); 2164 } 2165 2166 #ifdef CONFIG_ARM64_PAN 2167 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2168 { 2169 /* 2170 * We modify PSTATE. This won't work from irq context as the PSTATE 2171 * is discarded once we return from the exception. 2172 */ 2173 WARN_ON_ONCE(in_interrupt()); 2174 2175 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2176 set_pstate_pan(1); 2177 } 2178 #endif /* CONFIG_ARM64_PAN */ 2179 2180 #ifdef CONFIG_ARM64_RAS_EXTN 2181 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2182 { 2183 /* Firmware may have left a deferred SError in this register. */ 2184 write_sysreg_s(0, SYS_DISR_EL1); 2185 } 2186 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2187 { 2188 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2189 { 2190 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2191 }, 2192 { 2193 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2194 }, 2195 { 2196 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2197 }, 2198 }; 2199 2200 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2201 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2202 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2203 } 2204 #endif /* CONFIG_ARM64_RAS_EXTN */ 2205 2206 #ifdef CONFIG_ARM64_PTR_AUTH 2207 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2208 { 2209 int boot_val, sec_val; 2210 2211 /* We don't expect to be called with SCOPE_SYSTEM */ 2212 WARN_ON(scope == SCOPE_SYSTEM); 2213 /* 2214 * The ptr-auth feature levels are not intercompatible with lower 2215 * levels. Hence we must match ptr-auth feature level of the secondary 2216 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2217 * from the sanitised register whereas direct register read is done for 2218 * the secondary CPUs. 2219 * The sanitised feature state is guaranteed to match that of the 2220 * boot CPU as a mismatched secondary CPU is parked before it gets 2221 * a chance to update the state, with the capability. 2222 */ 2223 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2224 entry->field_pos, entry->sign); 2225 if (scope & SCOPE_BOOT_CPU) 2226 return boot_val >= entry->min_field_value; 2227 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2228 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2229 entry->field_pos, entry->sign); 2230 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2231 } 2232 2233 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2234 int scope) 2235 { 2236 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2237 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2238 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2239 2240 return apa || apa3 || api; 2241 } 2242 2243 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2244 int __unused) 2245 { 2246 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2247 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2248 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2249 2250 return gpa || gpa3 || gpi; 2251 } 2252 #endif /* CONFIG_ARM64_PTR_AUTH */ 2253 2254 #ifdef CONFIG_ARM64_E0PD 2255 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2256 { 2257 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2258 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2259 } 2260 #endif /* CONFIG_ARM64_E0PD */ 2261 2262 #ifdef CONFIG_ARM64_PSEUDO_NMI 2263 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2264 int scope) 2265 { 2266 /* 2267 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2268 * feature, so will be detected earlier. 2269 */ 2270 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2271 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2272 return false; 2273 2274 return enable_pseudo_nmi; 2275 } 2276 2277 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2278 int scope) 2279 { 2280 /* 2281 * If we're not using priority masking then we won't be poking PMR_EL1, 2282 * and there's no need to relax synchronization of writes to it, and 2283 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2284 * that. 2285 * 2286 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2287 * feature, so will be detected earlier. 2288 */ 2289 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2290 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2291 return false; 2292 2293 /* 2294 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2295 * hint for interrupt distribution, a DSB is not necessary when 2296 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2297 * 2298 * Linux itself doesn't use 1:N distribution, so has no need to 2299 * set PMHE. The only reason to have it set is if EL3 requires it 2300 * (and we can't change it). 2301 */ 2302 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2303 } 2304 #endif 2305 2306 #ifdef CONFIG_ARM64_BTI 2307 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2308 { 2309 /* 2310 * Use of X16/X17 for tail-calls and trampolines that jump to 2311 * function entry points using BR is a requirement for 2312 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2313 * So, be strict and forbid other BRs using other registers to 2314 * jump onto a PACIxSP instruction: 2315 */ 2316 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2317 isb(); 2318 } 2319 #endif /* CONFIG_ARM64_BTI */ 2320 2321 #ifdef CONFIG_ARM64_MTE 2322 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2323 { 2324 static bool cleared_zero_page = false; 2325 2326 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2327 2328 mte_cpu_setup(); 2329 2330 /* 2331 * Clear the tags in the zero page. This needs to be done via the 2332 * linear map which has the Tagged attribute. Since this page is 2333 * always mapped as pte_special(), set_pte_at() will not attempt to 2334 * clear the tags or set PG_mte_tagged. 2335 */ 2336 if (!cleared_zero_page) { 2337 cleared_zero_page = true; 2338 mte_clear_page_tags(lm_alias(empty_zero_page)); 2339 } 2340 2341 kasan_init_hw_tags_cpu(); 2342 } 2343 #endif /* CONFIG_ARM64_MTE */ 2344 2345 static void user_feature_fixup(void) 2346 { 2347 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2348 struct arm64_ftr_reg *regp; 2349 2350 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2351 if (regp) 2352 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2353 } 2354 2355 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2356 struct arm64_ftr_reg *regp; 2357 2358 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2359 if (regp) 2360 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2361 } 2362 } 2363 2364 static void elf_hwcap_fixup(void) 2365 { 2366 #ifdef CONFIG_COMPAT 2367 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2368 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2369 #endif /* CONFIG_COMPAT */ 2370 } 2371 2372 #ifdef CONFIG_KVM 2373 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2374 { 2375 return kvm_get_mode() == KVM_MODE_PROTECTED; 2376 } 2377 #endif /* CONFIG_KVM */ 2378 2379 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2380 { 2381 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2382 } 2383 2384 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2385 { 2386 set_pstate_dit(1); 2387 } 2388 2389 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2390 { 2391 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2392 } 2393 2394 #ifdef CONFIG_ARM64_POE 2395 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2396 { 2397 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2398 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2399 } 2400 #endif 2401 2402 #ifdef CONFIG_ARM64_GCS 2403 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2404 { 2405 /* GCSPR_EL0 is always readable */ 2406 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2407 } 2408 #endif 2409 2410 /* Internal helper functions to match cpu capability type */ 2411 static bool 2412 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2413 { 2414 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2415 } 2416 2417 static bool 2418 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2419 { 2420 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2421 } 2422 2423 static bool 2424 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2425 { 2426 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2427 } 2428 2429 static bool 2430 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2431 { 2432 if (!has_cpuid_feature(entry, scope)) 2433 return false; 2434 2435 /* Check firmware actually enabled MPAM on this cpu. */ 2436 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2437 } 2438 2439 static void 2440 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2441 { 2442 /* 2443 * Access by the kernel (at EL1) should use the reserved PARTID 2444 * which is configured unrestricted. This avoids priority-inversion 2445 * where latency sensitive tasks have to wait for a task that has 2446 * been throttled to release the lock. 2447 */ 2448 write_sysreg_s(0, SYS_MPAM1_EL1); 2449 } 2450 2451 static bool 2452 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2453 { 2454 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2455 2456 return idr & MPAMIDR_EL1_HAS_HCR; 2457 } 2458 2459 static bool 2460 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2461 { 2462 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2463 return false; 2464 2465 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2466 } 2467 2468 static const struct arm64_cpu_capabilities arm64_features[] = { 2469 { 2470 .capability = ARM64_ALWAYS_BOOT, 2471 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2472 .matches = has_always, 2473 }, 2474 { 2475 .capability = ARM64_ALWAYS_SYSTEM, 2476 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2477 .matches = has_always, 2478 }, 2479 { 2480 .desc = "GICv3 CPU interface", 2481 .capability = ARM64_HAS_GICV3_CPUIF, 2482 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2483 .matches = has_useable_gicv3_cpuif, 2484 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2485 }, 2486 { 2487 .desc = "Enhanced Counter Virtualization", 2488 .capability = ARM64_HAS_ECV, 2489 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2490 .matches = has_cpuid_feature, 2491 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2492 }, 2493 { 2494 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2495 .capability = ARM64_HAS_ECV_CNTPOFF, 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .matches = has_cpuid_feature, 2498 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2499 }, 2500 #ifdef CONFIG_ARM64_PAN 2501 { 2502 .desc = "Privileged Access Never", 2503 .capability = ARM64_HAS_PAN, 2504 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2505 .matches = has_cpuid_feature, 2506 .cpu_enable = cpu_enable_pan, 2507 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2508 }, 2509 #endif /* CONFIG_ARM64_PAN */ 2510 #ifdef CONFIG_ARM64_EPAN 2511 { 2512 .desc = "Enhanced Privileged Access Never", 2513 .capability = ARM64_HAS_EPAN, 2514 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2515 .matches = has_cpuid_feature, 2516 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2517 }, 2518 #endif /* CONFIG_ARM64_EPAN */ 2519 #ifdef CONFIG_ARM64_LSE_ATOMICS 2520 { 2521 .desc = "LSE atomic instructions", 2522 .capability = ARM64_HAS_LSE_ATOMICS, 2523 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2524 .matches = has_cpuid_feature, 2525 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2526 }, 2527 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2528 { 2529 .desc = "Virtualization Host Extensions", 2530 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2531 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2532 .matches = runs_at_el2, 2533 .cpu_enable = cpu_copy_el2regs, 2534 }, 2535 { 2536 .desc = "Nested Virtualization Support", 2537 .capability = ARM64_HAS_NESTED_VIRT, 2538 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2539 .matches = has_nested_virt_support, 2540 .match_list = (const struct arm64_cpu_capabilities []){ 2541 { 2542 .matches = has_cpuid_feature, 2543 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2544 }, 2545 { 2546 .matches = has_cpuid_feature, 2547 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2548 }, 2549 { /* Sentinel */ } 2550 }, 2551 }, 2552 { 2553 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2554 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2555 .matches = has_32bit_el0, 2556 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2557 }, 2558 #ifdef CONFIG_KVM 2559 { 2560 .desc = "32-bit EL1 Support", 2561 .capability = ARM64_HAS_32BIT_EL1, 2562 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2563 .matches = has_cpuid_feature, 2564 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2565 }, 2566 { 2567 .desc = "Protected KVM", 2568 .capability = ARM64_KVM_PROTECTED_MODE, 2569 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2570 .matches = is_kvm_protected_mode, 2571 }, 2572 { 2573 .desc = "HCRX_EL2 register", 2574 .capability = ARM64_HAS_HCX, 2575 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2576 .matches = has_cpuid_feature, 2577 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2578 }, 2579 #endif 2580 { 2581 .desc = "Kernel page table isolation (KPTI)", 2582 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2583 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2584 .cpu_enable = cpu_enable_kpti, 2585 .matches = unmap_kernel_at_el0, 2586 /* 2587 * The ID feature fields below are used to indicate that 2588 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2589 * more details. 2590 */ 2591 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2592 }, 2593 { 2594 .capability = ARM64_HAS_FPSIMD, 2595 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2596 .matches = has_cpuid_feature, 2597 .cpu_enable = cpu_enable_fpsimd, 2598 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2599 }, 2600 #ifdef CONFIG_ARM64_PMEM 2601 { 2602 .desc = "Data cache clean to Point of Persistence", 2603 .capability = ARM64_HAS_DCPOP, 2604 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2605 .matches = has_cpuid_feature, 2606 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2607 }, 2608 { 2609 .desc = "Data cache clean to Point of Deep Persistence", 2610 .capability = ARM64_HAS_DCPODP, 2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2612 .matches = has_cpuid_feature, 2613 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2614 }, 2615 #endif 2616 #ifdef CONFIG_ARM64_SVE 2617 { 2618 .desc = "Scalable Vector Extension", 2619 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2620 .capability = ARM64_SVE, 2621 .cpu_enable = cpu_enable_sve, 2622 .matches = has_cpuid_feature, 2623 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2624 }, 2625 #endif /* CONFIG_ARM64_SVE */ 2626 #ifdef CONFIG_ARM64_RAS_EXTN 2627 { 2628 .desc = "RAS Extension Support", 2629 .capability = ARM64_HAS_RAS_EXTN, 2630 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2631 .matches = has_cpuid_feature, 2632 .cpu_enable = cpu_clear_disr, 2633 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2634 }, 2635 { 2636 .desc = "RASv1p1 Extension Support", 2637 .capability = ARM64_HAS_RASV1P1_EXTN, 2638 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2639 .matches = has_rasv1p1, 2640 }, 2641 #endif /* CONFIG_ARM64_RAS_EXTN */ 2642 #ifdef CONFIG_ARM64_AMU_EXTN 2643 { 2644 .desc = "Activity Monitors Unit (AMU)", 2645 .capability = ARM64_HAS_AMU_EXTN, 2646 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2647 .matches = has_amu, 2648 .cpu_enable = cpu_amu_enable, 2649 .cpus = &amu_cpus, 2650 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2651 }, 2652 #endif /* CONFIG_ARM64_AMU_EXTN */ 2653 { 2654 .desc = "Data cache clean to the PoU not required for I/D coherence", 2655 .capability = ARM64_HAS_CACHE_IDC, 2656 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2657 .matches = has_cache_idc, 2658 .cpu_enable = cpu_emulate_effective_ctr, 2659 }, 2660 { 2661 .desc = "Instruction cache invalidation not required for I/D coherence", 2662 .capability = ARM64_HAS_CACHE_DIC, 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .matches = has_cache_dic, 2665 }, 2666 { 2667 .desc = "Stage-2 Force Write-Back", 2668 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2669 .capability = ARM64_HAS_STAGE2_FWB, 2670 .matches = has_cpuid_feature, 2671 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2672 }, 2673 { 2674 .desc = "ARMv8.4 Translation Table Level", 2675 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2676 .capability = ARM64_HAS_ARMv8_4_TTL, 2677 .matches = has_cpuid_feature, 2678 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2679 }, 2680 { 2681 .desc = "TLB range maintenance instructions", 2682 .capability = ARM64_HAS_TLB_RANGE, 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .matches = has_cpuid_feature, 2685 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2686 }, 2687 #ifdef CONFIG_ARM64_HW_AFDBM 2688 { 2689 .desc = "Hardware dirty bit management", 2690 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2691 .capability = ARM64_HW_DBM, 2692 .matches = has_hw_dbm, 2693 .cpu_enable = cpu_enable_hw_dbm, 2694 .cpus = &dbm_cpus, 2695 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2696 }, 2697 #endif 2698 #ifdef CONFIG_ARM64_HAFT 2699 { 2700 .desc = "Hardware managed Access Flag for Table Descriptors", 2701 /* 2702 * Contrary to the page/block access flag, the table access flag 2703 * cannot be emulated in software (no access fault will occur). 2704 * Therefore this should be used only if it's supported system 2705 * wide. 2706 */ 2707 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2708 .capability = ARM64_HAFT, 2709 .matches = has_cpuid_feature, 2710 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2711 }, 2712 #endif 2713 { 2714 .desc = "CRC32 instructions", 2715 .capability = ARM64_HAS_CRC32, 2716 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2717 .matches = has_cpuid_feature, 2718 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2719 }, 2720 { 2721 .desc = "Speculative Store Bypassing Safe (SSBS)", 2722 .capability = ARM64_SSBS, 2723 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2724 .matches = has_cpuid_feature, 2725 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2726 }, 2727 #ifdef CONFIG_ARM64_CNP 2728 { 2729 .desc = "Common not Private translations", 2730 .capability = ARM64_HAS_CNP, 2731 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2732 .matches = has_useable_cnp, 2733 .cpu_enable = cpu_enable_cnp, 2734 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2735 }, 2736 #endif 2737 { 2738 .desc = "Speculation barrier (SB)", 2739 .capability = ARM64_HAS_SB, 2740 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2741 .matches = has_cpuid_feature, 2742 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2743 }, 2744 #ifdef CONFIG_ARM64_PTR_AUTH 2745 { 2746 .desc = "Address authentication (architected QARMA5 algorithm)", 2747 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2748 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2749 .matches = has_address_auth_cpucap, 2750 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2751 }, 2752 { 2753 .desc = "Address authentication (architected QARMA3 algorithm)", 2754 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2755 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2756 .matches = has_address_auth_cpucap, 2757 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2758 }, 2759 { 2760 .desc = "Address authentication (IMP DEF algorithm)", 2761 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2762 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2763 .matches = has_address_auth_cpucap, 2764 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2765 }, 2766 { 2767 .capability = ARM64_HAS_ADDRESS_AUTH, 2768 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2769 .matches = has_address_auth_metacap, 2770 }, 2771 { 2772 .desc = "Generic authentication (architected QARMA5 algorithm)", 2773 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2774 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2775 .matches = has_cpuid_feature, 2776 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2777 }, 2778 { 2779 .desc = "Generic authentication (architected QARMA3 algorithm)", 2780 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2782 .matches = has_cpuid_feature, 2783 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2784 }, 2785 { 2786 .desc = "Generic authentication (IMP DEF algorithm)", 2787 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2789 .matches = has_cpuid_feature, 2790 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2791 }, 2792 { 2793 .capability = ARM64_HAS_GENERIC_AUTH, 2794 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2795 .matches = has_generic_auth, 2796 }, 2797 #endif /* CONFIG_ARM64_PTR_AUTH */ 2798 #ifdef CONFIG_ARM64_PSEUDO_NMI 2799 { 2800 /* 2801 * Depends on having GICv3 2802 */ 2803 .desc = "IRQ priority masking", 2804 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2805 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2806 .matches = can_use_gic_priorities, 2807 }, 2808 { 2809 /* 2810 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2811 */ 2812 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2813 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2814 .matches = has_gic_prio_relaxed_sync, 2815 }, 2816 #endif 2817 #ifdef CONFIG_ARM64_E0PD 2818 { 2819 .desc = "E0PD", 2820 .capability = ARM64_HAS_E0PD, 2821 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2822 .cpu_enable = cpu_enable_e0pd, 2823 .matches = has_cpuid_feature, 2824 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2825 }, 2826 #endif 2827 { 2828 .desc = "Random Number Generator", 2829 .capability = ARM64_HAS_RNG, 2830 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2831 .matches = has_cpuid_feature, 2832 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2833 }, 2834 #ifdef CONFIG_ARM64_BTI 2835 { 2836 .desc = "Branch Target Identification", 2837 .capability = ARM64_BTI, 2838 #ifdef CONFIG_ARM64_BTI_KERNEL 2839 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2840 #else 2841 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2842 #endif 2843 .matches = has_cpuid_feature, 2844 .cpu_enable = bti_enable, 2845 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2846 }, 2847 #endif 2848 #ifdef CONFIG_ARM64_MTE 2849 { 2850 .desc = "Memory Tagging Extension", 2851 .capability = ARM64_MTE, 2852 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2853 .matches = has_cpuid_feature, 2854 .cpu_enable = cpu_enable_mte, 2855 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2856 }, 2857 { 2858 .desc = "Asymmetric MTE Tag Check Fault", 2859 .capability = ARM64_MTE_ASYMM, 2860 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2861 .matches = has_cpuid_feature, 2862 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2863 }, 2864 { 2865 .desc = "FAR on MTE Tag Check Fault", 2866 .capability = ARM64_MTE_FAR, 2867 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2868 .matches = has_cpuid_feature, 2869 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2870 }, 2871 { 2872 .desc = "Store Only MTE Tag Check", 2873 .capability = ARM64_MTE_STORE_ONLY, 2874 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2875 .matches = has_cpuid_feature, 2876 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2877 }, 2878 #endif /* CONFIG_ARM64_MTE */ 2879 { 2880 .desc = "RCpc load-acquire (LDAPR)", 2881 .capability = ARM64_HAS_LDAPR, 2882 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2883 .matches = has_cpuid_feature, 2884 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2885 }, 2886 { 2887 .desc = "Fine Grained Traps", 2888 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2889 .capability = ARM64_HAS_FGT, 2890 .matches = has_cpuid_feature, 2891 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2892 }, 2893 { 2894 .desc = "Fine Grained Traps 2", 2895 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2896 .capability = ARM64_HAS_FGT2, 2897 .matches = has_cpuid_feature, 2898 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2899 }, 2900 #ifdef CONFIG_ARM64_SME 2901 { 2902 .desc = "Scalable Matrix Extension", 2903 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2904 .capability = ARM64_SME, 2905 .matches = has_cpuid_feature, 2906 .cpu_enable = cpu_enable_sme, 2907 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2908 }, 2909 /* FA64 should be sorted after the base SME capability */ 2910 { 2911 .desc = "FA64", 2912 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2913 .capability = ARM64_SME_FA64, 2914 .matches = has_cpuid_feature, 2915 .cpu_enable = cpu_enable_fa64, 2916 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2917 }, 2918 { 2919 .desc = "SME2", 2920 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2921 .capability = ARM64_SME2, 2922 .matches = has_cpuid_feature, 2923 .cpu_enable = cpu_enable_sme2, 2924 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2925 }, 2926 #endif /* CONFIG_ARM64_SME */ 2927 { 2928 .desc = "WFx with timeout", 2929 .capability = ARM64_HAS_WFXT, 2930 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2931 .matches = has_cpuid_feature, 2932 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2933 }, 2934 { 2935 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2936 .capability = ARM64_HAS_TIDCP1, 2937 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2938 .matches = has_cpuid_feature, 2939 .cpu_enable = cpu_trap_el0_impdef, 2940 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2941 }, 2942 { 2943 .desc = "Data independent timing control (DIT)", 2944 .capability = ARM64_HAS_DIT, 2945 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2946 .matches = has_cpuid_feature, 2947 .cpu_enable = cpu_enable_dit, 2948 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2949 }, 2950 { 2951 .desc = "Memory Copy and Memory Set instructions", 2952 .capability = ARM64_HAS_MOPS, 2953 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2954 .matches = has_cpuid_feature, 2955 .cpu_enable = cpu_enable_mops, 2956 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2957 }, 2958 { 2959 .capability = ARM64_HAS_TCR2, 2960 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2961 .matches = has_cpuid_feature, 2962 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2963 }, 2964 { 2965 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2966 .capability = ARM64_HAS_S1PIE, 2967 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2968 .matches = has_cpuid_feature, 2969 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2970 }, 2971 { 2972 .desc = "VHE for hypervisor only", 2973 .capability = ARM64_KVM_HVHE, 2974 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2975 .matches = hvhe_possible, 2976 }, 2977 { 2978 .desc = "Enhanced Virtualization Traps", 2979 .capability = ARM64_HAS_EVT, 2980 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2981 .matches = has_cpuid_feature, 2982 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2983 }, 2984 { 2985 .desc = "BBM Level 2 without TLB conflict abort", 2986 .capability = ARM64_HAS_BBML2_NOABORT, 2987 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2988 .matches = has_bbml2_noabort, 2989 }, 2990 { 2991 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2992 .capability = ARM64_HAS_LPA2, 2993 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2994 .matches = has_lpa2, 2995 }, 2996 { 2997 .desc = "FPMR", 2998 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2999 .capability = ARM64_HAS_FPMR, 3000 .matches = has_cpuid_feature, 3001 .cpu_enable = cpu_enable_fpmr, 3002 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3003 }, 3004 #ifdef CONFIG_ARM64_VA_BITS_52 3005 { 3006 .capability = ARM64_HAS_VA52, 3007 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3008 .matches = has_cpuid_feature, 3009 #ifdef CONFIG_ARM64_64K_PAGES 3010 .desc = "52-bit Virtual Addressing (LVA)", 3011 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3012 #else 3013 .desc = "52-bit Virtual Addressing (LPA2)", 3014 #ifdef CONFIG_ARM64_4K_PAGES 3015 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3016 #else 3017 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3018 #endif 3019 #endif 3020 }, 3021 #endif 3022 { 3023 .desc = "Memory Partitioning And Monitoring", 3024 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3025 .capability = ARM64_MPAM, 3026 .matches = test_has_mpam, 3027 .cpu_enable = cpu_enable_mpam, 3028 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3029 }, 3030 { 3031 .desc = "Memory Partitioning And Monitoring Virtualisation", 3032 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3033 .capability = ARM64_MPAM_HCR, 3034 .matches = test_has_mpam_hcr, 3035 }, 3036 { 3037 .desc = "NV1", 3038 .capability = ARM64_HAS_HCR_NV1, 3039 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3040 .matches = has_nv1, 3041 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3042 }, 3043 #ifdef CONFIG_ARM64_POE 3044 { 3045 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3046 .capability = ARM64_HAS_S1POE, 3047 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3048 .matches = has_cpuid_feature, 3049 .cpu_enable = cpu_enable_poe, 3050 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3051 }, 3052 #endif 3053 #ifdef CONFIG_ARM64_GCS 3054 { 3055 .desc = "Guarded Control Stack (GCS)", 3056 .capability = ARM64_HAS_GCS, 3057 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3058 .cpu_enable = cpu_enable_gcs, 3059 .matches = has_cpuid_feature, 3060 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3061 }, 3062 #endif 3063 #ifdef CONFIG_HW_PERF_EVENTS 3064 { 3065 .desc = "PMUv3", 3066 .capability = ARM64_HAS_PMUV3, 3067 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3068 .matches = has_pmuv3, 3069 }, 3070 #endif 3071 { 3072 .desc = "SCTLR2", 3073 .capability = ARM64_HAS_SCTLR2, 3074 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3075 .matches = has_cpuid_feature, 3076 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3077 }, 3078 { 3079 .desc = "GICv5 CPU interface", 3080 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3081 .capability = ARM64_HAS_GICV5_CPUIF, 3082 .matches = has_cpuid_feature, 3083 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3084 }, 3085 { 3086 .desc = "GICv5 Legacy vCPU interface", 3087 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3088 .capability = ARM64_HAS_GICV5_LEGACY, 3089 .matches = test_has_gicv5_legacy, 3090 }, 3091 {}, 3092 }; 3093 3094 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3095 .matches = has_user_cpuid_feature, \ 3096 ARM64_CPUID_FIELDS(reg, field, min_value) 3097 3098 #define __HWCAP_CAP(name, cap_type, cap) \ 3099 .desc = name, \ 3100 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3101 .hwcap_type = cap_type, \ 3102 .hwcap = cap, \ 3103 3104 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3105 { \ 3106 __HWCAP_CAP(#cap, cap_type, cap) \ 3107 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3108 } 3109 3110 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3111 { \ 3112 __HWCAP_CAP(#cap, cap_type, cap) \ 3113 .matches = cpucap_multi_entry_cap_matches, \ 3114 .match_list = list, \ 3115 } 3116 3117 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3118 { \ 3119 __HWCAP_CAP(#cap, cap_type, cap) \ 3120 .matches = match, \ 3121 } 3122 3123 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3124 { \ 3125 __HWCAP_CAP(#cap, cap_type, cap) \ 3126 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3127 .matches = match, \ 3128 } 3129 3130 #ifdef CONFIG_ARM64_PTR_AUTH 3131 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3132 { 3133 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3134 }, 3135 { 3136 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3137 }, 3138 { 3139 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3140 }, 3141 {}, 3142 }; 3143 3144 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3145 { 3146 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3147 }, 3148 { 3149 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3150 }, 3151 { 3152 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3153 }, 3154 {}, 3155 }; 3156 #endif 3157 3158 #ifdef CONFIG_ARM64_SVE 3159 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3160 { 3161 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3162 } 3163 #endif 3164 3165 #ifdef CONFIG_ARM64_SME 3166 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3167 { 3168 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3169 } 3170 #endif 3171 3172 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3173 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3174 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3175 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3176 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3177 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3178 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3179 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3180 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3181 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3182 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3183 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3184 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3185 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3186 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3187 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3188 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3189 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3190 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3191 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3192 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3193 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3194 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3195 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3196 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3197 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3198 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3199 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3200 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3201 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3202 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3203 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3204 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3205 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3206 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3207 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3208 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3209 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3210 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3211 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3212 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3213 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3214 #ifdef CONFIG_ARM64_SVE 3215 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3216 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3217 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3218 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3219 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3220 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3221 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3222 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3223 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3224 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3225 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3226 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3227 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3228 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3229 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3230 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3231 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3232 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3233 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3234 #endif 3235 #ifdef CONFIG_ARM64_GCS 3236 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3237 #endif 3238 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3239 #ifdef CONFIG_ARM64_BTI 3240 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3241 #endif 3242 #ifdef CONFIG_ARM64_PTR_AUTH 3243 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3244 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3245 #endif 3246 #ifdef CONFIG_ARM64_MTE 3247 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3248 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3249 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3250 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3251 #endif /* CONFIG_ARM64_MTE */ 3252 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3253 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3254 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3255 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3256 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3257 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3258 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3259 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3260 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3261 #ifdef CONFIG_ARM64_SME 3262 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3263 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3264 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3265 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3266 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3267 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3268 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3269 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3270 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3271 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3272 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3273 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3274 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3275 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3276 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3277 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3278 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3279 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3280 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3281 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3282 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3283 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3284 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3285 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3286 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3287 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3288 #endif /* CONFIG_ARM64_SME */ 3289 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3290 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3291 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3292 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3293 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3294 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3295 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3296 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3297 #ifdef CONFIG_ARM64_POE 3298 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3299 #endif 3300 {}, 3301 }; 3302 3303 #ifdef CONFIG_COMPAT 3304 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3305 { 3306 /* 3307 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3308 * in line with that of arm32 as in vfp_init(). We make sure that the 3309 * check is future proof, by making sure value is non-zero. 3310 */ 3311 u32 mvfr1; 3312 3313 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3314 if (scope == SCOPE_SYSTEM) 3315 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3316 else 3317 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3318 3319 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3320 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3321 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3322 } 3323 #endif 3324 3325 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3326 #ifdef CONFIG_COMPAT 3327 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3328 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3329 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3330 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3331 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3332 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3333 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3334 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3335 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3336 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3337 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3338 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3339 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3340 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3341 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3342 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3343 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3344 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3345 #endif 3346 {}, 3347 }; 3348 3349 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3350 { 3351 switch (cap->hwcap_type) { 3352 case CAP_HWCAP: 3353 cpu_set_feature(cap->hwcap); 3354 break; 3355 #ifdef CONFIG_COMPAT 3356 case CAP_COMPAT_HWCAP: 3357 compat_elf_hwcap |= (u32)cap->hwcap; 3358 break; 3359 case CAP_COMPAT_HWCAP2: 3360 compat_elf_hwcap2 |= (u32)cap->hwcap; 3361 break; 3362 #endif 3363 default: 3364 WARN_ON(1); 3365 break; 3366 } 3367 } 3368 3369 /* Check if we have a particular HWCAP enabled */ 3370 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3371 { 3372 bool rc; 3373 3374 switch (cap->hwcap_type) { 3375 case CAP_HWCAP: 3376 rc = cpu_have_feature(cap->hwcap); 3377 break; 3378 #ifdef CONFIG_COMPAT 3379 case CAP_COMPAT_HWCAP: 3380 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3381 break; 3382 case CAP_COMPAT_HWCAP2: 3383 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3384 break; 3385 #endif 3386 default: 3387 WARN_ON(1); 3388 rc = false; 3389 } 3390 3391 return rc; 3392 } 3393 3394 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3395 { 3396 /* We support emulation of accesses to CPU ID feature registers */ 3397 cpu_set_named_feature(CPUID); 3398 for (; hwcaps->matches; hwcaps++) 3399 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3400 cap_set_elf_hwcap(hwcaps); 3401 } 3402 3403 static void update_cpu_capabilities(u16 scope_mask) 3404 { 3405 int i; 3406 const struct arm64_cpu_capabilities *caps; 3407 3408 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3409 for (i = 0; i < ARM64_NCAPS; i++) { 3410 bool match_all = false; 3411 bool caps_set = false; 3412 bool boot_cpu = false; 3413 3414 caps = cpucap_ptrs[i]; 3415 if (!caps || !(caps->type & scope_mask)) 3416 continue; 3417 3418 match_all = cpucap_match_all_early_cpus(caps); 3419 caps_set = cpus_have_cap(caps->capability); 3420 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3421 3422 /* 3423 * Unless it's a match-all CPUs feature, avoid probing if 3424 * already detected. 3425 */ 3426 if (!match_all && caps_set) 3427 continue; 3428 3429 /* 3430 * A match-all CPUs capability is only set when probing the 3431 * boot CPU. It may be cleared subsequently if not detected on 3432 * secondary ones. 3433 */ 3434 if (match_all && !caps_set && !boot_cpu) 3435 continue; 3436 3437 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3438 if (match_all) 3439 __clear_bit(caps->capability, system_cpucaps); 3440 continue; 3441 } 3442 3443 /* 3444 * Match-all CPUs capabilities are logged later when the 3445 * system capabilities are finalised. 3446 */ 3447 if (!match_all && caps->desc && !caps->cpus) 3448 pr_info("detected: %s\n", caps->desc); 3449 3450 __set_bit(caps->capability, system_cpucaps); 3451 3452 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3453 set_bit(caps->capability, boot_cpucaps); 3454 } 3455 } 3456 3457 /* 3458 * Enable all the available capabilities on this CPU. The capabilities 3459 * with BOOT_CPU scope are handled separately and hence skipped here. 3460 */ 3461 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3462 { 3463 int i; 3464 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3465 3466 for_each_available_cap(i) { 3467 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3468 3469 if (WARN_ON(!cap)) 3470 continue; 3471 3472 if (!(cap->type & non_boot_scope)) 3473 continue; 3474 3475 if (cap->cpu_enable) 3476 cap->cpu_enable(cap); 3477 } 3478 return 0; 3479 } 3480 3481 /* 3482 * Run through the enabled capabilities and enable() it on all active 3483 * CPUs 3484 */ 3485 static void __init enable_cpu_capabilities(u16 scope_mask) 3486 { 3487 int i; 3488 const struct arm64_cpu_capabilities *caps; 3489 bool boot_scope; 3490 3491 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3492 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3493 3494 for (i = 0; i < ARM64_NCAPS; i++) { 3495 caps = cpucap_ptrs[i]; 3496 if (!caps || !(caps->type & scope_mask) || 3497 !cpus_have_cap(caps->capability)) 3498 continue; 3499 3500 if (boot_scope && caps->cpu_enable) 3501 /* 3502 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3503 * before any secondary CPU boots. Thus, each secondary 3504 * will enable the capability as appropriate via 3505 * check_local_cpu_capabilities(). The only exception is 3506 * the boot CPU, for which the capability must be 3507 * enabled here. This approach avoids costly 3508 * stop_machine() calls for this case. 3509 */ 3510 caps->cpu_enable(caps); 3511 } 3512 3513 /* 3514 * For all non-boot scope capabilities, use stop_machine() 3515 * as it schedules the work allowing us to modify PSTATE, 3516 * instead of on_each_cpu() which uses an IPI, giving us a 3517 * PSTATE that disappears when we return. 3518 */ 3519 if (!boot_scope) 3520 stop_machine(cpu_enable_non_boot_scope_capabilities, 3521 NULL, cpu_online_mask); 3522 } 3523 3524 /* 3525 * Run through the list of capabilities to check for conflicts. 3526 * If the system has already detected a capability, take necessary 3527 * action on this CPU. 3528 */ 3529 static void verify_local_cpu_caps(u16 scope_mask) 3530 { 3531 int i; 3532 bool cpu_has_cap, system_has_cap; 3533 const struct arm64_cpu_capabilities *caps; 3534 3535 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3536 3537 for (i = 0; i < ARM64_NCAPS; i++) { 3538 caps = cpucap_ptrs[i]; 3539 if (!caps || !(caps->type & scope_mask)) 3540 continue; 3541 3542 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3543 system_has_cap = cpus_have_cap(caps->capability); 3544 3545 if (system_has_cap) { 3546 /* 3547 * Check if the new CPU misses an advertised feature, 3548 * which is not safe to miss. 3549 */ 3550 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3551 break; 3552 /* 3553 * We have to issue cpu_enable() irrespective of 3554 * whether the CPU has it or not, as it is enabeld 3555 * system wide. It is upto the call back to take 3556 * appropriate action on this CPU. 3557 */ 3558 if (caps->cpu_enable) 3559 caps->cpu_enable(caps); 3560 } else { 3561 /* 3562 * Check if the CPU has this capability if it isn't 3563 * safe to have when the system doesn't. 3564 */ 3565 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3566 break; 3567 } 3568 } 3569 3570 if (i < ARM64_NCAPS) { 3571 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3572 smp_processor_id(), caps->capability, 3573 caps->desc, system_has_cap, cpu_has_cap); 3574 3575 if (cpucap_panic_on_conflict(caps)) 3576 cpu_panic_kernel(); 3577 else 3578 cpu_die_early(); 3579 } 3580 } 3581 3582 /* 3583 * Check for CPU features that are used in early boot 3584 * based on the Boot CPU value. 3585 */ 3586 static void check_early_cpu_features(void) 3587 { 3588 verify_cpu_asid_bits(); 3589 3590 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3591 } 3592 3593 static void 3594 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3595 { 3596 3597 for (; caps->matches; caps++) 3598 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3599 pr_crit("CPU%d: missing HWCAP: %s\n", 3600 smp_processor_id(), caps->desc); 3601 cpu_die_early(); 3602 } 3603 } 3604 3605 static void verify_local_elf_hwcaps(void) 3606 { 3607 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3608 3609 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3610 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3611 } 3612 3613 static void verify_sve_features(void) 3614 { 3615 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3616 3617 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3618 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3619 smp_processor_id()); 3620 cpu_die_early(); 3621 } 3622 3623 cpacr_restore(cpacr); 3624 } 3625 3626 static void verify_sme_features(void) 3627 { 3628 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3629 3630 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3631 pr_crit("CPU%d: SME: vector length support mismatch\n", 3632 smp_processor_id()); 3633 cpu_die_early(); 3634 } 3635 3636 cpacr_restore(cpacr); 3637 } 3638 3639 static void verify_hyp_capabilities(void) 3640 { 3641 u64 safe_mmfr1, mmfr0, mmfr1; 3642 int parange, ipa_max; 3643 unsigned int safe_vmid_bits, vmid_bits; 3644 3645 if (!IS_ENABLED(CONFIG_KVM)) 3646 return; 3647 3648 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3649 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3650 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3651 3652 /* Verify VMID bits */ 3653 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3654 vmid_bits = get_vmid_bits(mmfr1); 3655 if (vmid_bits < safe_vmid_bits) { 3656 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3657 cpu_die_early(); 3658 } 3659 3660 /* Verify IPA range */ 3661 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3662 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3663 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3664 if (ipa_max < get_kvm_ipa_limit()) { 3665 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3666 cpu_die_early(); 3667 } 3668 } 3669 3670 static void verify_mpam_capabilities(void) 3671 { 3672 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3673 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3674 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3675 3676 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3677 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3678 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3679 cpu_die_early(); 3680 } 3681 3682 cpu_idr = read_cpuid(MPAMIDR_EL1); 3683 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3684 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3685 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3686 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3687 cpu_die_early(); 3688 } 3689 3690 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3691 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3692 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3693 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3694 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3695 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3696 cpu_die_early(); 3697 } 3698 } 3699 3700 /* 3701 * Run through the enabled system capabilities and enable() it on this CPU. 3702 * The capabilities were decided based on the available CPUs at the boot time. 3703 * Any new CPU should match the system wide status of the capability. If the 3704 * new CPU doesn't have a capability which the system now has enabled, we 3705 * cannot do anything to fix it up and could cause unexpected failures. So 3706 * we park the CPU. 3707 */ 3708 static void verify_local_cpu_capabilities(void) 3709 { 3710 /* 3711 * The capabilities with SCOPE_BOOT_CPU are checked from 3712 * check_early_cpu_features(), as they need to be verified 3713 * on all secondary CPUs. 3714 */ 3715 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3716 verify_local_elf_hwcaps(); 3717 3718 if (system_supports_sve()) 3719 verify_sve_features(); 3720 3721 if (system_supports_sme()) 3722 verify_sme_features(); 3723 3724 if (is_hyp_mode_available()) 3725 verify_hyp_capabilities(); 3726 3727 if (system_supports_mpam()) 3728 verify_mpam_capabilities(); 3729 } 3730 3731 void check_local_cpu_capabilities(void) 3732 { 3733 /* 3734 * All secondary CPUs should conform to the early CPU features 3735 * in use by the kernel based on boot CPU. 3736 */ 3737 check_early_cpu_features(); 3738 3739 /* 3740 * If we haven't finalised the system capabilities, this CPU gets 3741 * a chance to update the errata work arounds and local features. 3742 * Otherwise, this CPU should verify that it has all the system 3743 * advertised capabilities. 3744 */ 3745 if (!system_capabilities_finalized()) 3746 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3747 else 3748 verify_local_cpu_capabilities(); 3749 } 3750 3751 bool this_cpu_has_cap(unsigned int n) 3752 { 3753 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3754 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3755 3756 if (cap) 3757 return cap->matches(cap, SCOPE_LOCAL_CPU); 3758 } 3759 3760 return false; 3761 } 3762 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3763 3764 /* 3765 * This helper function is used in a narrow window when, 3766 * - The system wide safe registers are set with all the SMP CPUs and, 3767 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3768 */ 3769 static bool __maybe_unused __system_matches_cap(unsigned int n) 3770 { 3771 if (n < ARM64_NCAPS) { 3772 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3773 3774 if (cap) 3775 return cap->matches(cap, SCOPE_SYSTEM); 3776 } 3777 return false; 3778 } 3779 3780 void cpu_set_feature(unsigned int num) 3781 { 3782 set_bit(num, elf_hwcap); 3783 } 3784 3785 bool cpu_have_feature(unsigned int num) 3786 { 3787 return test_bit(num, elf_hwcap); 3788 } 3789 EXPORT_SYMBOL_GPL(cpu_have_feature); 3790 3791 unsigned long cpu_get_elf_hwcap(void) 3792 { 3793 /* 3794 * We currently only populate the first 32 bits of AT_HWCAP. Please 3795 * note that for userspace compatibility we guarantee that bits 62 3796 * and 63 will always be returned as 0. 3797 */ 3798 return elf_hwcap[0]; 3799 } 3800 3801 unsigned long cpu_get_elf_hwcap2(void) 3802 { 3803 return elf_hwcap[1]; 3804 } 3805 3806 unsigned long cpu_get_elf_hwcap3(void) 3807 { 3808 return elf_hwcap[2]; 3809 } 3810 3811 static void __init setup_boot_cpu_capabilities(void) 3812 { 3813 kvm_arm_target_impl_cpu_init(); 3814 /* 3815 * The boot CPU's feature register values have been recorded. Detect 3816 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3817 * patch alternatives for the available boot cpucaps. 3818 */ 3819 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3820 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3821 apply_boot_alternatives(); 3822 } 3823 3824 void __init setup_boot_cpu_features(void) 3825 { 3826 /* 3827 * Initialize the indirect array of CPU capabilities pointers before we 3828 * handle the boot CPU. 3829 */ 3830 init_cpucap_indirect_list(); 3831 3832 /* 3833 * Detect broken pseudo-NMI. Must be called _before_ the call to 3834 * setup_boot_cpu_capabilities() since it interacts with 3835 * can_use_gic_priorities(). 3836 */ 3837 detect_system_supports_pseudo_nmi(); 3838 3839 setup_boot_cpu_capabilities(); 3840 } 3841 3842 static void __init setup_system_capabilities(void) 3843 { 3844 /* 3845 * The system-wide safe feature register values have been finalized. 3846 * Detect, enable, and patch alternatives for the available system 3847 * cpucaps. 3848 */ 3849 update_cpu_capabilities(SCOPE_SYSTEM); 3850 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3851 apply_alternatives_all(); 3852 3853 for (int i = 0; i < ARM64_NCAPS; i++) { 3854 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3855 3856 if (!caps || !caps->desc) 3857 continue; 3858 3859 /* 3860 * Log any cpucaps with a cpumask as these aren't logged by 3861 * update_cpu_capabilities(). 3862 */ 3863 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3864 pr_info("detected: %s on CPU%*pbl\n", 3865 caps->desc, cpumask_pr_args(caps->cpus)); 3866 3867 /* Log match-all CPUs capabilities */ 3868 if (cpucap_match_all_early_cpus(caps) && 3869 cpus_have_cap(caps->capability)) 3870 pr_info("detected: %s\n", caps->desc); 3871 } 3872 3873 /* 3874 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3875 */ 3876 if (system_uses_ttbr0_pan()) 3877 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3878 } 3879 3880 void __init setup_system_features(void) 3881 { 3882 setup_system_capabilities(); 3883 3884 linear_map_maybe_split_to_ptes(); 3885 kpti_install_ng_mappings(); 3886 3887 sve_setup(); 3888 sme_setup(); 3889 3890 /* 3891 * Check for sane CTR_EL0.CWG value. 3892 */ 3893 if (!cache_type_cwg()) 3894 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3895 ARCH_DMA_MINALIGN); 3896 } 3897 3898 void __init setup_user_features(void) 3899 { 3900 user_feature_fixup(); 3901 3902 setup_elf_hwcaps(arm64_elf_hwcaps); 3903 3904 if (system_supports_32bit_el0()) { 3905 setup_elf_hwcaps(compat_elf_hwcaps); 3906 elf_hwcap_fixup(); 3907 } 3908 3909 minsigstksz_setup(); 3910 } 3911 3912 static int enable_mismatched_32bit_el0(unsigned int cpu) 3913 { 3914 /* 3915 * The first 32-bit-capable CPU we detected and so can no longer 3916 * be offlined by userspace. -1 indicates we haven't yet onlined 3917 * a 32-bit-capable CPU. 3918 */ 3919 static int lucky_winner = -1; 3920 3921 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3922 bool cpu_32bit = false; 3923 3924 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3925 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3926 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3927 else 3928 cpu_32bit = true; 3929 } 3930 3931 if (cpu_32bit) { 3932 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3933 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3934 } 3935 3936 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3937 return 0; 3938 3939 if (lucky_winner >= 0) 3940 return 0; 3941 3942 /* 3943 * We've detected a mismatch. We need to keep one of our CPUs with 3944 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3945 * every CPU in the system for a 32-bit task. 3946 */ 3947 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3948 cpu_active_mask); 3949 get_cpu_device(lucky_winner)->offline_disabled = true; 3950 setup_elf_hwcaps(compat_elf_hwcaps); 3951 elf_hwcap_fixup(); 3952 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3953 cpu, lucky_winner); 3954 return 0; 3955 } 3956 3957 static int __init init_32bit_el0_mask(void) 3958 { 3959 if (!allow_mismatched_32bit_el0) 3960 return 0; 3961 3962 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3963 return -ENOMEM; 3964 3965 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3966 "arm64/mismatched_32bit_el0:online", 3967 enable_mismatched_32bit_el0, NULL); 3968 } 3969 subsys_initcall_sync(init_32bit_el0_mask); 3970 3971 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3972 { 3973 cpu_enable_swapper_cnp(); 3974 } 3975 3976 /* 3977 * We emulate only the following system register space. 3978 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3979 * See Table C5-6 System instruction encodings for System register accesses, 3980 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3981 */ 3982 static inline bool __attribute_const__ is_emulated(u32 id) 3983 { 3984 return (sys_reg_Op0(id) == 0x3 && 3985 sys_reg_CRn(id) == 0x0 && 3986 sys_reg_Op1(id) == 0x0 && 3987 (sys_reg_CRm(id) == 0 || 3988 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3989 } 3990 3991 /* 3992 * With CRm == 0, reg should be one of : 3993 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3994 */ 3995 static inline int emulate_id_reg(u32 id, u64 *valp) 3996 { 3997 switch (id) { 3998 case SYS_MIDR_EL1: 3999 *valp = read_cpuid_id(); 4000 break; 4001 case SYS_MPIDR_EL1: 4002 *valp = SYS_MPIDR_SAFE_VAL; 4003 break; 4004 case SYS_REVIDR_EL1: 4005 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4006 *valp = 0; 4007 break; 4008 default: 4009 return -EINVAL; 4010 } 4011 4012 return 0; 4013 } 4014 4015 static int emulate_sys_reg(u32 id, u64 *valp) 4016 { 4017 struct arm64_ftr_reg *regp; 4018 4019 if (!is_emulated(id)) 4020 return -EINVAL; 4021 4022 if (sys_reg_CRm(id) == 0) 4023 return emulate_id_reg(id, valp); 4024 4025 regp = get_arm64_ftr_reg_nowarn(id); 4026 if (regp) 4027 *valp = arm64_ftr_reg_user_value(regp); 4028 else 4029 /* 4030 * The untracked registers are either IMPLEMENTATION DEFINED 4031 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4032 */ 4033 *valp = 0; 4034 return 0; 4035 } 4036 4037 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4038 { 4039 int rc; 4040 u64 val; 4041 4042 rc = emulate_sys_reg(sys_reg, &val); 4043 if (!rc) { 4044 pt_regs_write_reg(regs, rt, val); 4045 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4046 } 4047 return rc; 4048 } 4049 4050 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4051 { 4052 u32 sys_reg, rt; 4053 4054 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4055 return false; 4056 4057 /* 4058 * sys_reg values are defined as used in mrs/msr instruction. 4059 * shift the imm value to get the encoding. 4060 */ 4061 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4062 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4063 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4064 } 4065 4066 enum mitigation_state arm64_get_meltdown_state(void) 4067 { 4068 if (__meltdown_safe) 4069 return SPECTRE_UNAFFECTED; 4070 4071 if (arm64_kernel_unmapped_at_el0()) 4072 return SPECTRE_MITIGATED; 4073 4074 return SPECTRE_VULNERABLE; 4075 } 4076 4077 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4078 char *buf) 4079 { 4080 switch (arm64_get_meltdown_state()) { 4081 case SPECTRE_UNAFFECTED: 4082 return sprintf(buf, "Not affected\n"); 4083 4084 case SPECTRE_MITIGATED: 4085 return sprintf(buf, "Mitigation: PTI\n"); 4086 4087 default: 4088 return sprintf(buf, "Vulnerable\n"); 4089 } 4090 } 4091