1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 unsigned int compat_elf_hwcap3 __read_mostly; 107 #endif 108 109 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 110 EXPORT_SYMBOL(system_cpucaps); 111 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 112 113 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 114 115 bool arm64_use_ng_mappings = false; 116 EXPORT_SYMBOL(arm64_use_ng_mappings); 117 118 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 119 120 /* 121 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 122 * support it? 123 */ 124 static bool __read_mostly allow_mismatched_32bit_el0; 125 126 /* 127 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 128 * seen at least one CPU capable of 32-bit EL0. 129 */ 130 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 131 132 /* 133 * Mask of CPUs supporting 32-bit EL0. 134 * Only valid if arm64_mismatched_32bit_el0 is enabled. 135 */ 136 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 137 138 void dump_cpu_features(void) 139 { 140 /* file-wide pr_fmt adds "CPU features: " prefix */ 141 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 142 } 143 144 #define __ARM64_MAX_POSITIVE(reg, field) \ 145 ((reg##_##field##_SIGNED ? \ 146 BIT(reg##_##field##_WIDTH - 1) : \ 147 BIT(reg##_##field##_WIDTH)) - 1) 148 149 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 150 151 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 152 .sys_reg = SYS_##reg, \ 153 .field_pos = reg##_##field##_SHIFT, \ 154 .field_width = reg##_##field##_WIDTH, \ 155 .sign = reg##_##field##_SIGNED, \ 156 .min_field_value = min_value, \ 157 .max_field_value = max_value, 158 159 /* 160 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 161 * an implicit maximum that depends on the sign-ess of the field. 162 * 163 * An unsigned field will be capped at all ones, while a signed field 164 * will be limited to the positive half only. 165 */ 166 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 167 __ARM64_CPUID_FIELDS(reg, field, \ 168 SYS_FIELD_VALUE(reg, field, min_value), \ 169 __ARM64_MAX_POSITIVE(reg, field)) 170 171 /* 172 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 173 * implicit minimal value to max_value. This should be used when 174 * matching a non-implemented property. 175 */ 176 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 177 __ARM64_CPUID_FIELDS(reg, field, \ 178 __ARM64_MIN_NEGATIVE(reg, field), \ 179 SYS_FIELD_VALUE(reg, field, max_value)) 180 181 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 182 { \ 183 .sign = SIGNED, \ 184 .visible = VISIBLE, \ 185 .strict = STRICT, \ 186 .type = TYPE, \ 187 .shift = SHIFT, \ 188 .width = WIDTH, \ 189 .safe_val = SAFE_VAL, \ 190 } 191 192 /* Define a feature with unsigned values */ 193 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 194 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 195 196 /* Define a feature with a signed value */ 197 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 198 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 199 200 #define ARM64_FTR_END \ 201 { \ 202 .width = 0, \ 203 } 204 205 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 206 207 static bool __system_matches_cap(unsigned int n); 208 209 /* 210 * NOTE: Any changes to the visibility of features should be kept in 211 * sync with the documentation of the CPU feature register ABI. 212 */ 213 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 228 ARM64_FTR_END, 229 }; 230 231 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 251 ARM64_FTR_END, 252 }; 253 254 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 273 ARM64_FTR_END, 274 }; 275 276 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 287 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 288 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 293 ARM64_FTR_END, 294 }; 295 296 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 297 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 298 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 300 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 304 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 305 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 308 ARM64_FTR_END, 309 }; 310 311 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 312 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 313 ARM64_FTR_END, 314 }; 315 316 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 320 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 322 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 324 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 326 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 328 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 330 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 332 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 341 ARM64_FTR_END, 342 }; 343 344 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 346 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 348 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 350 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 352 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 354 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 356 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 358 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 360 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 391 ARM64_FTR_END, 392 }; 393 394 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 395 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 403 ARM64_FTR_END, 404 }; 405 406 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 410 /* 411 * Page size not being supported at Stage-2 is not fatal. You 412 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 413 * your favourite nesting hypervisor. 414 * 415 * There is a small corner case where the hypervisor explicitly 416 * advertises a given granule size at Stage-2 (value 2) on some 417 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 418 * vCPUs. Although this is not forbidden by the architecture, it 419 * indicates that the hypervisor is being silly (or buggy). 420 * 421 * We make no effort to cope with this and pretend that if these 422 * fields are inconsistent across vCPUs, then it isn't worth 423 * trying to bring KVM up. 424 */ 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 428 /* 429 * We already refuse to boot CPUs that don't support our configured 430 * page size, so we can only detect mismatches for a page size other 431 * than the one we're currently using. Unfortunately, SoCs like this 432 * exist in the wild so, even though we don't like it, we'll have to go 433 * along with it and treat them as non-strict. 434 */ 435 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 436 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 438 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 440 /* Linux shouldn't care about secure memory */ 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 444 /* 445 * Differing PARange is fine as long as all peripherals and memory are mapped 446 * within the minimum PARange of all CPUs 447 */ 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 449 ARM64_FTR_END, 450 }; 451 452 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 467 ARM64_FTR_END, 468 }; 469 470 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 486 ARM64_FTR_END, 487 }; 488 489 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 490 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 491 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 494 ARM64_FTR_END, 495 }; 496 497 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 498 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static const struct arm64_ftr_bits ftr_ctr[] = { 503 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 504 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 505 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 506 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 509 /* 510 * Linux can handle differing I-cache policies. Userspace JITs will 511 * make use of *minLine. 512 * If we have differing I-cache policies, report it as the weakest - VIPT. 513 */ 514 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 516 ARM64_FTR_END, 517 }; 518 519 static struct arm64_ftr_override __ro_after_init no_override = { }; 520 521 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 522 .name = "SYS_CTR_EL0", 523 .ftr_bits = ftr_ctr, 524 .override = &no_override, 525 }; 526 527 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 528 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 533 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 534 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 536 ARM64_FTR_END, 537 }; 538 539 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 540 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 545 /* 546 * We can instantiate multiple PMU instances with different levels 547 * of support. 548 */ 549 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 550 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 551 ARM64_FTR_END, 552 }; 553 554 static const struct arm64_ftr_bits ftr_mvfr0[] = { 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 560 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 563 ARM64_FTR_END, 564 }; 565 566 static const struct arm64_ftr_bits ftr_mvfr1[] = { 567 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_mvfr2[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 581 ARM64_FTR_END, 582 }; 583 584 static const struct arm64_ftr_bits ftr_dczid[] = { 585 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 587 ARM64_FTR_END, 588 }; 589 590 static const struct arm64_ftr_bits ftr_gmid[] = { 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 592 ARM64_FTR_END, 593 }; 594 595 static const struct arm64_ftr_bits ftr_id_isar0[] = { 596 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 603 ARM64_FTR_END, 604 }; 605 606 static const struct arm64_ftr_bits ftr_id_isar5[] = { 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 608 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 624 625 /* 626 * SpecSEI = 1 indicates that the PE might generate an SError on an 627 * external abort on speculative read. It is safe to assume that an 628 * SError might be generated than it will not be. Hence it has been 629 * classified as FTR_HIGHER_SAFE. 630 */ 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_isar4[] = { 636 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 644 ARM64_FTR_END, 645 }; 646 647 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 649 ARM64_FTR_END, 650 }; 651 652 static const struct arm64_ftr_bits ftr_id_isar6[] = { 653 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 656 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 657 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 660 ARM64_FTR_END, 661 }; 662 663 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 670 ARM64_FTR_END, 671 }; 672 673 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 682 ARM64_FTR_END, 683 }; 684 685 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 686 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 688 ARM64_FTR_END, 689 }; 690 691 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 692 /* [31:28] TraceFilt */ 693 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 700 ARM64_FTR_END, 701 }; 702 703 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 704 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 705 ARM64_FTR_END, 706 }; 707 708 static const struct arm64_ftr_bits ftr_mpamidr[] = { 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 713 ARM64_FTR_END, 714 }; 715 716 /* 717 * Common ftr bits for a 32bit register with all hidden, strict 718 * attributes, with 4bit feature fields and a default safe value of 719 * 0. Covers the following 32bit registers: 720 * id_isar[1-3], id_mmfr[1-3] 721 */ 722 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 727 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 728 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 729 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 730 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 731 ARM64_FTR_END, 732 }; 733 734 /* Table for a single 32bit feature value */ 735 static const struct arm64_ftr_bits ftr_single32[] = { 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 737 ARM64_FTR_END, 738 }; 739 740 static const struct arm64_ftr_bits ftr_raz[] = { 741 ARM64_FTR_END, 742 }; 743 744 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 745 .sys_id = id, \ 746 .reg = &(struct arm64_ftr_reg){ \ 747 .name = id_str, \ 748 .override = (ovr), \ 749 .ftr_bits = &((table)[0]), \ 750 }} 751 752 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 753 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 754 755 #define ARM64_FTR_REG(id, table) \ 756 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 757 758 struct arm64_ftr_override id_aa64mmfr0_override; 759 struct arm64_ftr_override id_aa64mmfr1_override; 760 struct arm64_ftr_override id_aa64mmfr2_override; 761 struct arm64_ftr_override id_aa64pfr0_override; 762 struct arm64_ftr_override id_aa64pfr1_override; 763 struct arm64_ftr_override id_aa64zfr0_override; 764 struct arm64_ftr_override id_aa64smfr0_override; 765 struct arm64_ftr_override id_aa64isar1_override; 766 struct arm64_ftr_override id_aa64isar2_override; 767 768 struct arm64_ftr_override arm64_sw_feature_override; 769 770 static const struct __ftr_reg_entry { 771 u32 sys_id; 772 struct arm64_ftr_reg *reg; 773 } arm64_ftr_regs[] = { 774 775 /* Op1 = 0, CRn = 0, CRm = 1 */ 776 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 777 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 778 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 779 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 780 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 781 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 782 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 783 784 /* Op1 = 0, CRn = 0, CRm = 2 */ 785 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 786 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 787 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 788 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 789 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 790 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 791 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 792 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 793 794 /* Op1 = 0, CRn = 0, CRm = 3 */ 795 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 796 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 797 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 798 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 799 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 800 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 801 802 /* Op1 = 0, CRn = 0, CRm = 4 */ 803 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 804 &id_aa64pfr0_override), 805 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 806 &id_aa64pfr1_override), 807 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 808 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 809 &id_aa64zfr0_override), 810 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 811 &id_aa64smfr0_override), 812 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 813 814 /* Op1 = 0, CRn = 0, CRm = 5 */ 815 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 816 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 817 818 /* Op1 = 0, CRn = 0, CRm = 6 */ 819 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 820 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 821 &id_aa64isar1_override), 822 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 823 &id_aa64isar2_override), 824 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 825 826 /* Op1 = 0, CRn = 0, CRm = 7 */ 827 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 828 &id_aa64mmfr0_override), 829 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 830 &id_aa64mmfr1_override), 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 832 &id_aa64mmfr2_override), 833 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 834 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 835 836 /* Op1 = 0, CRn = 10, CRm = 4 */ 837 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 838 839 /* Op1 = 1, CRn = 0, CRm = 0 */ 840 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 841 842 /* Op1 = 3, CRn = 0, CRm = 0 */ 843 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 844 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 845 846 /* Op1 = 3, CRn = 14, CRm = 0 */ 847 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 848 }; 849 850 static int search_cmp_ftr_reg(const void *id, const void *regp) 851 { 852 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 853 } 854 855 /* 856 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 857 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 858 * ascending order of sys_id, we use binary search to find a matching 859 * entry. 860 * 861 * returns - Upon success, matching ftr_reg entry for id. 862 * - NULL on failure. It is upto the caller to decide 863 * the impact of a failure. 864 */ 865 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 866 { 867 const struct __ftr_reg_entry *ret; 868 869 ret = bsearch((const void *)(unsigned long)sys_id, 870 arm64_ftr_regs, 871 ARRAY_SIZE(arm64_ftr_regs), 872 sizeof(arm64_ftr_regs[0]), 873 search_cmp_ftr_reg); 874 if (ret) 875 return ret->reg; 876 return NULL; 877 } 878 879 /* 880 * get_arm64_ftr_reg - Looks up a feature register entry using 881 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 882 * 883 * returns - Upon success, matching ftr_reg entry for id. 884 * - NULL on failure but with an WARN_ON(). 885 */ 886 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 887 { 888 struct arm64_ftr_reg *reg; 889 890 reg = get_arm64_ftr_reg_nowarn(sys_id); 891 892 /* 893 * Requesting a non-existent register search is an error. Warn 894 * and let the caller handle it. 895 */ 896 WARN_ON(!reg); 897 return reg; 898 } 899 900 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 901 s64 ftr_val) 902 { 903 u64 mask = arm64_ftr_mask(ftrp); 904 905 reg &= ~mask; 906 reg |= (ftr_val << ftrp->shift) & mask; 907 return reg; 908 } 909 910 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 911 s64 cur) 912 { 913 s64 ret = 0; 914 915 switch (ftrp->type) { 916 case FTR_EXACT: 917 ret = ftrp->safe_val; 918 break; 919 case FTR_LOWER_SAFE: 920 ret = min(new, cur); 921 break; 922 case FTR_HIGHER_OR_ZERO_SAFE: 923 if (!cur || !new) 924 break; 925 fallthrough; 926 case FTR_HIGHER_SAFE: 927 ret = max(new, cur); 928 break; 929 default: 930 BUG(); 931 } 932 933 return ret; 934 } 935 936 static void __init sort_ftr_regs(void) 937 { 938 unsigned int i; 939 940 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 941 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 942 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 943 unsigned int j = 0; 944 945 /* 946 * Features here must be sorted in descending order with respect 947 * to their shift values and should not overlap with each other. 948 */ 949 for (; ftr_bits->width != 0; ftr_bits++, j++) { 950 unsigned int width = ftr_reg->ftr_bits[j].width; 951 unsigned int shift = ftr_reg->ftr_bits[j].shift; 952 unsigned int prev_shift; 953 954 WARN((shift + width) > 64, 955 "%s has invalid feature at shift %d\n", 956 ftr_reg->name, shift); 957 958 /* 959 * Skip the first feature. There is nothing to 960 * compare against for now. 961 */ 962 if (j == 0) 963 continue; 964 965 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 966 WARN((shift + width) > prev_shift, 967 "%s has feature overlap at shift %d\n", 968 ftr_reg->name, shift); 969 } 970 971 /* 972 * Skip the first register. There is nothing to 973 * compare against for now. 974 */ 975 if (i == 0) 976 continue; 977 /* 978 * Registers here must be sorted in ascending order with respect 979 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 980 * to work correctly. 981 */ 982 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 983 } 984 } 985 986 /* 987 * Initialise the CPU feature register from Boot CPU values. 988 * Also initiliases the strict_mask for the register. 989 * Any bits that are not covered by an arm64_ftr_bits entry are considered 990 * RES0 for the system-wide value, and must strictly match. 991 */ 992 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 993 { 994 u64 val = 0; 995 u64 strict_mask = ~0x0ULL; 996 u64 user_mask = 0; 997 u64 valid_mask = 0; 998 999 const struct arm64_ftr_bits *ftrp; 1000 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1001 1002 if (!reg) 1003 return; 1004 1005 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1006 u64 ftr_mask = arm64_ftr_mask(ftrp); 1007 s64 ftr_new = arm64_ftr_value(ftrp, new); 1008 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1009 1010 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1011 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1012 char *str = NULL; 1013 1014 if (ftr_ovr != tmp) { 1015 /* Unsafe, remove the override */ 1016 reg->override->mask &= ~ftr_mask; 1017 reg->override->val &= ~ftr_mask; 1018 tmp = ftr_ovr; 1019 str = "ignoring override"; 1020 } else if (ftr_new != tmp) { 1021 /* Override was valid */ 1022 ftr_new = tmp; 1023 str = "forced"; 1024 } else { 1025 /* Override was the safe value */ 1026 str = "already set"; 1027 } 1028 1029 pr_warn("%s[%d:%d]: %s to %llx\n", 1030 reg->name, 1031 ftrp->shift + ftrp->width - 1, 1032 ftrp->shift, str, 1033 tmp & (BIT(ftrp->width) - 1)); 1034 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1035 reg->override->val &= ~ftr_mask; 1036 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1037 reg->name, 1038 ftrp->shift + ftrp->width - 1, 1039 ftrp->shift); 1040 } 1041 1042 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1043 1044 valid_mask |= ftr_mask; 1045 if (!ftrp->strict) 1046 strict_mask &= ~ftr_mask; 1047 if (ftrp->visible) 1048 user_mask |= ftr_mask; 1049 else 1050 reg->user_val = arm64_ftr_set_value(ftrp, 1051 reg->user_val, 1052 ftrp->safe_val); 1053 } 1054 1055 val &= valid_mask; 1056 1057 reg->sys_val = val; 1058 reg->strict_mask = strict_mask; 1059 reg->user_mask = user_mask; 1060 } 1061 1062 extern const struct arm64_cpu_capabilities arm64_errata[]; 1063 static const struct arm64_cpu_capabilities arm64_features[]; 1064 1065 static void __init 1066 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1067 { 1068 for (; caps->matches; caps++) { 1069 if (WARN(caps->capability >= ARM64_NCAPS, 1070 "Invalid capability %d\n", caps->capability)) 1071 continue; 1072 if (WARN(cpucap_ptrs[caps->capability], 1073 "Duplicate entry for capability %d\n", 1074 caps->capability)) 1075 continue; 1076 cpucap_ptrs[caps->capability] = caps; 1077 } 1078 } 1079 1080 static void __init init_cpucap_indirect_list(void) 1081 { 1082 init_cpucap_indirect_list_from_array(arm64_features); 1083 init_cpucap_indirect_list_from_array(arm64_errata); 1084 } 1085 1086 static void __init setup_boot_cpu_capabilities(void); 1087 1088 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1089 { 1090 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1091 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1092 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1093 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1094 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1095 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1096 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1097 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1098 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1099 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1100 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1101 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1102 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1103 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1104 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1105 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1106 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1107 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1108 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1109 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1110 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1111 } 1112 1113 #ifdef CONFIG_ARM64_PSEUDO_NMI 1114 static bool enable_pseudo_nmi; 1115 1116 static int __init early_enable_pseudo_nmi(char *p) 1117 { 1118 return kstrtobool(p, &enable_pseudo_nmi); 1119 } 1120 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1121 1122 static __init void detect_system_supports_pseudo_nmi(void) 1123 { 1124 struct device_node *np; 1125 1126 if (!enable_pseudo_nmi) 1127 return; 1128 1129 /* 1130 * Detect broken MediaTek firmware that doesn't properly save and 1131 * restore GIC priorities. 1132 */ 1133 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1134 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1135 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1136 enable_pseudo_nmi = false; 1137 } 1138 of_node_put(np); 1139 } 1140 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1141 static inline void detect_system_supports_pseudo_nmi(void) { } 1142 #endif 1143 1144 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1145 { 1146 /* Before we start using the tables, make sure it is sorted */ 1147 sort_ftr_regs(); 1148 1149 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1150 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1151 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1152 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1153 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1154 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1155 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1156 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1157 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1158 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1159 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1160 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1161 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1162 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1163 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1164 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1165 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1166 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1167 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1168 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1169 1170 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1171 init_32bit_cpu_features(&info->aarch32); 1172 1173 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1174 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1175 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1176 1177 vec_init_vq_map(ARM64_VEC_SVE); 1178 1179 cpacr_restore(cpacr); 1180 } 1181 1182 if (IS_ENABLED(CONFIG_ARM64_SME) && 1183 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1184 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1185 1186 vec_init_vq_map(ARM64_VEC_SME); 1187 1188 cpacr_restore(cpacr); 1189 } 1190 1191 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1192 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1193 1194 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1195 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1196 } 1197 1198 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1199 { 1200 const struct arm64_ftr_bits *ftrp; 1201 1202 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1203 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1204 s64 ftr_new = arm64_ftr_value(ftrp, new); 1205 1206 if (ftr_cur == ftr_new) 1207 continue; 1208 /* Find a safe value */ 1209 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1210 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1211 } 1212 1213 } 1214 1215 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1216 { 1217 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1218 1219 if (!regp) 1220 return 0; 1221 1222 update_cpu_ftr_reg(regp, val); 1223 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1224 return 0; 1225 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1226 regp->name, boot, cpu, val); 1227 return 1; 1228 } 1229 1230 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1231 { 1232 const struct arm64_ftr_bits *ftrp; 1233 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1234 1235 if (!regp) 1236 return; 1237 1238 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1239 if (ftrp->shift == field) { 1240 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1241 break; 1242 } 1243 } 1244 1245 /* Bogus field? */ 1246 WARN_ON(!ftrp->width); 1247 } 1248 1249 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1250 struct cpuinfo_arm64 *boot) 1251 { 1252 static bool boot_cpu_32bit_regs_overridden = false; 1253 1254 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1255 return; 1256 1257 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1258 return; 1259 1260 boot->aarch32 = info->aarch32; 1261 init_32bit_cpu_features(&boot->aarch32); 1262 boot_cpu_32bit_regs_overridden = true; 1263 } 1264 1265 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1266 struct cpuinfo_32bit *boot) 1267 { 1268 int taint = 0; 1269 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1270 1271 /* 1272 * If we don't have AArch32 at EL1, then relax the strictness of 1273 * EL1-dependent register fields to avoid spurious sanity check fails. 1274 */ 1275 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1276 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1277 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1278 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1279 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1280 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1281 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1282 } 1283 1284 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1285 info->reg_id_dfr0, boot->reg_id_dfr0); 1286 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1287 info->reg_id_dfr1, boot->reg_id_dfr1); 1288 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1289 info->reg_id_isar0, boot->reg_id_isar0); 1290 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1291 info->reg_id_isar1, boot->reg_id_isar1); 1292 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1293 info->reg_id_isar2, boot->reg_id_isar2); 1294 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1295 info->reg_id_isar3, boot->reg_id_isar3); 1296 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1297 info->reg_id_isar4, boot->reg_id_isar4); 1298 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1299 info->reg_id_isar5, boot->reg_id_isar5); 1300 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1301 info->reg_id_isar6, boot->reg_id_isar6); 1302 1303 /* 1304 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1305 * ACTLR formats could differ across CPUs and therefore would have to 1306 * be trapped for virtualization anyway. 1307 */ 1308 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1309 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1310 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1311 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1312 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1313 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1314 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1315 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1316 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1317 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1318 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1319 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1320 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1321 info->reg_id_pfr0, boot->reg_id_pfr0); 1322 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1323 info->reg_id_pfr1, boot->reg_id_pfr1); 1324 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1325 info->reg_id_pfr2, boot->reg_id_pfr2); 1326 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1327 info->reg_mvfr0, boot->reg_mvfr0); 1328 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1329 info->reg_mvfr1, boot->reg_mvfr1); 1330 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1331 info->reg_mvfr2, boot->reg_mvfr2); 1332 1333 return taint; 1334 } 1335 1336 /* 1337 * Update system wide CPU feature registers with the values from a 1338 * non-boot CPU. Also performs SANITY checks to make sure that there 1339 * aren't any insane variations from that of the boot CPU. 1340 */ 1341 void update_cpu_features(int cpu, 1342 struct cpuinfo_arm64 *info, 1343 struct cpuinfo_arm64 *boot) 1344 { 1345 int taint = 0; 1346 1347 /* 1348 * The kernel can handle differing I-cache policies, but otherwise 1349 * caches should look identical. Userspace JITs will make use of 1350 * *minLine. 1351 */ 1352 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1353 info->reg_ctr, boot->reg_ctr); 1354 1355 /* 1356 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1357 * could result in too much or too little memory being zeroed if a 1358 * process is preempted and migrated between CPUs. 1359 */ 1360 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1361 info->reg_dczid, boot->reg_dczid); 1362 1363 /* If different, timekeeping will be broken (especially with KVM) */ 1364 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1365 info->reg_cntfrq, boot->reg_cntfrq); 1366 1367 /* 1368 * The kernel uses self-hosted debug features and expects CPUs to 1369 * support identical debug features. We presently need CTX_CMPs, WRPs, 1370 * and BRPs to be identical. 1371 * ID_AA64DFR1 is currently RES0. 1372 */ 1373 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1374 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1375 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1376 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1377 /* 1378 * Even in big.LITTLE, processors should be identical instruction-set 1379 * wise. 1380 */ 1381 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1382 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1383 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1384 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1385 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1386 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1387 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1388 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1389 1390 /* 1391 * Differing PARange support is fine as long as all peripherals and 1392 * memory are mapped within the minimum PARange of all CPUs. 1393 * Linux should not care about secure memory. 1394 */ 1395 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1396 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1397 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1398 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1399 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1400 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1401 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1402 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1403 1404 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1405 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1406 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1407 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1408 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1409 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1410 1411 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1412 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1413 1414 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1415 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1416 1417 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1418 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1419 1420 /* Probe vector lengths */ 1421 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1422 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1423 if (!system_capabilities_finalized()) { 1424 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1425 1426 vec_update_vq_map(ARM64_VEC_SVE); 1427 1428 cpacr_restore(cpacr); 1429 } 1430 } 1431 1432 if (IS_ENABLED(CONFIG_ARM64_SME) && 1433 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1434 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1435 1436 /* Probe vector lengths */ 1437 if (!system_capabilities_finalized()) 1438 vec_update_vq_map(ARM64_VEC_SME); 1439 1440 cpacr_restore(cpacr); 1441 } 1442 1443 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1444 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1445 info->reg_mpamidr, boot->reg_mpamidr); 1446 } 1447 1448 /* 1449 * The kernel uses the LDGM/STGM instructions and the number of tags 1450 * they read/write depends on the GMID_EL1.BS field. Check that the 1451 * value is the same on all CPUs. 1452 */ 1453 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1454 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1455 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1456 info->reg_gmid, boot->reg_gmid); 1457 } 1458 1459 /* 1460 * If we don't have AArch32 at all then skip the checks entirely 1461 * as the register values may be UNKNOWN and we're not going to be 1462 * using them for anything. 1463 * 1464 * This relies on a sanitised view of the AArch64 ID registers 1465 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1466 */ 1467 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1468 lazy_init_32bit_cpu_features(info, boot); 1469 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1470 &boot->aarch32); 1471 } 1472 1473 /* 1474 * Mismatched CPU features are a recipe for disaster. Don't even 1475 * pretend to support them. 1476 */ 1477 if (taint) { 1478 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1479 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1480 } 1481 } 1482 1483 u64 read_sanitised_ftr_reg(u32 id) 1484 { 1485 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1486 1487 if (!regp) 1488 return 0; 1489 return regp->sys_val; 1490 } 1491 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1492 1493 #define read_sysreg_case(r) \ 1494 case r: val = read_sysreg_s(r); break; 1495 1496 /* 1497 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1498 * Read the system register on the current CPU 1499 */ 1500 u64 __read_sysreg_by_encoding(u32 sys_id) 1501 { 1502 struct arm64_ftr_reg *regp; 1503 u64 val; 1504 1505 switch (sys_id) { 1506 read_sysreg_case(SYS_ID_PFR0_EL1); 1507 read_sysreg_case(SYS_ID_PFR1_EL1); 1508 read_sysreg_case(SYS_ID_PFR2_EL1); 1509 read_sysreg_case(SYS_ID_DFR0_EL1); 1510 read_sysreg_case(SYS_ID_DFR1_EL1); 1511 read_sysreg_case(SYS_ID_MMFR0_EL1); 1512 read_sysreg_case(SYS_ID_MMFR1_EL1); 1513 read_sysreg_case(SYS_ID_MMFR2_EL1); 1514 read_sysreg_case(SYS_ID_MMFR3_EL1); 1515 read_sysreg_case(SYS_ID_MMFR4_EL1); 1516 read_sysreg_case(SYS_ID_MMFR5_EL1); 1517 read_sysreg_case(SYS_ID_ISAR0_EL1); 1518 read_sysreg_case(SYS_ID_ISAR1_EL1); 1519 read_sysreg_case(SYS_ID_ISAR2_EL1); 1520 read_sysreg_case(SYS_ID_ISAR3_EL1); 1521 read_sysreg_case(SYS_ID_ISAR4_EL1); 1522 read_sysreg_case(SYS_ID_ISAR5_EL1); 1523 read_sysreg_case(SYS_ID_ISAR6_EL1); 1524 read_sysreg_case(SYS_MVFR0_EL1); 1525 read_sysreg_case(SYS_MVFR1_EL1); 1526 read_sysreg_case(SYS_MVFR2_EL1); 1527 1528 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1529 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1530 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1531 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1532 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1533 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1534 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1535 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1536 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1537 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1538 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1539 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1540 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1541 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1542 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1543 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1544 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1545 1546 read_sysreg_case(SYS_CNTFRQ_EL0); 1547 read_sysreg_case(SYS_CTR_EL0); 1548 read_sysreg_case(SYS_DCZID_EL0); 1549 1550 default: 1551 BUG(); 1552 return 0; 1553 } 1554 1555 regp = get_arm64_ftr_reg(sys_id); 1556 if (regp) { 1557 val &= ~regp->override->mask; 1558 val |= (regp->override->val & regp->override->mask); 1559 } 1560 1561 return val; 1562 } 1563 1564 #include <linux/irqchip/arm-gic-v3.h> 1565 1566 static bool 1567 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1568 { 1569 return true; 1570 } 1571 1572 static bool 1573 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1574 { 1575 int val, min, max; 1576 u64 tmp; 1577 1578 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1579 entry->field_width, 1580 entry->sign); 1581 1582 tmp = entry->min_field_value; 1583 tmp <<= entry->field_pos; 1584 1585 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1586 entry->field_width, 1587 entry->sign); 1588 1589 tmp = entry->max_field_value; 1590 tmp <<= entry->field_pos; 1591 1592 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1593 entry->field_width, 1594 entry->sign); 1595 1596 return val >= min && val <= max; 1597 } 1598 1599 static u64 1600 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1601 { 1602 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1603 if (scope == SCOPE_SYSTEM) 1604 return read_sanitised_ftr_reg(entry->sys_reg); 1605 else 1606 return __read_sysreg_by_encoding(entry->sys_reg); 1607 } 1608 1609 static bool 1610 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1611 { 1612 int mask; 1613 struct arm64_ftr_reg *regp; 1614 u64 val = read_scoped_sysreg(entry, scope); 1615 1616 regp = get_arm64_ftr_reg(entry->sys_reg); 1617 if (!regp) 1618 return false; 1619 1620 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1621 entry->field_pos, 1622 entry->field_width); 1623 if (!mask) 1624 return false; 1625 1626 return feature_matches(val, entry); 1627 } 1628 1629 static bool 1630 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1631 { 1632 u64 val = read_scoped_sysreg(entry, scope); 1633 return feature_matches(val, entry); 1634 } 1635 1636 const struct cpumask *system_32bit_el0_cpumask(void) 1637 { 1638 if (!system_supports_32bit_el0()) 1639 return cpu_none_mask; 1640 1641 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1642 return cpu_32bit_el0_mask; 1643 1644 return cpu_possible_mask; 1645 } 1646 1647 static int __init parse_32bit_el0_param(char *str) 1648 { 1649 allow_mismatched_32bit_el0 = true; 1650 return 0; 1651 } 1652 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1653 1654 static ssize_t aarch32_el0_show(struct device *dev, 1655 struct device_attribute *attr, char *buf) 1656 { 1657 const struct cpumask *mask = system_32bit_el0_cpumask(); 1658 1659 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1660 } 1661 static const DEVICE_ATTR_RO(aarch32_el0); 1662 1663 static int __init aarch32_el0_sysfs_init(void) 1664 { 1665 struct device *dev_root; 1666 int ret = 0; 1667 1668 if (!allow_mismatched_32bit_el0) 1669 return 0; 1670 1671 dev_root = bus_get_dev_root(&cpu_subsys); 1672 if (dev_root) { 1673 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1674 put_device(dev_root); 1675 } 1676 return ret; 1677 } 1678 device_initcall(aarch32_el0_sysfs_init); 1679 1680 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1681 { 1682 if (!has_cpuid_feature(entry, scope)) 1683 return allow_mismatched_32bit_el0; 1684 1685 if (scope == SCOPE_SYSTEM) 1686 pr_info("detected: 32-bit EL0 Support\n"); 1687 1688 return true; 1689 } 1690 1691 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1692 { 1693 bool has_sre; 1694 1695 if (!has_cpuid_feature(entry, scope)) 1696 return false; 1697 1698 has_sre = gic_enable_sre(); 1699 if (!has_sre) 1700 pr_warn_once("%s present but disabled by higher exception level\n", 1701 entry->desc); 1702 1703 return has_sre; 1704 } 1705 1706 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1707 int scope) 1708 { 1709 u64 ctr; 1710 1711 if (scope == SCOPE_SYSTEM) 1712 ctr = arm64_ftr_reg_ctrel0.sys_val; 1713 else 1714 ctr = read_cpuid_effective_cachetype(); 1715 1716 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1717 } 1718 1719 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1720 { 1721 /* 1722 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1723 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1724 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1725 * value. 1726 */ 1727 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1728 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1729 } 1730 1731 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1732 int scope) 1733 { 1734 u64 ctr; 1735 1736 if (scope == SCOPE_SYSTEM) 1737 ctr = arm64_ftr_reg_ctrel0.sys_val; 1738 else 1739 ctr = read_cpuid_cachetype(); 1740 1741 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1742 } 1743 1744 static bool __maybe_unused 1745 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1746 { 1747 /* 1748 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1749 * may share TLB entries with a CPU stuck in the crashed 1750 * kernel. 1751 */ 1752 if (is_kdump_kernel()) 1753 return false; 1754 1755 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1756 return false; 1757 1758 return has_cpuid_feature(entry, scope); 1759 } 1760 1761 static bool __meltdown_safe = true; 1762 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1763 1764 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1765 int scope) 1766 { 1767 /* List of CPUs that are not vulnerable and don't need KPTI */ 1768 static const struct midr_range kpti_safe_list[] = { 1769 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1770 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1771 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1772 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1773 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1774 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1775 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1776 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1777 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1778 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1779 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1780 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1781 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1782 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1783 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1784 { /* sentinel */ } 1785 }; 1786 char const *str = "kpti command line option"; 1787 bool meltdown_safe; 1788 1789 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1790 1791 /* Defer to CPU feature registers */ 1792 if (has_cpuid_feature(entry, scope)) 1793 meltdown_safe = true; 1794 1795 if (!meltdown_safe) 1796 __meltdown_safe = false; 1797 1798 /* 1799 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1800 * ThunderX leads to apparent I-cache corruption of kernel text, which 1801 * ends as well as you might imagine. Don't even try. We cannot rely 1802 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1803 * because cpucap detection order may change. However, since we know 1804 * affected CPUs are always in a homogeneous configuration, it is 1805 * safe to rely on this_cpu_has_cap() here. 1806 */ 1807 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1808 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1809 __kpti_forced = -1; 1810 } 1811 1812 /* Useful for KASLR robustness */ 1813 if (kaslr_enabled() && kaslr_requires_kpti()) { 1814 if (!__kpti_forced) { 1815 str = "KASLR"; 1816 __kpti_forced = 1; 1817 } 1818 } 1819 1820 if (cpu_mitigations_off() && !__kpti_forced) { 1821 str = "mitigations=off"; 1822 __kpti_forced = -1; 1823 } 1824 1825 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1826 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1827 return false; 1828 } 1829 1830 /* Forced? */ 1831 if (__kpti_forced) { 1832 pr_info_once("kernel page table isolation forced %s by %s\n", 1833 __kpti_forced > 0 ? "ON" : "OFF", str); 1834 return __kpti_forced > 0; 1835 } 1836 1837 return !meltdown_safe; 1838 } 1839 1840 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1841 { 1842 /* 1843 * Although the Apple M2 family appears to support NV1, the 1844 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1845 * that it doesn't support NV1 at all. 1846 */ 1847 static const struct midr_range nv1_ni_list[] = { 1848 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1849 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1850 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1851 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1852 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1853 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1854 {} 1855 }; 1856 1857 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1858 !(has_cpuid_feature(entry, scope) || 1859 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1860 } 1861 1862 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1863 static bool has_lpa2_at_stage1(u64 mmfr0) 1864 { 1865 unsigned int tgran; 1866 1867 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1868 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1869 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1870 } 1871 1872 static bool has_lpa2_at_stage2(u64 mmfr0) 1873 { 1874 unsigned int tgran; 1875 1876 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1877 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1878 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1879 } 1880 1881 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1882 { 1883 u64 mmfr0; 1884 1885 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1886 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1887 } 1888 #else 1889 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1890 { 1891 return false; 1892 } 1893 #endif 1894 1895 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1896 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1897 1898 extern 1899 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1900 phys_addr_t size, pgprot_t prot, 1901 phys_addr_t (*pgtable_alloc)(int), int flags); 1902 1903 static phys_addr_t __initdata kpti_ng_temp_alloc; 1904 1905 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1906 { 1907 kpti_ng_temp_alloc -= PAGE_SIZE; 1908 return kpti_ng_temp_alloc; 1909 } 1910 1911 static int __init __kpti_install_ng_mappings(void *__unused) 1912 { 1913 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1914 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1915 kpti_remap_fn *remap_fn; 1916 1917 int cpu = smp_processor_id(); 1918 int levels = CONFIG_PGTABLE_LEVELS; 1919 int order = order_base_2(levels); 1920 u64 kpti_ng_temp_pgd_pa = 0; 1921 pgd_t *kpti_ng_temp_pgd; 1922 u64 alloc = 0; 1923 1924 if (levels == 5 && !pgtable_l5_enabled()) 1925 levels = 4; 1926 else if (levels == 4 && !pgtable_l4_enabled()) 1927 levels = 3; 1928 1929 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1930 1931 if (!cpu) { 1932 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1933 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1934 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1935 1936 // 1937 // Create a minimal page table hierarchy that permits us to map 1938 // the swapper page tables temporarily as we traverse them. 1939 // 1940 // The physical pages are laid out as follows: 1941 // 1942 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1943 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1944 // +--------+-\-------+-\------ +-\------ +-///--------+ 1945 // ^ 1946 // The first page is mapped into this hierarchy at a PMD_SHIFT 1947 // aligned virtual address, so that we can manipulate the PTE 1948 // level entries while the mapping is active. The first entry 1949 // covers the PTE[] page itself, the remaining entries are free 1950 // to be used as a ad-hoc fixmap. 1951 // 1952 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1953 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1954 kpti_ng_pgd_alloc, 0); 1955 } 1956 1957 cpu_install_idmap(); 1958 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1959 cpu_uninstall_idmap(); 1960 1961 if (!cpu) { 1962 free_pages(alloc, order); 1963 arm64_use_ng_mappings = true; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static void __init kpti_install_ng_mappings(void) 1970 { 1971 /* Check whether KPTI is going to be used */ 1972 if (!arm64_kernel_unmapped_at_el0()) 1973 return; 1974 1975 /* 1976 * We don't need to rewrite the page-tables if either we've done 1977 * it already or we have KASLR enabled and therefore have not 1978 * created any global mappings at all. 1979 */ 1980 if (arm64_use_ng_mappings) 1981 return; 1982 1983 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1984 } 1985 1986 #else 1987 static inline void kpti_install_ng_mappings(void) 1988 { 1989 } 1990 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1991 1992 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1993 { 1994 if (__this_cpu_read(this_cpu_vector) == vectors) { 1995 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1996 1997 __this_cpu_write(this_cpu_vector, v); 1998 } 1999 2000 } 2001 2002 static int __init parse_kpti(char *str) 2003 { 2004 bool enabled; 2005 int ret = kstrtobool(str, &enabled); 2006 2007 if (ret) 2008 return ret; 2009 2010 __kpti_forced = enabled ? 1 : -1; 2011 return 0; 2012 } 2013 early_param("kpti", parse_kpti); 2014 2015 #ifdef CONFIG_ARM64_HW_AFDBM 2016 static struct cpumask dbm_cpus __read_mostly; 2017 2018 static inline void __cpu_enable_hw_dbm(void) 2019 { 2020 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2021 2022 write_sysreg(tcr, tcr_el1); 2023 isb(); 2024 local_flush_tlb_all(); 2025 } 2026 2027 static bool cpu_has_broken_dbm(void) 2028 { 2029 /* List of CPUs which have broken DBM support. */ 2030 static const struct midr_range cpus[] = { 2031 #ifdef CONFIG_ARM64_ERRATUM_1024718 2032 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2033 /* Kryo4xx Silver (rdpe => r1p0) */ 2034 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2035 #endif 2036 #ifdef CONFIG_ARM64_ERRATUM_2051678 2037 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2038 #endif 2039 {}, 2040 }; 2041 2042 return is_midr_in_range_list(read_cpuid_id(), cpus); 2043 } 2044 2045 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2046 { 2047 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2048 !cpu_has_broken_dbm(); 2049 } 2050 2051 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2052 { 2053 if (cpu_can_use_dbm(cap)) { 2054 __cpu_enable_hw_dbm(); 2055 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2056 } 2057 } 2058 2059 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2060 int __unused) 2061 { 2062 /* 2063 * DBM is a non-conflicting feature. i.e, the kernel can safely 2064 * run a mix of CPUs with and without the feature. So, we 2065 * unconditionally enable the capability to allow any late CPU 2066 * to use the feature. We only enable the control bits on the 2067 * CPU, if it is supported. 2068 */ 2069 2070 return true; 2071 } 2072 2073 #endif 2074 2075 #ifdef CONFIG_ARM64_AMU_EXTN 2076 2077 /* 2078 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2079 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2080 * information regarding all the events that it supports. When a CPU bit is 2081 * set in the cpumask, the user of this feature can only rely on the presence 2082 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2083 * counters are enabled or access to these counters is enabled by code 2084 * executed at higher exception levels (firmware). 2085 */ 2086 static struct cpumask amu_cpus __read_mostly; 2087 2088 bool cpu_has_amu_feat(int cpu) 2089 { 2090 return cpumask_test_cpu(cpu, &amu_cpus); 2091 } 2092 2093 int get_cpu_with_amu_feat(void) 2094 { 2095 return cpumask_any(&amu_cpus); 2096 } 2097 2098 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2099 { 2100 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2101 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2102 2103 /* 0 reference values signal broken/disabled counters */ 2104 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2105 update_freq_counters_refs(); 2106 } 2107 } 2108 2109 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2110 int __unused) 2111 { 2112 /* 2113 * The AMU extension is a non-conflicting feature: the kernel can 2114 * safely run a mix of CPUs with and without support for the 2115 * activity monitors extension. Therefore, unconditionally enable 2116 * the capability to allow any late CPU to use the feature. 2117 * 2118 * With this feature unconditionally enabled, the cpu_enable 2119 * function will be called for all CPUs that match the criteria, 2120 * including secondary and hotplugged, marking this feature as 2121 * present on that respective CPU. The enable function will also 2122 * print a detection message. 2123 */ 2124 2125 return true; 2126 } 2127 #else 2128 int get_cpu_with_amu_feat(void) 2129 { 2130 return nr_cpu_ids; 2131 } 2132 #endif 2133 2134 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2135 { 2136 return is_kernel_in_hyp_mode(); 2137 } 2138 2139 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2140 { 2141 /* 2142 * Copy register values that aren't redirected by hardware. 2143 * 2144 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2145 * this value to tpidr_el2 before we patch the code. Once we've done 2146 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2147 * do anything here. 2148 */ 2149 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2150 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2151 } 2152 2153 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2154 int scope) 2155 { 2156 if (kvm_get_mode() != KVM_MODE_NV) 2157 return false; 2158 2159 if (!has_cpuid_feature(cap, scope)) { 2160 pr_warn("unavailable: %s\n", cap->desc); 2161 return false; 2162 } 2163 2164 return true; 2165 } 2166 2167 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2168 int __unused) 2169 { 2170 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2171 } 2172 2173 #ifdef CONFIG_ARM64_PAN 2174 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2175 { 2176 /* 2177 * We modify PSTATE. This won't work from irq context as the PSTATE 2178 * is discarded once we return from the exception. 2179 */ 2180 WARN_ON_ONCE(in_interrupt()); 2181 2182 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2183 set_pstate_pan(1); 2184 } 2185 #endif /* CONFIG_ARM64_PAN */ 2186 2187 #ifdef CONFIG_ARM64_RAS_EXTN 2188 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2189 { 2190 /* Firmware may have left a deferred SError in this register. */ 2191 write_sysreg_s(0, SYS_DISR_EL1); 2192 } 2193 #endif /* CONFIG_ARM64_RAS_EXTN */ 2194 2195 #ifdef CONFIG_ARM64_PTR_AUTH 2196 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2197 { 2198 int boot_val, sec_val; 2199 2200 /* We don't expect to be called with SCOPE_SYSTEM */ 2201 WARN_ON(scope == SCOPE_SYSTEM); 2202 /* 2203 * The ptr-auth feature levels are not intercompatible with lower 2204 * levels. Hence we must match ptr-auth feature level of the secondary 2205 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2206 * from the sanitised register whereas direct register read is done for 2207 * the secondary CPUs. 2208 * The sanitised feature state is guaranteed to match that of the 2209 * boot CPU as a mismatched secondary CPU is parked before it gets 2210 * a chance to update the state, with the capability. 2211 */ 2212 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2213 entry->field_pos, entry->sign); 2214 if (scope & SCOPE_BOOT_CPU) 2215 return boot_val >= entry->min_field_value; 2216 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2217 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2218 entry->field_pos, entry->sign); 2219 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2220 } 2221 2222 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2223 int scope) 2224 { 2225 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2226 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2227 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2228 2229 return apa || apa3 || api; 2230 } 2231 2232 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2233 int __unused) 2234 { 2235 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2236 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2237 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2238 2239 return gpa || gpa3 || gpi; 2240 } 2241 #endif /* CONFIG_ARM64_PTR_AUTH */ 2242 2243 #ifdef CONFIG_ARM64_E0PD 2244 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2245 { 2246 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2247 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2248 } 2249 #endif /* CONFIG_ARM64_E0PD */ 2250 2251 #ifdef CONFIG_ARM64_PSEUDO_NMI 2252 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2253 int scope) 2254 { 2255 /* 2256 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2257 * feature, so will be detected earlier. 2258 */ 2259 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2260 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2261 return false; 2262 2263 return enable_pseudo_nmi; 2264 } 2265 2266 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2267 int scope) 2268 { 2269 /* 2270 * If we're not using priority masking then we won't be poking PMR_EL1, 2271 * and there's no need to relax synchronization of writes to it, and 2272 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2273 * that. 2274 * 2275 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2276 * feature, so will be detected earlier. 2277 */ 2278 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2279 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2280 return false; 2281 2282 /* 2283 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2284 * hint for interrupt distribution, a DSB is not necessary when 2285 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2286 * 2287 * Linux itself doesn't use 1:N distribution, so has no need to 2288 * set PMHE. The only reason to have it set is if EL3 requires it 2289 * (and we can't change it). 2290 */ 2291 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2292 } 2293 #endif 2294 2295 #ifdef CONFIG_ARM64_BTI 2296 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2297 { 2298 /* 2299 * Use of X16/X17 for tail-calls and trampolines that jump to 2300 * function entry points using BR is a requirement for 2301 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2302 * So, be strict and forbid other BRs using other registers to 2303 * jump onto a PACIxSP instruction: 2304 */ 2305 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2306 isb(); 2307 } 2308 #endif /* CONFIG_ARM64_BTI */ 2309 2310 #ifdef CONFIG_ARM64_MTE 2311 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2312 { 2313 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2314 2315 mte_cpu_setup(); 2316 2317 /* 2318 * Clear the tags in the zero page. This needs to be done via the 2319 * linear map which has the Tagged attribute. 2320 */ 2321 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2322 mte_clear_page_tags(lm_alias(empty_zero_page)); 2323 set_page_mte_tagged(ZERO_PAGE(0)); 2324 } 2325 2326 kasan_init_hw_tags_cpu(); 2327 } 2328 #endif /* CONFIG_ARM64_MTE */ 2329 2330 static void user_feature_fixup(void) 2331 { 2332 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2333 struct arm64_ftr_reg *regp; 2334 2335 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2336 if (regp) 2337 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2338 } 2339 2340 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2341 struct arm64_ftr_reg *regp; 2342 2343 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2344 if (regp) 2345 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2346 } 2347 } 2348 2349 static void elf_hwcap_fixup(void) 2350 { 2351 #ifdef CONFIG_COMPAT 2352 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2353 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2354 #endif /* CONFIG_COMPAT */ 2355 } 2356 2357 #ifdef CONFIG_KVM 2358 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2359 { 2360 return kvm_get_mode() == KVM_MODE_PROTECTED; 2361 } 2362 #endif /* CONFIG_KVM */ 2363 2364 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2365 { 2366 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2367 } 2368 2369 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2370 { 2371 set_pstate_dit(1); 2372 } 2373 2374 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2375 { 2376 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2377 } 2378 2379 #ifdef CONFIG_ARM64_POE 2380 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2381 { 2382 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2383 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2384 } 2385 #endif 2386 2387 #ifdef CONFIG_ARM64_GCS 2388 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2389 { 2390 /* GCSPR_EL0 is always readable */ 2391 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2392 } 2393 #endif 2394 2395 /* Internal helper functions to match cpu capability type */ 2396 static bool 2397 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2398 { 2399 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2400 } 2401 2402 static bool 2403 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2404 { 2405 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2406 } 2407 2408 static bool 2409 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2410 { 2411 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2412 } 2413 2414 static bool 2415 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2416 { 2417 if (!has_cpuid_feature(entry, scope)) 2418 return false; 2419 2420 /* Check firmware actually enabled MPAM on this cpu. */ 2421 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2422 } 2423 2424 static void 2425 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2426 { 2427 /* 2428 * Access by the kernel (at EL1) should use the reserved PARTID 2429 * which is configured unrestricted. This avoids priority-inversion 2430 * where latency sensitive tasks have to wait for a task that has 2431 * been throttled to release the lock. 2432 */ 2433 write_sysreg_s(0, SYS_MPAM1_EL1); 2434 } 2435 2436 static bool 2437 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2438 { 2439 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2440 2441 return idr & MPAMIDR_EL1_HAS_HCR; 2442 } 2443 2444 static const struct arm64_cpu_capabilities arm64_features[] = { 2445 { 2446 .capability = ARM64_ALWAYS_BOOT, 2447 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2448 .matches = has_always, 2449 }, 2450 { 2451 .capability = ARM64_ALWAYS_SYSTEM, 2452 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2453 .matches = has_always, 2454 }, 2455 { 2456 .desc = "GIC system register CPU interface", 2457 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2458 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2459 .matches = has_useable_gicv3_cpuif, 2460 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2461 }, 2462 { 2463 .desc = "Enhanced Counter Virtualization", 2464 .capability = ARM64_HAS_ECV, 2465 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2466 .matches = has_cpuid_feature, 2467 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2468 }, 2469 { 2470 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2471 .capability = ARM64_HAS_ECV_CNTPOFF, 2472 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2473 .matches = has_cpuid_feature, 2474 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2475 }, 2476 #ifdef CONFIG_ARM64_PAN 2477 { 2478 .desc = "Privileged Access Never", 2479 .capability = ARM64_HAS_PAN, 2480 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2481 .matches = has_cpuid_feature, 2482 .cpu_enable = cpu_enable_pan, 2483 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2484 }, 2485 #endif /* CONFIG_ARM64_PAN */ 2486 #ifdef CONFIG_ARM64_EPAN 2487 { 2488 .desc = "Enhanced Privileged Access Never", 2489 .capability = ARM64_HAS_EPAN, 2490 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2491 .matches = has_cpuid_feature, 2492 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2493 }, 2494 #endif /* CONFIG_ARM64_EPAN */ 2495 #ifdef CONFIG_ARM64_LSE_ATOMICS 2496 { 2497 .desc = "LSE atomic instructions", 2498 .capability = ARM64_HAS_LSE_ATOMICS, 2499 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2500 .matches = has_cpuid_feature, 2501 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2502 }, 2503 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2504 { 2505 .desc = "Virtualization Host Extensions", 2506 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2507 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2508 .matches = runs_at_el2, 2509 .cpu_enable = cpu_copy_el2regs, 2510 }, 2511 { 2512 .desc = "Nested Virtualization Support", 2513 .capability = ARM64_HAS_NESTED_VIRT, 2514 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2515 .matches = has_nested_virt_support, 2516 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2517 }, 2518 { 2519 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2520 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2521 .matches = has_32bit_el0, 2522 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2523 }, 2524 #ifdef CONFIG_KVM 2525 { 2526 .desc = "32-bit EL1 Support", 2527 .capability = ARM64_HAS_32BIT_EL1, 2528 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2529 .matches = has_cpuid_feature, 2530 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2531 }, 2532 { 2533 .desc = "Protected KVM", 2534 .capability = ARM64_KVM_PROTECTED_MODE, 2535 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2536 .matches = is_kvm_protected_mode, 2537 }, 2538 { 2539 .desc = "HCRX_EL2 register", 2540 .capability = ARM64_HAS_HCX, 2541 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2542 .matches = has_cpuid_feature, 2543 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2544 }, 2545 #endif 2546 { 2547 .desc = "Kernel page table isolation (KPTI)", 2548 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2549 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2550 .cpu_enable = cpu_enable_kpti, 2551 .matches = unmap_kernel_at_el0, 2552 /* 2553 * The ID feature fields below are used to indicate that 2554 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2555 * more details. 2556 */ 2557 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2558 }, 2559 { 2560 .capability = ARM64_HAS_FPSIMD, 2561 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2562 .matches = has_cpuid_feature, 2563 .cpu_enable = cpu_enable_fpsimd, 2564 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2565 }, 2566 #ifdef CONFIG_ARM64_PMEM 2567 { 2568 .desc = "Data cache clean to Point of Persistence", 2569 .capability = ARM64_HAS_DCPOP, 2570 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2571 .matches = has_cpuid_feature, 2572 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2573 }, 2574 { 2575 .desc = "Data cache clean to Point of Deep Persistence", 2576 .capability = ARM64_HAS_DCPODP, 2577 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2578 .matches = has_cpuid_feature, 2579 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2580 }, 2581 #endif 2582 #ifdef CONFIG_ARM64_SVE 2583 { 2584 .desc = "Scalable Vector Extension", 2585 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2586 .capability = ARM64_SVE, 2587 .cpu_enable = cpu_enable_sve, 2588 .matches = has_cpuid_feature, 2589 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2590 }, 2591 #endif /* CONFIG_ARM64_SVE */ 2592 #ifdef CONFIG_ARM64_RAS_EXTN 2593 { 2594 .desc = "RAS Extension Support", 2595 .capability = ARM64_HAS_RAS_EXTN, 2596 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2597 .matches = has_cpuid_feature, 2598 .cpu_enable = cpu_clear_disr, 2599 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2600 }, 2601 #endif /* CONFIG_ARM64_RAS_EXTN */ 2602 #ifdef CONFIG_ARM64_AMU_EXTN 2603 { 2604 .desc = "Activity Monitors Unit (AMU)", 2605 .capability = ARM64_HAS_AMU_EXTN, 2606 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2607 .matches = has_amu, 2608 .cpu_enable = cpu_amu_enable, 2609 .cpus = &amu_cpus, 2610 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2611 }, 2612 #endif /* CONFIG_ARM64_AMU_EXTN */ 2613 { 2614 .desc = "Data cache clean to the PoU not required for I/D coherence", 2615 .capability = ARM64_HAS_CACHE_IDC, 2616 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2617 .matches = has_cache_idc, 2618 .cpu_enable = cpu_emulate_effective_ctr, 2619 }, 2620 { 2621 .desc = "Instruction cache invalidation not required for I/D coherence", 2622 .capability = ARM64_HAS_CACHE_DIC, 2623 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2624 .matches = has_cache_dic, 2625 }, 2626 { 2627 .desc = "Stage-2 Force Write-Back", 2628 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2629 .capability = ARM64_HAS_STAGE2_FWB, 2630 .matches = has_cpuid_feature, 2631 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2632 }, 2633 { 2634 .desc = "ARMv8.4 Translation Table Level", 2635 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2636 .capability = ARM64_HAS_ARMv8_4_TTL, 2637 .matches = has_cpuid_feature, 2638 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2639 }, 2640 { 2641 .desc = "TLB range maintenance instructions", 2642 .capability = ARM64_HAS_TLB_RANGE, 2643 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2644 .matches = has_cpuid_feature, 2645 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2646 }, 2647 #ifdef CONFIG_ARM64_HW_AFDBM 2648 { 2649 .desc = "Hardware dirty bit management", 2650 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2651 .capability = ARM64_HW_DBM, 2652 .matches = has_hw_dbm, 2653 .cpu_enable = cpu_enable_hw_dbm, 2654 .cpus = &dbm_cpus, 2655 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2656 }, 2657 #endif 2658 #ifdef CONFIG_ARM64_HAFT 2659 { 2660 .desc = "Hardware managed Access Flag for Table Descriptors", 2661 /* 2662 * Contrary to the page/block access flag, the table access flag 2663 * cannot be emulated in software (no access fault will occur). 2664 * Therefore this should be used only if it's supported system 2665 * wide. 2666 */ 2667 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2668 .capability = ARM64_HAFT, 2669 .matches = has_cpuid_feature, 2670 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2671 }, 2672 #endif 2673 { 2674 .desc = "CRC32 instructions", 2675 .capability = ARM64_HAS_CRC32, 2676 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2677 .matches = has_cpuid_feature, 2678 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2679 }, 2680 { 2681 .desc = "Speculative Store Bypassing Safe (SSBS)", 2682 .capability = ARM64_SSBS, 2683 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2684 .matches = has_cpuid_feature, 2685 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2686 }, 2687 #ifdef CONFIG_ARM64_CNP 2688 { 2689 .desc = "Common not Private translations", 2690 .capability = ARM64_HAS_CNP, 2691 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2692 .matches = has_useable_cnp, 2693 .cpu_enable = cpu_enable_cnp, 2694 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2695 }, 2696 #endif 2697 { 2698 .desc = "Speculation barrier (SB)", 2699 .capability = ARM64_HAS_SB, 2700 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2701 .matches = has_cpuid_feature, 2702 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2703 }, 2704 #ifdef CONFIG_ARM64_PTR_AUTH 2705 { 2706 .desc = "Address authentication (architected QARMA5 algorithm)", 2707 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2708 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2709 .matches = has_address_auth_cpucap, 2710 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2711 }, 2712 { 2713 .desc = "Address authentication (architected QARMA3 algorithm)", 2714 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2715 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2716 .matches = has_address_auth_cpucap, 2717 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2718 }, 2719 { 2720 .desc = "Address authentication (IMP DEF algorithm)", 2721 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2722 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2723 .matches = has_address_auth_cpucap, 2724 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2725 }, 2726 { 2727 .capability = ARM64_HAS_ADDRESS_AUTH, 2728 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2729 .matches = has_address_auth_metacap, 2730 }, 2731 { 2732 .desc = "Generic authentication (architected QARMA5 algorithm)", 2733 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2734 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2735 .matches = has_cpuid_feature, 2736 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2737 }, 2738 { 2739 .desc = "Generic authentication (architected QARMA3 algorithm)", 2740 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2741 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2742 .matches = has_cpuid_feature, 2743 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2744 }, 2745 { 2746 .desc = "Generic authentication (IMP DEF algorithm)", 2747 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2748 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2749 .matches = has_cpuid_feature, 2750 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2751 }, 2752 { 2753 .capability = ARM64_HAS_GENERIC_AUTH, 2754 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2755 .matches = has_generic_auth, 2756 }, 2757 #endif /* CONFIG_ARM64_PTR_AUTH */ 2758 #ifdef CONFIG_ARM64_PSEUDO_NMI 2759 { 2760 /* 2761 * Depends on having GICv3 2762 */ 2763 .desc = "IRQ priority masking", 2764 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2765 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2766 .matches = can_use_gic_priorities, 2767 }, 2768 { 2769 /* 2770 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2771 */ 2772 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2773 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2774 .matches = has_gic_prio_relaxed_sync, 2775 }, 2776 #endif 2777 #ifdef CONFIG_ARM64_E0PD 2778 { 2779 .desc = "E0PD", 2780 .capability = ARM64_HAS_E0PD, 2781 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2782 .cpu_enable = cpu_enable_e0pd, 2783 .matches = has_cpuid_feature, 2784 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2785 }, 2786 #endif 2787 { 2788 .desc = "Random Number Generator", 2789 .capability = ARM64_HAS_RNG, 2790 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2791 .matches = has_cpuid_feature, 2792 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2793 }, 2794 #ifdef CONFIG_ARM64_BTI 2795 { 2796 .desc = "Branch Target Identification", 2797 .capability = ARM64_BTI, 2798 #ifdef CONFIG_ARM64_BTI_KERNEL 2799 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2800 #else 2801 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2802 #endif 2803 .matches = has_cpuid_feature, 2804 .cpu_enable = bti_enable, 2805 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2806 }, 2807 #endif 2808 #ifdef CONFIG_ARM64_MTE 2809 { 2810 .desc = "Memory Tagging Extension", 2811 .capability = ARM64_MTE, 2812 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2813 .matches = has_cpuid_feature, 2814 .cpu_enable = cpu_enable_mte, 2815 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2816 }, 2817 { 2818 .desc = "Asymmetric MTE Tag Check Fault", 2819 .capability = ARM64_MTE_ASYMM, 2820 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2821 .matches = has_cpuid_feature, 2822 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2823 }, 2824 #endif /* CONFIG_ARM64_MTE */ 2825 { 2826 .desc = "RCpc load-acquire (LDAPR)", 2827 .capability = ARM64_HAS_LDAPR, 2828 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2829 .matches = has_cpuid_feature, 2830 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2831 }, 2832 { 2833 .desc = "Fine Grained Traps", 2834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2835 .capability = ARM64_HAS_FGT, 2836 .matches = has_cpuid_feature, 2837 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2838 }, 2839 #ifdef CONFIG_ARM64_SME 2840 { 2841 .desc = "Scalable Matrix Extension", 2842 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2843 .capability = ARM64_SME, 2844 .matches = has_cpuid_feature, 2845 .cpu_enable = cpu_enable_sme, 2846 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2847 }, 2848 /* FA64 should be sorted after the base SME capability */ 2849 { 2850 .desc = "FA64", 2851 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2852 .capability = ARM64_SME_FA64, 2853 .matches = has_cpuid_feature, 2854 .cpu_enable = cpu_enable_fa64, 2855 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2856 }, 2857 { 2858 .desc = "SME2", 2859 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2860 .capability = ARM64_SME2, 2861 .matches = has_cpuid_feature, 2862 .cpu_enable = cpu_enable_sme2, 2863 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2864 }, 2865 #endif /* CONFIG_ARM64_SME */ 2866 { 2867 .desc = "WFx with timeout", 2868 .capability = ARM64_HAS_WFXT, 2869 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2870 .matches = has_cpuid_feature, 2871 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2872 }, 2873 { 2874 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2875 .capability = ARM64_HAS_TIDCP1, 2876 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2877 .matches = has_cpuid_feature, 2878 .cpu_enable = cpu_trap_el0_impdef, 2879 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2880 }, 2881 { 2882 .desc = "Data independent timing control (DIT)", 2883 .capability = ARM64_HAS_DIT, 2884 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2885 .matches = has_cpuid_feature, 2886 .cpu_enable = cpu_enable_dit, 2887 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2888 }, 2889 { 2890 .desc = "Memory Copy and Memory Set instructions", 2891 .capability = ARM64_HAS_MOPS, 2892 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2893 .matches = has_cpuid_feature, 2894 .cpu_enable = cpu_enable_mops, 2895 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2896 }, 2897 { 2898 .capability = ARM64_HAS_TCR2, 2899 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2900 .matches = has_cpuid_feature, 2901 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2902 }, 2903 { 2904 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2905 .capability = ARM64_HAS_S1PIE, 2906 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2907 .matches = has_cpuid_feature, 2908 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2909 }, 2910 { 2911 .desc = "VHE for hypervisor only", 2912 .capability = ARM64_KVM_HVHE, 2913 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2914 .matches = hvhe_possible, 2915 }, 2916 { 2917 .desc = "Enhanced Virtualization Traps", 2918 .capability = ARM64_HAS_EVT, 2919 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2920 .matches = has_cpuid_feature, 2921 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2922 }, 2923 { 2924 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2925 .capability = ARM64_HAS_LPA2, 2926 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2927 .matches = has_lpa2, 2928 }, 2929 { 2930 .desc = "FPMR", 2931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2932 .capability = ARM64_HAS_FPMR, 2933 .matches = has_cpuid_feature, 2934 .cpu_enable = cpu_enable_fpmr, 2935 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2936 }, 2937 #ifdef CONFIG_ARM64_VA_BITS_52 2938 { 2939 .capability = ARM64_HAS_VA52, 2940 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2941 .matches = has_cpuid_feature, 2942 #ifdef CONFIG_ARM64_64K_PAGES 2943 .desc = "52-bit Virtual Addressing (LVA)", 2944 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2945 #else 2946 .desc = "52-bit Virtual Addressing (LPA2)", 2947 #ifdef CONFIG_ARM64_4K_PAGES 2948 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2949 #else 2950 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2951 #endif 2952 #endif 2953 }, 2954 #endif 2955 { 2956 .desc = "Memory Partitioning And Monitoring", 2957 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2958 .capability = ARM64_MPAM, 2959 .matches = test_has_mpam, 2960 .cpu_enable = cpu_enable_mpam, 2961 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 2962 }, 2963 { 2964 .desc = "Memory Partitioning And Monitoring Virtualisation", 2965 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2966 .capability = ARM64_MPAM_HCR, 2967 .matches = test_has_mpam_hcr, 2968 }, 2969 { 2970 .desc = "NV1", 2971 .capability = ARM64_HAS_HCR_NV1, 2972 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2973 .matches = has_nv1, 2974 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2975 }, 2976 #ifdef CONFIG_ARM64_POE 2977 { 2978 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2979 .capability = ARM64_HAS_S1POE, 2980 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2981 .matches = has_cpuid_feature, 2982 .cpu_enable = cpu_enable_poe, 2983 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2984 }, 2985 #endif 2986 #ifdef CONFIG_ARM64_GCS 2987 { 2988 .desc = "Guarded Control Stack (GCS)", 2989 .capability = ARM64_HAS_GCS, 2990 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2991 .cpu_enable = cpu_enable_gcs, 2992 .matches = has_cpuid_feature, 2993 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 2994 }, 2995 #endif 2996 {}, 2997 }; 2998 2999 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3000 .matches = has_user_cpuid_feature, \ 3001 ARM64_CPUID_FIELDS(reg, field, min_value) 3002 3003 #define __HWCAP_CAP(name, cap_type, cap) \ 3004 .desc = name, \ 3005 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3006 .hwcap_type = cap_type, \ 3007 .hwcap = cap, \ 3008 3009 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3010 { \ 3011 __HWCAP_CAP(#cap, cap_type, cap) \ 3012 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3013 } 3014 3015 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3016 { \ 3017 __HWCAP_CAP(#cap, cap_type, cap) \ 3018 .matches = cpucap_multi_entry_cap_matches, \ 3019 .match_list = list, \ 3020 } 3021 3022 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3023 { \ 3024 __HWCAP_CAP(#cap, cap_type, cap) \ 3025 .matches = match, \ 3026 } 3027 3028 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3029 { \ 3030 __HWCAP_CAP(#cap, cap_type, cap) \ 3031 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3032 .matches = match, \ 3033 } 3034 3035 #ifdef CONFIG_ARM64_PTR_AUTH 3036 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3037 { 3038 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3039 }, 3040 { 3041 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3042 }, 3043 { 3044 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3045 }, 3046 {}, 3047 }; 3048 3049 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3050 { 3051 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3052 }, 3053 { 3054 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3055 }, 3056 { 3057 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3058 }, 3059 {}, 3060 }; 3061 #endif 3062 3063 #ifdef CONFIG_ARM64_SVE 3064 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3065 { 3066 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3067 } 3068 #endif 3069 3070 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3071 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3072 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3073 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3074 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3075 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3076 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3077 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3078 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3079 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3080 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3081 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3082 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3083 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3084 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3085 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3086 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3087 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3088 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3089 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3090 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3091 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3092 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3093 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3094 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3095 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3096 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3097 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3098 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3099 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3100 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3101 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3102 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3103 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3104 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3105 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3106 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3107 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3108 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3109 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3110 #ifdef CONFIG_ARM64_SVE 3111 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3112 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3113 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3114 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3115 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3116 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3117 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3118 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3119 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3120 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3121 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3122 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3123 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3124 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3125 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3126 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3127 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3128 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3129 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3130 #endif 3131 #ifdef CONFIG_ARM64_GCS 3132 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3133 #endif 3134 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3135 #ifdef CONFIG_ARM64_BTI 3136 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3137 #endif 3138 #ifdef CONFIG_ARM64_PTR_AUTH 3139 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3140 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3141 #endif 3142 #ifdef CONFIG_ARM64_MTE 3143 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3144 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3145 #endif /* CONFIG_ARM64_MTE */ 3146 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3147 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3148 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3149 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3150 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3151 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3152 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3153 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3154 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3155 #ifdef CONFIG_ARM64_SME 3156 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3157 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3158 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3159 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3160 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3161 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3162 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3163 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3164 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3165 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3166 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3167 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3168 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3169 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3170 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3171 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3172 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3173 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3174 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3175 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3176 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3177 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM8), 3178 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM4), 3179 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3180 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3181 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3182 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3183 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3184 #endif /* CONFIG_ARM64_SME */ 3185 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3186 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3187 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3188 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3189 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3190 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3191 #ifdef CONFIG_ARM64_POE 3192 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3193 #endif 3194 {}, 3195 }; 3196 3197 #ifdef CONFIG_COMPAT 3198 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3199 { 3200 /* 3201 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3202 * in line with that of arm32 as in vfp_init(). We make sure that the 3203 * check is future proof, by making sure value is non-zero. 3204 */ 3205 u32 mvfr1; 3206 3207 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3208 if (scope == SCOPE_SYSTEM) 3209 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3210 else 3211 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3212 3213 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3214 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3215 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3216 } 3217 #endif 3218 3219 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3220 #ifdef CONFIG_COMPAT 3221 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3222 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3223 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3224 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3225 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3226 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3227 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3228 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3229 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3230 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3231 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3232 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3233 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3234 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3235 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3236 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3237 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3238 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3239 #endif 3240 {}, 3241 }; 3242 3243 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3244 { 3245 switch (cap->hwcap_type) { 3246 case CAP_HWCAP: 3247 cpu_set_feature(cap->hwcap); 3248 break; 3249 #ifdef CONFIG_COMPAT 3250 case CAP_COMPAT_HWCAP: 3251 compat_elf_hwcap |= (u32)cap->hwcap; 3252 break; 3253 case CAP_COMPAT_HWCAP2: 3254 compat_elf_hwcap2 |= (u32)cap->hwcap; 3255 break; 3256 #endif 3257 default: 3258 WARN_ON(1); 3259 break; 3260 } 3261 } 3262 3263 /* Check if we have a particular HWCAP enabled */ 3264 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3265 { 3266 bool rc; 3267 3268 switch (cap->hwcap_type) { 3269 case CAP_HWCAP: 3270 rc = cpu_have_feature(cap->hwcap); 3271 break; 3272 #ifdef CONFIG_COMPAT 3273 case CAP_COMPAT_HWCAP: 3274 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3275 break; 3276 case CAP_COMPAT_HWCAP2: 3277 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3278 break; 3279 #endif 3280 default: 3281 WARN_ON(1); 3282 rc = false; 3283 } 3284 3285 return rc; 3286 } 3287 3288 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3289 { 3290 /* We support emulation of accesses to CPU ID feature registers */ 3291 cpu_set_named_feature(CPUID); 3292 for (; hwcaps->matches; hwcaps++) 3293 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3294 cap_set_elf_hwcap(hwcaps); 3295 } 3296 3297 static void update_cpu_capabilities(u16 scope_mask) 3298 { 3299 int i; 3300 const struct arm64_cpu_capabilities *caps; 3301 3302 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3303 for (i = 0; i < ARM64_NCAPS; i++) { 3304 caps = cpucap_ptrs[i]; 3305 if (!caps || !(caps->type & scope_mask) || 3306 cpus_have_cap(caps->capability) || 3307 !caps->matches(caps, cpucap_default_scope(caps))) 3308 continue; 3309 3310 if (caps->desc && !caps->cpus) 3311 pr_info("detected: %s\n", caps->desc); 3312 3313 __set_bit(caps->capability, system_cpucaps); 3314 3315 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3316 set_bit(caps->capability, boot_cpucaps); 3317 } 3318 } 3319 3320 /* 3321 * Enable all the available capabilities on this CPU. The capabilities 3322 * with BOOT_CPU scope are handled separately and hence skipped here. 3323 */ 3324 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3325 { 3326 int i; 3327 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3328 3329 for_each_available_cap(i) { 3330 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3331 3332 if (WARN_ON(!cap)) 3333 continue; 3334 3335 if (!(cap->type & non_boot_scope)) 3336 continue; 3337 3338 if (cap->cpu_enable) 3339 cap->cpu_enable(cap); 3340 } 3341 return 0; 3342 } 3343 3344 /* 3345 * Run through the enabled capabilities and enable() it on all active 3346 * CPUs 3347 */ 3348 static void __init enable_cpu_capabilities(u16 scope_mask) 3349 { 3350 int i; 3351 const struct arm64_cpu_capabilities *caps; 3352 bool boot_scope; 3353 3354 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3355 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3356 3357 for (i = 0; i < ARM64_NCAPS; i++) { 3358 caps = cpucap_ptrs[i]; 3359 if (!caps || !(caps->type & scope_mask) || 3360 !cpus_have_cap(caps->capability)) 3361 continue; 3362 3363 if (boot_scope && caps->cpu_enable) 3364 /* 3365 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3366 * before any secondary CPU boots. Thus, each secondary 3367 * will enable the capability as appropriate via 3368 * check_local_cpu_capabilities(). The only exception is 3369 * the boot CPU, for which the capability must be 3370 * enabled here. This approach avoids costly 3371 * stop_machine() calls for this case. 3372 */ 3373 caps->cpu_enable(caps); 3374 } 3375 3376 /* 3377 * For all non-boot scope capabilities, use stop_machine() 3378 * as it schedules the work allowing us to modify PSTATE, 3379 * instead of on_each_cpu() which uses an IPI, giving us a 3380 * PSTATE that disappears when we return. 3381 */ 3382 if (!boot_scope) 3383 stop_machine(cpu_enable_non_boot_scope_capabilities, 3384 NULL, cpu_online_mask); 3385 } 3386 3387 /* 3388 * Run through the list of capabilities to check for conflicts. 3389 * If the system has already detected a capability, take necessary 3390 * action on this CPU. 3391 */ 3392 static void verify_local_cpu_caps(u16 scope_mask) 3393 { 3394 int i; 3395 bool cpu_has_cap, system_has_cap; 3396 const struct arm64_cpu_capabilities *caps; 3397 3398 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3399 3400 for (i = 0; i < ARM64_NCAPS; i++) { 3401 caps = cpucap_ptrs[i]; 3402 if (!caps || !(caps->type & scope_mask)) 3403 continue; 3404 3405 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3406 system_has_cap = cpus_have_cap(caps->capability); 3407 3408 if (system_has_cap) { 3409 /* 3410 * Check if the new CPU misses an advertised feature, 3411 * which is not safe to miss. 3412 */ 3413 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3414 break; 3415 /* 3416 * We have to issue cpu_enable() irrespective of 3417 * whether the CPU has it or not, as it is enabeld 3418 * system wide. It is upto the call back to take 3419 * appropriate action on this CPU. 3420 */ 3421 if (caps->cpu_enable) 3422 caps->cpu_enable(caps); 3423 } else { 3424 /* 3425 * Check if the CPU has this capability if it isn't 3426 * safe to have when the system doesn't. 3427 */ 3428 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3429 break; 3430 } 3431 } 3432 3433 if (i < ARM64_NCAPS) { 3434 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3435 smp_processor_id(), caps->capability, 3436 caps->desc, system_has_cap, cpu_has_cap); 3437 3438 if (cpucap_panic_on_conflict(caps)) 3439 cpu_panic_kernel(); 3440 else 3441 cpu_die_early(); 3442 } 3443 } 3444 3445 /* 3446 * Check for CPU features that are used in early boot 3447 * based on the Boot CPU value. 3448 */ 3449 static void check_early_cpu_features(void) 3450 { 3451 verify_cpu_asid_bits(); 3452 3453 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3454 } 3455 3456 static void 3457 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3458 { 3459 3460 for (; caps->matches; caps++) 3461 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3462 pr_crit("CPU%d: missing HWCAP: %s\n", 3463 smp_processor_id(), caps->desc); 3464 cpu_die_early(); 3465 } 3466 } 3467 3468 static void verify_local_elf_hwcaps(void) 3469 { 3470 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3471 3472 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3473 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3474 } 3475 3476 static void verify_sve_features(void) 3477 { 3478 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3479 3480 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3481 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3482 smp_processor_id()); 3483 cpu_die_early(); 3484 } 3485 3486 cpacr_restore(cpacr); 3487 } 3488 3489 static void verify_sme_features(void) 3490 { 3491 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3492 3493 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3494 pr_crit("CPU%d: SME: vector length support mismatch\n", 3495 smp_processor_id()); 3496 cpu_die_early(); 3497 } 3498 3499 cpacr_restore(cpacr); 3500 } 3501 3502 static void verify_hyp_capabilities(void) 3503 { 3504 u64 safe_mmfr1, mmfr0, mmfr1; 3505 int parange, ipa_max; 3506 unsigned int safe_vmid_bits, vmid_bits; 3507 3508 if (!IS_ENABLED(CONFIG_KVM)) 3509 return; 3510 3511 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3512 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3513 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3514 3515 /* Verify VMID bits */ 3516 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3517 vmid_bits = get_vmid_bits(mmfr1); 3518 if (vmid_bits < safe_vmid_bits) { 3519 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3520 cpu_die_early(); 3521 } 3522 3523 /* Verify IPA range */ 3524 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3525 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3526 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3527 if (ipa_max < get_kvm_ipa_limit()) { 3528 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3529 cpu_die_early(); 3530 } 3531 } 3532 3533 static void verify_mpam_capabilities(void) 3534 { 3535 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3536 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3537 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3538 3539 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3540 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3541 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3542 cpu_die_early(); 3543 } 3544 3545 cpu_idr = read_cpuid(MPAMIDR_EL1); 3546 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3547 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3548 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3549 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3550 cpu_die_early(); 3551 } 3552 3553 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3554 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3555 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3556 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3557 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3558 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3559 cpu_die_early(); 3560 } 3561 } 3562 3563 /* 3564 * Run through the enabled system capabilities and enable() it on this CPU. 3565 * The capabilities were decided based on the available CPUs at the boot time. 3566 * Any new CPU should match the system wide status of the capability. If the 3567 * new CPU doesn't have a capability which the system now has enabled, we 3568 * cannot do anything to fix it up and could cause unexpected failures. So 3569 * we park the CPU. 3570 */ 3571 static void verify_local_cpu_capabilities(void) 3572 { 3573 /* 3574 * The capabilities with SCOPE_BOOT_CPU are checked from 3575 * check_early_cpu_features(), as they need to be verified 3576 * on all secondary CPUs. 3577 */ 3578 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3579 verify_local_elf_hwcaps(); 3580 3581 if (system_supports_sve()) 3582 verify_sve_features(); 3583 3584 if (system_supports_sme()) 3585 verify_sme_features(); 3586 3587 if (is_hyp_mode_available()) 3588 verify_hyp_capabilities(); 3589 3590 if (system_supports_mpam()) 3591 verify_mpam_capabilities(); 3592 } 3593 3594 void check_local_cpu_capabilities(void) 3595 { 3596 /* 3597 * All secondary CPUs should conform to the early CPU features 3598 * in use by the kernel based on boot CPU. 3599 */ 3600 check_early_cpu_features(); 3601 3602 /* 3603 * If we haven't finalised the system capabilities, this CPU gets 3604 * a chance to update the errata work arounds and local features. 3605 * Otherwise, this CPU should verify that it has all the system 3606 * advertised capabilities. 3607 */ 3608 if (!system_capabilities_finalized()) 3609 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3610 else 3611 verify_local_cpu_capabilities(); 3612 } 3613 3614 bool this_cpu_has_cap(unsigned int n) 3615 { 3616 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3617 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3618 3619 if (cap) 3620 return cap->matches(cap, SCOPE_LOCAL_CPU); 3621 } 3622 3623 return false; 3624 } 3625 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3626 3627 /* 3628 * This helper function is used in a narrow window when, 3629 * - The system wide safe registers are set with all the SMP CPUs and, 3630 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3631 */ 3632 static bool __maybe_unused __system_matches_cap(unsigned int n) 3633 { 3634 if (n < ARM64_NCAPS) { 3635 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3636 3637 if (cap) 3638 return cap->matches(cap, SCOPE_SYSTEM); 3639 } 3640 return false; 3641 } 3642 3643 void cpu_set_feature(unsigned int num) 3644 { 3645 set_bit(num, elf_hwcap); 3646 } 3647 3648 bool cpu_have_feature(unsigned int num) 3649 { 3650 return test_bit(num, elf_hwcap); 3651 } 3652 EXPORT_SYMBOL_GPL(cpu_have_feature); 3653 3654 unsigned long cpu_get_elf_hwcap(void) 3655 { 3656 /* 3657 * We currently only populate the first 32 bits of AT_HWCAP. Please 3658 * note that for userspace compatibility we guarantee that bits 62 3659 * and 63 will always be returned as 0. 3660 */ 3661 return elf_hwcap[0]; 3662 } 3663 3664 unsigned long cpu_get_elf_hwcap2(void) 3665 { 3666 return elf_hwcap[1]; 3667 } 3668 3669 unsigned long cpu_get_elf_hwcap3(void) 3670 { 3671 return elf_hwcap[2]; 3672 } 3673 3674 static void __init setup_boot_cpu_capabilities(void) 3675 { 3676 /* 3677 * The boot CPU's feature register values have been recorded. Detect 3678 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3679 * patch alternatives for the available boot cpucaps. 3680 */ 3681 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3682 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3683 apply_boot_alternatives(); 3684 } 3685 3686 void __init setup_boot_cpu_features(void) 3687 { 3688 /* 3689 * Initialize the indirect array of CPU capabilities pointers before we 3690 * handle the boot CPU. 3691 */ 3692 init_cpucap_indirect_list(); 3693 3694 /* 3695 * Detect broken pseudo-NMI. Must be called _before_ the call to 3696 * setup_boot_cpu_capabilities() since it interacts with 3697 * can_use_gic_priorities(). 3698 */ 3699 detect_system_supports_pseudo_nmi(); 3700 3701 setup_boot_cpu_capabilities(); 3702 } 3703 3704 static void __init setup_system_capabilities(void) 3705 { 3706 /* 3707 * The system-wide safe feature register values have been finalized. 3708 * Detect, enable, and patch alternatives for the available system 3709 * cpucaps. 3710 */ 3711 update_cpu_capabilities(SCOPE_SYSTEM); 3712 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3713 apply_alternatives_all(); 3714 3715 /* 3716 * Log any cpucaps with a cpumask as these aren't logged by 3717 * update_cpu_capabilities(). 3718 */ 3719 for (int i = 0; i < ARM64_NCAPS; i++) { 3720 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3721 3722 if (caps && caps->cpus && caps->desc && 3723 cpumask_any(caps->cpus) < nr_cpu_ids) 3724 pr_info("detected: %s on CPU%*pbl\n", 3725 caps->desc, cpumask_pr_args(caps->cpus)); 3726 } 3727 3728 /* 3729 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3730 */ 3731 if (system_uses_ttbr0_pan()) 3732 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3733 } 3734 3735 void __init setup_system_features(void) 3736 { 3737 setup_system_capabilities(); 3738 3739 kpti_install_ng_mappings(); 3740 3741 sve_setup(); 3742 sme_setup(); 3743 3744 /* 3745 * Check for sane CTR_EL0.CWG value. 3746 */ 3747 if (!cache_type_cwg()) 3748 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3749 ARCH_DMA_MINALIGN); 3750 } 3751 3752 void __init setup_user_features(void) 3753 { 3754 user_feature_fixup(); 3755 3756 setup_elf_hwcaps(arm64_elf_hwcaps); 3757 3758 if (system_supports_32bit_el0()) { 3759 setup_elf_hwcaps(compat_elf_hwcaps); 3760 elf_hwcap_fixup(); 3761 } 3762 3763 minsigstksz_setup(); 3764 } 3765 3766 static int enable_mismatched_32bit_el0(unsigned int cpu) 3767 { 3768 /* 3769 * The first 32-bit-capable CPU we detected and so can no longer 3770 * be offlined by userspace. -1 indicates we haven't yet onlined 3771 * a 32-bit-capable CPU. 3772 */ 3773 static int lucky_winner = -1; 3774 3775 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3776 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3777 3778 if (cpu_32bit) { 3779 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3780 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3781 } 3782 3783 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3784 return 0; 3785 3786 if (lucky_winner >= 0) 3787 return 0; 3788 3789 /* 3790 * We've detected a mismatch. We need to keep one of our CPUs with 3791 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3792 * every CPU in the system for a 32-bit task. 3793 */ 3794 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3795 cpu_active_mask); 3796 get_cpu_device(lucky_winner)->offline_disabled = true; 3797 setup_elf_hwcaps(compat_elf_hwcaps); 3798 elf_hwcap_fixup(); 3799 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3800 cpu, lucky_winner); 3801 return 0; 3802 } 3803 3804 static int __init init_32bit_el0_mask(void) 3805 { 3806 if (!allow_mismatched_32bit_el0) 3807 return 0; 3808 3809 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3810 return -ENOMEM; 3811 3812 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3813 "arm64/mismatched_32bit_el0:online", 3814 enable_mismatched_32bit_el0, NULL); 3815 } 3816 subsys_initcall_sync(init_32bit_el0_mask); 3817 3818 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3819 { 3820 cpu_enable_swapper_cnp(); 3821 } 3822 3823 /* 3824 * We emulate only the following system register space. 3825 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3826 * See Table C5-6 System instruction encodings for System register accesses, 3827 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3828 */ 3829 static inline bool __attribute_const__ is_emulated(u32 id) 3830 { 3831 return (sys_reg_Op0(id) == 0x3 && 3832 sys_reg_CRn(id) == 0x0 && 3833 sys_reg_Op1(id) == 0x0 && 3834 (sys_reg_CRm(id) == 0 || 3835 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3836 } 3837 3838 /* 3839 * With CRm == 0, reg should be one of : 3840 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3841 */ 3842 static inline int emulate_id_reg(u32 id, u64 *valp) 3843 { 3844 switch (id) { 3845 case SYS_MIDR_EL1: 3846 *valp = read_cpuid_id(); 3847 break; 3848 case SYS_MPIDR_EL1: 3849 *valp = SYS_MPIDR_SAFE_VAL; 3850 break; 3851 case SYS_REVIDR_EL1: 3852 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3853 *valp = 0; 3854 break; 3855 default: 3856 return -EINVAL; 3857 } 3858 3859 return 0; 3860 } 3861 3862 static int emulate_sys_reg(u32 id, u64 *valp) 3863 { 3864 struct arm64_ftr_reg *regp; 3865 3866 if (!is_emulated(id)) 3867 return -EINVAL; 3868 3869 if (sys_reg_CRm(id) == 0) 3870 return emulate_id_reg(id, valp); 3871 3872 regp = get_arm64_ftr_reg_nowarn(id); 3873 if (regp) 3874 *valp = arm64_ftr_reg_user_value(regp); 3875 else 3876 /* 3877 * The untracked registers are either IMPLEMENTATION DEFINED 3878 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3879 */ 3880 *valp = 0; 3881 return 0; 3882 } 3883 3884 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3885 { 3886 int rc; 3887 u64 val; 3888 3889 rc = emulate_sys_reg(sys_reg, &val); 3890 if (!rc) { 3891 pt_regs_write_reg(regs, rt, val); 3892 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3893 } 3894 return rc; 3895 } 3896 3897 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3898 { 3899 u32 sys_reg, rt; 3900 3901 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3902 return false; 3903 3904 /* 3905 * sys_reg values are defined as used in mrs/msr instruction. 3906 * shift the imm value to get the encoding. 3907 */ 3908 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3909 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3910 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3911 } 3912 3913 enum mitigation_state arm64_get_meltdown_state(void) 3914 { 3915 if (__meltdown_safe) 3916 return SPECTRE_UNAFFECTED; 3917 3918 if (arm64_kernel_unmapped_at_el0()) 3919 return SPECTRE_MITIGATED; 3920 3921 return SPECTRE_VULNERABLE; 3922 } 3923 3924 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3925 char *buf) 3926 { 3927 switch (arm64_get_meltdown_state()) { 3928 case SPECTRE_UNAFFECTED: 3929 return sprintf(buf, "Not affected\n"); 3930 3931 case SPECTRE_MITIGATED: 3932 return sprintf(buf, "Mitigation: PTI\n"); 3933 3934 default: 3935 return sprintf(buf, "Vulnerable\n"); 3936 } 3937 } 3938