1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 */ 7 8 #define pr_fmt(fmt) "CPU features: " fmt 9 10 #include <linux/bsearch.h> 11 #include <linux/cpumask.h> 12 #include <linux/crash_dump.h> 13 #include <linux/sort.h> 14 #include <linux/stop_machine.h> 15 #include <linux/types.h> 16 #include <linux/mm.h> 17 #include <linux/cpu.h> 18 #include <asm/cpu.h> 19 #include <asm/cpufeature.h> 20 #include <asm/cpu_ops.h> 21 #include <asm/fpsimd.h> 22 #include <asm/mmu_context.h> 23 #include <asm/processor.h> 24 #include <asm/sysreg.h> 25 #include <asm/traps.h> 26 #include <asm/virt.h> 27 28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 29 static unsigned long elf_hwcap __read_mostly; 30 31 #ifdef CONFIG_COMPAT 32 #define COMPAT_ELF_HWCAP_DEFAULT \ 33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 36 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 37 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 38 COMPAT_HWCAP_LPAE) 39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 40 unsigned int compat_elf_hwcap2 __read_mostly; 41 #endif 42 43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 44 EXPORT_SYMBOL(cpu_hwcaps); 45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 46 47 /* Need also bit for ARM64_CB_PATCH */ 48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 49 50 /* 51 * Flag to indicate if we have computed the system wide 52 * capabilities based on the boot time active CPUs. This 53 * will be used to determine if a new booting CPU should 54 * go through the verification process to make sure that it 55 * supports the system capabilities, without using a hotplug 56 * notifier. 57 */ 58 static bool sys_caps_initialised; 59 60 static inline void set_sys_caps_initialised(void) 61 { 62 sys_caps_initialised = true; 63 } 64 65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 66 { 67 /* file-wide pr_fmt adds "CPU features: " prefix */ 68 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 69 return 0; 70 } 71 72 static struct notifier_block cpu_hwcaps_notifier = { 73 .notifier_call = dump_cpu_hwcaps 74 }; 75 76 static int __init register_cpu_hwcaps_dumper(void) 77 { 78 atomic_notifier_chain_register(&panic_notifier_list, 79 &cpu_hwcaps_notifier); 80 return 0; 81 } 82 __initcall(register_cpu_hwcaps_dumper); 83 84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 85 EXPORT_SYMBOL(cpu_hwcap_keys); 86 87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 88 { \ 89 .sign = SIGNED, \ 90 .visible = VISIBLE, \ 91 .strict = STRICT, \ 92 .type = TYPE, \ 93 .shift = SHIFT, \ 94 .width = WIDTH, \ 95 .safe_val = SAFE_VAL, \ 96 } 97 98 /* Define a feature with unsigned values */ 99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 100 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 101 102 /* Define a feature with a signed value */ 103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 104 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 105 106 #define ARM64_FTR_END \ 107 { \ 108 .width = 0, \ 109 } 110 111 /* meta feature for alternatives */ 112 static bool __maybe_unused 113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 114 115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 116 117 /* 118 * NOTE: Any changes to the visibility of features should be kept in 119 * sync with the documentation of the CPU feature register ABI. 120 */ 121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 122 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 123 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 124 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 134 ARM64_FTR_END, 135 }; 136 137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 139 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 140 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 141 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 142 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 146 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 147 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0), 148 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 149 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0), 150 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 151 ARM64_FTR_END, 152 }; 153 154 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 155 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 157 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 158 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 159 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 162 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 163 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 164 /* Linux doesn't care about the EL3 */ 165 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 169 ARM64_FTR_END, 170 }; 171 172 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 174 ARM64_FTR_END, 175 }; 176 177 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 181 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 182 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 183 ARM64_FTR_END, 184 }; 185 186 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 187 /* 188 * We already refuse to boot CPUs that don't support our configured 189 * page size, so we can only detect mismatches for a page size other 190 * than the one we're currently using. Unfortunately, SoCs like this 191 * exist in the wild so, even though we don't like it, we'll have to go 192 * along with it and treat them as non-strict. 193 */ 194 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 195 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 197 198 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 199 /* Linux shouldn't care about secure memory */ 200 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 201 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 203 /* 204 * Differing PARange is fine as long as all peripherals and memory are mapped 205 * within the minimum PARange of all CPUs 206 */ 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 208 ARM64_FTR_END, 209 }; 210 211 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 214 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 218 ARM64_FTR_END, 219 }; 220 221 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 229 ARM64_FTR_END, 230 }; 231 232 static const struct arm64_ftr_bits ftr_ctr[] = { 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 239 /* 240 * Linux can handle differing I-cache policies. Userspace JITs will 241 * make use of *minLine. 242 * If we have differing I-cache policies, report it as the weakest - VIPT. 243 */ 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 246 ARM64_FTR_END, 247 }; 248 249 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 250 .name = "SYS_CTR_EL0", 251 .ftr_bits = ftr_ctr 252 }; 253 254 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 255 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 256 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 257 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 259 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 260 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 263 ARM64_FTR_END, 264 }; 265 266 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 272 /* 273 * We can instantiate multiple PMU instances with different levels 274 * of support. 275 */ 276 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 279 ARM64_FTR_END, 280 }; 281 282 static const struct arm64_ftr_bits ftr_mvfr2[] = { 283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 285 ARM64_FTR_END, 286 }; 287 288 static const struct arm64_ftr_bits ftr_dczid[] = { 289 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 290 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 291 ARM64_FTR_END, 292 }; 293 294 295 static const struct arm64_ftr_bits ftr_id_isar5[] = { 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 307 ARM64_FTR_END, 308 }; 309 310 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 315 ARM64_FTR_END, 316 }; 317 318 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 320 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 326 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 327 ARM64_FTR_END, 328 }; 329 330 static const struct arm64_ftr_bits ftr_zcr[] = { 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 332 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 333 ARM64_FTR_END, 334 }; 335 336 /* 337 * Common ftr bits for a 32bit register with all hidden, strict 338 * attributes, with 4bit feature fields and a default safe value of 339 * 0. Covers the following 32bit registers: 340 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 341 */ 342 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 351 ARM64_FTR_END, 352 }; 353 354 /* Table for a single 32bit feature value */ 355 static const struct arm64_ftr_bits ftr_single32[] = { 356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 357 ARM64_FTR_END, 358 }; 359 360 static const struct arm64_ftr_bits ftr_raz[] = { 361 ARM64_FTR_END, 362 }; 363 364 #define ARM64_FTR_REG(id, table) { \ 365 .sys_id = id, \ 366 .reg = &(struct arm64_ftr_reg){ \ 367 .name = #id, \ 368 .ftr_bits = &((table)[0]), \ 369 }} 370 371 static const struct __ftr_reg_entry { 372 u32 sys_id; 373 struct arm64_ftr_reg *reg; 374 } arm64_ftr_regs[] = { 375 376 /* Op1 = 0, CRn = 0, CRm = 1 */ 377 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 378 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 379 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 380 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 381 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 382 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 383 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 384 385 /* Op1 = 0, CRn = 0, CRm = 2 */ 386 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 387 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 388 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 389 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 390 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 391 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 392 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 393 394 /* Op1 = 0, CRn = 0, CRm = 3 */ 395 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 396 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 397 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 398 399 /* Op1 = 0, CRn = 0, CRm = 4 */ 400 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 401 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 402 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 403 404 /* Op1 = 0, CRn = 0, CRm = 5 */ 405 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 406 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 407 408 /* Op1 = 0, CRn = 0, CRm = 6 */ 409 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 410 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 411 412 /* Op1 = 0, CRn = 0, CRm = 7 */ 413 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 414 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 415 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 416 417 /* Op1 = 0, CRn = 1, CRm = 2 */ 418 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 419 420 /* Op1 = 3, CRn = 0, CRm = 0 */ 421 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 422 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 423 424 /* Op1 = 3, CRn = 14, CRm = 0 */ 425 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 426 }; 427 428 static int search_cmp_ftr_reg(const void *id, const void *regp) 429 { 430 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 431 } 432 433 /* 434 * get_arm64_ftr_reg - Lookup a feature register entry using its 435 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 436 * ascending order of sys_id , we use binary search to find a matching 437 * entry. 438 * 439 * returns - Upon success, matching ftr_reg entry for id. 440 * - NULL on failure. It is upto the caller to decide 441 * the impact of a failure. 442 */ 443 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 444 { 445 const struct __ftr_reg_entry *ret; 446 447 ret = bsearch((const void *)(unsigned long)sys_id, 448 arm64_ftr_regs, 449 ARRAY_SIZE(arm64_ftr_regs), 450 sizeof(arm64_ftr_regs[0]), 451 search_cmp_ftr_reg); 452 if (ret) 453 return ret->reg; 454 return NULL; 455 } 456 457 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 458 s64 ftr_val) 459 { 460 u64 mask = arm64_ftr_mask(ftrp); 461 462 reg &= ~mask; 463 reg |= (ftr_val << ftrp->shift) & mask; 464 return reg; 465 } 466 467 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 468 s64 cur) 469 { 470 s64 ret = 0; 471 472 switch (ftrp->type) { 473 case FTR_EXACT: 474 ret = ftrp->safe_val; 475 break; 476 case FTR_LOWER_SAFE: 477 ret = new < cur ? new : cur; 478 break; 479 case FTR_HIGHER_OR_ZERO_SAFE: 480 if (!cur || !new) 481 break; 482 /* Fallthrough */ 483 case FTR_HIGHER_SAFE: 484 ret = new > cur ? new : cur; 485 break; 486 default: 487 BUG(); 488 } 489 490 return ret; 491 } 492 493 static void __init sort_ftr_regs(void) 494 { 495 int i; 496 497 /* Check that the array is sorted so that we can do the binary search */ 498 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 499 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 500 } 501 502 /* 503 * Initialise the CPU feature register from Boot CPU values. 504 * Also initiliases the strict_mask for the register. 505 * Any bits that are not covered by an arm64_ftr_bits entry are considered 506 * RES0 for the system-wide value, and must strictly match. 507 */ 508 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 509 { 510 u64 val = 0; 511 u64 strict_mask = ~0x0ULL; 512 u64 user_mask = 0; 513 u64 valid_mask = 0; 514 515 const struct arm64_ftr_bits *ftrp; 516 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 517 518 BUG_ON(!reg); 519 520 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 521 u64 ftr_mask = arm64_ftr_mask(ftrp); 522 s64 ftr_new = arm64_ftr_value(ftrp, new); 523 524 val = arm64_ftr_set_value(ftrp, val, ftr_new); 525 526 valid_mask |= ftr_mask; 527 if (!ftrp->strict) 528 strict_mask &= ~ftr_mask; 529 if (ftrp->visible) 530 user_mask |= ftr_mask; 531 else 532 reg->user_val = arm64_ftr_set_value(ftrp, 533 reg->user_val, 534 ftrp->safe_val); 535 } 536 537 val &= valid_mask; 538 539 reg->sys_val = val; 540 reg->strict_mask = strict_mask; 541 reg->user_mask = user_mask; 542 } 543 544 extern const struct arm64_cpu_capabilities arm64_errata[]; 545 static const struct arm64_cpu_capabilities arm64_features[]; 546 547 static void __init 548 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 549 { 550 for (; caps->matches; caps++) { 551 if (WARN(caps->capability >= ARM64_NCAPS, 552 "Invalid capability %d\n", caps->capability)) 553 continue; 554 if (WARN(cpu_hwcaps_ptrs[caps->capability], 555 "Duplicate entry for capability %d\n", 556 caps->capability)) 557 continue; 558 cpu_hwcaps_ptrs[caps->capability] = caps; 559 } 560 } 561 562 static void __init init_cpu_hwcaps_indirect_list(void) 563 { 564 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 565 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 566 } 567 568 static void __init setup_boot_cpu_capabilities(void); 569 570 void __init init_cpu_features(struct cpuinfo_arm64 *info) 571 { 572 /* Before we start using the tables, make sure it is sorted */ 573 sort_ftr_regs(); 574 575 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 576 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 577 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 578 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 579 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 580 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 581 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 582 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 583 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 584 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 585 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 586 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 587 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 588 589 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 590 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 591 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 592 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 593 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 594 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 595 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 596 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 597 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 598 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 599 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 600 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 601 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 602 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 603 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 604 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 605 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 606 } 607 608 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 609 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 610 sve_init_vq_map(); 611 } 612 613 /* 614 * Initialize the indirect array of CPU hwcaps capabilities pointers 615 * before we handle the boot CPU below. 616 */ 617 init_cpu_hwcaps_indirect_list(); 618 619 /* 620 * Detect and enable early CPU capabilities based on the boot CPU, 621 * after we have initialised the CPU feature infrastructure. 622 */ 623 setup_boot_cpu_capabilities(); 624 } 625 626 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 627 { 628 const struct arm64_ftr_bits *ftrp; 629 630 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 631 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 632 s64 ftr_new = arm64_ftr_value(ftrp, new); 633 634 if (ftr_cur == ftr_new) 635 continue; 636 /* Find a safe value */ 637 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 638 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 639 } 640 641 } 642 643 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 644 { 645 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 646 647 BUG_ON(!regp); 648 update_cpu_ftr_reg(regp, val); 649 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 650 return 0; 651 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 652 regp->name, boot, cpu, val); 653 return 1; 654 } 655 656 /* 657 * Update system wide CPU feature registers with the values from a 658 * non-boot CPU. Also performs SANITY checks to make sure that there 659 * aren't any insane variations from that of the boot CPU. 660 */ 661 void update_cpu_features(int cpu, 662 struct cpuinfo_arm64 *info, 663 struct cpuinfo_arm64 *boot) 664 { 665 int taint = 0; 666 667 /* 668 * The kernel can handle differing I-cache policies, but otherwise 669 * caches should look identical. Userspace JITs will make use of 670 * *minLine. 671 */ 672 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 673 info->reg_ctr, boot->reg_ctr); 674 675 /* 676 * Userspace may perform DC ZVA instructions. Mismatched block sizes 677 * could result in too much or too little memory being zeroed if a 678 * process is preempted and migrated between CPUs. 679 */ 680 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 681 info->reg_dczid, boot->reg_dczid); 682 683 /* If different, timekeeping will be broken (especially with KVM) */ 684 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 685 info->reg_cntfrq, boot->reg_cntfrq); 686 687 /* 688 * The kernel uses self-hosted debug features and expects CPUs to 689 * support identical debug features. We presently need CTX_CMPs, WRPs, 690 * and BRPs to be identical. 691 * ID_AA64DFR1 is currently RES0. 692 */ 693 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 694 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 695 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 696 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 697 /* 698 * Even in big.LITTLE, processors should be identical instruction-set 699 * wise. 700 */ 701 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 702 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 703 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 704 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 705 706 /* 707 * Differing PARange support is fine as long as all peripherals and 708 * memory are mapped within the minimum PARange of all CPUs. 709 * Linux should not care about secure memory. 710 */ 711 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 712 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 713 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 714 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 715 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 716 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 717 718 /* 719 * EL3 is not our concern. 720 */ 721 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 722 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 723 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 724 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 725 726 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 727 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 728 729 /* 730 * If we have AArch32, we care about 32-bit features for compat. 731 * If the system doesn't support AArch32, don't update them. 732 */ 733 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 734 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 735 736 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 737 info->reg_id_dfr0, boot->reg_id_dfr0); 738 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 739 info->reg_id_isar0, boot->reg_id_isar0); 740 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 741 info->reg_id_isar1, boot->reg_id_isar1); 742 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 743 info->reg_id_isar2, boot->reg_id_isar2); 744 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 745 info->reg_id_isar3, boot->reg_id_isar3); 746 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 747 info->reg_id_isar4, boot->reg_id_isar4); 748 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 749 info->reg_id_isar5, boot->reg_id_isar5); 750 751 /* 752 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 753 * ACTLR formats could differ across CPUs and therefore would have to 754 * be trapped for virtualization anyway. 755 */ 756 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 757 info->reg_id_mmfr0, boot->reg_id_mmfr0); 758 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 759 info->reg_id_mmfr1, boot->reg_id_mmfr1); 760 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 761 info->reg_id_mmfr2, boot->reg_id_mmfr2); 762 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 763 info->reg_id_mmfr3, boot->reg_id_mmfr3); 764 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 765 info->reg_id_pfr0, boot->reg_id_pfr0); 766 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 767 info->reg_id_pfr1, boot->reg_id_pfr1); 768 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 769 info->reg_mvfr0, boot->reg_mvfr0); 770 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 771 info->reg_mvfr1, boot->reg_mvfr1); 772 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 773 info->reg_mvfr2, boot->reg_mvfr2); 774 } 775 776 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 777 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 778 info->reg_zcr, boot->reg_zcr); 779 780 /* Probe vector lengths, unless we already gave up on SVE */ 781 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 782 !sys_caps_initialised) 783 sve_update_vq_map(); 784 } 785 786 /* 787 * Mismatched CPU features are a recipe for disaster. Don't even 788 * pretend to support them. 789 */ 790 if (taint) { 791 pr_warn_once("Unsupported CPU feature variation detected.\n"); 792 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 793 } 794 } 795 796 u64 read_sanitised_ftr_reg(u32 id) 797 { 798 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 799 800 /* We shouldn't get a request for an unsupported register */ 801 BUG_ON(!regp); 802 return regp->sys_val; 803 } 804 805 #define read_sysreg_case(r) \ 806 case r: return read_sysreg_s(r) 807 808 /* 809 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 810 * Read the system register on the current CPU 811 */ 812 static u64 __read_sysreg_by_encoding(u32 sys_id) 813 { 814 switch (sys_id) { 815 read_sysreg_case(SYS_ID_PFR0_EL1); 816 read_sysreg_case(SYS_ID_PFR1_EL1); 817 read_sysreg_case(SYS_ID_DFR0_EL1); 818 read_sysreg_case(SYS_ID_MMFR0_EL1); 819 read_sysreg_case(SYS_ID_MMFR1_EL1); 820 read_sysreg_case(SYS_ID_MMFR2_EL1); 821 read_sysreg_case(SYS_ID_MMFR3_EL1); 822 read_sysreg_case(SYS_ID_ISAR0_EL1); 823 read_sysreg_case(SYS_ID_ISAR1_EL1); 824 read_sysreg_case(SYS_ID_ISAR2_EL1); 825 read_sysreg_case(SYS_ID_ISAR3_EL1); 826 read_sysreg_case(SYS_ID_ISAR4_EL1); 827 read_sysreg_case(SYS_ID_ISAR5_EL1); 828 read_sysreg_case(SYS_MVFR0_EL1); 829 read_sysreg_case(SYS_MVFR1_EL1); 830 read_sysreg_case(SYS_MVFR2_EL1); 831 832 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 833 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 834 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 835 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 836 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 837 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 838 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 839 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 840 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 841 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 842 843 read_sysreg_case(SYS_CNTFRQ_EL0); 844 read_sysreg_case(SYS_CTR_EL0); 845 read_sysreg_case(SYS_DCZID_EL0); 846 847 default: 848 BUG(); 849 return 0; 850 } 851 } 852 853 #include <linux/irqchip/arm-gic-v3.h> 854 855 static bool 856 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 857 { 858 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 859 860 return val >= entry->min_field_value; 861 } 862 863 static bool 864 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 865 { 866 u64 val; 867 868 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 869 if (scope == SCOPE_SYSTEM) 870 val = read_sanitised_ftr_reg(entry->sys_reg); 871 else 872 val = __read_sysreg_by_encoding(entry->sys_reg); 873 874 return feature_matches(val, entry); 875 } 876 877 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 878 { 879 bool has_sre; 880 881 if (!has_cpuid_feature(entry, scope)) 882 return false; 883 884 has_sre = gic_enable_sre(); 885 if (!has_sre) 886 pr_warn_once("%s present but disabled by higher exception level\n", 887 entry->desc); 888 889 return has_sre; 890 } 891 892 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 893 { 894 u32 midr = read_cpuid_id(); 895 896 /* Cavium ThunderX pass 1.x and 2.x */ 897 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 898 MIDR_CPU_VAR_REV(0, 0), 899 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 900 } 901 902 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 903 { 904 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 905 906 return cpuid_feature_extract_signed_field(pfr0, 907 ID_AA64PFR0_FP_SHIFT) < 0; 908 } 909 910 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 911 int scope) 912 { 913 u64 ctr; 914 915 if (scope == SCOPE_SYSTEM) 916 ctr = arm64_ftr_reg_ctrel0.sys_val; 917 else 918 ctr = read_cpuid_effective_cachetype(); 919 920 return ctr & BIT(CTR_IDC_SHIFT); 921 } 922 923 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 924 { 925 /* 926 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 927 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 928 * to the CTR_EL0 on this CPU and emulate it with the real/safe 929 * value. 930 */ 931 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 932 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 933 } 934 935 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 936 int scope) 937 { 938 u64 ctr; 939 940 if (scope == SCOPE_SYSTEM) 941 ctr = arm64_ftr_reg_ctrel0.sys_val; 942 else 943 ctr = read_cpuid_cachetype(); 944 945 return ctr & BIT(CTR_DIC_SHIFT); 946 } 947 948 static bool __maybe_unused 949 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 950 { 951 /* 952 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 953 * may share TLB entries with a CPU stuck in the crashed 954 * kernel. 955 */ 956 if (is_kdump_kernel()) 957 return false; 958 959 return has_cpuid_feature(entry, scope); 960 } 961 962 static bool __meltdown_safe = true; 963 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 964 965 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 966 int scope) 967 { 968 /* List of CPUs that are not vulnerable and don't need KPTI */ 969 static const struct midr_range kpti_safe_list[] = { 970 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 971 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 972 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 973 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 974 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 975 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 976 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 977 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 978 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 979 { /* sentinel */ } 980 }; 981 char const *str = "kpti command line option"; 982 bool meltdown_safe; 983 984 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 985 986 /* Defer to CPU feature registers */ 987 if (has_cpuid_feature(entry, scope)) 988 meltdown_safe = true; 989 990 if (!meltdown_safe) 991 __meltdown_safe = false; 992 993 /* 994 * For reasons that aren't entirely clear, enabling KPTI on Cavium 995 * ThunderX leads to apparent I-cache corruption of kernel text, which 996 * ends as well as you might imagine. Don't even try. 997 */ 998 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 999 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1000 __kpti_forced = -1; 1001 } 1002 1003 /* Useful for KASLR robustness */ 1004 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) { 1005 if (!__kpti_forced) { 1006 str = "KASLR"; 1007 __kpti_forced = 1; 1008 } 1009 } 1010 1011 if (cpu_mitigations_off() && !__kpti_forced) { 1012 str = "mitigations=off"; 1013 __kpti_forced = -1; 1014 } 1015 1016 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1017 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1018 return false; 1019 } 1020 1021 /* Forced? */ 1022 if (__kpti_forced) { 1023 pr_info_once("kernel page table isolation forced %s by %s\n", 1024 __kpti_forced > 0 ? "ON" : "OFF", str); 1025 return __kpti_forced > 0; 1026 } 1027 1028 return !meltdown_safe; 1029 } 1030 1031 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1032 static void 1033 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1034 { 1035 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1036 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1037 kpti_remap_fn *remap_fn; 1038 1039 static bool kpti_applied = false; 1040 int cpu = smp_processor_id(); 1041 1042 /* 1043 * We don't need to rewrite the page-tables if either we've done 1044 * it already or we have KASLR enabled and therefore have not 1045 * created any global mappings at all. 1046 */ 1047 if (kpti_applied || kaslr_offset() > 0) 1048 return; 1049 1050 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1051 1052 cpu_install_idmap(); 1053 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1054 cpu_uninstall_idmap(); 1055 1056 if (!cpu) 1057 kpti_applied = true; 1058 1059 return; 1060 } 1061 #else 1062 static void 1063 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1064 { 1065 } 1066 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1067 1068 static int __init parse_kpti(char *str) 1069 { 1070 bool enabled; 1071 int ret = strtobool(str, &enabled); 1072 1073 if (ret) 1074 return ret; 1075 1076 __kpti_forced = enabled ? 1 : -1; 1077 return 0; 1078 } 1079 early_param("kpti", parse_kpti); 1080 1081 #ifdef CONFIG_ARM64_HW_AFDBM 1082 static inline void __cpu_enable_hw_dbm(void) 1083 { 1084 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1085 1086 write_sysreg(tcr, tcr_el1); 1087 isb(); 1088 } 1089 1090 static bool cpu_has_broken_dbm(void) 1091 { 1092 /* List of CPUs which have broken DBM support. */ 1093 static const struct midr_range cpus[] = { 1094 #ifdef CONFIG_ARM64_ERRATUM_1024718 1095 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1096 #endif 1097 {}, 1098 }; 1099 1100 return is_midr_in_range_list(read_cpuid_id(), cpus); 1101 } 1102 1103 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1104 { 1105 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1106 !cpu_has_broken_dbm(); 1107 } 1108 1109 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1110 { 1111 if (cpu_can_use_dbm(cap)) 1112 __cpu_enable_hw_dbm(); 1113 } 1114 1115 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1116 int __unused) 1117 { 1118 static bool detected = false; 1119 /* 1120 * DBM is a non-conflicting feature. i.e, the kernel can safely 1121 * run a mix of CPUs with and without the feature. So, we 1122 * unconditionally enable the capability to allow any late CPU 1123 * to use the feature. We only enable the control bits on the 1124 * CPU, if it actually supports. 1125 * 1126 * We have to make sure we print the "feature" detection only 1127 * when at least one CPU actually uses it. So check if this CPU 1128 * can actually use it and print the message exactly once. 1129 * 1130 * This is safe as all CPUs (including secondary CPUs - due to the 1131 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1132 * goes through the "matches" check exactly once. Also if a CPU 1133 * matches the criteria, it is guaranteed that the CPU will turn 1134 * the DBM on, as the capability is unconditionally enabled. 1135 */ 1136 if (!detected && cpu_can_use_dbm(cap)) { 1137 detected = true; 1138 pr_info("detected: Hardware dirty bit management\n"); 1139 } 1140 1141 return true; 1142 } 1143 1144 #endif 1145 1146 #ifdef CONFIG_ARM64_VHE 1147 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1148 { 1149 return is_kernel_in_hyp_mode(); 1150 } 1151 1152 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1153 { 1154 /* 1155 * Copy register values that aren't redirected by hardware. 1156 * 1157 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1158 * this value to tpidr_el2 before we patch the code. Once we've done 1159 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1160 * do anything here. 1161 */ 1162 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1163 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1164 } 1165 #endif 1166 1167 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1168 { 1169 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1170 1171 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1172 WARN_ON(val & (7 << 27 | 7 << 21)); 1173 } 1174 1175 #ifdef CONFIG_ARM64_SSBD 1176 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr) 1177 { 1178 if (user_mode(regs)) 1179 return 1; 1180 1181 if (instr & BIT(PSTATE_Imm_shift)) 1182 regs->pstate |= PSR_SSBS_BIT; 1183 else 1184 regs->pstate &= ~PSR_SSBS_BIT; 1185 1186 arm64_skip_faulting_instruction(regs, 4); 1187 return 0; 1188 } 1189 1190 static struct undef_hook ssbs_emulation_hook = { 1191 .instr_mask = ~(1U << PSTATE_Imm_shift), 1192 .instr_val = 0xd500401f | PSTATE_SSBS, 1193 .fn = ssbs_emulation_handler, 1194 }; 1195 1196 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 1197 { 1198 static bool undef_hook_registered = false; 1199 static DEFINE_RAW_SPINLOCK(hook_lock); 1200 1201 raw_spin_lock(&hook_lock); 1202 if (!undef_hook_registered) { 1203 register_undef_hook(&ssbs_emulation_hook); 1204 undef_hook_registered = true; 1205 } 1206 raw_spin_unlock(&hook_lock); 1207 1208 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 1209 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS); 1210 arm64_set_ssbd_mitigation(false); 1211 } else { 1212 arm64_set_ssbd_mitigation(true); 1213 } 1214 } 1215 #endif /* CONFIG_ARM64_SSBD */ 1216 1217 #ifdef CONFIG_ARM64_PAN 1218 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1219 { 1220 /* 1221 * We modify PSTATE. This won't work from irq context as the PSTATE 1222 * is discarded once we return from the exception. 1223 */ 1224 WARN_ON_ONCE(in_interrupt()); 1225 1226 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1227 asm(SET_PSTATE_PAN(1)); 1228 } 1229 #endif /* CONFIG_ARM64_PAN */ 1230 1231 #ifdef CONFIG_ARM64_RAS_EXTN 1232 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1233 { 1234 /* Firmware may have left a deferred SError in this register. */ 1235 write_sysreg_s(0, SYS_DISR_EL1); 1236 } 1237 #endif /* CONFIG_ARM64_RAS_EXTN */ 1238 1239 #ifdef CONFIG_ARM64_PTR_AUTH 1240 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) 1241 { 1242 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | 1243 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB); 1244 } 1245 #endif /* CONFIG_ARM64_PTR_AUTH */ 1246 1247 #ifdef CONFIG_ARM64_PSEUDO_NMI 1248 static bool enable_pseudo_nmi; 1249 1250 static int __init early_enable_pseudo_nmi(char *p) 1251 { 1252 return strtobool(p, &enable_pseudo_nmi); 1253 } 1254 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1255 1256 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1257 int scope) 1258 { 1259 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1260 } 1261 #endif 1262 1263 static const struct arm64_cpu_capabilities arm64_features[] = { 1264 { 1265 .desc = "GIC system register CPU interface", 1266 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1267 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1268 .matches = has_useable_gicv3_cpuif, 1269 .sys_reg = SYS_ID_AA64PFR0_EL1, 1270 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1271 .sign = FTR_UNSIGNED, 1272 .min_field_value = 1, 1273 }, 1274 #ifdef CONFIG_ARM64_PAN 1275 { 1276 .desc = "Privileged Access Never", 1277 .capability = ARM64_HAS_PAN, 1278 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1279 .matches = has_cpuid_feature, 1280 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1281 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1282 .sign = FTR_UNSIGNED, 1283 .min_field_value = 1, 1284 .cpu_enable = cpu_enable_pan, 1285 }, 1286 #endif /* CONFIG_ARM64_PAN */ 1287 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 1288 { 1289 .desc = "LSE atomic instructions", 1290 .capability = ARM64_HAS_LSE_ATOMICS, 1291 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1292 .matches = has_cpuid_feature, 1293 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1294 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1295 .sign = FTR_UNSIGNED, 1296 .min_field_value = 2, 1297 }, 1298 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 1299 { 1300 .desc = "Software prefetching using PRFM", 1301 .capability = ARM64_HAS_NO_HW_PREFETCH, 1302 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1303 .matches = has_no_hw_prefetch, 1304 }, 1305 #ifdef CONFIG_ARM64_UAO 1306 { 1307 .desc = "User Access Override", 1308 .capability = ARM64_HAS_UAO, 1309 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1310 .matches = has_cpuid_feature, 1311 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1312 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 1313 .min_field_value = 1, 1314 /* 1315 * We rely on stop_machine() calling uao_thread_switch() to set 1316 * UAO immediately after patching. 1317 */ 1318 }, 1319 #endif /* CONFIG_ARM64_UAO */ 1320 #ifdef CONFIG_ARM64_PAN 1321 { 1322 .capability = ARM64_ALT_PAN_NOT_UAO, 1323 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1324 .matches = cpufeature_pan_not_uao, 1325 }, 1326 #endif /* CONFIG_ARM64_PAN */ 1327 #ifdef CONFIG_ARM64_VHE 1328 { 1329 .desc = "Virtualization Host Extensions", 1330 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1331 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1332 .matches = runs_at_el2, 1333 .cpu_enable = cpu_copy_el2regs, 1334 }, 1335 #endif /* CONFIG_ARM64_VHE */ 1336 { 1337 .desc = "32-bit EL0 Support", 1338 .capability = ARM64_HAS_32BIT_EL0, 1339 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1340 .matches = has_cpuid_feature, 1341 .sys_reg = SYS_ID_AA64PFR0_EL1, 1342 .sign = FTR_UNSIGNED, 1343 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1344 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1345 }, 1346 { 1347 .desc = "Kernel page table isolation (KPTI)", 1348 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1349 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1350 /* 1351 * The ID feature fields below are used to indicate that 1352 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1353 * more details. 1354 */ 1355 .sys_reg = SYS_ID_AA64PFR0_EL1, 1356 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1357 .min_field_value = 1, 1358 .matches = unmap_kernel_at_el0, 1359 .cpu_enable = kpti_install_ng_mappings, 1360 }, 1361 { 1362 /* FP/SIMD is not implemented */ 1363 .capability = ARM64_HAS_NO_FPSIMD, 1364 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1365 .min_field_value = 0, 1366 .matches = has_no_fpsimd, 1367 }, 1368 #ifdef CONFIG_ARM64_PMEM 1369 { 1370 .desc = "Data cache clean to Point of Persistence", 1371 .capability = ARM64_HAS_DCPOP, 1372 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1373 .matches = has_cpuid_feature, 1374 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1375 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1376 .min_field_value = 1, 1377 }, 1378 { 1379 .desc = "Data cache clean to Point of Deep Persistence", 1380 .capability = ARM64_HAS_DCPODP, 1381 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1382 .matches = has_cpuid_feature, 1383 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1384 .sign = FTR_UNSIGNED, 1385 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1386 .min_field_value = 2, 1387 }, 1388 #endif 1389 #ifdef CONFIG_ARM64_SVE 1390 { 1391 .desc = "Scalable Vector Extension", 1392 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1393 .capability = ARM64_SVE, 1394 .sys_reg = SYS_ID_AA64PFR0_EL1, 1395 .sign = FTR_UNSIGNED, 1396 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1397 .min_field_value = ID_AA64PFR0_SVE, 1398 .matches = has_cpuid_feature, 1399 .cpu_enable = sve_kernel_enable, 1400 }, 1401 #endif /* CONFIG_ARM64_SVE */ 1402 #ifdef CONFIG_ARM64_RAS_EXTN 1403 { 1404 .desc = "RAS Extension Support", 1405 .capability = ARM64_HAS_RAS_EXTN, 1406 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1407 .matches = has_cpuid_feature, 1408 .sys_reg = SYS_ID_AA64PFR0_EL1, 1409 .sign = FTR_UNSIGNED, 1410 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1411 .min_field_value = ID_AA64PFR0_RAS_V1, 1412 .cpu_enable = cpu_clear_disr, 1413 }, 1414 #endif /* CONFIG_ARM64_RAS_EXTN */ 1415 { 1416 .desc = "Data cache clean to the PoU not required for I/D coherence", 1417 .capability = ARM64_HAS_CACHE_IDC, 1418 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1419 .matches = has_cache_idc, 1420 .cpu_enable = cpu_emulate_effective_ctr, 1421 }, 1422 { 1423 .desc = "Instruction cache invalidation not required for I/D coherence", 1424 .capability = ARM64_HAS_CACHE_DIC, 1425 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1426 .matches = has_cache_dic, 1427 }, 1428 { 1429 .desc = "Stage-2 Force Write-Back", 1430 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1431 .capability = ARM64_HAS_STAGE2_FWB, 1432 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1433 .sign = FTR_UNSIGNED, 1434 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1435 .min_field_value = 1, 1436 .matches = has_cpuid_feature, 1437 .cpu_enable = cpu_has_fwb, 1438 }, 1439 #ifdef CONFIG_ARM64_HW_AFDBM 1440 { 1441 /* 1442 * Since we turn this on always, we don't want the user to 1443 * think that the feature is available when it may not be. 1444 * So hide the description. 1445 * 1446 * .desc = "Hardware pagetable Dirty Bit Management", 1447 * 1448 */ 1449 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1450 .capability = ARM64_HW_DBM, 1451 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1452 .sign = FTR_UNSIGNED, 1453 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1454 .min_field_value = 2, 1455 .matches = has_hw_dbm, 1456 .cpu_enable = cpu_enable_hw_dbm, 1457 }, 1458 #endif 1459 { 1460 .desc = "CRC32 instructions", 1461 .capability = ARM64_HAS_CRC32, 1462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1463 .matches = has_cpuid_feature, 1464 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1465 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1466 .min_field_value = 1, 1467 }, 1468 #ifdef CONFIG_ARM64_SSBD 1469 { 1470 .desc = "Speculative Store Bypassing Safe (SSBS)", 1471 .capability = ARM64_SSBS, 1472 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1473 .matches = has_cpuid_feature, 1474 .sys_reg = SYS_ID_AA64PFR1_EL1, 1475 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1476 .sign = FTR_UNSIGNED, 1477 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1478 .cpu_enable = cpu_enable_ssbs, 1479 }, 1480 #endif 1481 #ifdef CONFIG_ARM64_CNP 1482 { 1483 .desc = "Common not Private translations", 1484 .capability = ARM64_HAS_CNP, 1485 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1486 .matches = has_useable_cnp, 1487 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1488 .sign = FTR_UNSIGNED, 1489 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 1490 .min_field_value = 1, 1491 .cpu_enable = cpu_enable_cnp, 1492 }, 1493 #endif 1494 { 1495 .desc = "Speculation barrier (SB)", 1496 .capability = ARM64_HAS_SB, 1497 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1498 .matches = has_cpuid_feature, 1499 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1500 .field_pos = ID_AA64ISAR1_SB_SHIFT, 1501 .sign = FTR_UNSIGNED, 1502 .min_field_value = 1, 1503 }, 1504 #ifdef CONFIG_ARM64_PTR_AUTH 1505 { 1506 .desc = "Address authentication (architected algorithm)", 1507 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 1508 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1509 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1510 .sign = FTR_UNSIGNED, 1511 .field_pos = ID_AA64ISAR1_APA_SHIFT, 1512 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 1513 .matches = has_cpuid_feature, 1514 .cpu_enable = cpu_enable_address_auth, 1515 }, 1516 { 1517 .desc = "Address authentication (IMP DEF algorithm)", 1518 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 1519 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1520 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1521 .sign = FTR_UNSIGNED, 1522 .field_pos = ID_AA64ISAR1_API_SHIFT, 1523 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 1524 .matches = has_cpuid_feature, 1525 .cpu_enable = cpu_enable_address_auth, 1526 }, 1527 { 1528 .desc = "Generic authentication (architected algorithm)", 1529 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 1530 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1531 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1532 .sign = FTR_UNSIGNED, 1533 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 1534 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 1535 .matches = has_cpuid_feature, 1536 }, 1537 { 1538 .desc = "Generic authentication (IMP DEF algorithm)", 1539 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 1540 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1541 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1542 .sign = FTR_UNSIGNED, 1543 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 1544 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 1545 .matches = has_cpuid_feature, 1546 }, 1547 #endif /* CONFIG_ARM64_PTR_AUTH */ 1548 #ifdef CONFIG_ARM64_PSEUDO_NMI 1549 { 1550 /* 1551 * Depends on having GICv3 1552 */ 1553 .desc = "IRQ priority masking", 1554 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 1555 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1556 .matches = can_use_gic_priorities, 1557 .sys_reg = SYS_ID_AA64PFR0_EL1, 1558 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1559 .sign = FTR_UNSIGNED, 1560 .min_field_value = 1, 1561 }, 1562 #endif 1563 {}, 1564 }; 1565 1566 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1567 .matches = has_cpuid_feature, \ 1568 .sys_reg = reg, \ 1569 .field_pos = field, \ 1570 .sign = s, \ 1571 .min_field_value = min_value, 1572 1573 #define __HWCAP_CAP(name, cap_type, cap) \ 1574 .desc = name, \ 1575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 1576 .hwcap_type = cap_type, \ 1577 .hwcap = cap, \ 1578 1579 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 1580 { \ 1581 __HWCAP_CAP(#cap, cap_type, cap) \ 1582 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 1583 } 1584 1585 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 1586 { \ 1587 __HWCAP_CAP(#cap, cap_type, cap) \ 1588 .matches = cpucap_multi_entry_cap_matches, \ 1589 .match_list = list, \ 1590 } 1591 1592 #ifdef CONFIG_ARM64_PTR_AUTH 1593 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 1594 { 1595 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 1596 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 1597 }, 1598 { 1599 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 1600 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 1601 }, 1602 {}, 1603 }; 1604 1605 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 1606 { 1607 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 1608 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 1609 }, 1610 { 1611 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 1612 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 1613 }, 1614 {}, 1615 }; 1616 #endif 1617 1618 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 1619 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 1620 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 1621 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 1622 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 1623 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 1624 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 1625 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 1626 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 1627 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 1628 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 1629 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 1630 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 1631 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 1632 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 1633 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 1634 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 1635 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 1636 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 1637 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 1638 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 1639 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 1640 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 1641 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 1642 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 1643 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 1644 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 1645 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 1646 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 1647 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 1648 #ifdef CONFIG_ARM64_SVE 1649 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 1650 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 1651 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 1652 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 1653 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 1654 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 1655 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 1656 #endif 1657 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 1658 #ifdef CONFIG_ARM64_PTR_AUTH 1659 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 1660 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 1661 #endif 1662 {}, 1663 }; 1664 1665 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 1666 #ifdef CONFIG_COMPAT 1667 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 1668 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 1669 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 1670 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 1671 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 1672 #endif 1673 {}, 1674 }; 1675 1676 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1677 { 1678 switch (cap->hwcap_type) { 1679 case CAP_HWCAP: 1680 cpu_set_feature(cap->hwcap); 1681 break; 1682 #ifdef CONFIG_COMPAT 1683 case CAP_COMPAT_HWCAP: 1684 compat_elf_hwcap |= (u32)cap->hwcap; 1685 break; 1686 case CAP_COMPAT_HWCAP2: 1687 compat_elf_hwcap2 |= (u32)cap->hwcap; 1688 break; 1689 #endif 1690 default: 1691 WARN_ON(1); 1692 break; 1693 } 1694 } 1695 1696 /* Check if we have a particular HWCAP enabled */ 1697 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1698 { 1699 bool rc; 1700 1701 switch (cap->hwcap_type) { 1702 case CAP_HWCAP: 1703 rc = cpu_have_feature(cap->hwcap); 1704 break; 1705 #ifdef CONFIG_COMPAT 1706 case CAP_COMPAT_HWCAP: 1707 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 1708 break; 1709 case CAP_COMPAT_HWCAP2: 1710 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 1711 break; 1712 #endif 1713 default: 1714 WARN_ON(1); 1715 rc = false; 1716 } 1717 1718 return rc; 1719 } 1720 1721 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 1722 { 1723 /* We support emulation of accesses to CPU ID feature registers */ 1724 cpu_set_named_feature(CPUID); 1725 for (; hwcaps->matches; hwcaps++) 1726 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 1727 cap_set_elf_hwcap(hwcaps); 1728 } 1729 1730 static void update_cpu_capabilities(u16 scope_mask) 1731 { 1732 int i; 1733 const struct arm64_cpu_capabilities *caps; 1734 1735 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1736 for (i = 0; i < ARM64_NCAPS; i++) { 1737 caps = cpu_hwcaps_ptrs[i]; 1738 if (!caps || !(caps->type & scope_mask) || 1739 cpus_have_cap(caps->capability) || 1740 !caps->matches(caps, cpucap_default_scope(caps))) 1741 continue; 1742 1743 if (caps->desc) 1744 pr_info("detected: %s\n", caps->desc); 1745 cpus_set_cap(caps->capability); 1746 1747 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 1748 set_bit(caps->capability, boot_capabilities); 1749 } 1750 } 1751 1752 /* 1753 * Enable all the available capabilities on this CPU. The capabilities 1754 * with BOOT_CPU scope are handled separately and hence skipped here. 1755 */ 1756 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 1757 { 1758 int i; 1759 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 1760 1761 for_each_available_cap(i) { 1762 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 1763 1764 if (WARN_ON(!cap)) 1765 continue; 1766 1767 if (!(cap->type & non_boot_scope)) 1768 continue; 1769 1770 if (cap->cpu_enable) 1771 cap->cpu_enable(cap); 1772 } 1773 return 0; 1774 } 1775 1776 /* 1777 * Run through the enabled capabilities and enable() it on all active 1778 * CPUs 1779 */ 1780 static void __init enable_cpu_capabilities(u16 scope_mask) 1781 { 1782 int i; 1783 const struct arm64_cpu_capabilities *caps; 1784 bool boot_scope; 1785 1786 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1787 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 1788 1789 for (i = 0; i < ARM64_NCAPS; i++) { 1790 unsigned int num; 1791 1792 caps = cpu_hwcaps_ptrs[i]; 1793 if (!caps || !(caps->type & scope_mask)) 1794 continue; 1795 num = caps->capability; 1796 if (!cpus_have_cap(num)) 1797 continue; 1798 1799 /* Ensure cpus_have_const_cap(num) works */ 1800 static_branch_enable(&cpu_hwcap_keys[num]); 1801 1802 if (boot_scope && caps->cpu_enable) 1803 /* 1804 * Capabilities with SCOPE_BOOT_CPU scope are finalised 1805 * before any secondary CPU boots. Thus, each secondary 1806 * will enable the capability as appropriate via 1807 * check_local_cpu_capabilities(). The only exception is 1808 * the boot CPU, for which the capability must be 1809 * enabled here. This approach avoids costly 1810 * stop_machine() calls for this case. 1811 */ 1812 caps->cpu_enable(caps); 1813 } 1814 1815 /* 1816 * For all non-boot scope capabilities, use stop_machine() 1817 * as it schedules the work allowing us to modify PSTATE, 1818 * instead of on_each_cpu() which uses an IPI, giving us a 1819 * PSTATE that disappears when we return. 1820 */ 1821 if (!boot_scope) 1822 stop_machine(cpu_enable_non_boot_scope_capabilities, 1823 NULL, cpu_online_mask); 1824 } 1825 1826 /* 1827 * Run through the list of capabilities to check for conflicts. 1828 * If the system has already detected a capability, take necessary 1829 * action on this CPU. 1830 * 1831 * Returns "false" on conflicts. 1832 */ 1833 static bool verify_local_cpu_caps(u16 scope_mask) 1834 { 1835 int i; 1836 bool cpu_has_cap, system_has_cap; 1837 const struct arm64_cpu_capabilities *caps; 1838 1839 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 1840 1841 for (i = 0; i < ARM64_NCAPS; i++) { 1842 caps = cpu_hwcaps_ptrs[i]; 1843 if (!caps || !(caps->type & scope_mask)) 1844 continue; 1845 1846 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 1847 system_has_cap = cpus_have_cap(caps->capability); 1848 1849 if (system_has_cap) { 1850 /* 1851 * Check if the new CPU misses an advertised feature, 1852 * which is not safe to miss. 1853 */ 1854 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 1855 break; 1856 /* 1857 * We have to issue cpu_enable() irrespective of 1858 * whether the CPU has it or not, as it is enabeld 1859 * system wide. It is upto the call back to take 1860 * appropriate action on this CPU. 1861 */ 1862 if (caps->cpu_enable) 1863 caps->cpu_enable(caps); 1864 } else { 1865 /* 1866 * Check if the CPU has this capability if it isn't 1867 * safe to have when the system doesn't. 1868 */ 1869 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 1870 break; 1871 } 1872 } 1873 1874 if (i < ARM64_NCAPS) { 1875 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 1876 smp_processor_id(), caps->capability, 1877 caps->desc, system_has_cap, cpu_has_cap); 1878 return false; 1879 } 1880 1881 return true; 1882 } 1883 1884 /* 1885 * Check for CPU features that are used in early boot 1886 * based on the Boot CPU value. 1887 */ 1888 static void check_early_cpu_features(void) 1889 { 1890 verify_cpu_asid_bits(); 1891 /* 1892 * Early features are used by the kernel already. If there 1893 * is a conflict, we cannot proceed further. 1894 */ 1895 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU)) 1896 cpu_panic_kernel(); 1897 } 1898 1899 static void 1900 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1901 { 1902 1903 for (; caps->matches; caps++) 1904 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1905 pr_crit("CPU%d: missing HWCAP: %s\n", 1906 smp_processor_id(), caps->desc); 1907 cpu_die_early(); 1908 } 1909 } 1910 1911 static void verify_sve_features(void) 1912 { 1913 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1914 u64 zcr = read_zcr_features(); 1915 1916 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 1917 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 1918 1919 if (len < safe_len || sve_verify_vq_map()) { 1920 pr_crit("CPU%d: SVE: vector length support mismatch\n", 1921 smp_processor_id()); 1922 cpu_die_early(); 1923 } 1924 1925 /* Add checks on other ZCR bits here if necessary */ 1926 } 1927 1928 1929 /* 1930 * Run through the enabled system capabilities and enable() it on this CPU. 1931 * The capabilities were decided based on the available CPUs at the boot time. 1932 * Any new CPU should match the system wide status of the capability. If the 1933 * new CPU doesn't have a capability which the system now has enabled, we 1934 * cannot do anything to fix it up and could cause unexpected failures. So 1935 * we park the CPU. 1936 */ 1937 static void verify_local_cpu_capabilities(void) 1938 { 1939 /* 1940 * The capabilities with SCOPE_BOOT_CPU are checked from 1941 * check_early_cpu_features(), as they need to be verified 1942 * on all secondary CPUs. 1943 */ 1944 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU)) 1945 cpu_die_early(); 1946 1947 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1948 1949 if (system_supports_32bit_el0()) 1950 verify_local_elf_hwcaps(compat_elf_hwcaps); 1951 1952 if (system_supports_sve()) 1953 verify_sve_features(); 1954 } 1955 1956 void check_local_cpu_capabilities(void) 1957 { 1958 /* 1959 * All secondary CPUs should conform to the early CPU features 1960 * in use by the kernel based on boot CPU. 1961 */ 1962 check_early_cpu_features(); 1963 1964 /* 1965 * If we haven't finalised the system capabilities, this CPU gets 1966 * a chance to update the errata work arounds and local features. 1967 * Otherwise, this CPU should verify that it has all the system 1968 * advertised capabilities. 1969 */ 1970 if (!sys_caps_initialised) 1971 update_cpu_capabilities(SCOPE_LOCAL_CPU); 1972 else 1973 verify_local_cpu_capabilities(); 1974 } 1975 1976 static void __init setup_boot_cpu_capabilities(void) 1977 { 1978 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 1979 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 1980 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 1981 enable_cpu_capabilities(SCOPE_BOOT_CPU); 1982 } 1983 1984 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 1985 EXPORT_SYMBOL(arm64_const_caps_ready); 1986 1987 static void __init mark_const_caps_ready(void) 1988 { 1989 static_branch_enable(&arm64_const_caps_ready); 1990 } 1991 1992 bool this_cpu_has_cap(unsigned int n) 1993 { 1994 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 1995 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 1996 1997 if (cap) 1998 return cap->matches(cap, SCOPE_LOCAL_CPU); 1999 } 2000 2001 return false; 2002 } 2003 2004 void cpu_set_feature(unsigned int num) 2005 { 2006 WARN_ON(num >= MAX_CPU_FEATURES); 2007 elf_hwcap |= BIT(num); 2008 } 2009 EXPORT_SYMBOL_GPL(cpu_set_feature); 2010 2011 bool cpu_have_feature(unsigned int num) 2012 { 2013 WARN_ON(num >= MAX_CPU_FEATURES); 2014 return elf_hwcap & BIT(num); 2015 } 2016 EXPORT_SYMBOL_GPL(cpu_have_feature); 2017 2018 unsigned long cpu_get_elf_hwcap(void) 2019 { 2020 /* 2021 * We currently only populate the first 32 bits of AT_HWCAP. Please 2022 * note that for userspace compatibility we guarantee that bits 62 2023 * and 63 will always be returned as 0. 2024 */ 2025 return lower_32_bits(elf_hwcap); 2026 } 2027 2028 unsigned long cpu_get_elf_hwcap2(void) 2029 { 2030 return upper_32_bits(elf_hwcap); 2031 } 2032 2033 static void __init setup_system_capabilities(void) 2034 { 2035 /* 2036 * We have finalised the system-wide safe feature 2037 * registers, finalise the capabilities that depend 2038 * on it. Also enable all the available capabilities, 2039 * that are not enabled already. 2040 */ 2041 update_cpu_capabilities(SCOPE_SYSTEM); 2042 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2043 } 2044 2045 void __init setup_cpu_features(void) 2046 { 2047 u32 cwg; 2048 2049 setup_system_capabilities(); 2050 mark_const_caps_ready(); 2051 setup_elf_hwcaps(arm64_elf_hwcaps); 2052 2053 if (system_supports_32bit_el0()) 2054 setup_elf_hwcaps(compat_elf_hwcaps); 2055 2056 if (system_uses_ttbr0_pan()) 2057 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2058 2059 sve_setup(); 2060 minsigstksz_setup(); 2061 2062 /* Advertise that we have computed the system capabilities */ 2063 set_sys_caps_initialised(); 2064 2065 /* 2066 * Check for sane CTR_EL0.CWG value. 2067 */ 2068 cwg = cache_type_cwg(); 2069 if (!cwg) 2070 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2071 ARCH_DMA_MINALIGN); 2072 } 2073 2074 static bool __maybe_unused 2075 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 2076 { 2077 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 2078 } 2079 2080 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2081 { 2082 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2083 } 2084 2085 /* 2086 * We emulate only the following system register space. 2087 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2088 * See Table C5-6 System instruction encodings for System register accesses, 2089 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2090 */ 2091 static inline bool __attribute_const__ is_emulated(u32 id) 2092 { 2093 return (sys_reg_Op0(id) == 0x3 && 2094 sys_reg_CRn(id) == 0x0 && 2095 sys_reg_Op1(id) == 0x0 && 2096 (sys_reg_CRm(id) == 0 || 2097 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2098 } 2099 2100 /* 2101 * With CRm == 0, reg should be one of : 2102 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2103 */ 2104 static inline int emulate_id_reg(u32 id, u64 *valp) 2105 { 2106 switch (id) { 2107 case SYS_MIDR_EL1: 2108 *valp = read_cpuid_id(); 2109 break; 2110 case SYS_MPIDR_EL1: 2111 *valp = SYS_MPIDR_SAFE_VAL; 2112 break; 2113 case SYS_REVIDR_EL1: 2114 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2115 *valp = 0; 2116 break; 2117 default: 2118 return -EINVAL; 2119 } 2120 2121 return 0; 2122 } 2123 2124 static int emulate_sys_reg(u32 id, u64 *valp) 2125 { 2126 struct arm64_ftr_reg *regp; 2127 2128 if (!is_emulated(id)) 2129 return -EINVAL; 2130 2131 if (sys_reg_CRm(id) == 0) 2132 return emulate_id_reg(id, valp); 2133 2134 regp = get_arm64_ftr_reg(id); 2135 if (regp) 2136 *valp = arm64_ftr_reg_user_value(regp); 2137 else 2138 /* 2139 * The untracked registers are either IMPLEMENTATION DEFINED 2140 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2141 */ 2142 *valp = 0; 2143 return 0; 2144 } 2145 2146 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2147 { 2148 int rc; 2149 u64 val; 2150 2151 rc = emulate_sys_reg(sys_reg, &val); 2152 if (!rc) { 2153 pt_regs_write_reg(regs, rt, val); 2154 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2155 } 2156 return rc; 2157 } 2158 2159 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2160 { 2161 u32 sys_reg, rt; 2162 2163 /* 2164 * sys_reg values are defined as used in mrs/msr instruction. 2165 * shift the imm value to get the encoding. 2166 */ 2167 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2168 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2169 return do_emulate_mrs(regs, sys_reg, rt); 2170 } 2171 2172 static struct undef_hook mrs_hook = { 2173 .instr_mask = 0xfff00000, 2174 .instr_val = 0xd5300000, 2175 .pstate_mask = PSR_AA32_MODE_MASK, 2176 .pstate_val = PSR_MODE_EL0t, 2177 .fn = emulate_mrs, 2178 }; 2179 2180 static int __init enable_mrs_emulation(void) 2181 { 2182 register_undef_hook(&mrs_hook); 2183 return 0; 2184 } 2185 2186 core_initcall(enable_mrs_emulation); 2187 2188 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2189 char *buf) 2190 { 2191 if (__meltdown_safe) 2192 return sprintf(buf, "Not affected\n"); 2193 2194 if (arm64_kernel_unmapped_at_el0()) 2195 return sprintf(buf, "Mitigation: PTI\n"); 2196 2197 return sprintf(buf, "Vulnerable\n"); 2198 } 2199