1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/sort.h> 69 #include <linux/stop_machine.h> 70 #include <linux/types.h> 71 #include <linux/mm.h> 72 #include <linux/cpu.h> 73 #include <linux/kasan.h> 74 #include <asm/cpu.h> 75 #include <asm/cpufeature.h> 76 #include <asm/cpu_ops.h> 77 #include <asm/fpsimd.h> 78 #include <asm/kvm_host.h> 79 #include <asm/mmu_context.h> 80 #include <asm/mte.h> 81 #include <asm/processor.h> 82 #include <asm/sysreg.h> 83 #include <asm/traps.h> 84 #include <asm/virt.h> 85 86 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 87 static unsigned long elf_hwcap __read_mostly; 88 89 #ifdef CONFIG_COMPAT 90 #define COMPAT_ELF_HWCAP_DEFAULT \ 91 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 92 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 93 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 94 COMPAT_HWCAP_LPAE) 95 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 96 unsigned int compat_elf_hwcap2 __read_mostly; 97 #endif 98 99 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 100 EXPORT_SYMBOL(cpu_hwcaps); 101 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS]; 102 103 /* Need also bit for ARM64_CB_PATCH */ 104 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 105 106 bool arm64_use_ng_mappings = false; 107 EXPORT_SYMBOL(arm64_use_ng_mappings); 108 109 /* 110 * Flag to indicate if we have computed the system wide 111 * capabilities based on the boot time active CPUs. This 112 * will be used to determine if a new booting CPU should 113 * go through the verification process to make sure that it 114 * supports the system capabilities, without using a hotplug 115 * notifier. This is also used to decide if we could use 116 * the fast path for checking constant CPU caps. 117 */ 118 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 119 EXPORT_SYMBOL(arm64_const_caps_ready); 120 static inline void finalize_system_capabilities(void) 121 { 122 static_branch_enable(&arm64_const_caps_ready); 123 } 124 125 void dump_cpu_features(void) 126 { 127 /* file-wide pr_fmt adds "CPU features: " prefix */ 128 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 129 } 130 131 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 132 EXPORT_SYMBOL(cpu_hwcap_keys); 133 134 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 135 { \ 136 .sign = SIGNED, \ 137 .visible = VISIBLE, \ 138 .strict = STRICT, \ 139 .type = TYPE, \ 140 .shift = SHIFT, \ 141 .width = WIDTH, \ 142 .safe_val = SAFE_VAL, \ 143 } 144 145 /* Define a feature with unsigned values */ 146 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 147 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 148 149 /* Define a feature with a signed value */ 150 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 151 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 152 153 #define ARM64_FTR_END \ 154 { \ 155 .width = 0, \ 156 } 157 158 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 159 160 static bool __system_matches_cap(unsigned int n); 161 162 /* 163 * NOTE: Any changes to the visibility of features should be kept in 164 * sync with the documentation of the CPU feature register ABI. 165 */ 166 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 167 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), 169 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), 170 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 171 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 175 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 176 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 177 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 178 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 179 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 180 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 181 ARM64_FTR_END, 182 }; 183 184 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 185 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0), 189 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), 190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), 191 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 192 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), 193 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 194 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 198 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 199 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0), 200 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 201 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0), 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 203 ARM64_FTR_END, 204 }; 205 206 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 209 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0), 210 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0), 211 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0), 212 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0), 213 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 214 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 217 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 218 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 223 ARM64_FTR_END, 224 }; 225 226 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 227 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 230 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI), 232 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 233 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0), 234 ARM64_FTR_END, 235 }; 236 237 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 238 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 239 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 241 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 243 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 245 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 253 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 255 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0), 256 ARM64_FTR_END, 257 }; 258 259 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0), 263 /* 264 * Page size not being supported at Stage-2 is not fatal. You 265 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 266 * your favourite nesting hypervisor. 267 * 268 * There is a small corner case where the hypervisor explicitly 269 * advertises a given granule size at Stage-2 (value 2) on some 270 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 271 * vCPUs. Although this is not forbidden by the architecture, it 272 * indicates that the hypervisor is being silly (or buggy). 273 * 274 * We make no effort to cope with this and pretend that if these 275 * fields are inconsistent across vCPUs, then it isn't worth 276 * trying to bring KVM up. 277 */ 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1), 281 /* 282 * We already refuse to boot CPUs that don't support our configured 283 * page size, so we can only detect mismatches for a page size other 284 * than the one we're currently using. Unfortunately, SoCs like this 285 * exist in the wild so, even though we don't like it, we'll have to go 286 * along with it and treat them as non-strict. 287 */ 288 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 289 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 291 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 293 /* Linux shouldn't care about secure memory */ 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 297 /* 298 * Differing PARange is fine as long as all peripherals and memory are mapped 299 * within the minimum PARange of all CPUs 300 */ 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 316 ARM64_FTR_END, 317 }; 318 319 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0), 325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0), 327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_ctr[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 340 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1), 341 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1), 342 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1), 345 /* 346 * Linux can handle differing I-cache policies. Userspace JITs will 347 * make use of *minLine. 348 * If we have differing I-cache policies, report it as the weakest - VIPT. 349 */ 350 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 351 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0), 352 ARM64_FTR_END, 353 }; 354 355 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 356 .name = "SYS_CTR_EL0", 357 .ftr_bits = ftr_ctr 358 }; 359 360 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 361 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf), 362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0), 365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0), 366 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf), 367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0), 369 ARM64_FTR_END, 370 }; 371 372 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 373 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 378 /* 379 * We can instantiate multiple PMU instances with different levels 380 * of support. 381 */ 382 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 383 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 384 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 385 ARM64_FTR_END, 386 }; 387 388 static const struct arm64_ftr_bits ftr_mvfr2[] = { 389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0), 391 ARM64_FTR_END, 392 }; 393 394 static const struct arm64_ftr_bits ftr_dczid[] = { 395 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), 396 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), 397 ARM64_FTR_END, 398 }; 399 400 static const struct arm64_ftr_bits ftr_id_isar0[] = { 401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0), 402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0), 403 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0), 404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0), 405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0), 406 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0), 407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0), 408 ARM64_FTR_END, 409 }; 410 411 static const struct arm64_ftr_bits ftr_id_isar5[] = { 412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 415 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 416 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 418 ARM64_FTR_END, 419 }; 420 421 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0), 423 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0), 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0), 427 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0), 428 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0), 429 430 /* 431 * SpecSEI = 1 indicates that the PE might generate an SError on an 432 * external abort on speculative read. It is safe to assume that an 433 * SError might be generated than it will not be. Hence it has been 434 * classified as FTR_HIGHER_SAFE. 435 */ 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0), 437 ARM64_FTR_END, 438 }; 439 440 static const struct arm64_ftr_bits ftr_id_isar4[] = { 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0), 449 ARM64_FTR_END, 450 }; 451 452 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), 454 ARM64_FTR_END, 455 }; 456 457 static const struct arm64_ftr_bits ftr_id_isar6[] = { 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0), 465 ARM64_FTR_END, 466 }; 467 468 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0), 475 ARM64_FTR_END, 476 }; 477 478 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0), 487 ARM64_FTR_END, 488 }; 489 490 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0), 493 ARM64_FTR_END, 494 }; 495 496 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 497 /* [31:28] TraceFilt */ 498 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0), 505 ARM64_FTR_END, 506 }; 507 508 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 509 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_zcr[] = { 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 515 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 516 ARM64_FTR_END, 517 }; 518 519 /* 520 * Common ftr bits for a 32bit register with all hidden, strict 521 * attributes, with 4bit feature fields and a default safe value of 522 * 0. Covers the following 32bit registers: 523 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 524 */ 525 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 534 ARM64_FTR_END, 535 }; 536 537 /* Table for a single 32bit feature value */ 538 static const struct arm64_ftr_bits ftr_single32[] = { 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 540 ARM64_FTR_END, 541 }; 542 543 static const struct arm64_ftr_bits ftr_raz[] = { 544 ARM64_FTR_END, 545 }; 546 547 #define ARM64_FTR_REG(id, table) { \ 548 .sys_id = id, \ 549 .reg = &(struct arm64_ftr_reg){ \ 550 .name = #id, \ 551 .ftr_bits = &((table)[0]), \ 552 }} 553 554 static const struct __ftr_reg_entry { 555 u32 sys_id; 556 struct arm64_ftr_reg *reg; 557 } arm64_ftr_regs[] = { 558 559 /* Op1 = 0, CRn = 0, CRm = 1 */ 560 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 561 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 562 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 563 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 564 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 565 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 566 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 567 568 /* Op1 = 0, CRn = 0, CRm = 2 */ 569 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 570 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 571 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 572 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 573 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 574 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 575 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 576 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 577 578 /* Op1 = 0, CRn = 0, CRm = 3 */ 579 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 580 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 581 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 582 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 583 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 584 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 585 586 /* Op1 = 0, CRn = 0, CRm = 4 */ 587 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 588 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1), 589 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0), 590 591 /* Op1 = 0, CRn = 0, CRm = 5 */ 592 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 593 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 594 595 /* Op1 = 0, CRn = 0, CRm = 6 */ 596 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 597 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 598 599 /* Op1 = 0, CRn = 0, CRm = 7 */ 600 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 601 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 602 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 603 604 /* Op1 = 0, CRn = 1, CRm = 2 */ 605 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 606 607 /* Op1 = 3, CRn = 0, CRm = 0 */ 608 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 609 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 610 611 /* Op1 = 3, CRn = 14, CRm = 0 */ 612 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 613 }; 614 615 static int search_cmp_ftr_reg(const void *id, const void *regp) 616 { 617 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 618 } 619 620 /* 621 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 622 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 623 * ascending order of sys_id, we use binary search to find a matching 624 * entry. 625 * 626 * returns - Upon success, matching ftr_reg entry for id. 627 * - NULL on failure. It is upto the caller to decide 628 * the impact of a failure. 629 */ 630 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 631 { 632 const struct __ftr_reg_entry *ret; 633 634 ret = bsearch((const void *)(unsigned long)sys_id, 635 arm64_ftr_regs, 636 ARRAY_SIZE(arm64_ftr_regs), 637 sizeof(arm64_ftr_regs[0]), 638 search_cmp_ftr_reg); 639 if (ret) 640 return ret->reg; 641 return NULL; 642 } 643 644 /* 645 * get_arm64_ftr_reg - Looks up a feature register entry using 646 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 647 * 648 * returns - Upon success, matching ftr_reg entry for id. 649 * - NULL on failure but with an WARN_ON(). 650 */ 651 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 652 { 653 struct arm64_ftr_reg *reg; 654 655 reg = get_arm64_ftr_reg_nowarn(sys_id); 656 657 /* 658 * Requesting a non-existent register search is an error. Warn 659 * and let the caller handle it. 660 */ 661 WARN_ON(!reg); 662 return reg; 663 } 664 665 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 666 s64 ftr_val) 667 { 668 u64 mask = arm64_ftr_mask(ftrp); 669 670 reg &= ~mask; 671 reg |= (ftr_val << ftrp->shift) & mask; 672 return reg; 673 } 674 675 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 676 s64 cur) 677 { 678 s64 ret = 0; 679 680 switch (ftrp->type) { 681 case FTR_EXACT: 682 ret = ftrp->safe_val; 683 break; 684 case FTR_LOWER_SAFE: 685 ret = new < cur ? new : cur; 686 break; 687 case FTR_HIGHER_OR_ZERO_SAFE: 688 if (!cur || !new) 689 break; 690 fallthrough; 691 case FTR_HIGHER_SAFE: 692 ret = new > cur ? new : cur; 693 break; 694 default: 695 BUG(); 696 } 697 698 return ret; 699 } 700 701 static void __init sort_ftr_regs(void) 702 { 703 unsigned int i; 704 705 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 706 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 707 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 708 unsigned int j = 0; 709 710 /* 711 * Features here must be sorted in descending order with respect 712 * to their shift values and should not overlap with each other. 713 */ 714 for (; ftr_bits->width != 0; ftr_bits++, j++) { 715 unsigned int width = ftr_reg->ftr_bits[j].width; 716 unsigned int shift = ftr_reg->ftr_bits[j].shift; 717 unsigned int prev_shift; 718 719 WARN((shift + width) > 64, 720 "%s has invalid feature at shift %d\n", 721 ftr_reg->name, shift); 722 723 /* 724 * Skip the first feature. There is nothing to 725 * compare against for now. 726 */ 727 if (j == 0) 728 continue; 729 730 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 731 WARN((shift + width) > prev_shift, 732 "%s has feature overlap at shift %d\n", 733 ftr_reg->name, shift); 734 } 735 736 /* 737 * Skip the first register. There is nothing to 738 * compare against for now. 739 */ 740 if (i == 0) 741 continue; 742 /* 743 * Registers here must be sorted in ascending order with respect 744 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 745 * to work correctly. 746 */ 747 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 748 } 749 } 750 751 /* 752 * Initialise the CPU feature register from Boot CPU values. 753 * Also initiliases the strict_mask for the register. 754 * Any bits that are not covered by an arm64_ftr_bits entry are considered 755 * RES0 for the system-wide value, and must strictly match. 756 */ 757 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 758 { 759 u64 val = 0; 760 u64 strict_mask = ~0x0ULL; 761 u64 user_mask = 0; 762 u64 valid_mask = 0; 763 764 const struct arm64_ftr_bits *ftrp; 765 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 766 767 if (!reg) 768 return; 769 770 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 771 u64 ftr_mask = arm64_ftr_mask(ftrp); 772 s64 ftr_new = arm64_ftr_value(ftrp, new); 773 774 val = arm64_ftr_set_value(ftrp, val, ftr_new); 775 776 valid_mask |= ftr_mask; 777 if (!ftrp->strict) 778 strict_mask &= ~ftr_mask; 779 if (ftrp->visible) 780 user_mask |= ftr_mask; 781 else 782 reg->user_val = arm64_ftr_set_value(ftrp, 783 reg->user_val, 784 ftrp->safe_val); 785 } 786 787 val &= valid_mask; 788 789 reg->sys_val = val; 790 reg->strict_mask = strict_mask; 791 reg->user_mask = user_mask; 792 } 793 794 extern const struct arm64_cpu_capabilities arm64_errata[]; 795 static const struct arm64_cpu_capabilities arm64_features[]; 796 797 static void __init 798 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 799 { 800 for (; caps->matches; caps++) { 801 if (WARN(caps->capability >= ARM64_NCAPS, 802 "Invalid capability %d\n", caps->capability)) 803 continue; 804 if (WARN(cpu_hwcaps_ptrs[caps->capability], 805 "Duplicate entry for capability %d\n", 806 caps->capability)) 807 continue; 808 cpu_hwcaps_ptrs[caps->capability] = caps; 809 } 810 } 811 812 static void __init init_cpu_hwcaps_indirect_list(void) 813 { 814 init_cpu_hwcaps_indirect_list_from_array(arm64_features); 815 init_cpu_hwcaps_indirect_list_from_array(arm64_errata); 816 } 817 818 static void __init setup_boot_cpu_capabilities(void); 819 820 void __init init_cpu_features(struct cpuinfo_arm64 *info) 821 { 822 /* Before we start using the tables, make sure it is sorted */ 823 sort_ftr_regs(); 824 825 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 826 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 827 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 828 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 829 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 830 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 831 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 832 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 833 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 834 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 835 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 836 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 837 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 838 839 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 840 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 841 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 842 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 843 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 844 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 845 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 846 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 847 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 848 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 849 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 850 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 851 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 852 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 853 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 854 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 855 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 856 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 857 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 858 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 859 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 860 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 861 } 862 863 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 864 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 865 sve_init_vq_map(); 866 } 867 868 /* 869 * Initialize the indirect array of CPU hwcaps capabilities pointers 870 * before we handle the boot CPU below. 871 */ 872 init_cpu_hwcaps_indirect_list(); 873 874 /* 875 * Detect and enable early CPU capabilities based on the boot CPU, 876 * after we have initialised the CPU feature infrastructure. 877 */ 878 setup_boot_cpu_capabilities(); 879 } 880 881 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 882 { 883 const struct arm64_ftr_bits *ftrp; 884 885 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 886 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 887 s64 ftr_new = arm64_ftr_value(ftrp, new); 888 889 if (ftr_cur == ftr_new) 890 continue; 891 /* Find a safe value */ 892 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 893 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 894 } 895 896 } 897 898 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 899 { 900 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 901 902 if (!regp) 903 return 0; 904 905 update_cpu_ftr_reg(regp, val); 906 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 907 return 0; 908 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 909 regp->name, boot, cpu, val); 910 return 1; 911 } 912 913 static void relax_cpu_ftr_reg(u32 sys_id, int field) 914 { 915 const struct arm64_ftr_bits *ftrp; 916 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 917 918 if (!regp) 919 return; 920 921 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 922 if (ftrp->shift == field) { 923 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 924 break; 925 } 926 } 927 928 /* Bogus field? */ 929 WARN_ON(!ftrp->width); 930 } 931 932 static int update_32bit_cpu_features(int cpu, struct cpuinfo_arm64 *info, 933 struct cpuinfo_arm64 *boot) 934 { 935 int taint = 0; 936 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 937 938 /* 939 * If we don't have AArch32 at all then skip the checks entirely 940 * as the register values may be UNKNOWN and we're not going to be 941 * using them for anything. 942 */ 943 if (!id_aa64pfr0_32bit_el0(pfr0)) 944 return taint; 945 946 /* 947 * If we don't have AArch32 at EL1, then relax the strictness of 948 * EL1-dependent register fields to avoid spurious sanity check fails. 949 */ 950 if (!id_aa64pfr0_32bit_el1(pfr0)) { 951 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT); 952 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT); 953 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT); 954 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT); 955 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT); 956 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT); 957 } 958 959 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 960 info->reg_id_dfr0, boot->reg_id_dfr0); 961 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 962 info->reg_id_dfr1, boot->reg_id_dfr1); 963 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 964 info->reg_id_isar0, boot->reg_id_isar0); 965 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 966 info->reg_id_isar1, boot->reg_id_isar1); 967 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 968 info->reg_id_isar2, boot->reg_id_isar2); 969 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 970 info->reg_id_isar3, boot->reg_id_isar3); 971 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 972 info->reg_id_isar4, boot->reg_id_isar4); 973 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 974 info->reg_id_isar5, boot->reg_id_isar5); 975 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 976 info->reg_id_isar6, boot->reg_id_isar6); 977 978 /* 979 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 980 * ACTLR formats could differ across CPUs and therefore would have to 981 * be trapped for virtualization anyway. 982 */ 983 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 984 info->reg_id_mmfr0, boot->reg_id_mmfr0); 985 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 986 info->reg_id_mmfr1, boot->reg_id_mmfr1); 987 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 988 info->reg_id_mmfr2, boot->reg_id_mmfr2); 989 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 990 info->reg_id_mmfr3, boot->reg_id_mmfr3); 991 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 992 info->reg_id_mmfr4, boot->reg_id_mmfr4); 993 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 994 info->reg_id_mmfr5, boot->reg_id_mmfr5); 995 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 996 info->reg_id_pfr0, boot->reg_id_pfr0); 997 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 998 info->reg_id_pfr1, boot->reg_id_pfr1); 999 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1000 info->reg_id_pfr2, boot->reg_id_pfr2); 1001 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1002 info->reg_mvfr0, boot->reg_mvfr0); 1003 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1004 info->reg_mvfr1, boot->reg_mvfr1); 1005 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1006 info->reg_mvfr2, boot->reg_mvfr2); 1007 1008 return taint; 1009 } 1010 1011 /* 1012 * Update system wide CPU feature registers with the values from a 1013 * non-boot CPU. Also performs SANITY checks to make sure that there 1014 * aren't any insane variations from that of the boot CPU. 1015 */ 1016 void update_cpu_features(int cpu, 1017 struct cpuinfo_arm64 *info, 1018 struct cpuinfo_arm64 *boot) 1019 { 1020 int taint = 0; 1021 1022 /* 1023 * The kernel can handle differing I-cache policies, but otherwise 1024 * caches should look identical. Userspace JITs will make use of 1025 * *minLine. 1026 */ 1027 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1028 info->reg_ctr, boot->reg_ctr); 1029 1030 /* 1031 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1032 * could result in too much or too little memory being zeroed if a 1033 * process is preempted and migrated between CPUs. 1034 */ 1035 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1036 info->reg_dczid, boot->reg_dczid); 1037 1038 /* If different, timekeeping will be broken (especially with KVM) */ 1039 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1040 info->reg_cntfrq, boot->reg_cntfrq); 1041 1042 /* 1043 * The kernel uses self-hosted debug features and expects CPUs to 1044 * support identical debug features. We presently need CTX_CMPs, WRPs, 1045 * and BRPs to be identical. 1046 * ID_AA64DFR1 is currently RES0. 1047 */ 1048 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1049 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1050 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1051 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1052 /* 1053 * Even in big.LITTLE, processors should be identical instruction-set 1054 * wise. 1055 */ 1056 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1057 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1058 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1059 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1060 1061 /* 1062 * Differing PARange support is fine as long as all peripherals and 1063 * memory are mapped within the minimum PARange of all CPUs. 1064 * Linux should not care about secure memory. 1065 */ 1066 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1067 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1068 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1069 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1070 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1071 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1072 1073 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1074 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1075 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1076 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1077 1078 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1079 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1080 1081 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 1082 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 1083 info->reg_zcr, boot->reg_zcr); 1084 1085 /* Probe vector lengths, unless we already gave up on SVE */ 1086 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 1087 !system_capabilities_finalized()) 1088 sve_update_vq_map(); 1089 } 1090 1091 /* 1092 * This relies on a sanitised view of the AArch64 ID registers 1093 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1094 */ 1095 taint |= update_32bit_cpu_features(cpu, info, boot); 1096 1097 /* 1098 * Mismatched CPU features are a recipe for disaster. Don't even 1099 * pretend to support them. 1100 */ 1101 if (taint) { 1102 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1103 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1104 } 1105 } 1106 1107 u64 read_sanitised_ftr_reg(u32 id) 1108 { 1109 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1110 1111 if (!regp) 1112 return 0; 1113 return regp->sys_val; 1114 } 1115 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1116 1117 #define read_sysreg_case(r) \ 1118 case r: return read_sysreg_s(r) 1119 1120 /* 1121 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1122 * Read the system register on the current CPU 1123 */ 1124 static u64 __read_sysreg_by_encoding(u32 sys_id) 1125 { 1126 switch (sys_id) { 1127 read_sysreg_case(SYS_ID_PFR0_EL1); 1128 read_sysreg_case(SYS_ID_PFR1_EL1); 1129 read_sysreg_case(SYS_ID_PFR2_EL1); 1130 read_sysreg_case(SYS_ID_DFR0_EL1); 1131 read_sysreg_case(SYS_ID_DFR1_EL1); 1132 read_sysreg_case(SYS_ID_MMFR0_EL1); 1133 read_sysreg_case(SYS_ID_MMFR1_EL1); 1134 read_sysreg_case(SYS_ID_MMFR2_EL1); 1135 read_sysreg_case(SYS_ID_MMFR3_EL1); 1136 read_sysreg_case(SYS_ID_MMFR4_EL1); 1137 read_sysreg_case(SYS_ID_MMFR5_EL1); 1138 read_sysreg_case(SYS_ID_ISAR0_EL1); 1139 read_sysreg_case(SYS_ID_ISAR1_EL1); 1140 read_sysreg_case(SYS_ID_ISAR2_EL1); 1141 read_sysreg_case(SYS_ID_ISAR3_EL1); 1142 read_sysreg_case(SYS_ID_ISAR4_EL1); 1143 read_sysreg_case(SYS_ID_ISAR5_EL1); 1144 read_sysreg_case(SYS_ID_ISAR6_EL1); 1145 read_sysreg_case(SYS_MVFR0_EL1); 1146 read_sysreg_case(SYS_MVFR1_EL1); 1147 read_sysreg_case(SYS_MVFR2_EL1); 1148 1149 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1150 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1151 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1152 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1153 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1154 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1155 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1156 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1157 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1158 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1159 1160 read_sysreg_case(SYS_CNTFRQ_EL0); 1161 read_sysreg_case(SYS_CTR_EL0); 1162 read_sysreg_case(SYS_DCZID_EL0); 1163 1164 default: 1165 BUG(); 1166 return 0; 1167 } 1168 } 1169 1170 #include <linux/irqchip/arm-gic-v3.h> 1171 1172 static bool 1173 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1174 { 1175 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 1176 1177 return val >= entry->min_field_value; 1178 } 1179 1180 static bool 1181 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1182 { 1183 u64 val; 1184 1185 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1186 if (scope == SCOPE_SYSTEM) 1187 val = read_sanitised_ftr_reg(entry->sys_reg); 1188 else 1189 val = __read_sysreg_by_encoding(entry->sys_reg); 1190 1191 return feature_matches(val, entry); 1192 } 1193 1194 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1195 { 1196 bool has_sre; 1197 1198 if (!has_cpuid_feature(entry, scope)) 1199 return false; 1200 1201 has_sre = gic_enable_sre(); 1202 if (!has_sre) 1203 pr_warn_once("%s present but disabled by higher exception level\n", 1204 entry->desc); 1205 1206 return has_sre; 1207 } 1208 1209 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 1210 { 1211 u32 midr = read_cpuid_id(); 1212 1213 /* Cavium ThunderX pass 1.x and 2.x */ 1214 return midr_is_cpu_model_range(midr, MIDR_THUNDERX, 1215 MIDR_CPU_VAR_REV(0, 0), 1216 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 1217 } 1218 1219 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 1220 { 1221 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1222 1223 return cpuid_feature_extract_signed_field(pfr0, 1224 ID_AA64PFR0_FP_SHIFT) < 0; 1225 } 1226 1227 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1228 int scope) 1229 { 1230 u64 ctr; 1231 1232 if (scope == SCOPE_SYSTEM) 1233 ctr = arm64_ftr_reg_ctrel0.sys_val; 1234 else 1235 ctr = read_cpuid_effective_cachetype(); 1236 1237 return ctr & BIT(CTR_IDC_SHIFT); 1238 } 1239 1240 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1241 { 1242 /* 1243 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1244 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1245 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1246 * value. 1247 */ 1248 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT))) 1249 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1250 } 1251 1252 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1253 int scope) 1254 { 1255 u64 ctr; 1256 1257 if (scope == SCOPE_SYSTEM) 1258 ctr = arm64_ftr_reg_ctrel0.sys_val; 1259 else 1260 ctr = read_cpuid_cachetype(); 1261 1262 return ctr & BIT(CTR_DIC_SHIFT); 1263 } 1264 1265 static bool __maybe_unused 1266 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1267 { 1268 /* 1269 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1270 * may share TLB entries with a CPU stuck in the crashed 1271 * kernel. 1272 */ 1273 if (is_kdump_kernel()) 1274 return false; 1275 1276 return has_cpuid_feature(entry, scope); 1277 } 1278 1279 /* 1280 * This check is triggered during the early boot before the cpufeature 1281 * is initialised. Checking the status on the local CPU allows the boot 1282 * CPU to detect the need for non-global mappings and thus avoiding a 1283 * pagetable re-write after all the CPUs are booted. This check will be 1284 * anyway run on individual CPUs, allowing us to get the consistent 1285 * state once the SMP CPUs are up and thus make the switch to non-global 1286 * mappings if required. 1287 */ 1288 bool kaslr_requires_kpti(void) 1289 { 1290 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 1291 return false; 1292 1293 /* 1294 * E0PD does a similar job to KPTI so can be used instead 1295 * where available. 1296 */ 1297 if (IS_ENABLED(CONFIG_ARM64_E0PD)) { 1298 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1); 1299 if (cpuid_feature_extract_unsigned_field(mmfr2, 1300 ID_AA64MMFR2_E0PD_SHIFT)) 1301 return false; 1302 } 1303 1304 /* 1305 * Systems affected by Cavium erratum 24756 are incompatible 1306 * with KPTI. 1307 */ 1308 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) { 1309 extern const struct midr_range cavium_erratum_27456_cpus[]; 1310 1311 if (is_midr_in_range_list(read_cpuid_id(), 1312 cavium_erratum_27456_cpus)) 1313 return false; 1314 } 1315 1316 return kaslr_offset() > 0; 1317 } 1318 1319 static bool __meltdown_safe = true; 1320 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1321 1322 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1323 int scope) 1324 { 1325 /* List of CPUs that are not vulnerable and don't need KPTI */ 1326 static const struct midr_range kpti_safe_list[] = { 1327 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1328 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1329 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1330 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1331 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1332 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1333 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1334 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1335 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1336 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1337 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1338 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1339 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1340 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1341 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1342 { /* sentinel */ } 1343 }; 1344 char const *str = "kpti command line option"; 1345 bool meltdown_safe; 1346 1347 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1348 1349 /* Defer to CPU feature registers */ 1350 if (has_cpuid_feature(entry, scope)) 1351 meltdown_safe = true; 1352 1353 if (!meltdown_safe) 1354 __meltdown_safe = false; 1355 1356 /* 1357 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1358 * ThunderX leads to apparent I-cache corruption of kernel text, which 1359 * ends as well as you might imagine. Don't even try. 1360 */ 1361 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1362 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1363 __kpti_forced = -1; 1364 } 1365 1366 /* Useful for KASLR robustness */ 1367 if (kaslr_requires_kpti()) { 1368 if (!__kpti_forced) { 1369 str = "KASLR"; 1370 __kpti_forced = 1; 1371 } 1372 } 1373 1374 if (cpu_mitigations_off() && !__kpti_forced) { 1375 str = "mitigations=off"; 1376 __kpti_forced = -1; 1377 } 1378 1379 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1380 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1381 return false; 1382 } 1383 1384 /* Forced? */ 1385 if (__kpti_forced) { 1386 pr_info_once("kernel page table isolation forced %s by %s\n", 1387 __kpti_forced > 0 ? "ON" : "OFF", str); 1388 return __kpti_forced > 0; 1389 } 1390 1391 return !meltdown_safe; 1392 } 1393 1394 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1395 static void 1396 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1397 { 1398 typedef void (kpti_remap_fn)(int, int, phys_addr_t); 1399 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1400 kpti_remap_fn *remap_fn; 1401 1402 int cpu = smp_processor_id(); 1403 1404 /* 1405 * We don't need to rewrite the page-tables if either we've done 1406 * it already or we have KASLR enabled and therefore have not 1407 * created any global mappings at all. 1408 */ 1409 if (arm64_use_ng_mappings) 1410 return; 1411 1412 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1413 1414 cpu_install_idmap(); 1415 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir)); 1416 cpu_uninstall_idmap(); 1417 1418 if (!cpu) 1419 arm64_use_ng_mappings = true; 1420 1421 return; 1422 } 1423 #else 1424 static void 1425 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) 1426 { 1427 } 1428 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1429 1430 static int __init parse_kpti(char *str) 1431 { 1432 bool enabled; 1433 int ret = strtobool(str, &enabled); 1434 1435 if (ret) 1436 return ret; 1437 1438 __kpti_forced = enabled ? 1 : -1; 1439 return 0; 1440 } 1441 early_param("kpti", parse_kpti); 1442 1443 #ifdef CONFIG_ARM64_HW_AFDBM 1444 static inline void __cpu_enable_hw_dbm(void) 1445 { 1446 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 1447 1448 write_sysreg(tcr, tcr_el1); 1449 isb(); 1450 local_flush_tlb_all(); 1451 } 1452 1453 static bool cpu_has_broken_dbm(void) 1454 { 1455 /* List of CPUs which have broken DBM support. */ 1456 static const struct midr_range cpus[] = { 1457 #ifdef CONFIG_ARM64_ERRATUM_1024718 1458 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0 1459 /* Kryo4xx Silver (rdpe => r1p0) */ 1460 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1461 #endif 1462 {}, 1463 }; 1464 1465 return is_midr_in_range_list(read_cpuid_id(), cpus); 1466 } 1467 1468 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 1469 { 1470 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 1471 !cpu_has_broken_dbm(); 1472 } 1473 1474 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 1475 { 1476 if (cpu_can_use_dbm(cap)) 1477 __cpu_enable_hw_dbm(); 1478 } 1479 1480 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 1481 int __unused) 1482 { 1483 static bool detected = false; 1484 /* 1485 * DBM is a non-conflicting feature. i.e, the kernel can safely 1486 * run a mix of CPUs with and without the feature. So, we 1487 * unconditionally enable the capability to allow any late CPU 1488 * to use the feature. We only enable the control bits on the 1489 * CPU, if it actually supports. 1490 * 1491 * We have to make sure we print the "feature" detection only 1492 * when at least one CPU actually uses it. So check if this CPU 1493 * can actually use it and print the message exactly once. 1494 * 1495 * This is safe as all CPUs (including secondary CPUs - due to the 1496 * LOCAL_CPU scope - and the hotplugged CPUs - via verification) 1497 * goes through the "matches" check exactly once. Also if a CPU 1498 * matches the criteria, it is guaranteed that the CPU will turn 1499 * the DBM on, as the capability is unconditionally enabled. 1500 */ 1501 if (!detected && cpu_can_use_dbm(cap)) { 1502 detected = true; 1503 pr_info("detected: Hardware dirty bit management\n"); 1504 } 1505 1506 return true; 1507 } 1508 1509 #endif 1510 1511 #ifdef CONFIG_ARM64_AMU_EXTN 1512 1513 /* 1514 * The "amu_cpus" cpumask only signals that the CPU implementation for the 1515 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 1516 * information regarding all the events that it supports. When a CPU bit is 1517 * set in the cpumask, the user of this feature can only rely on the presence 1518 * of the 4 fixed counters for that CPU. But this does not guarantee that the 1519 * counters are enabled or access to these counters is enabled by code 1520 * executed at higher exception levels (firmware). 1521 */ 1522 static struct cpumask amu_cpus __read_mostly; 1523 1524 bool cpu_has_amu_feat(int cpu) 1525 { 1526 return cpumask_test_cpu(cpu, &amu_cpus); 1527 } 1528 1529 int get_cpu_with_amu_feat(void) 1530 { 1531 return cpumask_any(&amu_cpus); 1532 } 1533 1534 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 1535 { 1536 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 1537 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", 1538 smp_processor_id()); 1539 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 1540 update_freq_counters_refs(); 1541 } 1542 } 1543 1544 static bool has_amu(const struct arm64_cpu_capabilities *cap, 1545 int __unused) 1546 { 1547 /* 1548 * The AMU extension is a non-conflicting feature: the kernel can 1549 * safely run a mix of CPUs with and without support for the 1550 * activity monitors extension. Therefore, unconditionally enable 1551 * the capability to allow any late CPU to use the feature. 1552 * 1553 * With this feature unconditionally enabled, the cpu_enable 1554 * function will be called for all CPUs that match the criteria, 1555 * including secondary and hotplugged, marking this feature as 1556 * present on that respective CPU. The enable function will also 1557 * print a detection message. 1558 */ 1559 1560 return true; 1561 } 1562 #else 1563 int get_cpu_with_amu_feat(void) 1564 { 1565 return nr_cpu_ids; 1566 } 1567 #endif 1568 1569 #ifdef CONFIG_ARM64_VHE 1570 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 1571 { 1572 return is_kernel_in_hyp_mode(); 1573 } 1574 1575 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 1576 { 1577 /* 1578 * Copy register values that aren't redirected by hardware. 1579 * 1580 * Before code patching, we only set tpidr_el1, all CPUs need to copy 1581 * this value to tpidr_el2 before we patch the code. Once we've done 1582 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 1583 * do anything here. 1584 */ 1585 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 1586 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 1587 } 1588 #endif 1589 1590 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused) 1591 { 1592 u64 val = read_sysreg_s(SYS_CLIDR_EL1); 1593 1594 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */ 1595 WARN_ON(val & (7 << 27 | 7 << 21)); 1596 } 1597 1598 #ifdef CONFIG_ARM64_PAN 1599 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 1600 { 1601 /* 1602 * We modify PSTATE. This won't work from irq context as the PSTATE 1603 * is discarded once we return from the exception. 1604 */ 1605 WARN_ON_ONCE(in_interrupt()); 1606 1607 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 1608 set_pstate_pan(1); 1609 } 1610 #endif /* CONFIG_ARM64_PAN */ 1611 1612 #ifdef CONFIG_ARM64_RAS_EXTN 1613 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 1614 { 1615 /* Firmware may have left a deferred SError in this register. */ 1616 write_sysreg_s(0, SYS_DISR_EL1); 1617 } 1618 #endif /* CONFIG_ARM64_RAS_EXTN */ 1619 1620 #ifdef CONFIG_ARM64_PTR_AUTH 1621 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 1622 { 1623 int boot_val, sec_val; 1624 1625 /* We don't expect to be called with SCOPE_SYSTEM */ 1626 WARN_ON(scope == SCOPE_SYSTEM); 1627 /* 1628 * The ptr-auth feature levels are not intercompatible with lower 1629 * levels. Hence we must match ptr-auth feature level of the secondary 1630 * CPUs with that of the boot CPU. The level of boot cpu is fetched 1631 * from the sanitised register whereas direct register read is done for 1632 * the secondary CPUs. 1633 * The sanitised feature state is guaranteed to match that of the 1634 * boot CPU as a mismatched secondary CPU is parked before it gets 1635 * a chance to update the state, with the capability. 1636 */ 1637 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 1638 entry->field_pos, entry->sign); 1639 if (scope & SCOPE_BOOT_CPU) 1640 return boot_val >= entry->min_field_value; 1641 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 1642 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 1643 entry->field_pos, entry->sign); 1644 return sec_val == boot_val; 1645 } 1646 1647 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 1648 int scope) 1649 { 1650 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) || 1651 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 1652 } 1653 1654 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 1655 int __unused) 1656 { 1657 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 1658 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 1659 } 1660 #endif /* CONFIG_ARM64_PTR_AUTH */ 1661 1662 #ifdef CONFIG_ARM64_E0PD 1663 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 1664 { 1665 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 1666 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 1667 } 1668 #endif /* CONFIG_ARM64_E0PD */ 1669 1670 #ifdef CONFIG_ARM64_PSEUDO_NMI 1671 static bool enable_pseudo_nmi; 1672 1673 static int __init early_enable_pseudo_nmi(char *p) 1674 { 1675 return strtobool(p, &enable_pseudo_nmi); 1676 } 1677 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1678 1679 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 1680 int scope) 1681 { 1682 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope); 1683 } 1684 #endif 1685 1686 #ifdef CONFIG_ARM64_BTI 1687 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 1688 { 1689 /* 1690 * Use of X16/X17 for tail-calls and trampolines that jump to 1691 * function entry points using BR is a requirement for 1692 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 1693 * So, be strict and forbid other BRs using other registers to 1694 * jump onto a PACIxSP instruction: 1695 */ 1696 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 1697 isb(); 1698 } 1699 #endif /* CONFIG_ARM64_BTI */ 1700 1701 #ifdef CONFIG_ARM64_MTE 1702 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 1703 { 1704 /* 1705 * Clear the tags in the zero page. This needs to be done via the 1706 * linear map which has the Tagged attribute. 1707 */ 1708 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags)) 1709 mte_clear_page_tags(lm_alias(empty_zero_page)); 1710 1711 kasan_init_hw_tags_cpu(); 1712 } 1713 #endif /* CONFIG_ARM64_MTE */ 1714 1715 #ifdef CONFIG_KVM 1716 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 1717 { 1718 if (kvm_get_mode() != KVM_MODE_PROTECTED) 1719 return false; 1720 1721 if (is_kernel_in_hyp_mode()) { 1722 pr_warn("Protected KVM not available with VHE\n"); 1723 return false; 1724 } 1725 1726 return true; 1727 } 1728 #endif /* CONFIG_KVM */ 1729 1730 /* Internal helper functions to match cpu capability type */ 1731 static bool 1732 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 1733 { 1734 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 1735 } 1736 1737 static bool 1738 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 1739 { 1740 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 1741 } 1742 1743 static bool 1744 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 1745 { 1746 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 1747 } 1748 1749 static const struct arm64_cpu_capabilities arm64_features[] = { 1750 { 1751 .desc = "GIC system register CPU interface", 1752 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 1753 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1754 .matches = has_useable_gicv3_cpuif, 1755 .sys_reg = SYS_ID_AA64PFR0_EL1, 1756 .field_pos = ID_AA64PFR0_GIC_SHIFT, 1757 .sign = FTR_UNSIGNED, 1758 .min_field_value = 1, 1759 }, 1760 #ifdef CONFIG_ARM64_PAN 1761 { 1762 .desc = "Privileged Access Never", 1763 .capability = ARM64_HAS_PAN, 1764 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1765 .matches = has_cpuid_feature, 1766 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1767 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 1768 .sign = FTR_UNSIGNED, 1769 .min_field_value = 1, 1770 .cpu_enable = cpu_enable_pan, 1771 }, 1772 #endif /* CONFIG_ARM64_PAN */ 1773 #ifdef CONFIG_ARM64_LSE_ATOMICS 1774 { 1775 .desc = "LSE atomic instructions", 1776 .capability = ARM64_HAS_LSE_ATOMICS, 1777 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1778 .matches = has_cpuid_feature, 1779 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1780 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 1781 .sign = FTR_UNSIGNED, 1782 .min_field_value = 2, 1783 }, 1784 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 1785 { 1786 .desc = "Software prefetching using PRFM", 1787 .capability = ARM64_HAS_NO_HW_PREFETCH, 1788 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1789 .matches = has_no_hw_prefetch, 1790 }, 1791 #ifdef CONFIG_ARM64_VHE 1792 { 1793 .desc = "Virtualization Host Extensions", 1794 .capability = ARM64_HAS_VIRT_HOST_EXTN, 1795 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 1796 .matches = runs_at_el2, 1797 .cpu_enable = cpu_copy_el2regs, 1798 }, 1799 #endif /* CONFIG_ARM64_VHE */ 1800 { 1801 .desc = "32-bit EL0 Support", 1802 .capability = ARM64_HAS_32BIT_EL0, 1803 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1804 .matches = has_cpuid_feature, 1805 .sys_reg = SYS_ID_AA64PFR0_EL1, 1806 .sign = FTR_UNSIGNED, 1807 .field_pos = ID_AA64PFR0_EL0_SHIFT, 1808 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 1809 }, 1810 #ifdef CONFIG_KVM 1811 { 1812 .desc = "32-bit EL1 Support", 1813 .capability = ARM64_HAS_32BIT_EL1, 1814 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1815 .matches = has_cpuid_feature, 1816 .sys_reg = SYS_ID_AA64PFR0_EL1, 1817 .sign = FTR_UNSIGNED, 1818 .field_pos = ID_AA64PFR0_EL1_SHIFT, 1819 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT, 1820 }, 1821 { 1822 .desc = "Protected KVM", 1823 .capability = ARM64_KVM_PROTECTED_MODE, 1824 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1825 .matches = is_kvm_protected_mode, 1826 }, 1827 #endif 1828 { 1829 .desc = "Kernel page table isolation (KPTI)", 1830 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1831 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1832 /* 1833 * The ID feature fields below are used to indicate that 1834 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 1835 * more details. 1836 */ 1837 .sys_reg = SYS_ID_AA64PFR0_EL1, 1838 .field_pos = ID_AA64PFR0_CSV3_SHIFT, 1839 .min_field_value = 1, 1840 .matches = unmap_kernel_at_el0, 1841 .cpu_enable = kpti_install_ng_mappings, 1842 }, 1843 { 1844 /* FP/SIMD is not implemented */ 1845 .capability = ARM64_HAS_NO_FPSIMD, 1846 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 1847 .min_field_value = 0, 1848 .matches = has_no_fpsimd, 1849 }, 1850 #ifdef CONFIG_ARM64_PMEM 1851 { 1852 .desc = "Data cache clean to Point of Persistence", 1853 .capability = ARM64_HAS_DCPOP, 1854 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1855 .matches = has_cpuid_feature, 1856 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1857 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1858 .min_field_value = 1, 1859 }, 1860 { 1861 .desc = "Data cache clean to Point of Deep Persistence", 1862 .capability = ARM64_HAS_DCPODP, 1863 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1864 .matches = has_cpuid_feature, 1865 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1866 .sign = FTR_UNSIGNED, 1867 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1868 .min_field_value = 2, 1869 }, 1870 #endif 1871 #ifdef CONFIG_ARM64_SVE 1872 { 1873 .desc = "Scalable Vector Extension", 1874 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1875 .capability = ARM64_SVE, 1876 .sys_reg = SYS_ID_AA64PFR0_EL1, 1877 .sign = FTR_UNSIGNED, 1878 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1879 .min_field_value = ID_AA64PFR0_SVE, 1880 .matches = has_cpuid_feature, 1881 .cpu_enable = sve_kernel_enable, 1882 }, 1883 #endif /* CONFIG_ARM64_SVE */ 1884 #ifdef CONFIG_ARM64_RAS_EXTN 1885 { 1886 .desc = "RAS Extension Support", 1887 .capability = ARM64_HAS_RAS_EXTN, 1888 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1889 .matches = has_cpuid_feature, 1890 .sys_reg = SYS_ID_AA64PFR0_EL1, 1891 .sign = FTR_UNSIGNED, 1892 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1893 .min_field_value = ID_AA64PFR0_RAS_V1, 1894 .cpu_enable = cpu_clear_disr, 1895 }, 1896 #endif /* CONFIG_ARM64_RAS_EXTN */ 1897 #ifdef CONFIG_ARM64_AMU_EXTN 1898 { 1899 /* 1900 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. 1901 * Therefore, don't provide .desc as we don't want the detection 1902 * message to be shown until at least one CPU is detected to 1903 * support the feature. 1904 */ 1905 .capability = ARM64_HAS_AMU_EXTN, 1906 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1907 .matches = has_amu, 1908 .sys_reg = SYS_ID_AA64PFR0_EL1, 1909 .sign = FTR_UNSIGNED, 1910 .field_pos = ID_AA64PFR0_AMU_SHIFT, 1911 .min_field_value = ID_AA64PFR0_AMU, 1912 .cpu_enable = cpu_amu_enable, 1913 }, 1914 #endif /* CONFIG_ARM64_AMU_EXTN */ 1915 { 1916 .desc = "Data cache clean to the PoU not required for I/D coherence", 1917 .capability = ARM64_HAS_CACHE_IDC, 1918 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1919 .matches = has_cache_idc, 1920 .cpu_enable = cpu_emulate_effective_ctr, 1921 }, 1922 { 1923 .desc = "Instruction cache invalidation not required for I/D coherence", 1924 .capability = ARM64_HAS_CACHE_DIC, 1925 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1926 .matches = has_cache_dic, 1927 }, 1928 { 1929 .desc = "Stage-2 Force Write-Back", 1930 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1931 .capability = ARM64_HAS_STAGE2_FWB, 1932 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1933 .sign = FTR_UNSIGNED, 1934 .field_pos = ID_AA64MMFR2_FWB_SHIFT, 1935 .min_field_value = 1, 1936 .matches = has_cpuid_feature, 1937 .cpu_enable = cpu_has_fwb, 1938 }, 1939 { 1940 .desc = "ARMv8.4 Translation Table Level", 1941 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1942 .capability = ARM64_HAS_ARMv8_4_TTL, 1943 .sys_reg = SYS_ID_AA64MMFR2_EL1, 1944 .sign = FTR_UNSIGNED, 1945 .field_pos = ID_AA64MMFR2_TTL_SHIFT, 1946 .min_field_value = 1, 1947 .matches = has_cpuid_feature, 1948 }, 1949 { 1950 .desc = "TLB range maintenance instructions", 1951 .capability = ARM64_HAS_TLB_RANGE, 1952 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1953 .matches = has_cpuid_feature, 1954 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1955 .field_pos = ID_AA64ISAR0_TLB_SHIFT, 1956 .sign = FTR_UNSIGNED, 1957 .min_field_value = ID_AA64ISAR0_TLB_RANGE, 1958 }, 1959 #ifdef CONFIG_ARM64_HW_AFDBM 1960 { 1961 /* 1962 * Since we turn this on always, we don't want the user to 1963 * think that the feature is available when it may not be. 1964 * So hide the description. 1965 * 1966 * .desc = "Hardware pagetable Dirty Bit Management", 1967 * 1968 */ 1969 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 1970 .capability = ARM64_HW_DBM, 1971 .sys_reg = SYS_ID_AA64MMFR1_EL1, 1972 .sign = FTR_UNSIGNED, 1973 .field_pos = ID_AA64MMFR1_HADBS_SHIFT, 1974 .min_field_value = 2, 1975 .matches = has_hw_dbm, 1976 .cpu_enable = cpu_enable_hw_dbm, 1977 }, 1978 #endif 1979 { 1980 .desc = "CRC32 instructions", 1981 .capability = ARM64_HAS_CRC32, 1982 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1983 .matches = has_cpuid_feature, 1984 .sys_reg = SYS_ID_AA64ISAR0_EL1, 1985 .field_pos = ID_AA64ISAR0_CRC32_SHIFT, 1986 .min_field_value = 1, 1987 }, 1988 { 1989 .desc = "Speculative Store Bypassing Safe (SSBS)", 1990 .capability = ARM64_SSBS, 1991 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1992 .matches = has_cpuid_feature, 1993 .sys_reg = SYS_ID_AA64PFR1_EL1, 1994 .field_pos = ID_AA64PFR1_SSBS_SHIFT, 1995 .sign = FTR_UNSIGNED, 1996 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY, 1997 }, 1998 #ifdef CONFIG_ARM64_CNP 1999 { 2000 .desc = "Common not Private translations", 2001 .capability = ARM64_HAS_CNP, 2002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2003 .matches = has_useable_cnp, 2004 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2005 .sign = FTR_UNSIGNED, 2006 .field_pos = ID_AA64MMFR2_CNP_SHIFT, 2007 .min_field_value = 1, 2008 .cpu_enable = cpu_enable_cnp, 2009 }, 2010 #endif 2011 { 2012 .desc = "Speculation barrier (SB)", 2013 .capability = ARM64_HAS_SB, 2014 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2015 .matches = has_cpuid_feature, 2016 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2017 .field_pos = ID_AA64ISAR1_SB_SHIFT, 2018 .sign = FTR_UNSIGNED, 2019 .min_field_value = 1, 2020 }, 2021 #ifdef CONFIG_ARM64_PTR_AUTH 2022 { 2023 .desc = "Address authentication (architected algorithm)", 2024 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH, 2025 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2026 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2027 .sign = FTR_UNSIGNED, 2028 .field_pos = ID_AA64ISAR1_APA_SHIFT, 2029 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED, 2030 .matches = has_address_auth_cpucap, 2031 }, 2032 { 2033 .desc = "Address authentication (IMP DEF algorithm)", 2034 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2035 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2036 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2037 .sign = FTR_UNSIGNED, 2038 .field_pos = ID_AA64ISAR1_API_SHIFT, 2039 .min_field_value = ID_AA64ISAR1_API_IMP_DEF, 2040 .matches = has_address_auth_cpucap, 2041 }, 2042 { 2043 .capability = ARM64_HAS_ADDRESS_AUTH, 2044 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2045 .matches = has_address_auth_metacap, 2046 }, 2047 { 2048 .desc = "Generic authentication (architected algorithm)", 2049 .capability = ARM64_HAS_GENERIC_AUTH_ARCH, 2050 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2051 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2052 .sign = FTR_UNSIGNED, 2053 .field_pos = ID_AA64ISAR1_GPA_SHIFT, 2054 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED, 2055 .matches = has_cpuid_feature, 2056 }, 2057 { 2058 .desc = "Generic authentication (IMP DEF algorithm)", 2059 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2060 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2061 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2062 .sign = FTR_UNSIGNED, 2063 .field_pos = ID_AA64ISAR1_GPI_SHIFT, 2064 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF, 2065 .matches = has_cpuid_feature, 2066 }, 2067 { 2068 .capability = ARM64_HAS_GENERIC_AUTH, 2069 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2070 .matches = has_generic_auth, 2071 }, 2072 #endif /* CONFIG_ARM64_PTR_AUTH */ 2073 #ifdef CONFIG_ARM64_PSEUDO_NMI 2074 { 2075 /* 2076 * Depends on having GICv3 2077 */ 2078 .desc = "IRQ priority masking", 2079 .capability = ARM64_HAS_IRQ_PRIO_MASKING, 2080 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2081 .matches = can_use_gic_priorities, 2082 .sys_reg = SYS_ID_AA64PFR0_EL1, 2083 .field_pos = ID_AA64PFR0_GIC_SHIFT, 2084 .sign = FTR_UNSIGNED, 2085 .min_field_value = 1, 2086 }, 2087 #endif 2088 #ifdef CONFIG_ARM64_E0PD 2089 { 2090 .desc = "E0PD", 2091 .capability = ARM64_HAS_E0PD, 2092 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2093 .sys_reg = SYS_ID_AA64MMFR2_EL1, 2094 .sign = FTR_UNSIGNED, 2095 .field_pos = ID_AA64MMFR2_E0PD_SHIFT, 2096 .matches = has_cpuid_feature, 2097 .min_field_value = 1, 2098 .cpu_enable = cpu_enable_e0pd, 2099 }, 2100 #endif 2101 #ifdef CONFIG_ARCH_RANDOM 2102 { 2103 .desc = "Random Number Generator", 2104 .capability = ARM64_HAS_RNG, 2105 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2106 .matches = has_cpuid_feature, 2107 .sys_reg = SYS_ID_AA64ISAR0_EL1, 2108 .field_pos = ID_AA64ISAR0_RNDR_SHIFT, 2109 .sign = FTR_UNSIGNED, 2110 .min_field_value = 1, 2111 }, 2112 #endif 2113 #ifdef CONFIG_ARM64_BTI 2114 { 2115 .desc = "Branch Target Identification", 2116 .capability = ARM64_BTI, 2117 #ifdef CONFIG_ARM64_BTI_KERNEL 2118 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2119 #else 2120 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2121 #endif 2122 .matches = has_cpuid_feature, 2123 .cpu_enable = bti_enable, 2124 .sys_reg = SYS_ID_AA64PFR1_EL1, 2125 .field_pos = ID_AA64PFR1_BT_SHIFT, 2126 .min_field_value = ID_AA64PFR1_BT_BTI, 2127 .sign = FTR_UNSIGNED, 2128 }, 2129 #endif 2130 #ifdef CONFIG_ARM64_MTE 2131 { 2132 .desc = "Memory Tagging Extension", 2133 .capability = ARM64_MTE, 2134 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2135 .matches = has_cpuid_feature, 2136 .sys_reg = SYS_ID_AA64PFR1_EL1, 2137 .field_pos = ID_AA64PFR1_MTE_SHIFT, 2138 .min_field_value = ID_AA64PFR1_MTE, 2139 .sign = FTR_UNSIGNED, 2140 .cpu_enable = cpu_enable_mte, 2141 }, 2142 #endif /* CONFIG_ARM64_MTE */ 2143 { 2144 .desc = "RCpc load-acquire (LDAPR)", 2145 .capability = ARM64_HAS_LDAPR, 2146 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2147 .sys_reg = SYS_ID_AA64ISAR1_EL1, 2148 .sign = FTR_UNSIGNED, 2149 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, 2150 .matches = has_cpuid_feature, 2151 .min_field_value = 1, 2152 }, 2153 {}, 2154 }; 2155 2156 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2157 .matches = has_cpuid_feature, \ 2158 .sys_reg = reg, \ 2159 .field_pos = field, \ 2160 .sign = s, \ 2161 .min_field_value = min_value, 2162 2163 #define __HWCAP_CAP(name, cap_type, cap) \ 2164 .desc = name, \ 2165 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 2166 .hwcap_type = cap_type, \ 2167 .hwcap = cap, \ 2168 2169 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \ 2170 { \ 2171 __HWCAP_CAP(#cap, cap_type, cap) \ 2172 HWCAP_CPUID_MATCH(reg, field, s, min_value) \ 2173 } 2174 2175 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 2176 { \ 2177 __HWCAP_CAP(#cap, cap_type, cap) \ 2178 .matches = cpucap_multi_entry_cap_matches, \ 2179 .match_list = list, \ 2180 } 2181 2182 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 2183 { \ 2184 __HWCAP_CAP(#cap, cap_type, cap) \ 2185 .matches = match, \ 2186 } 2187 2188 #ifdef CONFIG_ARM64_PTR_AUTH 2189 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 2190 { 2191 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT, 2192 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED) 2193 }, 2194 { 2195 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT, 2196 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF) 2197 }, 2198 {}, 2199 }; 2200 2201 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 2202 { 2203 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT, 2204 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED) 2205 }, 2206 { 2207 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT, 2208 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF) 2209 }, 2210 {}, 2211 }; 2212 #endif 2213 2214 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 2215 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), 2216 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), 2217 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), 2218 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), 2219 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), 2220 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), 2221 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 2222 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 2223 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), 2224 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), 2225 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), 2226 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 2227 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 2228 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 2229 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 2230 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), 2231 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), 2232 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), 2233 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 2234 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 2235 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT), 2236 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 2237 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 2238 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 2239 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA), 2240 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 2241 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 2242 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT), 2243 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB), 2244 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16), 2245 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH), 2246 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM), 2247 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT), 2248 #ifdef CONFIG_ARM64_SVE 2249 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE), 2250 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 2251 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 2252 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 2253 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 2254 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 2255 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 2256 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 2257 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 2258 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 2259 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 2260 #endif 2261 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS), 2262 #ifdef CONFIG_ARM64_BTI 2263 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI), 2264 #endif 2265 #ifdef CONFIG_ARM64_PTR_AUTH 2266 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 2267 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 2268 #endif 2269 #ifdef CONFIG_ARM64_MTE 2270 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE), 2271 #endif /* CONFIG_ARM64_MTE */ 2272 {}, 2273 }; 2274 2275 #ifdef CONFIG_COMPAT 2276 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 2277 { 2278 /* 2279 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 2280 * in line with that of arm32 as in vfp_init(). We make sure that the 2281 * check is future proof, by making sure value is non-zero. 2282 */ 2283 u32 mvfr1; 2284 2285 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 2286 if (scope == SCOPE_SYSTEM) 2287 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 2288 else 2289 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 2290 2291 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) && 2292 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) && 2293 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT); 2294 } 2295 #endif 2296 2297 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 2298 #ifdef CONFIG_COMPAT 2299 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 2300 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 2301 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 2302 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 2303 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 2304 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 2305 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 2306 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 2307 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 2308 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 2309 #endif 2310 {}, 2311 }; 2312 2313 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2314 { 2315 switch (cap->hwcap_type) { 2316 case CAP_HWCAP: 2317 cpu_set_feature(cap->hwcap); 2318 break; 2319 #ifdef CONFIG_COMPAT 2320 case CAP_COMPAT_HWCAP: 2321 compat_elf_hwcap |= (u32)cap->hwcap; 2322 break; 2323 case CAP_COMPAT_HWCAP2: 2324 compat_elf_hwcap2 |= (u32)cap->hwcap; 2325 break; 2326 #endif 2327 default: 2328 WARN_ON(1); 2329 break; 2330 } 2331 } 2332 2333 /* Check if we have a particular HWCAP enabled */ 2334 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 2335 { 2336 bool rc; 2337 2338 switch (cap->hwcap_type) { 2339 case CAP_HWCAP: 2340 rc = cpu_have_feature(cap->hwcap); 2341 break; 2342 #ifdef CONFIG_COMPAT 2343 case CAP_COMPAT_HWCAP: 2344 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 2345 break; 2346 case CAP_COMPAT_HWCAP2: 2347 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 2348 break; 2349 #endif 2350 default: 2351 WARN_ON(1); 2352 rc = false; 2353 } 2354 2355 return rc; 2356 } 2357 2358 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 2359 { 2360 /* We support emulation of accesses to CPU ID feature registers */ 2361 cpu_set_named_feature(CPUID); 2362 for (; hwcaps->matches; hwcaps++) 2363 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 2364 cap_set_elf_hwcap(hwcaps); 2365 } 2366 2367 static void update_cpu_capabilities(u16 scope_mask) 2368 { 2369 int i; 2370 const struct arm64_cpu_capabilities *caps; 2371 2372 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2373 for (i = 0; i < ARM64_NCAPS; i++) { 2374 caps = cpu_hwcaps_ptrs[i]; 2375 if (!caps || !(caps->type & scope_mask) || 2376 cpus_have_cap(caps->capability) || 2377 !caps->matches(caps, cpucap_default_scope(caps))) 2378 continue; 2379 2380 if (caps->desc) 2381 pr_info("detected: %s\n", caps->desc); 2382 cpus_set_cap(caps->capability); 2383 2384 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 2385 set_bit(caps->capability, boot_capabilities); 2386 } 2387 } 2388 2389 /* 2390 * Enable all the available capabilities on this CPU. The capabilities 2391 * with BOOT_CPU scope are handled separately and hence skipped here. 2392 */ 2393 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 2394 { 2395 int i; 2396 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 2397 2398 for_each_available_cap(i) { 2399 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i]; 2400 2401 if (WARN_ON(!cap)) 2402 continue; 2403 2404 if (!(cap->type & non_boot_scope)) 2405 continue; 2406 2407 if (cap->cpu_enable) 2408 cap->cpu_enable(cap); 2409 } 2410 return 0; 2411 } 2412 2413 /* 2414 * Run through the enabled capabilities and enable() it on all active 2415 * CPUs 2416 */ 2417 static void __init enable_cpu_capabilities(u16 scope_mask) 2418 { 2419 int i; 2420 const struct arm64_cpu_capabilities *caps; 2421 bool boot_scope; 2422 2423 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2424 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 2425 2426 for (i = 0; i < ARM64_NCAPS; i++) { 2427 unsigned int num; 2428 2429 caps = cpu_hwcaps_ptrs[i]; 2430 if (!caps || !(caps->type & scope_mask)) 2431 continue; 2432 num = caps->capability; 2433 if (!cpus_have_cap(num)) 2434 continue; 2435 2436 /* Ensure cpus_have_const_cap(num) works */ 2437 static_branch_enable(&cpu_hwcap_keys[num]); 2438 2439 if (boot_scope && caps->cpu_enable) 2440 /* 2441 * Capabilities with SCOPE_BOOT_CPU scope are finalised 2442 * before any secondary CPU boots. Thus, each secondary 2443 * will enable the capability as appropriate via 2444 * check_local_cpu_capabilities(). The only exception is 2445 * the boot CPU, for which the capability must be 2446 * enabled here. This approach avoids costly 2447 * stop_machine() calls for this case. 2448 */ 2449 caps->cpu_enable(caps); 2450 } 2451 2452 /* 2453 * For all non-boot scope capabilities, use stop_machine() 2454 * as it schedules the work allowing us to modify PSTATE, 2455 * instead of on_each_cpu() which uses an IPI, giving us a 2456 * PSTATE that disappears when we return. 2457 */ 2458 if (!boot_scope) 2459 stop_machine(cpu_enable_non_boot_scope_capabilities, 2460 NULL, cpu_online_mask); 2461 } 2462 2463 /* 2464 * Run through the list of capabilities to check for conflicts. 2465 * If the system has already detected a capability, take necessary 2466 * action on this CPU. 2467 */ 2468 static void verify_local_cpu_caps(u16 scope_mask) 2469 { 2470 int i; 2471 bool cpu_has_cap, system_has_cap; 2472 const struct arm64_cpu_capabilities *caps; 2473 2474 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 2475 2476 for (i = 0; i < ARM64_NCAPS; i++) { 2477 caps = cpu_hwcaps_ptrs[i]; 2478 if (!caps || !(caps->type & scope_mask)) 2479 continue; 2480 2481 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 2482 system_has_cap = cpus_have_cap(caps->capability); 2483 2484 if (system_has_cap) { 2485 /* 2486 * Check if the new CPU misses an advertised feature, 2487 * which is not safe to miss. 2488 */ 2489 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 2490 break; 2491 /* 2492 * We have to issue cpu_enable() irrespective of 2493 * whether the CPU has it or not, as it is enabeld 2494 * system wide. It is upto the call back to take 2495 * appropriate action on this CPU. 2496 */ 2497 if (caps->cpu_enable) 2498 caps->cpu_enable(caps); 2499 } else { 2500 /* 2501 * Check if the CPU has this capability if it isn't 2502 * safe to have when the system doesn't. 2503 */ 2504 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 2505 break; 2506 } 2507 } 2508 2509 if (i < ARM64_NCAPS) { 2510 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 2511 smp_processor_id(), caps->capability, 2512 caps->desc, system_has_cap, cpu_has_cap); 2513 2514 if (cpucap_panic_on_conflict(caps)) 2515 cpu_panic_kernel(); 2516 else 2517 cpu_die_early(); 2518 } 2519 } 2520 2521 /* 2522 * Check for CPU features that are used in early boot 2523 * based on the Boot CPU value. 2524 */ 2525 static void check_early_cpu_features(void) 2526 { 2527 verify_cpu_asid_bits(); 2528 2529 verify_local_cpu_caps(SCOPE_BOOT_CPU); 2530 } 2531 2532 static void 2533 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 2534 { 2535 2536 for (; caps->matches; caps++) 2537 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 2538 pr_crit("CPU%d: missing HWCAP: %s\n", 2539 smp_processor_id(), caps->desc); 2540 cpu_die_early(); 2541 } 2542 } 2543 2544 static void verify_sve_features(void) 2545 { 2546 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 2547 u64 zcr = read_zcr_features(); 2548 2549 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 2550 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 2551 2552 if (len < safe_len || sve_verify_vq_map()) { 2553 pr_crit("CPU%d: SVE: vector length support mismatch\n", 2554 smp_processor_id()); 2555 cpu_die_early(); 2556 } 2557 2558 /* Add checks on other ZCR bits here if necessary */ 2559 } 2560 2561 static void verify_hyp_capabilities(void) 2562 { 2563 u64 safe_mmfr1, mmfr0, mmfr1; 2564 int parange, ipa_max; 2565 unsigned int safe_vmid_bits, vmid_bits; 2566 2567 if (!IS_ENABLED(CONFIG_KVM)) 2568 return; 2569 2570 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 2571 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 2572 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 2573 2574 /* Verify VMID bits */ 2575 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 2576 vmid_bits = get_vmid_bits(mmfr1); 2577 if (vmid_bits < safe_vmid_bits) { 2578 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 2579 cpu_die_early(); 2580 } 2581 2582 /* Verify IPA range */ 2583 parange = cpuid_feature_extract_unsigned_field(mmfr0, 2584 ID_AA64MMFR0_PARANGE_SHIFT); 2585 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 2586 if (ipa_max < get_kvm_ipa_limit()) { 2587 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 2588 cpu_die_early(); 2589 } 2590 } 2591 2592 /* 2593 * Run through the enabled system capabilities and enable() it on this CPU. 2594 * The capabilities were decided based on the available CPUs at the boot time. 2595 * Any new CPU should match the system wide status of the capability. If the 2596 * new CPU doesn't have a capability which the system now has enabled, we 2597 * cannot do anything to fix it up and could cause unexpected failures. So 2598 * we park the CPU. 2599 */ 2600 static void verify_local_cpu_capabilities(void) 2601 { 2602 /* 2603 * The capabilities with SCOPE_BOOT_CPU are checked from 2604 * check_early_cpu_features(), as they need to be verified 2605 * on all secondary CPUs. 2606 */ 2607 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2608 2609 verify_local_elf_hwcaps(arm64_elf_hwcaps); 2610 2611 if (system_supports_32bit_el0()) 2612 verify_local_elf_hwcaps(compat_elf_hwcaps); 2613 2614 if (system_supports_sve()) 2615 verify_sve_features(); 2616 2617 if (is_hyp_mode_available()) 2618 verify_hyp_capabilities(); 2619 } 2620 2621 void check_local_cpu_capabilities(void) 2622 { 2623 /* 2624 * All secondary CPUs should conform to the early CPU features 2625 * in use by the kernel based on boot CPU. 2626 */ 2627 check_early_cpu_features(); 2628 2629 /* 2630 * If we haven't finalised the system capabilities, this CPU gets 2631 * a chance to update the errata work arounds and local features. 2632 * Otherwise, this CPU should verify that it has all the system 2633 * advertised capabilities. 2634 */ 2635 if (!system_capabilities_finalized()) 2636 update_cpu_capabilities(SCOPE_LOCAL_CPU); 2637 else 2638 verify_local_cpu_capabilities(); 2639 } 2640 2641 static void __init setup_boot_cpu_capabilities(void) 2642 { 2643 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */ 2644 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 2645 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */ 2646 enable_cpu_capabilities(SCOPE_BOOT_CPU); 2647 } 2648 2649 bool this_cpu_has_cap(unsigned int n) 2650 { 2651 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 2652 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2653 2654 if (cap) 2655 return cap->matches(cap, SCOPE_LOCAL_CPU); 2656 } 2657 2658 return false; 2659 } 2660 2661 /* 2662 * This helper function is used in a narrow window when, 2663 * - The system wide safe registers are set with all the SMP CPUs and, 2664 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set. 2665 * In all other cases cpus_have_{const_}cap() should be used. 2666 */ 2667 static bool __maybe_unused __system_matches_cap(unsigned int n) 2668 { 2669 if (n < ARM64_NCAPS) { 2670 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n]; 2671 2672 if (cap) 2673 return cap->matches(cap, SCOPE_SYSTEM); 2674 } 2675 return false; 2676 } 2677 2678 void cpu_set_feature(unsigned int num) 2679 { 2680 WARN_ON(num >= MAX_CPU_FEATURES); 2681 elf_hwcap |= BIT(num); 2682 } 2683 EXPORT_SYMBOL_GPL(cpu_set_feature); 2684 2685 bool cpu_have_feature(unsigned int num) 2686 { 2687 WARN_ON(num >= MAX_CPU_FEATURES); 2688 return elf_hwcap & BIT(num); 2689 } 2690 EXPORT_SYMBOL_GPL(cpu_have_feature); 2691 2692 unsigned long cpu_get_elf_hwcap(void) 2693 { 2694 /* 2695 * We currently only populate the first 32 bits of AT_HWCAP. Please 2696 * note that for userspace compatibility we guarantee that bits 62 2697 * and 63 will always be returned as 0. 2698 */ 2699 return lower_32_bits(elf_hwcap); 2700 } 2701 2702 unsigned long cpu_get_elf_hwcap2(void) 2703 { 2704 return upper_32_bits(elf_hwcap); 2705 } 2706 2707 static void __init setup_system_capabilities(void) 2708 { 2709 /* 2710 * We have finalised the system-wide safe feature 2711 * registers, finalise the capabilities that depend 2712 * on it. Also enable all the available capabilities, 2713 * that are not enabled already. 2714 */ 2715 update_cpu_capabilities(SCOPE_SYSTEM); 2716 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 2717 } 2718 2719 void __init setup_cpu_features(void) 2720 { 2721 u32 cwg; 2722 2723 setup_system_capabilities(); 2724 setup_elf_hwcaps(arm64_elf_hwcaps); 2725 2726 if (system_supports_32bit_el0()) 2727 setup_elf_hwcaps(compat_elf_hwcaps); 2728 2729 if (system_uses_ttbr0_pan()) 2730 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 2731 2732 sve_setup(); 2733 minsigstksz_setup(); 2734 2735 /* Advertise that we have computed the system capabilities */ 2736 finalize_system_capabilities(); 2737 2738 /* 2739 * Check for sane CTR_EL0.CWG value. 2740 */ 2741 cwg = cache_type_cwg(); 2742 if (!cwg) 2743 pr_warn("No Cache Writeback Granule information, assuming %d\n", 2744 ARCH_DMA_MINALIGN); 2745 } 2746 2747 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 2748 { 2749 cpu_replace_ttbr1(lm_alias(swapper_pg_dir)); 2750 } 2751 2752 /* 2753 * We emulate only the following system register space. 2754 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 2755 * See Table C5-6 System instruction encodings for System register accesses, 2756 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 2757 */ 2758 static inline bool __attribute_const__ is_emulated(u32 id) 2759 { 2760 return (sys_reg_Op0(id) == 0x3 && 2761 sys_reg_CRn(id) == 0x0 && 2762 sys_reg_Op1(id) == 0x0 && 2763 (sys_reg_CRm(id) == 0 || 2764 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 2765 } 2766 2767 /* 2768 * With CRm == 0, reg should be one of : 2769 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 2770 */ 2771 static inline int emulate_id_reg(u32 id, u64 *valp) 2772 { 2773 switch (id) { 2774 case SYS_MIDR_EL1: 2775 *valp = read_cpuid_id(); 2776 break; 2777 case SYS_MPIDR_EL1: 2778 *valp = SYS_MPIDR_SAFE_VAL; 2779 break; 2780 case SYS_REVIDR_EL1: 2781 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 2782 *valp = 0; 2783 break; 2784 default: 2785 return -EINVAL; 2786 } 2787 2788 return 0; 2789 } 2790 2791 static int emulate_sys_reg(u32 id, u64 *valp) 2792 { 2793 struct arm64_ftr_reg *regp; 2794 2795 if (!is_emulated(id)) 2796 return -EINVAL; 2797 2798 if (sys_reg_CRm(id) == 0) 2799 return emulate_id_reg(id, valp); 2800 2801 regp = get_arm64_ftr_reg_nowarn(id); 2802 if (regp) 2803 *valp = arm64_ftr_reg_user_value(regp); 2804 else 2805 /* 2806 * The untracked registers are either IMPLEMENTATION DEFINED 2807 * (e.g, ID_AFR0_EL1) or reserved RAZ. 2808 */ 2809 *valp = 0; 2810 return 0; 2811 } 2812 2813 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 2814 { 2815 int rc; 2816 u64 val; 2817 2818 rc = emulate_sys_reg(sys_reg, &val); 2819 if (!rc) { 2820 pt_regs_write_reg(regs, rt, val); 2821 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 2822 } 2823 return rc; 2824 } 2825 2826 static int emulate_mrs(struct pt_regs *regs, u32 insn) 2827 { 2828 u32 sys_reg, rt; 2829 2830 /* 2831 * sys_reg values are defined as used in mrs/msr instruction. 2832 * shift the imm value to get the encoding. 2833 */ 2834 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 2835 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 2836 return do_emulate_mrs(regs, sys_reg, rt); 2837 } 2838 2839 static struct undef_hook mrs_hook = { 2840 .instr_mask = 0xfff00000, 2841 .instr_val = 0xd5300000, 2842 .pstate_mask = PSR_AA32_MODE_MASK, 2843 .pstate_val = PSR_MODE_EL0t, 2844 .fn = emulate_mrs, 2845 }; 2846 2847 static int __init enable_mrs_emulation(void) 2848 { 2849 register_undef_hook(&mrs_hook); 2850 return 0; 2851 } 2852 2853 core_initcall(enable_mrs_emulation); 2854 2855 enum mitigation_state arm64_get_meltdown_state(void) 2856 { 2857 if (__meltdown_safe) 2858 return SPECTRE_UNAFFECTED; 2859 2860 if (arm64_kernel_unmapped_at_el0()) 2861 return SPECTRE_MITIGATED; 2862 2863 return SPECTRE_VULNERABLE; 2864 } 2865 2866 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 2867 char *buf) 2868 { 2869 switch (arm64_get_meltdown_state()) { 2870 case SPECTRE_UNAFFECTED: 2871 return sprintf(buf, "Not affected\n"); 2872 2873 case SPECTRE_MITIGATED: 2874 return sprintf(buf, "Mitigation: PTI\n"); 2875 2876 default: 2877 return sprintf(buf, "Vulnerable\n"); 2878 } 2879 } 2880