1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 79 #include <asm/cpu.h> 80 #include <asm/cpufeature.h> 81 #include <asm/cpu_ops.h> 82 #include <asm/fpsimd.h> 83 #include <asm/hwcap.h> 84 #include <asm/insn.h> 85 #include <asm/kvm_host.h> 86 #include <asm/mmu_context.h> 87 #include <asm/mte.h> 88 #include <asm/processor.h> 89 #include <asm/smp.h> 90 #include <asm/sysreg.h> 91 #include <asm/traps.h> 92 #include <asm/vectors.h> 93 #include <asm/virt.h> 94 95 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 96 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 97 98 #ifdef CONFIG_COMPAT 99 #define COMPAT_ELF_HWCAP_DEFAULT \ 100 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 101 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 102 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 103 COMPAT_HWCAP_LPAE) 104 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 105 unsigned int compat_elf_hwcap2 __read_mostly; 106 unsigned int compat_elf_hwcap3 __read_mostly; 107 #endif 108 109 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 110 EXPORT_SYMBOL(system_cpucaps); 111 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 112 113 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 114 115 bool arm64_use_ng_mappings = false; 116 EXPORT_SYMBOL(arm64_use_ng_mappings); 117 118 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 119 120 /* 121 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 122 * support it? 123 */ 124 static bool __read_mostly allow_mismatched_32bit_el0; 125 126 /* 127 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 128 * seen at least one CPU capable of 32-bit EL0. 129 */ 130 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 131 132 /* 133 * Mask of CPUs supporting 32-bit EL0. 134 * Only valid if arm64_mismatched_32bit_el0 is enabled. 135 */ 136 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 137 138 void dump_cpu_features(void) 139 { 140 /* file-wide pr_fmt adds "CPU features: " prefix */ 141 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 142 } 143 144 #define __ARM64_MAX_POSITIVE(reg, field) \ 145 ((reg##_##field##_SIGNED ? \ 146 BIT(reg##_##field##_WIDTH - 1) : \ 147 BIT(reg##_##field##_WIDTH)) - 1) 148 149 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 150 151 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 152 .sys_reg = SYS_##reg, \ 153 .field_pos = reg##_##field##_SHIFT, \ 154 .field_width = reg##_##field##_WIDTH, \ 155 .sign = reg##_##field##_SIGNED, \ 156 .min_field_value = min_value, \ 157 .max_field_value = max_value, 158 159 /* 160 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 161 * an implicit maximum that depends on the sign-ess of the field. 162 * 163 * An unsigned field will be capped at all ones, while a signed field 164 * will be limited to the positive half only. 165 */ 166 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 167 __ARM64_CPUID_FIELDS(reg, field, \ 168 SYS_FIELD_VALUE(reg, field, min_value), \ 169 __ARM64_MAX_POSITIVE(reg, field)) 170 171 /* 172 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 173 * implicit minimal value to max_value. This should be used when 174 * matching a non-implemented property. 175 */ 176 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 177 __ARM64_CPUID_FIELDS(reg, field, \ 178 __ARM64_MIN_NEGATIVE(reg, field), \ 179 SYS_FIELD_VALUE(reg, field, max_value)) 180 181 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 182 { \ 183 .sign = SIGNED, \ 184 .visible = VISIBLE, \ 185 .strict = STRICT, \ 186 .type = TYPE, \ 187 .shift = SHIFT, \ 188 .width = WIDTH, \ 189 .safe_val = SAFE_VAL, \ 190 } 191 192 /* Define a feature with unsigned values */ 193 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 194 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 195 196 /* Define a feature with a signed value */ 197 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 198 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 199 200 #define ARM64_FTR_END \ 201 { \ 202 .width = 0, \ 203 } 204 205 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 206 207 static bool __system_matches_cap(unsigned int n); 208 209 /* 210 * NOTE: Any changes to the visibility of features should be kept in 211 * sync with the documentation of the CPU feature register ABI. 212 */ 213 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 219 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 220 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 221 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 228 ARM64_FTR_END, 229 }; 230 231 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 240 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 241 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 242 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 247 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 251 ARM64_FTR_END, 252 }; 253 254 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 255 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 262 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 267 ARM64_FTR_END, 268 }; 269 270 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 272 ARM64_FTR_END, 273 }; 274 275 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 282 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 283 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 285 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 286 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 287 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 292 ARM64_FTR_END, 293 }; 294 295 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 296 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 297 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 299 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 303 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 304 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 305 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 306 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 307 ARM64_FTR_END, 308 }; 309 310 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 311 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 312 ARM64_FTR_END, 313 }; 314 315 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 321 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 326 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 336 ARM64_FTR_END, 337 }; 338 339 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 341 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 343 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 345 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 347 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 349 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 351 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 353 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 355 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 376 ARM64_FTR_END, 377 }; 378 379 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 380 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 386 ARM64_FTR_END, 387 }; 388 389 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 390 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 393 /* 394 * Page size not being supported at Stage-2 is not fatal. You 395 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 396 * your favourite nesting hypervisor. 397 * 398 * There is a small corner case where the hypervisor explicitly 399 * advertises a given granule size at Stage-2 (value 2) on some 400 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 401 * vCPUs. Although this is not forbidden by the architecture, it 402 * indicates that the hypervisor is being silly (or buggy). 403 * 404 * We make no effort to cope with this and pretend that if these 405 * fields are inconsistent across vCPUs, then it isn't worth 406 * trying to bring KVM up. 407 */ 408 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 409 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 410 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 411 /* 412 * We already refuse to boot CPUs that don't support our configured 413 * page size, so we can only detect mismatches for a page size other 414 * than the one we're currently using. Unfortunately, SoCs like this 415 * exist in the wild so, even though we don't like it, we'll have to go 416 * along with it and treat them as non-strict. 417 */ 418 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 421 422 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 423 /* Linux shouldn't care about secure memory */ 424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 427 /* 428 * Differing PARange is fine as long as all peripherals and memory are mapped 429 * within the minimum PARange of all CPUs 430 */ 431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 432 ARM64_FTR_END, 433 }; 434 435 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 438 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 439 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 450 ARM64_FTR_END, 451 }; 452 453 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 460 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 469 ARM64_FTR_END, 470 }; 471 472 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 473 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 474 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 481 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 482 ARM64_FTR_END, 483 }; 484 485 static const struct arm64_ftr_bits ftr_ctr[] = { 486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 489 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 492 /* 493 * Linux can handle differing I-cache policies. Userspace JITs will 494 * make use of *minLine. 495 * If we have differing I-cache policies, report it as the weakest - VIPT. 496 */ 497 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 498 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 499 ARM64_FTR_END, 500 }; 501 502 static struct arm64_ftr_override __ro_after_init no_override = { }; 503 504 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 505 .name = "SYS_CTR_EL0", 506 .ftr_bits = ftr_ctr, 507 .override = &no_override, 508 }; 509 510 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 511 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 516 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 523 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 528 /* 529 * We can instantiate multiple PMU instances with different levels 530 * of support. 531 */ 532 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 534 ARM64_FTR_END, 535 }; 536 537 static const struct arm64_ftr_bits ftr_mvfr0[] = { 538 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 546 ARM64_FTR_END, 547 }; 548 549 static const struct arm64_ftr_bits ftr_mvfr1[] = { 550 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 551 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 558 ARM64_FTR_END, 559 }; 560 561 static const struct arm64_ftr_bits ftr_mvfr2[] = { 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 563 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 564 ARM64_FTR_END, 565 }; 566 567 static const struct arm64_ftr_bits ftr_dczid[] = { 568 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 569 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 570 ARM64_FTR_END, 571 }; 572 573 static const struct arm64_ftr_bits ftr_gmid[] = { 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_id_isar0[] = { 579 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 586 ARM64_FTR_END, 587 }; 588 589 static const struct arm64_ftr_bits ftr_id_isar5[] = { 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 593 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 596 ARM64_FTR_END, 597 }; 598 599 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 604 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 607 608 /* 609 * SpecSEI = 1 indicates that the PE might generate an SError on an 610 * external abort on speculative read. It is safe to assume that an 611 * SError might be generated than it will not be. Hence it has been 612 * classified as FTR_HIGHER_SAFE. 613 */ 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 615 ARM64_FTR_END, 616 }; 617 618 static const struct arm64_ftr_bits ftr_id_isar4[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 627 ARM64_FTR_END, 628 }; 629 630 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 632 ARM64_FTR_END, 633 }; 634 635 static const struct arm64_ftr_bits ftr_id_isar6[] = { 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 640 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 641 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 643 ARM64_FTR_END, 644 }; 645 646 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 653 ARM64_FTR_END, 654 }; 655 656 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 661 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 665 ARM64_FTR_END, 666 }; 667 668 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 675 /* [31:28] TraceFilt */ 676 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 683 ARM64_FTR_END, 684 }; 685 686 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 687 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 688 ARM64_FTR_END, 689 }; 690 691 static const struct arm64_ftr_bits ftr_mpamidr[] = { 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 696 ARM64_FTR_END, 697 }; 698 699 /* 700 * Common ftr bits for a 32bit register with all hidden, strict 701 * attributes, with 4bit feature fields and a default safe value of 702 * 0. Covers the following 32bit registers: 703 * id_isar[1-3], id_mmfr[1-3] 704 */ 705 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 712 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 714 ARM64_FTR_END, 715 }; 716 717 /* Table for a single 32bit feature value */ 718 static const struct arm64_ftr_bits ftr_single32[] = { 719 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 720 ARM64_FTR_END, 721 }; 722 723 static const struct arm64_ftr_bits ftr_raz[] = { 724 ARM64_FTR_END, 725 }; 726 727 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 728 .sys_id = id, \ 729 .reg = &(struct arm64_ftr_reg){ \ 730 .name = id_str, \ 731 .override = (ovr), \ 732 .ftr_bits = &((table)[0]), \ 733 }} 734 735 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 736 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 737 738 #define ARM64_FTR_REG(id, table) \ 739 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 740 741 struct arm64_ftr_override id_aa64mmfr0_override; 742 struct arm64_ftr_override id_aa64mmfr1_override; 743 struct arm64_ftr_override id_aa64mmfr2_override; 744 struct arm64_ftr_override id_aa64pfr0_override; 745 struct arm64_ftr_override id_aa64pfr1_override; 746 struct arm64_ftr_override id_aa64zfr0_override; 747 struct arm64_ftr_override id_aa64smfr0_override; 748 struct arm64_ftr_override id_aa64isar1_override; 749 struct arm64_ftr_override id_aa64isar2_override; 750 751 struct arm64_ftr_override arm64_sw_feature_override; 752 753 static const struct __ftr_reg_entry { 754 u32 sys_id; 755 struct arm64_ftr_reg *reg; 756 } arm64_ftr_regs[] = { 757 758 /* Op1 = 0, CRn = 0, CRm = 1 */ 759 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 760 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 761 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 762 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 763 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 764 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 765 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 766 767 /* Op1 = 0, CRn = 0, CRm = 2 */ 768 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 769 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 770 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 771 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 772 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 773 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 774 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 775 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 776 777 /* Op1 = 0, CRn = 0, CRm = 3 */ 778 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 779 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 780 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 781 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 782 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 783 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 784 785 /* Op1 = 0, CRn = 0, CRm = 4 */ 786 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 787 &id_aa64pfr0_override), 788 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 789 &id_aa64pfr1_override), 790 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 791 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 792 &id_aa64zfr0_override), 793 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 794 &id_aa64smfr0_override), 795 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 796 797 /* Op1 = 0, CRn = 0, CRm = 5 */ 798 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 799 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 800 801 /* Op1 = 0, CRn = 0, CRm = 6 */ 802 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 803 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 804 &id_aa64isar1_override), 805 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 806 &id_aa64isar2_override), 807 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 808 809 /* Op1 = 0, CRn = 0, CRm = 7 */ 810 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 811 &id_aa64mmfr0_override), 812 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 813 &id_aa64mmfr1_override), 814 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 815 &id_aa64mmfr2_override), 816 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 817 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 818 819 /* Op1 = 0, CRn = 10, CRm = 4 */ 820 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 821 822 /* Op1 = 1, CRn = 0, CRm = 0 */ 823 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 824 825 /* Op1 = 3, CRn = 0, CRm = 0 */ 826 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 827 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 828 829 /* Op1 = 3, CRn = 14, CRm = 0 */ 830 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 831 }; 832 833 static int search_cmp_ftr_reg(const void *id, const void *regp) 834 { 835 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 836 } 837 838 /* 839 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 840 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 841 * ascending order of sys_id, we use binary search to find a matching 842 * entry. 843 * 844 * returns - Upon success, matching ftr_reg entry for id. 845 * - NULL on failure. It is upto the caller to decide 846 * the impact of a failure. 847 */ 848 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 849 { 850 const struct __ftr_reg_entry *ret; 851 852 ret = bsearch((const void *)(unsigned long)sys_id, 853 arm64_ftr_regs, 854 ARRAY_SIZE(arm64_ftr_regs), 855 sizeof(arm64_ftr_regs[0]), 856 search_cmp_ftr_reg); 857 if (ret) 858 return ret->reg; 859 return NULL; 860 } 861 862 /* 863 * get_arm64_ftr_reg - Looks up a feature register entry using 864 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 865 * 866 * returns - Upon success, matching ftr_reg entry for id. 867 * - NULL on failure but with an WARN_ON(). 868 */ 869 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 870 { 871 struct arm64_ftr_reg *reg; 872 873 reg = get_arm64_ftr_reg_nowarn(sys_id); 874 875 /* 876 * Requesting a non-existent register search is an error. Warn 877 * and let the caller handle it. 878 */ 879 WARN_ON(!reg); 880 return reg; 881 } 882 883 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 884 s64 ftr_val) 885 { 886 u64 mask = arm64_ftr_mask(ftrp); 887 888 reg &= ~mask; 889 reg |= (ftr_val << ftrp->shift) & mask; 890 return reg; 891 } 892 893 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 894 s64 cur) 895 { 896 s64 ret = 0; 897 898 switch (ftrp->type) { 899 case FTR_EXACT: 900 ret = ftrp->safe_val; 901 break; 902 case FTR_LOWER_SAFE: 903 ret = min(new, cur); 904 break; 905 case FTR_HIGHER_OR_ZERO_SAFE: 906 if (!cur || !new) 907 break; 908 fallthrough; 909 case FTR_HIGHER_SAFE: 910 ret = max(new, cur); 911 break; 912 default: 913 BUG(); 914 } 915 916 return ret; 917 } 918 919 static void __init sort_ftr_regs(void) 920 { 921 unsigned int i; 922 923 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 924 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 925 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 926 unsigned int j = 0; 927 928 /* 929 * Features here must be sorted in descending order with respect 930 * to their shift values and should not overlap with each other. 931 */ 932 for (; ftr_bits->width != 0; ftr_bits++, j++) { 933 unsigned int width = ftr_reg->ftr_bits[j].width; 934 unsigned int shift = ftr_reg->ftr_bits[j].shift; 935 unsigned int prev_shift; 936 937 WARN((shift + width) > 64, 938 "%s has invalid feature at shift %d\n", 939 ftr_reg->name, shift); 940 941 /* 942 * Skip the first feature. There is nothing to 943 * compare against for now. 944 */ 945 if (j == 0) 946 continue; 947 948 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 949 WARN((shift + width) > prev_shift, 950 "%s has feature overlap at shift %d\n", 951 ftr_reg->name, shift); 952 } 953 954 /* 955 * Skip the first register. There is nothing to 956 * compare against for now. 957 */ 958 if (i == 0) 959 continue; 960 /* 961 * Registers here must be sorted in ascending order with respect 962 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 963 * to work correctly. 964 */ 965 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 966 } 967 } 968 969 /* 970 * Initialise the CPU feature register from Boot CPU values. 971 * Also initiliases the strict_mask for the register. 972 * Any bits that are not covered by an arm64_ftr_bits entry are considered 973 * RES0 for the system-wide value, and must strictly match. 974 */ 975 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 976 { 977 u64 val = 0; 978 u64 strict_mask = ~0x0ULL; 979 u64 user_mask = 0; 980 u64 valid_mask = 0; 981 982 const struct arm64_ftr_bits *ftrp; 983 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 984 985 if (!reg) 986 return; 987 988 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 989 u64 ftr_mask = arm64_ftr_mask(ftrp); 990 s64 ftr_new = arm64_ftr_value(ftrp, new); 991 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 992 993 if ((ftr_mask & reg->override->mask) == ftr_mask) { 994 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 995 char *str = NULL; 996 997 if (ftr_ovr != tmp) { 998 /* Unsafe, remove the override */ 999 reg->override->mask &= ~ftr_mask; 1000 reg->override->val &= ~ftr_mask; 1001 tmp = ftr_ovr; 1002 str = "ignoring override"; 1003 } else if (ftr_new != tmp) { 1004 /* Override was valid */ 1005 ftr_new = tmp; 1006 str = "forced"; 1007 } else if (ftr_ovr == tmp) { 1008 /* Override was the safe value */ 1009 str = "already set"; 1010 } 1011 1012 if (str) 1013 pr_warn("%s[%d:%d]: %s to %llx\n", 1014 reg->name, 1015 ftrp->shift + ftrp->width - 1, 1016 ftrp->shift, str, 1017 tmp & (BIT(ftrp->width) - 1)); 1018 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1019 reg->override->val &= ~ftr_mask; 1020 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1021 reg->name, 1022 ftrp->shift + ftrp->width - 1, 1023 ftrp->shift); 1024 } 1025 1026 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1027 1028 valid_mask |= ftr_mask; 1029 if (!ftrp->strict) 1030 strict_mask &= ~ftr_mask; 1031 if (ftrp->visible) 1032 user_mask |= ftr_mask; 1033 else 1034 reg->user_val = arm64_ftr_set_value(ftrp, 1035 reg->user_val, 1036 ftrp->safe_val); 1037 } 1038 1039 val &= valid_mask; 1040 1041 reg->sys_val = val; 1042 reg->strict_mask = strict_mask; 1043 reg->user_mask = user_mask; 1044 } 1045 1046 extern const struct arm64_cpu_capabilities arm64_errata[]; 1047 static const struct arm64_cpu_capabilities arm64_features[]; 1048 1049 static void __init 1050 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1051 { 1052 for (; caps->matches; caps++) { 1053 if (WARN(caps->capability >= ARM64_NCAPS, 1054 "Invalid capability %d\n", caps->capability)) 1055 continue; 1056 if (WARN(cpucap_ptrs[caps->capability], 1057 "Duplicate entry for capability %d\n", 1058 caps->capability)) 1059 continue; 1060 cpucap_ptrs[caps->capability] = caps; 1061 } 1062 } 1063 1064 static void __init init_cpucap_indirect_list(void) 1065 { 1066 init_cpucap_indirect_list_from_array(arm64_features); 1067 init_cpucap_indirect_list_from_array(arm64_errata); 1068 } 1069 1070 static void __init setup_boot_cpu_capabilities(void); 1071 1072 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1073 { 1074 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1075 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1076 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1077 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1078 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1079 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1080 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1081 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1082 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1083 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1084 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1085 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1086 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1087 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1088 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1089 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1090 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1091 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1092 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1093 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1094 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1095 } 1096 1097 #ifdef CONFIG_ARM64_PSEUDO_NMI 1098 static bool enable_pseudo_nmi; 1099 1100 static int __init early_enable_pseudo_nmi(char *p) 1101 { 1102 return kstrtobool(p, &enable_pseudo_nmi); 1103 } 1104 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1105 1106 static __init void detect_system_supports_pseudo_nmi(void) 1107 { 1108 struct device_node *np; 1109 1110 if (!enable_pseudo_nmi) 1111 return; 1112 1113 /* 1114 * Detect broken MediaTek firmware that doesn't properly save and 1115 * restore GIC priorities. 1116 */ 1117 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1118 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1119 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1120 enable_pseudo_nmi = false; 1121 } 1122 of_node_put(np); 1123 } 1124 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1125 static inline void detect_system_supports_pseudo_nmi(void) { } 1126 #endif 1127 1128 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1129 { 1130 /* Before we start using the tables, make sure it is sorted */ 1131 sort_ftr_regs(); 1132 1133 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1134 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1135 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1136 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1137 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1138 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1139 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1140 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1141 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1142 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1143 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1144 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1145 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1146 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1147 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1148 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1149 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1150 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1151 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1152 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1153 1154 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1155 init_32bit_cpu_features(&info->aarch32); 1156 1157 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1158 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1159 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1160 1161 vec_init_vq_map(ARM64_VEC_SVE); 1162 1163 cpacr_restore(cpacr); 1164 } 1165 1166 if (IS_ENABLED(CONFIG_ARM64_SME) && 1167 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1168 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1169 1170 /* 1171 * We mask out SMPS since even if the hardware 1172 * supports priorities the kernel does not at present 1173 * and we block access to them. 1174 */ 1175 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1176 vec_init_vq_map(ARM64_VEC_SME); 1177 1178 cpacr_restore(cpacr); 1179 } 1180 1181 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1182 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1183 1184 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1185 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1186 } 1187 1188 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1189 { 1190 const struct arm64_ftr_bits *ftrp; 1191 1192 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1193 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1194 s64 ftr_new = arm64_ftr_value(ftrp, new); 1195 1196 if (ftr_cur == ftr_new) 1197 continue; 1198 /* Find a safe value */ 1199 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1200 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1201 } 1202 1203 } 1204 1205 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1206 { 1207 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1208 1209 if (!regp) 1210 return 0; 1211 1212 update_cpu_ftr_reg(regp, val); 1213 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1214 return 0; 1215 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1216 regp->name, boot, cpu, val); 1217 return 1; 1218 } 1219 1220 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1221 { 1222 const struct arm64_ftr_bits *ftrp; 1223 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1224 1225 if (!regp) 1226 return; 1227 1228 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1229 if (ftrp->shift == field) { 1230 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1231 break; 1232 } 1233 } 1234 1235 /* Bogus field? */ 1236 WARN_ON(!ftrp->width); 1237 } 1238 1239 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1240 struct cpuinfo_arm64 *boot) 1241 { 1242 static bool boot_cpu_32bit_regs_overridden = false; 1243 1244 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1245 return; 1246 1247 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1248 return; 1249 1250 boot->aarch32 = info->aarch32; 1251 init_32bit_cpu_features(&boot->aarch32); 1252 boot_cpu_32bit_regs_overridden = true; 1253 } 1254 1255 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1256 struct cpuinfo_32bit *boot) 1257 { 1258 int taint = 0; 1259 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1260 1261 /* 1262 * If we don't have AArch32 at EL1, then relax the strictness of 1263 * EL1-dependent register fields to avoid spurious sanity check fails. 1264 */ 1265 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1266 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1267 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1268 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1269 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1270 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1271 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1272 } 1273 1274 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1275 info->reg_id_dfr0, boot->reg_id_dfr0); 1276 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1277 info->reg_id_dfr1, boot->reg_id_dfr1); 1278 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1279 info->reg_id_isar0, boot->reg_id_isar0); 1280 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1281 info->reg_id_isar1, boot->reg_id_isar1); 1282 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1283 info->reg_id_isar2, boot->reg_id_isar2); 1284 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1285 info->reg_id_isar3, boot->reg_id_isar3); 1286 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1287 info->reg_id_isar4, boot->reg_id_isar4); 1288 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1289 info->reg_id_isar5, boot->reg_id_isar5); 1290 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1291 info->reg_id_isar6, boot->reg_id_isar6); 1292 1293 /* 1294 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1295 * ACTLR formats could differ across CPUs and therefore would have to 1296 * be trapped for virtualization anyway. 1297 */ 1298 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1299 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1300 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1301 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1302 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1303 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1304 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1305 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1306 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1307 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1308 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1309 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1310 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1311 info->reg_id_pfr0, boot->reg_id_pfr0); 1312 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1313 info->reg_id_pfr1, boot->reg_id_pfr1); 1314 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1315 info->reg_id_pfr2, boot->reg_id_pfr2); 1316 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1317 info->reg_mvfr0, boot->reg_mvfr0); 1318 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1319 info->reg_mvfr1, boot->reg_mvfr1); 1320 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1321 info->reg_mvfr2, boot->reg_mvfr2); 1322 1323 return taint; 1324 } 1325 1326 /* 1327 * Update system wide CPU feature registers with the values from a 1328 * non-boot CPU. Also performs SANITY checks to make sure that there 1329 * aren't any insane variations from that of the boot CPU. 1330 */ 1331 void update_cpu_features(int cpu, 1332 struct cpuinfo_arm64 *info, 1333 struct cpuinfo_arm64 *boot) 1334 { 1335 int taint = 0; 1336 1337 /* 1338 * The kernel can handle differing I-cache policies, but otherwise 1339 * caches should look identical. Userspace JITs will make use of 1340 * *minLine. 1341 */ 1342 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1343 info->reg_ctr, boot->reg_ctr); 1344 1345 /* 1346 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1347 * could result in too much or too little memory being zeroed if a 1348 * process is preempted and migrated between CPUs. 1349 */ 1350 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1351 info->reg_dczid, boot->reg_dczid); 1352 1353 /* If different, timekeeping will be broken (especially with KVM) */ 1354 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1355 info->reg_cntfrq, boot->reg_cntfrq); 1356 1357 /* 1358 * The kernel uses self-hosted debug features and expects CPUs to 1359 * support identical debug features. We presently need CTX_CMPs, WRPs, 1360 * and BRPs to be identical. 1361 * ID_AA64DFR1 is currently RES0. 1362 */ 1363 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1364 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1365 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1366 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1367 /* 1368 * Even in big.LITTLE, processors should be identical instruction-set 1369 * wise. 1370 */ 1371 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1372 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1373 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1374 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1375 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1376 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1377 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1378 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1379 1380 /* 1381 * Differing PARange support is fine as long as all peripherals and 1382 * memory are mapped within the minimum PARange of all CPUs. 1383 * Linux should not care about secure memory. 1384 */ 1385 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1386 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1387 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1388 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1389 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1390 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1391 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1392 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1393 1394 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1395 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1396 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1397 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1398 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1399 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1400 1401 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1402 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1403 1404 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1405 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1406 1407 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1408 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1409 1410 /* Probe vector lengths */ 1411 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1412 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1413 if (!system_capabilities_finalized()) { 1414 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1415 1416 vec_update_vq_map(ARM64_VEC_SVE); 1417 1418 cpacr_restore(cpacr); 1419 } 1420 } 1421 1422 if (IS_ENABLED(CONFIG_ARM64_SME) && 1423 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1424 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1425 1426 /* 1427 * We mask out SMPS since even if the hardware 1428 * supports priorities the kernel does not at present 1429 * and we block access to them. 1430 */ 1431 info->reg_smidr = read_cpuid(SMIDR_EL1) & ~SMIDR_EL1_SMPS; 1432 1433 /* Probe vector lengths */ 1434 if (!system_capabilities_finalized()) 1435 vec_update_vq_map(ARM64_VEC_SME); 1436 1437 cpacr_restore(cpacr); 1438 } 1439 1440 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1441 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1442 info->reg_mpamidr, boot->reg_mpamidr); 1443 } 1444 1445 /* 1446 * The kernel uses the LDGM/STGM instructions and the number of tags 1447 * they read/write depends on the GMID_EL1.BS field. Check that the 1448 * value is the same on all CPUs. 1449 */ 1450 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1451 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1452 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1453 info->reg_gmid, boot->reg_gmid); 1454 } 1455 1456 /* 1457 * If we don't have AArch32 at all then skip the checks entirely 1458 * as the register values may be UNKNOWN and we're not going to be 1459 * using them for anything. 1460 * 1461 * This relies on a sanitised view of the AArch64 ID registers 1462 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1463 */ 1464 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1465 lazy_init_32bit_cpu_features(info, boot); 1466 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1467 &boot->aarch32); 1468 } 1469 1470 /* 1471 * Mismatched CPU features are a recipe for disaster. Don't even 1472 * pretend to support them. 1473 */ 1474 if (taint) { 1475 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1476 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1477 } 1478 } 1479 1480 u64 read_sanitised_ftr_reg(u32 id) 1481 { 1482 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1483 1484 if (!regp) 1485 return 0; 1486 return regp->sys_val; 1487 } 1488 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1489 1490 #define read_sysreg_case(r) \ 1491 case r: val = read_sysreg_s(r); break; 1492 1493 /* 1494 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1495 * Read the system register on the current CPU 1496 */ 1497 u64 __read_sysreg_by_encoding(u32 sys_id) 1498 { 1499 struct arm64_ftr_reg *regp; 1500 u64 val; 1501 1502 switch (sys_id) { 1503 read_sysreg_case(SYS_ID_PFR0_EL1); 1504 read_sysreg_case(SYS_ID_PFR1_EL1); 1505 read_sysreg_case(SYS_ID_PFR2_EL1); 1506 read_sysreg_case(SYS_ID_DFR0_EL1); 1507 read_sysreg_case(SYS_ID_DFR1_EL1); 1508 read_sysreg_case(SYS_ID_MMFR0_EL1); 1509 read_sysreg_case(SYS_ID_MMFR1_EL1); 1510 read_sysreg_case(SYS_ID_MMFR2_EL1); 1511 read_sysreg_case(SYS_ID_MMFR3_EL1); 1512 read_sysreg_case(SYS_ID_MMFR4_EL1); 1513 read_sysreg_case(SYS_ID_MMFR5_EL1); 1514 read_sysreg_case(SYS_ID_ISAR0_EL1); 1515 read_sysreg_case(SYS_ID_ISAR1_EL1); 1516 read_sysreg_case(SYS_ID_ISAR2_EL1); 1517 read_sysreg_case(SYS_ID_ISAR3_EL1); 1518 read_sysreg_case(SYS_ID_ISAR4_EL1); 1519 read_sysreg_case(SYS_ID_ISAR5_EL1); 1520 read_sysreg_case(SYS_ID_ISAR6_EL1); 1521 read_sysreg_case(SYS_MVFR0_EL1); 1522 read_sysreg_case(SYS_MVFR1_EL1); 1523 read_sysreg_case(SYS_MVFR2_EL1); 1524 1525 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1526 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1527 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1528 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1529 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1530 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1531 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1532 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1533 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1534 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1535 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1536 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1537 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1538 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1539 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1540 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1541 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1542 1543 read_sysreg_case(SYS_CNTFRQ_EL0); 1544 read_sysreg_case(SYS_CTR_EL0); 1545 read_sysreg_case(SYS_DCZID_EL0); 1546 1547 default: 1548 BUG(); 1549 return 0; 1550 } 1551 1552 regp = get_arm64_ftr_reg(sys_id); 1553 if (regp) { 1554 val &= ~regp->override->mask; 1555 val |= (regp->override->val & regp->override->mask); 1556 } 1557 1558 return val; 1559 } 1560 1561 #include <linux/irqchip/arm-gic-v3.h> 1562 1563 static bool 1564 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1565 { 1566 return true; 1567 } 1568 1569 static bool 1570 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1571 { 1572 int val, min, max; 1573 u64 tmp; 1574 1575 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1576 entry->field_width, 1577 entry->sign); 1578 1579 tmp = entry->min_field_value; 1580 tmp <<= entry->field_pos; 1581 1582 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1583 entry->field_width, 1584 entry->sign); 1585 1586 tmp = entry->max_field_value; 1587 tmp <<= entry->field_pos; 1588 1589 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1590 entry->field_width, 1591 entry->sign); 1592 1593 return val >= min && val <= max; 1594 } 1595 1596 static u64 1597 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1598 { 1599 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1600 if (scope == SCOPE_SYSTEM) 1601 return read_sanitised_ftr_reg(entry->sys_reg); 1602 else 1603 return __read_sysreg_by_encoding(entry->sys_reg); 1604 } 1605 1606 static bool 1607 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1608 { 1609 int mask; 1610 struct arm64_ftr_reg *regp; 1611 u64 val = read_scoped_sysreg(entry, scope); 1612 1613 regp = get_arm64_ftr_reg(entry->sys_reg); 1614 if (!regp) 1615 return false; 1616 1617 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1618 entry->field_pos, 1619 entry->field_width); 1620 if (!mask) 1621 return false; 1622 1623 return feature_matches(val, entry); 1624 } 1625 1626 static bool 1627 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1628 { 1629 u64 val = read_scoped_sysreg(entry, scope); 1630 return feature_matches(val, entry); 1631 } 1632 1633 const struct cpumask *system_32bit_el0_cpumask(void) 1634 { 1635 if (!system_supports_32bit_el0()) 1636 return cpu_none_mask; 1637 1638 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1639 return cpu_32bit_el0_mask; 1640 1641 return cpu_possible_mask; 1642 } 1643 1644 static int __init parse_32bit_el0_param(char *str) 1645 { 1646 allow_mismatched_32bit_el0 = true; 1647 return 0; 1648 } 1649 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1650 1651 static ssize_t aarch32_el0_show(struct device *dev, 1652 struct device_attribute *attr, char *buf) 1653 { 1654 const struct cpumask *mask = system_32bit_el0_cpumask(); 1655 1656 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1657 } 1658 static const DEVICE_ATTR_RO(aarch32_el0); 1659 1660 static int __init aarch32_el0_sysfs_init(void) 1661 { 1662 struct device *dev_root; 1663 int ret = 0; 1664 1665 if (!allow_mismatched_32bit_el0) 1666 return 0; 1667 1668 dev_root = bus_get_dev_root(&cpu_subsys); 1669 if (dev_root) { 1670 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1671 put_device(dev_root); 1672 } 1673 return ret; 1674 } 1675 device_initcall(aarch32_el0_sysfs_init); 1676 1677 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1678 { 1679 if (!has_cpuid_feature(entry, scope)) 1680 return allow_mismatched_32bit_el0; 1681 1682 if (scope == SCOPE_SYSTEM) 1683 pr_info("detected: 32-bit EL0 Support\n"); 1684 1685 return true; 1686 } 1687 1688 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1689 { 1690 bool has_sre; 1691 1692 if (!has_cpuid_feature(entry, scope)) 1693 return false; 1694 1695 has_sre = gic_enable_sre(); 1696 if (!has_sre) 1697 pr_warn_once("%s present but disabled by higher exception level\n", 1698 entry->desc); 1699 1700 return has_sre; 1701 } 1702 1703 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1704 int scope) 1705 { 1706 u64 ctr; 1707 1708 if (scope == SCOPE_SYSTEM) 1709 ctr = arm64_ftr_reg_ctrel0.sys_val; 1710 else 1711 ctr = read_cpuid_effective_cachetype(); 1712 1713 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1714 } 1715 1716 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1717 { 1718 /* 1719 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1720 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1721 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1722 * value. 1723 */ 1724 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1725 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1726 } 1727 1728 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1729 int scope) 1730 { 1731 u64 ctr; 1732 1733 if (scope == SCOPE_SYSTEM) 1734 ctr = arm64_ftr_reg_ctrel0.sys_val; 1735 else 1736 ctr = read_cpuid_cachetype(); 1737 1738 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1739 } 1740 1741 static bool __maybe_unused 1742 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1743 { 1744 /* 1745 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1746 * may share TLB entries with a CPU stuck in the crashed 1747 * kernel. 1748 */ 1749 if (is_kdump_kernel()) 1750 return false; 1751 1752 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1753 return false; 1754 1755 return has_cpuid_feature(entry, scope); 1756 } 1757 1758 static bool __meltdown_safe = true; 1759 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1760 1761 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1762 int scope) 1763 { 1764 /* List of CPUs that are not vulnerable and don't need KPTI */ 1765 static const struct midr_range kpti_safe_list[] = { 1766 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1767 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1768 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1769 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1770 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1771 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1772 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1773 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1774 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1775 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1776 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1777 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1778 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1779 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1780 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1781 { /* sentinel */ } 1782 }; 1783 char const *str = "kpti command line option"; 1784 bool meltdown_safe; 1785 1786 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list); 1787 1788 /* Defer to CPU feature registers */ 1789 if (has_cpuid_feature(entry, scope)) 1790 meltdown_safe = true; 1791 1792 if (!meltdown_safe) 1793 __meltdown_safe = false; 1794 1795 /* 1796 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1797 * ThunderX leads to apparent I-cache corruption of kernel text, which 1798 * ends as well as you might imagine. Don't even try. We cannot rely 1799 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1800 * because cpucap detection order may change. However, since we know 1801 * affected CPUs are always in a homogeneous configuration, it is 1802 * safe to rely on this_cpu_has_cap() here. 1803 */ 1804 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1805 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1806 __kpti_forced = -1; 1807 } 1808 1809 /* Useful for KASLR robustness */ 1810 if (kaslr_enabled() && kaslr_requires_kpti()) { 1811 if (!__kpti_forced) { 1812 str = "KASLR"; 1813 __kpti_forced = 1; 1814 } 1815 } 1816 1817 if (cpu_mitigations_off() && !__kpti_forced) { 1818 str = "mitigations=off"; 1819 __kpti_forced = -1; 1820 } 1821 1822 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1823 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1824 return false; 1825 } 1826 1827 /* Forced? */ 1828 if (__kpti_forced) { 1829 pr_info_once("kernel page table isolation forced %s by %s\n", 1830 __kpti_forced > 0 ? "ON" : "OFF", str); 1831 return __kpti_forced > 0; 1832 } 1833 1834 return !meltdown_safe; 1835 } 1836 1837 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1838 { 1839 /* 1840 * Although the Apple M2 family appears to support NV1, the 1841 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1842 * that it doesn't support NV1 at all. 1843 */ 1844 static const struct midr_range nv1_ni_list[] = { 1845 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1846 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1847 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1848 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1849 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1850 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1851 {} 1852 }; 1853 1854 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1855 !(has_cpuid_feature(entry, scope) || 1856 is_midr_in_range_list(read_cpuid_id(), nv1_ni_list))); 1857 } 1858 1859 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1860 static bool has_lpa2_at_stage1(u64 mmfr0) 1861 { 1862 unsigned int tgran; 1863 1864 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1865 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1866 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1867 } 1868 1869 static bool has_lpa2_at_stage2(u64 mmfr0) 1870 { 1871 unsigned int tgran; 1872 1873 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1874 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1875 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1876 } 1877 1878 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1879 { 1880 u64 mmfr0; 1881 1882 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1883 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1884 } 1885 #else 1886 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1887 { 1888 return false; 1889 } 1890 #endif 1891 1892 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1893 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1894 1895 extern 1896 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1897 phys_addr_t size, pgprot_t prot, 1898 phys_addr_t (*pgtable_alloc)(int), int flags); 1899 1900 static phys_addr_t __initdata kpti_ng_temp_alloc; 1901 1902 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1903 { 1904 kpti_ng_temp_alloc -= PAGE_SIZE; 1905 return kpti_ng_temp_alloc; 1906 } 1907 1908 static int __init __kpti_install_ng_mappings(void *__unused) 1909 { 1910 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1911 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1912 kpti_remap_fn *remap_fn; 1913 1914 int cpu = smp_processor_id(); 1915 int levels = CONFIG_PGTABLE_LEVELS; 1916 int order = order_base_2(levels); 1917 u64 kpti_ng_temp_pgd_pa = 0; 1918 pgd_t *kpti_ng_temp_pgd; 1919 u64 alloc = 0; 1920 1921 if (levels == 5 && !pgtable_l5_enabled()) 1922 levels = 4; 1923 else if (levels == 4 && !pgtable_l4_enabled()) 1924 levels = 3; 1925 1926 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1927 1928 if (!cpu) { 1929 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1930 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1931 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1932 1933 // 1934 // Create a minimal page table hierarchy that permits us to map 1935 // the swapper page tables temporarily as we traverse them. 1936 // 1937 // The physical pages are laid out as follows: 1938 // 1939 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1940 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1941 // +--------+-\-------+-\------ +-\------ +-///--------+ 1942 // ^ 1943 // The first page is mapped into this hierarchy at a PMD_SHIFT 1944 // aligned virtual address, so that we can manipulate the PTE 1945 // level entries while the mapping is active. The first entry 1946 // covers the PTE[] page itself, the remaining entries are free 1947 // to be used as a ad-hoc fixmap. 1948 // 1949 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1950 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1951 kpti_ng_pgd_alloc, 0); 1952 } 1953 1954 cpu_install_idmap(); 1955 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1956 cpu_uninstall_idmap(); 1957 1958 if (!cpu) { 1959 free_pages(alloc, order); 1960 arm64_use_ng_mappings = true; 1961 } 1962 1963 return 0; 1964 } 1965 1966 static void __init kpti_install_ng_mappings(void) 1967 { 1968 /* Check whether KPTI is going to be used */ 1969 if (!arm64_kernel_unmapped_at_el0()) 1970 return; 1971 1972 /* 1973 * We don't need to rewrite the page-tables if either we've done 1974 * it already or we have KASLR enabled and therefore have not 1975 * created any global mappings at all. 1976 */ 1977 if (arm64_use_ng_mappings) 1978 return; 1979 1980 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 1981 } 1982 1983 #else 1984 static inline void kpti_install_ng_mappings(void) 1985 { 1986 } 1987 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 1988 1989 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1990 { 1991 if (__this_cpu_read(this_cpu_vector) == vectors) { 1992 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1993 1994 __this_cpu_write(this_cpu_vector, v); 1995 } 1996 1997 } 1998 1999 static int __init parse_kpti(char *str) 2000 { 2001 bool enabled; 2002 int ret = kstrtobool(str, &enabled); 2003 2004 if (ret) 2005 return ret; 2006 2007 __kpti_forced = enabled ? 1 : -1; 2008 return 0; 2009 } 2010 early_param("kpti", parse_kpti); 2011 2012 #ifdef CONFIG_ARM64_HW_AFDBM 2013 static struct cpumask dbm_cpus __read_mostly; 2014 2015 static inline void __cpu_enable_hw_dbm(void) 2016 { 2017 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2018 2019 write_sysreg(tcr, tcr_el1); 2020 isb(); 2021 local_flush_tlb_all(); 2022 } 2023 2024 static bool cpu_has_broken_dbm(void) 2025 { 2026 /* List of CPUs which have broken DBM support. */ 2027 static const struct midr_range cpus[] = { 2028 #ifdef CONFIG_ARM64_ERRATUM_1024718 2029 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2030 /* Kryo4xx Silver (rdpe => r1p0) */ 2031 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2032 #endif 2033 #ifdef CONFIG_ARM64_ERRATUM_2051678 2034 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2035 #endif 2036 {}, 2037 }; 2038 2039 return is_midr_in_range_list(read_cpuid_id(), cpus); 2040 } 2041 2042 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2043 { 2044 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2045 !cpu_has_broken_dbm(); 2046 } 2047 2048 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2049 { 2050 if (cpu_can_use_dbm(cap)) { 2051 __cpu_enable_hw_dbm(); 2052 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2053 } 2054 } 2055 2056 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2057 int __unused) 2058 { 2059 /* 2060 * DBM is a non-conflicting feature. i.e, the kernel can safely 2061 * run a mix of CPUs with and without the feature. So, we 2062 * unconditionally enable the capability to allow any late CPU 2063 * to use the feature. We only enable the control bits on the 2064 * CPU, if it is supported. 2065 */ 2066 2067 return true; 2068 } 2069 2070 #endif 2071 2072 #ifdef CONFIG_ARM64_AMU_EXTN 2073 2074 /* 2075 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2076 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2077 * information regarding all the events that it supports. When a CPU bit is 2078 * set in the cpumask, the user of this feature can only rely on the presence 2079 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2080 * counters are enabled or access to these counters is enabled by code 2081 * executed at higher exception levels (firmware). 2082 */ 2083 static struct cpumask amu_cpus __read_mostly; 2084 2085 bool cpu_has_amu_feat(int cpu) 2086 { 2087 return cpumask_test_cpu(cpu, &amu_cpus); 2088 } 2089 2090 int get_cpu_with_amu_feat(void) 2091 { 2092 return cpumask_any(&amu_cpus); 2093 } 2094 2095 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2096 { 2097 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2098 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2099 2100 /* 0 reference values signal broken/disabled counters */ 2101 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2102 update_freq_counters_refs(); 2103 } 2104 } 2105 2106 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2107 int __unused) 2108 { 2109 /* 2110 * The AMU extension is a non-conflicting feature: the kernel can 2111 * safely run a mix of CPUs with and without support for the 2112 * activity monitors extension. Therefore, unconditionally enable 2113 * the capability to allow any late CPU to use the feature. 2114 * 2115 * With this feature unconditionally enabled, the cpu_enable 2116 * function will be called for all CPUs that match the criteria, 2117 * including secondary and hotplugged, marking this feature as 2118 * present on that respective CPU. The enable function will also 2119 * print a detection message. 2120 */ 2121 2122 return true; 2123 } 2124 #else 2125 int get_cpu_with_amu_feat(void) 2126 { 2127 return nr_cpu_ids; 2128 } 2129 #endif 2130 2131 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2132 { 2133 return is_kernel_in_hyp_mode(); 2134 } 2135 2136 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2137 { 2138 /* 2139 * Copy register values that aren't redirected by hardware. 2140 * 2141 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2142 * this value to tpidr_el2 before we patch the code. Once we've done 2143 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2144 * do anything here. 2145 */ 2146 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2147 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2148 } 2149 2150 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2151 int scope) 2152 { 2153 if (kvm_get_mode() != KVM_MODE_NV) 2154 return false; 2155 2156 if (!has_cpuid_feature(cap, scope)) { 2157 pr_warn("unavailable: %s\n", cap->desc); 2158 return false; 2159 } 2160 2161 return true; 2162 } 2163 2164 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2165 int __unused) 2166 { 2167 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2168 } 2169 2170 #ifdef CONFIG_ARM64_PAN 2171 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2172 { 2173 /* 2174 * We modify PSTATE. This won't work from irq context as the PSTATE 2175 * is discarded once we return from the exception. 2176 */ 2177 WARN_ON_ONCE(in_interrupt()); 2178 2179 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2180 set_pstate_pan(1); 2181 } 2182 #endif /* CONFIG_ARM64_PAN */ 2183 2184 #ifdef CONFIG_ARM64_RAS_EXTN 2185 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2186 { 2187 /* Firmware may have left a deferred SError in this register. */ 2188 write_sysreg_s(0, SYS_DISR_EL1); 2189 } 2190 #endif /* CONFIG_ARM64_RAS_EXTN */ 2191 2192 #ifdef CONFIG_ARM64_PTR_AUTH 2193 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2194 { 2195 int boot_val, sec_val; 2196 2197 /* We don't expect to be called with SCOPE_SYSTEM */ 2198 WARN_ON(scope == SCOPE_SYSTEM); 2199 /* 2200 * The ptr-auth feature levels are not intercompatible with lower 2201 * levels. Hence we must match ptr-auth feature level of the secondary 2202 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2203 * from the sanitised register whereas direct register read is done for 2204 * the secondary CPUs. 2205 * The sanitised feature state is guaranteed to match that of the 2206 * boot CPU as a mismatched secondary CPU is parked before it gets 2207 * a chance to update the state, with the capability. 2208 */ 2209 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2210 entry->field_pos, entry->sign); 2211 if (scope & SCOPE_BOOT_CPU) 2212 return boot_val >= entry->min_field_value; 2213 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2214 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2215 entry->field_pos, entry->sign); 2216 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2217 } 2218 2219 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2220 int scope) 2221 { 2222 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2223 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2224 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2225 2226 return apa || apa3 || api; 2227 } 2228 2229 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2230 int __unused) 2231 { 2232 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2233 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2234 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2235 2236 return gpa || gpa3 || gpi; 2237 } 2238 #endif /* CONFIG_ARM64_PTR_AUTH */ 2239 2240 #ifdef CONFIG_ARM64_E0PD 2241 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2242 { 2243 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2244 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2245 } 2246 #endif /* CONFIG_ARM64_E0PD */ 2247 2248 #ifdef CONFIG_ARM64_PSEUDO_NMI 2249 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2250 int scope) 2251 { 2252 /* 2253 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2254 * feature, so will be detected earlier. 2255 */ 2256 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2257 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2258 return false; 2259 2260 return enable_pseudo_nmi; 2261 } 2262 2263 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2264 int scope) 2265 { 2266 /* 2267 * If we're not using priority masking then we won't be poking PMR_EL1, 2268 * and there's no need to relax synchronization of writes to it, and 2269 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2270 * that. 2271 * 2272 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2273 * feature, so will be detected earlier. 2274 */ 2275 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2276 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2277 return false; 2278 2279 /* 2280 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2281 * hint for interrupt distribution, a DSB is not necessary when 2282 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2283 * 2284 * Linux itself doesn't use 1:N distribution, so has no need to 2285 * set PMHE. The only reason to have it set is if EL3 requires it 2286 * (and we can't change it). 2287 */ 2288 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2289 } 2290 #endif 2291 2292 #ifdef CONFIG_ARM64_BTI 2293 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2294 { 2295 /* 2296 * Use of X16/X17 for tail-calls and trampolines that jump to 2297 * function entry points using BR is a requirement for 2298 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2299 * So, be strict and forbid other BRs using other registers to 2300 * jump onto a PACIxSP instruction: 2301 */ 2302 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2303 isb(); 2304 } 2305 #endif /* CONFIG_ARM64_BTI */ 2306 2307 #ifdef CONFIG_ARM64_MTE 2308 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2309 { 2310 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2311 2312 mte_cpu_setup(); 2313 2314 /* 2315 * Clear the tags in the zero page. This needs to be done via the 2316 * linear map which has the Tagged attribute. 2317 */ 2318 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2319 mte_clear_page_tags(lm_alias(empty_zero_page)); 2320 set_page_mte_tagged(ZERO_PAGE(0)); 2321 } 2322 2323 kasan_init_hw_tags_cpu(); 2324 } 2325 #endif /* CONFIG_ARM64_MTE */ 2326 2327 static void user_feature_fixup(void) 2328 { 2329 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2330 struct arm64_ftr_reg *regp; 2331 2332 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2333 if (regp) 2334 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2335 } 2336 2337 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2338 struct arm64_ftr_reg *regp; 2339 2340 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2341 if (regp) 2342 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2343 } 2344 } 2345 2346 static void elf_hwcap_fixup(void) 2347 { 2348 #ifdef CONFIG_COMPAT 2349 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2350 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2351 #endif /* CONFIG_COMPAT */ 2352 } 2353 2354 #ifdef CONFIG_KVM 2355 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2356 { 2357 return kvm_get_mode() == KVM_MODE_PROTECTED; 2358 } 2359 #endif /* CONFIG_KVM */ 2360 2361 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2362 { 2363 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2364 } 2365 2366 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2367 { 2368 set_pstate_dit(1); 2369 } 2370 2371 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2372 { 2373 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2374 } 2375 2376 #ifdef CONFIG_ARM64_POE 2377 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2378 { 2379 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); 2380 sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); 2381 } 2382 #endif 2383 2384 #ifdef CONFIG_ARM64_GCS 2385 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2386 { 2387 /* GCSPR_EL0 is always readable */ 2388 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2389 } 2390 #endif 2391 2392 /* Internal helper functions to match cpu capability type */ 2393 static bool 2394 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2395 { 2396 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2397 } 2398 2399 static bool 2400 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2401 { 2402 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2403 } 2404 2405 static bool 2406 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2407 { 2408 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2409 } 2410 2411 static bool 2412 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2413 { 2414 if (!has_cpuid_feature(entry, scope)) 2415 return false; 2416 2417 /* Check firmware actually enabled MPAM on this cpu. */ 2418 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2419 } 2420 2421 static void 2422 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2423 { 2424 /* 2425 * Access by the kernel (at EL1) should use the reserved PARTID 2426 * which is configured unrestricted. This avoids priority-inversion 2427 * where latency sensitive tasks have to wait for a task that has 2428 * been throttled to release the lock. 2429 */ 2430 write_sysreg_s(0, SYS_MPAM1_EL1); 2431 } 2432 2433 static bool 2434 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2435 { 2436 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2437 2438 return idr & MPAMIDR_EL1_HAS_HCR; 2439 } 2440 2441 static const struct arm64_cpu_capabilities arm64_features[] = { 2442 { 2443 .capability = ARM64_ALWAYS_BOOT, 2444 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2445 .matches = has_always, 2446 }, 2447 { 2448 .capability = ARM64_ALWAYS_SYSTEM, 2449 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2450 .matches = has_always, 2451 }, 2452 { 2453 .desc = "GIC system register CPU interface", 2454 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2455 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2456 .matches = has_useable_gicv3_cpuif, 2457 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2458 }, 2459 { 2460 .desc = "Enhanced Counter Virtualization", 2461 .capability = ARM64_HAS_ECV, 2462 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2463 .matches = has_cpuid_feature, 2464 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2465 }, 2466 { 2467 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2468 .capability = ARM64_HAS_ECV_CNTPOFF, 2469 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2470 .matches = has_cpuid_feature, 2471 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2472 }, 2473 #ifdef CONFIG_ARM64_PAN 2474 { 2475 .desc = "Privileged Access Never", 2476 .capability = ARM64_HAS_PAN, 2477 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2478 .matches = has_cpuid_feature, 2479 .cpu_enable = cpu_enable_pan, 2480 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2481 }, 2482 #endif /* CONFIG_ARM64_PAN */ 2483 #ifdef CONFIG_ARM64_EPAN 2484 { 2485 .desc = "Enhanced Privileged Access Never", 2486 .capability = ARM64_HAS_EPAN, 2487 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2488 .matches = has_cpuid_feature, 2489 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2490 }, 2491 #endif /* CONFIG_ARM64_EPAN */ 2492 #ifdef CONFIG_ARM64_LSE_ATOMICS 2493 { 2494 .desc = "LSE atomic instructions", 2495 .capability = ARM64_HAS_LSE_ATOMICS, 2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2497 .matches = has_cpuid_feature, 2498 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2499 }, 2500 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2501 { 2502 .desc = "Virtualization Host Extensions", 2503 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2504 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2505 .matches = runs_at_el2, 2506 .cpu_enable = cpu_copy_el2regs, 2507 }, 2508 { 2509 .desc = "Nested Virtualization Support", 2510 .capability = ARM64_HAS_NESTED_VIRT, 2511 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2512 .matches = has_nested_virt_support, 2513 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2514 }, 2515 { 2516 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2517 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2518 .matches = has_32bit_el0, 2519 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2520 }, 2521 #ifdef CONFIG_KVM 2522 { 2523 .desc = "32-bit EL1 Support", 2524 .capability = ARM64_HAS_32BIT_EL1, 2525 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2526 .matches = has_cpuid_feature, 2527 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2528 }, 2529 { 2530 .desc = "Protected KVM", 2531 .capability = ARM64_KVM_PROTECTED_MODE, 2532 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2533 .matches = is_kvm_protected_mode, 2534 }, 2535 { 2536 .desc = "HCRX_EL2 register", 2537 .capability = ARM64_HAS_HCX, 2538 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2539 .matches = has_cpuid_feature, 2540 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2541 }, 2542 #endif 2543 { 2544 .desc = "Kernel page table isolation (KPTI)", 2545 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2546 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2547 .cpu_enable = cpu_enable_kpti, 2548 .matches = unmap_kernel_at_el0, 2549 /* 2550 * The ID feature fields below are used to indicate that 2551 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2552 * more details. 2553 */ 2554 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2555 }, 2556 { 2557 .capability = ARM64_HAS_FPSIMD, 2558 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2559 .matches = has_cpuid_feature, 2560 .cpu_enable = cpu_enable_fpsimd, 2561 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2562 }, 2563 #ifdef CONFIG_ARM64_PMEM 2564 { 2565 .desc = "Data cache clean to Point of Persistence", 2566 .capability = ARM64_HAS_DCPOP, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_cpuid_feature, 2569 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2570 }, 2571 { 2572 .desc = "Data cache clean to Point of Deep Persistence", 2573 .capability = ARM64_HAS_DCPODP, 2574 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2575 .matches = has_cpuid_feature, 2576 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2577 }, 2578 #endif 2579 #ifdef CONFIG_ARM64_SVE 2580 { 2581 .desc = "Scalable Vector Extension", 2582 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2583 .capability = ARM64_SVE, 2584 .cpu_enable = cpu_enable_sve, 2585 .matches = has_cpuid_feature, 2586 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2587 }, 2588 #endif /* CONFIG_ARM64_SVE */ 2589 #ifdef CONFIG_ARM64_RAS_EXTN 2590 { 2591 .desc = "RAS Extension Support", 2592 .capability = ARM64_HAS_RAS_EXTN, 2593 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2594 .matches = has_cpuid_feature, 2595 .cpu_enable = cpu_clear_disr, 2596 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2597 }, 2598 #endif /* CONFIG_ARM64_RAS_EXTN */ 2599 #ifdef CONFIG_ARM64_AMU_EXTN 2600 { 2601 .desc = "Activity Monitors Unit (AMU)", 2602 .capability = ARM64_HAS_AMU_EXTN, 2603 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2604 .matches = has_amu, 2605 .cpu_enable = cpu_amu_enable, 2606 .cpus = &amu_cpus, 2607 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2608 }, 2609 #endif /* CONFIG_ARM64_AMU_EXTN */ 2610 { 2611 .desc = "Data cache clean to the PoU not required for I/D coherence", 2612 .capability = ARM64_HAS_CACHE_IDC, 2613 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2614 .matches = has_cache_idc, 2615 .cpu_enable = cpu_emulate_effective_ctr, 2616 }, 2617 { 2618 .desc = "Instruction cache invalidation not required for I/D coherence", 2619 .capability = ARM64_HAS_CACHE_DIC, 2620 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2621 .matches = has_cache_dic, 2622 }, 2623 { 2624 .desc = "Stage-2 Force Write-Back", 2625 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2626 .capability = ARM64_HAS_STAGE2_FWB, 2627 .matches = has_cpuid_feature, 2628 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2629 }, 2630 { 2631 .desc = "ARMv8.4 Translation Table Level", 2632 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2633 .capability = ARM64_HAS_ARMv8_4_TTL, 2634 .matches = has_cpuid_feature, 2635 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2636 }, 2637 { 2638 .desc = "TLB range maintenance instructions", 2639 .capability = ARM64_HAS_TLB_RANGE, 2640 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2641 .matches = has_cpuid_feature, 2642 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2643 }, 2644 #ifdef CONFIG_ARM64_HW_AFDBM 2645 { 2646 .desc = "Hardware dirty bit management", 2647 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2648 .capability = ARM64_HW_DBM, 2649 .matches = has_hw_dbm, 2650 .cpu_enable = cpu_enable_hw_dbm, 2651 .cpus = &dbm_cpus, 2652 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2653 }, 2654 #endif 2655 #ifdef CONFIG_ARM64_HAFT 2656 { 2657 .desc = "Hardware managed Access Flag for Table Descriptors", 2658 /* 2659 * Contrary to the page/block access flag, the table access flag 2660 * cannot be emulated in software (no access fault will occur). 2661 * Therefore this should be used only if it's supported system 2662 * wide. 2663 */ 2664 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2665 .capability = ARM64_HAFT, 2666 .matches = has_cpuid_feature, 2667 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2668 }, 2669 #endif 2670 { 2671 .desc = "CRC32 instructions", 2672 .capability = ARM64_HAS_CRC32, 2673 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2674 .matches = has_cpuid_feature, 2675 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2676 }, 2677 { 2678 .desc = "Speculative Store Bypassing Safe (SSBS)", 2679 .capability = ARM64_SSBS, 2680 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2681 .matches = has_cpuid_feature, 2682 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2683 }, 2684 #ifdef CONFIG_ARM64_CNP 2685 { 2686 .desc = "Common not Private translations", 2687 .capability = ARM64_HAS_CNP, 2688 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2689 .matches = has_useable_cnp, 2690 .cpu_enable = cpu_enable_cnp, 2691 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2692 }, 2693 #endif 2694 { 2695 .desc = "Speculation barrier (SB)", 2696 .capability = ARM64_HAS_SB, 2697 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2698 .matches = has_cpuid_feature, 2699 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2700 }, 2701 #ifdef CONFIG_ARM64_PTR_AUTH 2702 { 2703 .desc = "Address authentication (architected QARMA5 algorithm)", 2704 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2705 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2706 .matches = has_address_auth_cpucap, 2707 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2708 }, 2709 { 2710 .desc = "Address authentication (architected QARMA3 algorithm)", 2711 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2712 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2713 .matches = has_address_auth_cpucap, 2714 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2715 }, 2716 { 2717 .desc = "Address authentication (IMP DEF algorithm)", 2718 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2719 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2720 .matches = has_address_auth_cpucap, 2721 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2722 }, 2723 { 2724 .capability = ARM64_HAS_ADDRESS_AUTH, 2725 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2726 .matches = has_address_auth_metacap, 2727 }, 2728 { 2729 .desc = "Generic authentication (architected QARMA5 algorithm)", 2730 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2731 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2732 .matches = has_cpuid_feature, 2733 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2734 }, 2735 { 2736 .desc = "Generic authentication (architected QARMA3 algorithm)", 2737 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2738 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2739 .matches = has_cpuid_feature, 2740 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2741 }, 2742 { 2743 .desc = "Generic authentication (IMP DEF algorithm)", 2744 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2745 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2746 .matches = has_cpuid_feature, 2747 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2748 }, 2749 { 2750 .capability = ARM64_HAS_GENERIC_AUTH, 2751 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2752 .matches = has_generic_auth, 2753 }, 2754 #endif /* CONFIG_ARM64_PTR_AUTH */ 2755 #ifdef CONFIG_ARM64_PSEUDO_NMI 2756 { 2757 /* 2758 * Depends on having GICv3 2759 */ 2760 .desc = "IRQ priority masking", 2761 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2762 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2763 .matches = can_use_gic_priorities, 2764 }, 2765 { 2766 /* 2767 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2768 */ 2769 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2770 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2771 .matches = has_gic_prio_relaxed_sync, 2772 }, 2773 #endif 2774 #ifdef CONFIG_ARM64_E0PD 2775 { 2776 .desc = "E0PD", 2777 .capability = ARM64_HAS_E0PD, 2778 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2779 .cpu_enable = cpu_enable_e0pd, 2780 .matches = has_cpuid_feature, 2781 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2782 }, 2783 #endif 2784 { 2785 .desc = "Random Number Generator", 2786 .capability = ARM64_HAS_RNG, 2787 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2788 .matches = has_cpuid_feature, 2789 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2790 }, 2791 #ifdef CONFIG_ARM64_BTI 2792 { 2793 .desc = "Branch Target Identification", 2794 .capability = ARM64_BTI, 2795 #ifdef CONFIG_ARM64_BTI_KERNEL 2796 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2797 #else 2798 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2799 #endif 2800 .matches = has_cpuid_feature, 2801 .cpu_enable = bti_enable, 2802 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2803 }, 2804 #endif 2805 #ifdef CONFIG_ARM64_MTE 2806 { 2807 .desc = "Memory Tagging Extension", 2808 .capability = ARM64_MTE, 2809 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2810 .matches = has_cpuid_feature, 2811 .cpu_enable = cpu_enable_mte, 2812 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2813 }, 2814 { 2815 .desc = "Asymmetric MTE Tag Check Fault", 2816 .capability = ARM64_MTE_ASYMM, 2817 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2818 .matches = has_cpuid_feature, 2819 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2820 }, 2821 #endif /* CONFIG_ARM64_MTE */ 2822 { 2823 .desc = "RCpc load-acquire (LDAPR)", 2824 .capability = ARM64_HAS_LDAPR, 2825 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2826 .matches = has_cpuid_feature, 2827 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2828 }, 2829 { 2830 .desc = "Fine Grained Traps", 2831 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2832 .capability = ARM64_HAS_FGT, 2833 .matches = has_cpuid_feature, 2834 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2835 }, 2836 #ifdef CONFIG_ARM64_SME 2837 { 2838 .desc = "Scalable Matrix Extension", 2839 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2840 .capability = ARM64_SME, 2841 .matches = has_cpuid_feature, 2842 .cpu_enable = cpu_enable_sme, 2843 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2844 }, 2845 /* FA64 should be sorted after the base SME capability */ 2846 { 2847 .desc = "FA64", 2848 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2849 .capability = ARM64_SME_FA64, 2850 .matches = has_cpuid_feature, 2851 .cpu_enable = cpu_enable_fa64, 2852 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2853 }, 2854 { 2855 .desc = "SME2", 2856 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2857 .capability = ARM64_SME2, 2858 .matches = has_cpuid_feature, 2859 .cpu_enable = cpu_enable_sme2, 2860 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2861 }, 2862 #endif /* CONFIG_ARM64_SME */ 2863 { 2864 .desc = "WFx with timeout", 2865 .capability = ARM64_HAS_WFXT, 2866 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2867 .matches = has_cpuid_feature, 2868 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2869 }, 2870 { 2871 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2872 .capability = ARM64_HAS_TIDCP1, 2873 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2874 .matches = has_cpuid_feature, 2875 .cpu_enable = cpu_trap_el0_impdef, 2876 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2877 }, 2878 { 2879 .desc = "Data independent timing control (DIT)", 2880 .capability = ARM64_HAS_DIT, 2881 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2882 .matches = has_cpuid_feature, 2883 .cpu_enable = cpu_enable_dit, 2884 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2885 }, 2886 { 2887 .desc = "Memory Copy and Memory Set instructions", 2888 .capability = ARM64_HAS_MOPS, 2889 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2890 .matches = has_cpuid_feature, 2891 .cpu_enable = cpu_enable_mops, 2892 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2893 }, 2894 { 2895 .capability = ARM64_HAS_TCR2, 2896 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2897 .matches = has_cpuid_feature, 2898 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2899 }, 2900 { 2901 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2902 .capability = ARM64_HAS_S1PIE, 2903 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2904 .matches = has_cpuid_feature, 2905 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2906 }, 2907 { 2908 .desc = "VHE for hypervisor only", 2909 .capability = ARM64_KVM_HVHE, 2910 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2911 .matches = hvhe_possible, 2912 }, 2913 { 2914 .desc = "Enhanced Virtualization Traps", 2915 .capability = ARM64_HAS_EVT, 2916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2917 .matches = has_cpuid_feature, 2918 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2919 }, 2920 { 2921 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2922 .capability = ARM64_HAS_LPA2, 2923 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2924 .matches = has_lpa2, 2925 }, 2926 { 2927 .desc = "FPMR", 2928 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2929 .capability = ARM64_HAS_FPMR, 2930 .matches = has_cpuid_feature, 2931 .cpu_enable = cpu_enable_fpmr, 2932 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2933 }, 2934 #ifdef CONFIG_ARM64_VA_BITS_52 2935 { 2936 .capability = ARM64_HAS_VA52, 2937 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2938 .matches = has_cpuid_feature, 2939 #ifdef CONFIG_ARM64_64K_PAGES 2940 .desc = "52-bit Virtual Addressing (LVA)", 2941 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 2942 #else 2943 .desc = "52-bit Virtual Addressing (LPA2)", 2944 #ifdef CONFIG_ARM64_4K_PAGES 2945 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 2946 #else 2947 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 2948 #endif 2949 #endif 2950 }, 2951 #endif 2952 { 2953 .desc = "Memory Partitioning And Monitoring", 2954 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2955 .capability = ARM64_MPAM, 2956 .matches = test_has_mpam, 2957 .cpu_enable = cpu_enable_mpam, 2958 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 2959 }, 2960 { 2961 .desc = "Memory Partitioning And Monitoring Virtualisation", 2962 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2963 .capability = ARM64_MPAM_HCR, 2964 .matches = test_has_mpam_hcr, 2965 }, 2966 { 2967 .desc = "NV1", 2968 .capability = ARM64_HAS_HCR_NV1, 2969 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2970 .matches = has_nv1, 2971 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 2972 }, 2973 #ifdef CONFIG_ARM64_POE 2974 { 2975 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 2976 .capability = ARM64_HAS_S1POE, 2977 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2978 .matches = has_cpuid_feature, 2979 .cpu_enable = cpu_enable_poe, 2980 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 2981 }, 2982 #endif 2983 #ifdef CONFIG_ARM64_GCS 2984 { 2985 .desc = "Guarded Control Stack (GCS)", 2986 .capability = ARM64_HAS_GCS, 2987 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2988 .cpu_enable = cpu_enable_gcs, 2989 .matches = has_cpuid_feature, 2990 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 2991 }, 2992 #endif 2993 {}, 2994 }; 2995 2996 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 2997 .matches = has_user_cpuid_feature, \ 2998 ARM64_CPUID_FIELDS(reg, field, min_value) 2999 3000 #define __HWCAP_CAP(name, cap_type, cap) \ 3001 .desc = name, \ 3002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3003 .hwcap_type = cap_type, \ 3004 .hwcap = cap, \ 3005 3006 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3007 { \ 3008 __HWCAP_CAP(#cap, cap_type, cap) \ 3009 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3010 } 3011 3012 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3013 { \ 3014 __HWCAP_CAP(#cap, cap_type, cap) \ 3015 .matches = cpucap_multi_entry_cap_matches, \ 3016 .match_list = list, \ 3017 } 3018 3019 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3020 { \ 3021 __HWCAP_CAP(#cap, cap_type, cap) \ 3022 .matches = match, \ 3023 } 3024 3025 #ifdef CONFIG_ARM64_PTR_AUTH 3026 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3027 { 3028 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3029 }, 3030 { 3031 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3032 }, 3033 { 3034 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3035 }, 3036 {}, 3037 }; 3038 3039 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3040 { 3041 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3042 }, 3043 { 3044 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3045 }, 3046 { 3047 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3048 }, 3049 {}, 3050 }; 3051 #endif 3052 3053 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3054 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3055 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3056 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3057 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3058 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3059 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3060 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3061 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3062 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3063 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3064 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3065 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3066 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3067 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3068 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3069 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3070 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3071 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3072 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3073 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3074 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3075 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3076 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3077 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3078 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3079 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3080 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3081 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3082 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3083 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3084 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3085 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3086 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3087 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3088 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3089 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3090 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3091 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3092 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3093 #ifdef CONFIG_ARM64_SVE 3094 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3095 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3096 HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3097 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3098 HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3099 HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3100 HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3101 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3102 HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3103 HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3104 HWCAP_CAP(ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3105 HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3106 HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3107 HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3108 #endif 3109 #ifdef CONFIG_ARM64_GCS 3110 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3111 #endif 3112 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3113 #ifdef CONFIG_ARM64_BTI 3114 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3115 #endif 3116 #ifdef CONFIG_ARM64_PTR_AUTH 3117 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3118 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3119 #endif 3120 #ifdef CONFIG_ARM64_MTE 3121 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3122 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3123 #endif /* CONFIG_ARM64_MTE */ 3124 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3125 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3126 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3127 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3128 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3129 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3130 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3131 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3132 #ifdef CONFIG_ARM64_SME 3133 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3134 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3135 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3136 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3137 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3138 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3139 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3140 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3141 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3142 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3143 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3144 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3145 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3146 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3147 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3148 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3149 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3150 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3151 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3152 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3153 #endif /* CONFIG_ARM64_SME */ 3154 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3155 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3156 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3157 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3158 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3159 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3160 #ifdef CONFIG_ARM64_POE 3161 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3162 #endif 3163 {}, 3164 }; 3165 3166 #ifdef CONFIG_COMPAT 3167 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3168 { 3169 /* 3170 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3171 * in line with that of arm32 as in vfp_init(). We make sure that the 3172 * check is future proof, by making sure value is non-zero. 3173 */ 3174 u32 mvfr1; 3175 3176 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3177 if (scope == SCOPE_SYSTEM) 3178 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3179 else 3180 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3181 3182 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3183 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3184 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3185 } 3186 #endif 3187 3188 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3189 #ifdef CONFIG_COMPAT 3190 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3191 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3192 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3193 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3194 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3195 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3196 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3197 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3198 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3199 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3200 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3201 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3202 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3203 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3204 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3205 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3206 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3207 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3208 #endif 3209 {}, 3210 }; 3211 3212 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3213 { 3214 switch (cap->hwcap_type) { 3215 case CAP_HWCAP: 3216 cpu_set_feature(cap->hwcap); 3217 break; 3218 #ifdef CONFIG_COMPAT 3219 case CAP_COMPAT_HWCAP: 3220 compat_elf_hwcap |= (u32)cap->hwcap; 3221 break; 3222 case CAP_COMPAT_HWCAP2: 3223 compat_elf_hwcap2 |= (u32)cap->hwcap; 3224 break; 3225 #endif 3226 default: 3227 WARN_ON(1); 3228 break; 3229 } 3230 } 3231 3232 /* Check if we have a particular HWCAP enabled */ 3233 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3234 { 3235 bool rc; 3236 3237 switch (cap->hwcap_type) { 3238 case CAP_HWCAP: 3239 rc = cpu_have_feature(cap->hwcap); 3240 break; 3241 #ifdef CONFIG_COMPAT 3242 case CAP_COMPAT_HWCAP: 3243 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3244 break; 3245 case CAP_COMPAT_HWCAP2: 3246 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3247 break; 3248 #endif 3249 default: 3250 WARN_ON(1); 3251 rc = false; 3252 } 3253 3254 return rc; 3255 } 3256 3257 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3258 { 3259 /* We support emulation of accesses to CPU ID feature registers */ 3260 cpu_set_named_feature(CPUID); 3261 for (; hwcaps->matches; hwcaps++) 3262 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3263 cap_set_elf_hwcap(hwcaps); 3264 } 3265 3266 static void update_cpu_capabilities(u16 scope_mask) 3267 { 3268 int i; 3269 const struct arm64_cpu_capabilities *caps; 3270 3271 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3272 for (i = 0; i < ARM64_NCAPS; i++) { 3273 caps = cpucap_ptrs[i]; 3274 if (!caps || !(caps->type & scope_mask) || 3275 cpus_have_cap(caps->capability) || 3276 !caps->matches(caps, cpucap_default_scope(caps))) 3277 continue; 3278 3279 if (caps->desc && !caps->cpus) 3280 pr_info("detected: %s\n", caps->desc); 3281 3282 __set_bit(caps->capability, system_cpucaps); 3283 3284 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3285 set_bit(caps->capability, boot_cpucaps); 3286 } 3287 } 3288 3289 /* 3290 * Enable all the available capabilities on this CPU. The capabilities 3291 * with BOOT_CPU scope are handled separately and hence skipped here. 3292 */ 3293 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3294 { 3295 int i; 3296 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3297 3298 for_each_available_cap(i) { 3299 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3300 3301 if (WARN_ON(!cap)) 3302 continue; 3303 3304 if (!(cap->type & non_boot_scope)) 3305 continue; 3306 3307 if (cap->cpu_enable) 3308 cap->cpu_enable(cap); 3309 } 3310 return 0; 3311 } 3312 3313 /* 3314 * Run through the enabled capabilities and enable() it on all active 3315 * CPUs 3316 */ 3317 static void __init enable_cpu_capabilities(u16 scope_mask) 3318 { 3319 int i; 3320 const struct arm64_cpu_capabilities *caps; 3321 bool boot_scope; 3322 3323 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3324 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3325 3326 for (i = 0; i < ARM64_NCAPS; i++) { 3327 caps = cpucap_ptrs[i]; 3328 if (!caps || !(caps->type & scope_mask) || 3329 !cpus_have_cap(caps->capability)) 3330 continue; 3331 3332 if (boot_scope && caps->cpu_enable) 3333 /* 3334 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3335 * before any secondary CPU boots. Thus, each secondary 3336 * will enable the capability as appropriate via 3337 * check_local_cpu_capabilities(). The only exception is 3338 * the boot CPU, for which the capability must be 3339 * enabled here. This approach avoids costly 3340 * stop_machine() calls for this case. 3341 */ 3342 caps->cpu_enable(caps); 3343 } 3344 3345 /* 3346 * For all non-boot scope capabilities, use stop_machine() 3347 * as it schedules the work allowing us to modify PSTATE, 3348 * instead of on_each_cpu() which uses an IPI, giving us a 3349 * PSTATE that disappears when we return. 3350 */ 3351 if (!boot_scope) 3352 stop_machine(cpu_enable_non_boot_scope_capabilities, 3353 NULL, cpu_online_mask); 3354 } 3355 3356 /* 3357 * Run through the list of capabilities to check for conflicts. 3358 * If the system has already detected a capability, take necessary 3359 * action on this CPU. 3360 */ 3361 static void verify_local_cpu_caps(u16 scope_mask) 3362 { 3363 int i; 3364 bool cpu_has_cap, system_has_cap; 3365 const struct arm64_cpu_capabilities *caps; 3366 3367 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3368 3369 for (i = 0; i < ARM64_NCAPS; i++) { 3370 caps = cpucap_ptrs[i]; 3371 if (!caps || !(caps->type & scope_mask)) 3372 continue; 3373 3374 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3375 system_has_cap = cpus_have_cap(caps->capability); 3376 3377 if (system_has_cap) { 3378 /* 3379 * Check if the new CPU misses an advertised feature, 3380 * which is not safe to miss. 3381 */ 3382 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3383 break; 3384 /* 3385 * We have to issue cpu_enable() irrespective of 3386 * whether the CPU has it or not, as it is enabeld 3387 * system wide. It is upto the call back to take 3388 * appropriate action on this CPU. 3389 */ 3390 if (caps->cpu_enable) 3391 caps->cpu_enable(caps); 3392 } else { 3393 /* 3394 * Check if the CPU has this capability if it isn't 3395 * safe to have when the system doesn't. 3396 */ 3397 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3398 break; 3399 } 3400 } 3401 3402 if (i < ARM64_NCAPS) { 3403 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3404 smp_processor_id(), caps->capability, 3405 caps->desc, system_has_cap, cpu_has_cap); 3406 3407 if (cpucap_panic_on_conflict(caps)) 3408 cpu_panic_kernel(); 3409 else 3410 cpu_die_early(); 3411 } 3412 } 3413 3414 /* 3415 * Check for CPU features that are used in early boot 3416 * based on the Boot CPU value. 3417 */ 3418 static void check_early_cpu_features(void) 3419 { 3420 verify_cpu_asid_bits(); 3421 3422 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3423 } 3424 3425 static void 3426 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3427 { 3428 3429 for (; caps->matches; caps++) 3430 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3431 pr_crit("CPU%d: missing HWCAP: %s\n", 3432 smp_processor_id(), caps->desc); 3433 cpu_die_early(); 3434 } 3435 } 3436 3437 static void verify_local_elf_hwcaps(void) 3438 { 3439 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3440 3441 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3442 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3443 } 3444 3445 static void verify_sve_features(void) 3446 { 3447 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3448 3449 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3450 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3451 smp_processor_id()); 3452 cpu_die_early(); 3453 } 3454 3455 cpacr_restore(cpacr); 3456 } 3457 3458 static void verify_sme_features(void) 3459 { 3460 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3461 3462 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3463 pr_crit("CPU%d: SME: vector length support mismatch\n", 3464 smp_processor_id()); 3465 cpu_die_early(); 3466 } 3467 3468 cpacr_restore(cpacr); 3469 } 3470 3471 static void verify_hyp_capabilities(void) 3472 { 3473 u64 safe_mmfr1, mmfr0, mmfr1; 3474 int parange, ipa_max; 3475 unsigned int safe_vmid_bits, vmid_bits; 3476 3477 if (!IS_ENABLED(CONFIG_KVM)) 3478 return; 3479 3480 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3481 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 3482 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3483 3484 /* Verify VMID bits */ 3485 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3486 vmid_bits = get_vmid_bits(mmfr1); 3487 if (vmid_bits < safe_vmid_bits) { 3488 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3489 cpu_die_early(); 3490 } 3491 3492 /* Verify IPA range */ 3493 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3494 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3495 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3496 if (ipa_max < get_kvm_ipa_limit()) { 3497 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3498 cpu_die_early(); 3499 } 3500 } 3501 3502 static void verify_mpam_capabilities(void) 3503 { 3504 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3505 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3506 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3507 3508 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3509 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3510 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3511 cpu_die_early(); 3512 } 3513 3514 cpu_idr = read_cpuid(MPAMIDR_EL1); 3515 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3516 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3517 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3518 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3519 cpu_die_early(); 3520 } 3521 3522 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3523 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3524 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3525 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3526 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3527 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3528 cpu_die_early(); 3529 } 3530 } 3531 3532 /* 3533 * Run through the enabled system capabilities and enable() it on this CPU. 3534 * The capabilities were decided based on the available CPUs at the boot time. 3535 * Any new CPU should match the system wide status of the capability. If the 3536 * new CPU doesn't have a capability which the system now has enabled, we 3537 * cannot do anything to fix it up and could cause unexpected failures. So 3538 * we park the CPU. 3539 */ 3540 static void verify_local_cpu_capabilities(void) 3541 { 3542 /* 3543 * The capabilities with SCOPE_BOOT_CPU are checked from 3544 * check_early_cpu_features(), as they need to be verified 3545 * on all secondary CPUs. 3546 */ 3547 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3548 verify_local_elf_hwcaps(); 3549 3550 if (system_supports_sve()) 3551 verify_sve_features(); 3552 3553 if (system_supports_sme()) 3554 verify_sme_features(); 3555 3556 if (is_hyp_mode_available()) 3557 verify_hyp_capabilities(); 3558 3559 if (system_supports_mpam()) 3560 verify_mpam_capabilities(); 3561 } 3562 3563 void check_local_cpu_capabilities(void) 3564 { 3565 /* 3566 * All secondary CPUs should conform to the early CPU features 3567 * in use by the kernel based on boot CPU. 3568 */ 3569 check_early_cpu_features(); 3570 3571 /* 3572 * If we haven't finalised the system capabilities, this CPU gets 3573 * a chance to update the errata work arounds and local features. 3574 * Otherwise, this CPU should verify that it has all the system 3575 * advertised capabilities. 3576 */ 3577 if (!system_capabilities_finalized()) 3578 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3579 else 3580 verify_local_cpu_capabilities(); 3581 } 3582 3583 bool this_cpu_has_cap(unsigned int n) 3584 { 3585 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3586 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3587 3588 if (cap) 3589 return cap->matches(cap, SCOPE_LOCAL_CPU); 3590 } 3591 3592 return false; 3593 } 3594 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3595 3596 /* 3597 * This helper function is used in a narrow window when, 3598 * - The system wide safe registers are set with all the SMP CPUs and, 3599 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3600 */ 3601 static bool __maybe_unused __system_matches_cap(unsigned int n) 3602 { 3603 if (n < ARM64_NCAPS) { 3604 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3605 3606 if (cap) 3607 return cap->matches(cap, SCOPE_SYSTEM); 3608 } 3609 return false; 3610 } 3611 3612 void cpu_set_feature(unsigned int num) 3613 { 3614 set_bit(num, elf_hwcap); 3615 } 3616 3617 bool cpu_have_feature(unsigned int num) 3618 { 3619 return test_bit(num, elf_hwcap); 3620 } 3621 EXPORT_SYMBOL_GPL(cpu_have_feature); 3622 3623 unsigned long cpu_get_elf_hwcap(void) 3624 { 3625 /* 3626 * We currently only populate the first 32 bits of AT_HWCAP. Please 3627 * note that for userspace compatibility we guarantee that bits 62 3628 * and 63 will always be returned as 0. 3629 */ 3630 return elf_hwcap[0]; 3631 } 3632 3633 unsigned long cpu_get_elf_hwcap2(void) 3634 { 3635 return elf_hwcap[1]; 3636 } 3637 3638 unsigned long cpu_get_elf_hwcap3(void) 3639 { 3640 return elf_hwcap[2]; 3641 } 3642 3643 static void __init setup_boot_cpu_capabilities(void) 3644 { 3645 /* 3646 * The boot CPU's feature register values have been recorded. Detect 3647 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3648 * patch alternatives for the available boot cpucaps. 3649 */ 3650 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3651 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3652 apply_boot_alternatives(); 3653 } 3654 3655 void __init setup_boot_cpu_features(void) 3656 { 3657 /* 3658 * Initialize the indirect array of CPU capabilities pointers before we 3659 * handle the boot CPU. 3660 */ 3661 init_cpucap_indirect_list(); 3662 3663 /* 3664 * Detect broken pseudo-NMI. Must be called _before_ the call to 3665 * setup_boot_cpu_capabilities() since it interacts with 3666 * can_use_gic_priorities(). 3667 */ 3668 detect_system_supports_pseudo_nmi(); 3669 3670 setup_boot_cpu_capabilities(); 3671 } 3672 3673 static void __init setup_system_capabilities(void) 3674 { 3675 /* 3676 * The system-wide safe feature register values have been finalized. 3677 * Detect, enable, and patch alternatives for the available system 3678 * cpucaps. 3679 */ 3680 update_cpu_capabilities(SCOPE_SYSTEM); 3681 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3682 apply_alternatives_all(); 3683 3684 /* 3685 * Log any cpucaps with a cpumask as these aren't logged by 3686 * update_cpu_capabilities(). 3687 */ 3688 for (int i = 0; i < ARM64_NCAPS; i++) { 3689 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3690 3691 if (caps && caps->cpus && caps->desc && 3692 cpumask_any(caps->cpus) < nr_cpu_ids) 3693 pr_info("detected: %s on CPU%*pbl\n", 3694 caps->desc, cpumask_pr_args(caps->cpus)); 3695 } 3696 3697 /* 3698 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3699 */ 3700 if (system_uses_ttbr0_pan()) 3701 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3702 } 3703 3704 void __init setup_system_features(void) 3705 { 3706 setup_system_capabilities(); 3707 3708 kpti_install_ng_mappings(); 3709 3710 sve_setup(); 3711 sme_setup(); 3712 3713 /* 3714 * Check for sane CTR_EL0.CWG value. 3715 */ 3716 if (!cache_type_cwg()) 3717 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3718 ARCH_DMA_MINALIGN); 3719 } 3720 3721 void __init setup_user_features(void) 3722 { 3723 user_feature_fixup(); 3724 3725 setup_elf_hwcaps(arm64_elf_hwcaps); 3726 3727 if (system_supports_32bit_el0()) { 3728 setup_elf_hwcaps(compat_elf_hwcaps); 3729 elf_hwcap_fixup(); 3730 } 3731 3732 minsigstksz_setup(); 3733 } 3734 3735 static int enable_mismatched_32bit_el0(unsigned int cpu) 3736 { 3737 /* 3738 * The first 32-bit-capable CPU we detected and so can no longer 3739 * be offlined by userspace. -1 indicates we haven't yet onlined 3740 * a 32-bit-capable CPU. 3741 */ 3742 static int lucky_winner = -1; 3743 3744 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3745 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); 3746 3747 if (cpu_32bit) { 3748 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3749 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3750 } 3751 3752 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3753 return 0; 3754 3755 if (lucky_winner >= 0) 3756 return 0; 3757 3758 /* 3759 * We've detected a mismatch. We need to keep one of our CPUs with 3760 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3761 * every CPU in the system for a 32-bit task. 3762 */ 3763 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3764 cpu_active_mask); 3765 get_cpu_device(lucky_winner)->offline_disabled = true; 3766 setup_elf_hwcaps(compat_elf_hwcaps); 3767 elf_hwcap_fixup(); 3768 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3769 cpu, lucky_winner); 3770 return 0; 3771 } 3772 3773 static int __init init_32bit_el0_mask(void) 3774 { 3775 if (!allow_mismatched_32bit_el0) 3776 return 0; 3777 3778 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3779 return -ENOMEM; 3780 3781 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3782 "arm64/mismatched_32bit_el0:online", 3783 enable_mismatched_32bit_el0, NULL); 3784 } 3785 subsys_initcall_sync(init_32bit_el0_mask); 3786 3787 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3788 { 3789 cpu_enable_swapper_cnp(); 3790 } 3791 3792 /* 3793 * We emulate only the following system register space. 3794 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3795 * See Table C5-6 System instruction encodings for System register accesses, 3796 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3797 */ 3798 static inline bool __attribute_const__ is_emulated(u32 id) 3799 { 3800 return (sys_reg_Op0(id) == 0x3 && 3801 sys_reg_CRn(id) == 0x0 && 3802 sys_reg_Op1(id) == 0x0 && 3803 (sys_reg_CRm(id) == 0 || 3804 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3805 } 3806 3807 /* 3808 * With CRm == 0, reg should be one of : 3809 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3810 */ 3811 static inline int emulate_id_reg(u32 id, u64 *valp) 3812 { 3813 switch (id) { 3814 case SYS_MIDR_EL1: 3815 *valp = read_cpuid_id(); 3816 break; 3817 case SYS_MPIDR_EL1: 3818 *valp = SYS_MPIDR_SAFE_VAL; 3819 break; 3820 case SYS_REVIDR_EL1: 3821 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3822 *valp = 0; 3823 break; 3824 default: 3825 return -EINVAL; 3826 } 3827 3828 return 0; 3829 } 3830 3831 static int emulate_sys_reg(u32 id, u64 *valp) 3832 { 3833 struct arm64_ftr_reg *regp; 3834 3835 if (!is_emulated(id)) 3836 return -EINVAL; 3837 3838 if (sys_reg_CRm(id) == 0) 3839 return emulate_id_reg(id, valp); 3840 3841 regp = get_arm64_ftr_reg_nowarn(id); 3842 if (regp) 3843 *valp = arm64_ftr_reg_user_value(regp); 3844 else 3845 /* 3846 * The untracked registers are either IMPLEMENTATION DEFINED 3847 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3848 */ 3849 *valp = 0; 3850 return 0; 3851 } 3852 3853 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3854 { 3855 int rc; 3856 u64 val; 3857 3858 rc = emulate_sys_reg(sys_reg, &val); 3859 if (!rc) { 3860 pt_regs_write_reg(regs, rt, val); 3861 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3862 } 3863 return rc; 3864 } 3865 3866 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3867 { 3868 u32 sys_reg, rt; 3869 3870 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3871 return false; 3872 3873 /* 3874 * sys_reg values are defined as used in mrs/msr instruction. 3875 * shift the imm value to get the encoding. 3876 */ 3877 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3878 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3879 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3880 } 3881 3882 enum mitigation_state arm64_get_meltdown_state(void) 3883 { 3884 if (__meltdown_safe) 3885 return SPECTRE_UNAFFECTED; 3886 3887 if (arm64_kernel_unmapped_at_el0()) 3888 return SPECTRE_MITIGATED; 3889 3890 return SPECTRE_VULNERABLE; 3891 } 3892 3893 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3894 char *buf) 3895 { 3896 switch (arm64_get_meltdown_state()) { 3897 case SPECTRE_UNAFFECTED: 3898 return sprintf(buf, "Not affected\n"); 3899 3900 case SPECTRE_MITIGATED: 3901 return sprintf(buf, "Mitigation: PTI\n"); 3902 3903 default: 3904 return sprintf(buf, "Vulnerable\n"); 3905 } 3906 } 3907