1 /* 2 * Contains CPU feature definitions 3 * 4 * Copyright (C) 2015 ARM Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #define pr_fmt(fmt) "CPU features: " fmt 20 21 #include <linux/bsearch.h> 22 #include <linux/cpumask.h> 23 #include <linux/sort.h> 24 #include <linux/stop_machine.h> 25 #include <linux/types.h> 26 #include <linux/mm.h> 27 #include <asm/cpu.h> 28 #include <asm/cpufeature.h> 29 #include <asm/cpu_ops.h> 30 #include <asm/fpsimd.h> 31 #include <asm/mmu_context.h> 32 #include <asm/processor.h> 33 #include <asm/sysreg.h> 34 #include <asm/traps.h> 35 #include <asm/virt.h> 36 37 unsigned long elf_hwcap __read_mostly; 38 EXPORT_SYMBOL_GPL(elf_hwcap); 39 40 #ifdef CONFIG_COMPAT 41 #define COMPAT_ELF_HWCAP_DEFAULT \ 42 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 43 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 44 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\ 45 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 46 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\ 47 COMPAT_HWCAP_LPAE) 48 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 49 unsigned int compat_elf_hwcap2 __read_mostly; 50 #endif 51 52 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 53 EXPORT_SYMBOL(cpu_hwcaps); 54 55 /* 56 * Flag to indicate if we have computed the system wide 57 * capabilities based on the boot time active CPUs. This 58 * will be used to determine if a new booting CPU should 59 * go through the verification process to make sure that it 60 * supports the system capabilities, without using a hotplug 61 * notifier. 62 */ 63 static bool sys_caps_initialised; 64 65 static inline void set_sys_caps_initialised(void) 66 { 67 sys_caps_initialised = true; 68 } 69 70 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p) 71 { 72 /* file-wide pr_fmt adds "CPU features: " prefix */ 73 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps); 74 return 0; 75 } 76 77 static struct notifier_block cpu_hwcaps_notifier = { 78 .notifier_call = dump_cpu_hwcaps 79 }; 80 81 static int __init register_cpu_hwcaps_dumper(void) 82 { 83 atomic_notifier_chain_register(&panic_notifier_list, 84 &cpu_hwcaps_notifier); 85 return 0; 86 } 87 __initcall(register_cpu_hwcaps_dumper); 88 89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS); 90 EXPORT_SYMBOL(cpu_hwcap_keys); 91 92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 93 { \ 94 .sign = SIGNED, \ 95 .visible = VISIBLE, \ 96 .strict = STRICT, \ 97 .type = TYPE, \ 98 .shift = SHIFT, \ 99 .width = WIDTH, \ 100 .safe_val = SAFE_VAL, \ 101 } 102 103 /* Define a feature with unsigned values */ 104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 105 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 106 107 /* Define a feature with a signed value */ 108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 109 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 110 111 #define ARM64_FTR_END \ 112 { \ 113 .width = 0, \ 114 } 115 116 /* meta feature for alternatives */ 117 static bool __maybe_unused 118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused); 119 120 121 /* 122 * NOTE: Any changes to the visibility of features should be kept in 123 * sync with the documentation of the CPU feature register ABI. 124 */ 125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), 127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), 128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), 129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), 130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), 131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), 132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), 133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), 134 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), 135 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), 136 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), 137 ARM64_FTR_END, 138 }; 139 140 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 141 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0), 142 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0), 143 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0), 144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0), 145 ARM64_FTR_END, 146 }; 147 148 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 149 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), 150 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), 151 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 152 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0), 153 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0), 154 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0), 155 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI), 156 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI), 157 /* Linux doesn't care about the EL3 */ 158 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), 159 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), 160 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), 161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), 162 ARM64_FTR_END, 163 }; 164 165 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 166 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI), 167 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI), 168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI), 169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0), 170 /* Linux shouldn't care about secure memory */ 171 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0), 172 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0), 173 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0), 174 /* 175 * Differing PARange is fine as long as all peripherals and memory are mapped 176 * within the minimum PARange of all CPUs 177 */ 178 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0), 179 ARM64_FTR_END, 180 }; 181 182 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 183 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0), 184 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0), 185 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0), 186 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0), 187 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0), 188 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0), 189 ARM64_FTR_END, 190 }; 191 192 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 193 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0), 194 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0), 195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0), 196 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0), 197 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0), 198 ARM64_FTR_END, 199 }; 200 201 static const struct arm64_ftr_bits ftr_ctr[] = { 202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ 203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ 204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ 205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ 206 /* 207 * Linux can handle differing I-cache policies. Userspace JITs will 208 * make use of *minLine. 209 * If we have differing I-cache policies, report it as the weakest - VIPT. 210 */ 211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */ 212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* IminLine */ 213 ARM64_FTR_END, 214 }; 215 216 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 217 .name = "SYS_CTR_EL0", 218 .ftr_bits = ftr_ctr 219 }; 220 221 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 222 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */ 223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */ 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */ 225 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */ 226 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */ 227 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */ 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */ 229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */ 230 ARM64_FTR_END, 231 }; 232 233 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0), 235 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0), 239 /* 240 * We can instantiate multiple PMU instances with different levels 241 * of support. 242 */ 243 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6), 246 ARM64_FTR_END, 247 }; 248 249 static const struct arm64_ftr_bits ftr_mvfr2[] = { 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */ 251 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */ 252 ARM64_FTR_END, 253 }; 254 255 static const struct arm64_ftr_bits ftr_dczid[] = { 256 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */ 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */ 258 ARM64_FTR_END, 259 }; 260 261 262 static const struct arm64_ftr_bits ftr_id_isar5[] = { 263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0), 269 ARM64_FTR_END, 270 }; 271 272 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */ 274 ARM64_FTR_END, 275 }; 276 277 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 278 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */ 279 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */ 280 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */ 281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */ 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 287 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */ 288 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 292 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 294 ARM64_FTR_END, 295 }; 296 297 static const struct arm64_ftr_bits ftr_zcr[] = { 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 299 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */ 300 ARM64_FTR_END, 301 }; 302 303 /* 304 * Common ftr bits for a 32bit register with all hidden, strict 305 * attributes, with 4bit feature fields and a default safe value of 306 * 0. Covers the following 32bit registers: 307 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1] 308 */ 309 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 318 ARM64_FTR_END, 319 }; 320 321 /* Table for a single 32bit feature value */ 322 static const struct arm64_ftr_bits ftr_single32[] = { 323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 324 ARM64_FTR_END, 325 }; 326 327 static const struct arm64_ftr_bits ftr_raz[] = { 328 ARM64_FTR_END, 329 }; 330 331 #define ARM64_FTR_REG(id, table) { \ 332 .sys_id = id, \ 333 .reg = &(struct arm64_ftr_reg){ \ 334 .name = #id, \ 335 .ftr_bits = &((table)[0]), \ 336 }} 337 338 static const struct __ftr_reg_entry { 339 u32 sys_id; 340 struct arm64_ftr_reg *reg; 341 } arm64_ftr_regs[] = { 342 343 /* Op1 = 0, CRn = 0, CRm = 1 */ 344 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 345 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits), 346 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 347 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 348 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 349 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 350 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 351 352 /* Op1 = 0, CRn = 0, CRm = 2 */ 353 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits), 354 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 355 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 356 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 357 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits), 358 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 359 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 360 361 /* Op1 = 0, CRn = 0, CRm = 3 */ 362 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits), 363 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits), 364 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 365 366 /* Op1 = 0, CRn = 0, CRm = 4 */ 367 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0), 368 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz), 369 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz), 370 371 /* Op1 = 0, CRn = 0, CRm = 5 */ 372 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 373 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 374 375 /* Op1 = 0, CRn = 0, CRm = 6 */ 376 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 377 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), 378 379 /* Op1 = 0, CRn = 0, CRm = 7 */ 380 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), 381 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1), 382 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2), 383 384 /* Op1 = 0, CRn = 1, CRm = 2 */ 385 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr), 386 387 /* Op1 = 3, CRn = 0, CRm = 0 */ 388 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 389 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 390 391 /* Op1 = 3, CRn = 14, CRm = 0 */ 392 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 393 }; 394 395 static int search_cmp_ftr_reg(const void *id, const void *regp) 396 { 397 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 398 } 399 400 /* 401 * get_arm64_ftr_reg - Lookup a feature register entry using its 402 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the 403 * ascending order of sys_id , we use binary search to find a matching 404 * entry. 405 * 406 * returns - Upon success, matching ftr_reg entry for id. 407 * - NULL on failure. It is upto the caller to decide 408 * the impact of a failure. 409 */ 410 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 411 { 412 const struct __ftr_reg_entry *ret; 413 414 ret = bsearch((const void *)(unsigned long)sys_id, 415 arm64_ftr_regs, 416 ARRAY_SIZE(arm64_ftr_regs), 417 sizeof(arm64_ftr_regs[0]), 418 search_cmp_ftr_reg); 419 if (ret) 420 return ret->reg; 421 return NULL; 422 } 423 424 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 425 s64 ftr_val) 426 { 427 u64 mask = arm64_ftr_mask(ftrp); 428 429 reg &= ~mask; 430 reg |= (ftr_val << ftrp->shift) & mask; 431 return reg; 432 } 433 434 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 435 s64 cur) 436 { 437 s64 ret = 0; 438 439 switch (ftrp->type) { 440 case FTR_EXACT: 441 ret = ftrp->safe_val; 442 break; 443 case FTR_LOWER_SAFE: 444 ret = new < cur ? new : cur; 445 break; 446 case FTR_HIGHER_SAFE: 447 ret = new > cur ? new : cur; 448 break; 449 default: 450 BUG(); 451 } 452 453 return ret; 454 } 455 456 static void __init sort_ftr_regs(void) 457 { 458 int i; 459 460 /* Check that the array is sorted so that we can do the binary search */ 461 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++) 462 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id); 463 } 464 465 /* 466 * Initialise the CPU feature register from Boot CPU values. 467 * Also initiliases the strict_mask for the register. 468 * Any bits that are not covered by an arm64_ftr_bits entry are considered 469 * RES0 for the system-wide value, and must strictly match. 470 */ 471 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new) 472 { 473 u64 val = 0; 474 u64 strict_mask = ~0x0ULL; 475 u64 user_mask = 0; 476 u64 valid_mask = 0; 477 478 const struct arm64_ftr_bits *ftrp; 479 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 480 481 BUG_ON(!reg); 482 483 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 484 u64 ftr_mask = arm64_ftr_mask(ftrp); 485 s64 ftr_new = arm64_ftr_value(ftrp, new); 486 487 val = arm64_ftr_set_value(ftrp, val, ftr_new); 488 489 valid_mask |= ftr_mask; 490 if (!ftrp->strict) 491 strict_mask &= ~ftr_mask; 492 if (ftrp->visible) 493 user_mask |= ftr_mask; 494 else 495 reg->user_val = arm64_ftr_set_value(ftrp, 496 reg->user_val, 497 ftrp->safe_val); 498 } 499 500 val &= valid_mask; 501 502 reg->sys_val = val; 503 reg->strict_mask = strict_mask; 504 reg->user_mask = user_mask; 505 } 506 507 void __init init_cpu_features(struct cpuinfo_arm64 *info) 508 { 509 /* Before we start using the tables, make sure it is sorted */ 510 sort_ftr_regs(); 511 512 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 513 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 514 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 515 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 516 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 517 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 518 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 519 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 520 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 521 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 522 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 523 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 524 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 525 526 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 527 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 528 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 529 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 530 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 531 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 532 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 533 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 534 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 535 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 536 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 537 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 538 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 539 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 540 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 541 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 542 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 543 } 544 545 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 546 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr); 547 sve_init_vq_map(); 548 } 549 } 550 551 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 552 { 553 const struct arm64_ftr_bits *ftrp; 554 555 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 556 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 557 s64 ftr_new = arm64_ftr_value(ftrp, new); 558 559 if (ftr_cur == ftr_new) 560 continue; 561 /* Find a safe value */ 562 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 563 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 564 } 565 566 } 567 568 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 569 { 570 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 571 572 BUG_ON(!regp); 573 update_cpu_ftr_reg(regp, val); 574 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 575 return 0; 576 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 577 regp->name, boot, cpu, val); 578 return 1; 579 } 580 581 /* 582 * Update system wide CPU feature registers with the values from a 583 * non-boot CPU. Also performs SANITY checks to make sure that there 584 * aren't any insane variations from that of the boot CPU. 585 */ 586 void update_cpu_features(int cpu, 587 struct cpuinfo_arm64 *info, 588 struct cpuinfo_arm64 *boot) 589 { 590 int taint = 0; 591 592 /* 593 * The kernel can handle differing I-cache policies, but otherwise 594 * caches should look identical. Userspace JITs will make use of 595 * *minLine. 596 */ 597 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 598 info->reg_ctr, boot->reg_ctr); 599 600 /* 601 * Userspace may perform DC ZVA instructions. Mismatched block sizes 602 * could result in too much or too little memory being zeroed if a 603 * process is preempted and migrated between CPUs. 604 */ 605 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 606 info->reg_dczid, boot->reg_dczid); 607 608 /* If different, timekeeping will be broken (especially with KVM) */ 609 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 610 info->reg_cntfrq, boot->reg_cntfrq); 611 612 /* 613 * The kernel uses self-hosted debug features and expects CPUs to 614 * support identical debug features. We presently need CTX_CMPs, WRPs, 615 * and BRPs to be identical. 616 * ID_AA64DFR1 is currently RES0. 617 */ 618 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 619 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 620 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 621 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 622 /* 623 * Even in big.LITTLE, processors should be identical instruction-set 624 * wise. 625 */ 626 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 627 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 628 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 629 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 630 631 /* 632 * Differing PARange support is fine as long as all peripherals and 633 * memory are mapped within the minimum PARange of all CPUs. 634 * Linux should not care about secure memory. 635 */ 636 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 637 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 638 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 639 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 640 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 641 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 642 643 /* 644 * EL3 is not our concern. 645 * ID_AA64PFR1 is currently RES0. 646 */ 647 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 648 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 649 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 650 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 651 652 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 653 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 654 655 /* 656 * If we have AArch32, we care about 32-bit features for compat. 657 * If the system doesn't support AArch32, don't update them. 658 */ 659 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 660 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 661 662 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 663 info->reg_id_dfr0, boot->reg_id_dfr0); 664 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 665 info->reg_id_isar0, boot->reg_id_isar0); 666 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 667 info->reg_id_isar1, boot->reg_id_isar1); 668 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 669 info->reg_id_isar2, boot->reg_id_isar2); 670 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 671 info->reg_id_isar3, boot->reg_id_isar3); 672 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 673 info->reg_id_isar4, boot->reg_id_isar4); 674 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 675 info->reg_id_isar5, boot->reg_id_isar5); 676 677 /* 678 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 679 * ACTLR formats could differ across CPUs and therefore would have to 680 * be trapped for virtualization anyway. 681 */ 682 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 683 info->reg_id_mmfr0, boot->reg_id_mmfr0); 684 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 685 info->reg_id_mmfr1, boot->reg_id_mmfr1); 686 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 687 info->reg_id_mmfr2, boot->reg_id_mmfr2); 688 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 689 info->reg_id_mmfr3, boot->reg_id_mmfr3); 690 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 691 info->reg_id_pfr0, boot->reg_id_pfr0); 692 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 693 info->reg_id_pfr1, boot->reg_id_pfr1); 694 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 695 info->reg_mvfr0, boot->reg_mvfr0); 696 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 697 info->reg_mvfr1, boot->reg_mvfr1); 698 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 699 info->reg_mvfr2, boot->reg_mvfr2); 700 } 701 702 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 703 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu, 704 info->reg_zcr, boot->reg_zcr); 705 706 /* Probe vector lengths, unless we already gave up on SVE */ 707 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) && 708 !sys_caps_initialised) 709 sve_update_vq_map(); 710 } 711 712 /* 713 * Mismatched CPU features are a recipe for disaster. Don't even 714 * pretend to support them. 715 */ 716 if (taint) { 717 pr_warn_once("Unsupported CPU feature variation detected.\n"); 718 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 719 } 720 } 721 722 u64 read_sanitised_ftr_reg(u32 id) 723 { 724 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 725 726 /* We shouldn't get a request for an unsupported register */ 727 BUG_ON(!regp); 728 return regp->sys_val; 729 } 730 731 #define read_sysreg_case(r) \ 732 case r: return read_sysreg_s(r) 733 734 /* 735 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 736 * Read the system register on the current CPU 737 */ 738 static u64 __read_sysreg_by_encoding(u32 sys_id) 739 { 740 switch (sys_id) { 741 read_sysreg_case(SYS_ID_PFR0_EL1); 742 read_sysreg_case(SYS_ID_PFR1_EL1); 743 read_sysreg_case(SYS_ID_DFR0_EL1); 744 read_sysreg_case(SYS_ID_MMFR0_EL1); 745 read_sysreg_case(SYS_ID_MMFR1_EL1); 746 read_sysreg_case(SYS_ID_MMFR2_EL1); 747 read_sysreg_case(SYS_ID_MMFR3_EL1); 748 read_sysreg_case(SYS_ID_ISAR0_EL1); 749 read_sysreg_case(SYS_ID_ISAR1_EL1); 750 read_sysreg_case(SYS_ID_ISAR2_EL1); 751 read_sysreg_case(SYS_ID_ISAR3_EL1); 752 read_sysreg_case(SYS_ID_ISAR4_EL1); 753 read_sysreg_case(SYS_ID_ISAR5_EL1); 754 read_sysreg_case(SYS_MVFR0_EL1); 755 read_sysreg_case(SYS_MVFR1_EL1); 756 read_sysreg_case(SYS_MVFR2_EL1); 757 758 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 759 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 760 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 761 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 762 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 763 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 764 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 765 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 766 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 767 768 read_sysreg_case(SYS_CNTFRQ_EL0); 769 read_sysreg_case(SYS_CTR_EL0); 770 read_sysreg_case(SYS_DCZID_EL0); 771 772 default: 773 BUG(); 774 return 0; 775 } 776 } 777 778 #include <linux/irqchip/arm-gic-v3.h> 779 780 static bool 781 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 782 { 783 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign); 784 785 return val >= entry->min_field_value; 786 } 787 788 static bool 789 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 790 { 791 u64 val; 792 793 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 794 if (scope == SCOPE_SYSTEM) 795 val = read_sanitised_ftr_reg(entry->sys_reg); 796 else 797 val = __read_sysreg_by_encoding(entry->sys_reg); 798 799 return feature_matches(val, entry); 800 } 801 802 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 803 { 804 bool has_sre; 805 806 if (!has_cpuid_feature(entry, scope)) 807 return false; 808 809 has_sre = gic_enable_sre(); 810 if (!has_sre) 811 pr_warn_once("%s present but disabled by higher exception level\n", 812 entry->desc); 813 814 return has_sre; 815 } 816 817 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) 818 { 819 u32 midr = read_cpuid_id(); 820 821 /* Cavium ThunderX pass 1.x and 2.x */ 822 return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, 823 MIDR_CPU_VAR_REV(0, 0), 824 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK)); 825 } 826 827 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 828 { 829 return is_kernel_in_hyp_mode(); 830 } 831 832 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry, 833 int __unused) 834 { 835 phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start); 836 837 /* 838 * Activate the lower HYP offset only if: 839 * - the idmap doesn't clash with it, 840 * - the kernel is not running at EL2. 841 */ 842 return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode(); 843 } 844 845 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused) 846 { 847 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 848 849 return cpuid_feature_extract_signed_field(pfr0, 850 ID_AA64PFR0_FP_SHIFT) < 0; 851 } 852 853 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 854 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 855 856 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 857 int __unused) 858 { 859 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 860 861 /* Forced on command line? */ 862 if (__kpti_forced) { 863 pr_info_once("kernel page table isolation forced %s by command line option\n", 864 __kpti_forced > 0 ? "ON" : "OFF"); 865 return __kpti_forced > 0; 866 } 867 868 /* Useful for KASLR robustness */ 869 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) 870 return true; 871 872 /* Don't force KPTI for CPUs that are not vulnerable */ 873 switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) { 874 case MIDR_CAVIUM_THUNDERX2: 875 case MIDR_BRCM_VULCAN: 876 return false; 877 } 878 879 /* Defer to CPU feature registers */ 880 return !cpuid_feature_extract_unsigned_field(pfr0, 881 ID_AA64PFR0_CSV3_SHIFT); 882 } 883 884 static int __init parse_kpti(char *str) 885 { 886 bool enabled; 887 int ret = strtobool(str, &enabled); 888 889 if (ret) 890 return ret; 891 892 __kpti_forced = enabled ? 1 : -1; 893 return 0; 894 } 895 __setup("kpti=", parse_kpti); 896 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 897 898 static int cpu_copy_el2regs(void *__unused) 899 { 900 /* 901 * Copy register values that aren't redirected by hardware. 902 * 903 * Before code patching, we only set tpidr_el1, all CPUs need to copy 904 * this value to tpidr_el2 before we patch the code. Once we've done 905 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 906 * do anything here. 907 */ 908 if (!alternatives_applied) 909 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 910 911 return 0; 912 } 913 914 static const struct arm64_cpu_capabilities arm64_features[] = { 915 { 916 .desc = "GIC system register CPU interface", 917 .capability = ARM64_HAS_SYSREG_GIC_CPUIF, 918 .def_scope = SCOPE_SYSTEM, 919 .matches = has_useable_gicv3_cpuif, 920 .sys_reg = SYS_ID_AA64PFR0_EL1, 921 .field_pos = ID_AA64PFR0_GIC_SHIFT, 922 .sign = FTR_UNSIGNED, 923 .min_field_value = 1, 924 }, 925 #ifdef CONFIG_ARM64_PAN 926 { 927 .desc = "Privileged Access Never", 928 .capability = ARM64_HAS_PAN, 929 .def_scope = SCOPE_SYSTEM, 930 .matches = has_cpuid_feature, 931 .sys_reg = SYS_ID_AA64MMFR1_EL1, 932 .field_pos = ID_AA64MMFR1_PAN_SHIFT, 933 .sign = FTR_UNSIGNED, 934 .min_field_value = 1, 935 .enable = cpu_enable_pan, 936 }, 937 #endif /* CONFIG_ARM64_PAN */ 938 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS) 939 { 940 .desc = "LSE atomic instructions", 941 .capability = ARM64_HAS_LSE_ATOMICS, 942 .def_scope = SCOPE_SYSTEM, 943 .matches = has_cpuid_feature, 944 .sys_reg = SYS_ID_AA64ISAR0_EL1, 945 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, 946 .sign = FTR_UNSIGNED, 947 .min_field_value = 2, 948 }, 949 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ 950 { 951 .desc = "Software prefetching using PRFM", 952 .capability = ARM64_HAS_NO_HW_PREFETCH, 953 .def_scope = SCOPE_SYSTEM, 954 .matches = has_no_hw_prefetch, 955 }, 956 #ifdef CONFIG_ARM64_UAO 957 { 958 .desc = "User Access Override", 959 .capability = ARM64_HAS_UAO, 960 .def_scope = SCOPE_SYSTEM, 961 .matches = has_cpuid_feature, 962 .sys_reg = SYS_ID_AA64MMFR2_EL1, 963 .field_pos = ID_AA64MMFR2_UAO_SHIFT, 964 .min_field_value = 1, 965 /* 966 * We rely on stop_machine() calling uao_thread_switch() to set 967 * UAO immediately after patching. 968 */ 969 }, 970 #endif /* CONFIG_ARM64_UAO */ 971 #ifdef CONFIG_ARM64_PAN 972 { 973 .capability = ARM64_ALT_PAN_NOT_UAO, 974 .def_scope = SCOPE_SYSTEM, 975 .matches = cpufeature_pan_not_uao, 976 }, 977 #endif /* CONFIG_ARM64_PAN */ 978 { 979 .desc = "Virtualization Host Extensions", 980 .capability = ARM64_HAS_VIRT_HOST_EXTN, 981 .def_scope = SCOPE_SYSTEM, 982 .matches = runs_at_el2, 983 .enable = cpu_copy_el2regs, 984 }, 985 { 986 .desc = "32-bit EL0 Support", 987 .capability = ARM64_HAS_32BIT_EL0, 988 .def_scope = SCOPE_SYSTEM, 989 .matches = has_cpuid_feature, 990 .sys_reg = SYS_ID_AA64PFR0_EL1, 991 .sign = FTR_UNSIGNED, 992 .field_pos = ID_AA64PFR0_EL0_SHIFT, 993 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT, 994 }, 995 { 996 .desc = "Reduced HYP mapping offset", 997 .capability = ARM64_HYP_OFFSET_LOW, 998 .def_scope = SCOPE_SYSTEM, 999 .matches = hyp_offset_low, 1000 }, 1001 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1002 { 1003 .desc = "Kernel page table isolation (KPTI)", 1004 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 1005 .def_scope = SCOPE_SYSTEM, 1006 .matches = unmap_kernel_at_el0, 1007 }, 1008 #endif 1009 { 1010 /* FP/SIMD is not implemented */ 1011 .capability = ARM64_HAS_NO_FPSIMD, 1012 .def_scope = SCOPE_SYSTEM, 1013 .min_field_value = 0, 1014 .matches = has_no_fpsimd, 1015 }, 1016 #ifdef CONFIG_ARM64_PMEM 1017 { 1018 .desc = "Data cache clean to Point of Persistence", 1019 .capability = ARM64_HAS_DCPOP, 1020 .def_scope = SCOPE_SYSTEM, 1021 .matches = has_cpuid_feature, 1022 .sys_reg = SYS_ID_AA64ISAR1_EL1, 1023 .field_pos = ID_AA64ISAR1_DPB_SHIFT, 1024 .min_field_value = 1, 1025 }, 1026 #endif 1027 #ifdef CONFIG_ARM64_SVE 1028 { 1029 .desc = "Scalable Vector Extension", 1030 .capability = ARM64_SVE, 1031 .def_scope = SCOPE_SYSTEM, 1032 .sys_reg = SYS_ID_AA64PFR0_EL1, 1033 .sign = FTR_UNSIGNED, 1034 .field_pos = ID_AA64PFR0_SVE_SHIFT, 1035 .min_field_value = ID_AA64PFR0_SVE, 1036 .matches = has_cpuid_feature, 1037 .enable = sve_kernel_enable, 1038 }, 1039 #endif /* CONFIG_ARM64_SVE */ 1040 #ifdef CONFIG_ARM64_RAS_EXTN 1041 { 1042 .desc = "RAS Extension Support", 1043 .capability = ARM64_HAS_RAS_EXTN, 1044 .def_scope = SCOPE_SYSTEM, 1045 .matches = has_cpuid_feature, 1046 .sys_reg = SYS_ID_AA64PFR0_EL1, 1047 .sign = FTR_UNSIGNED, 1048 .field_pos = ID_AA64PFR0_RAS_SHIFT, 1049 .min_field_value = ID_AA64PFR0_RAS_V1, 1050 .enable = cpu_clear_disr, 1051 }, 1052 #endif /* CONFIG_ARM64_RAS_EXTN */ 1053 {}, 1054 }; 1055 1056 #define HWCAP_CAP(reg, field, s, min_value, type, cap) \ 1057 { \ 1058 .desc = #cap, \ 1059 .def_scope = SCOPE_SYSTEM, \ 1060 .matches = has_cpuid_feature, \ 1061 .sys_reg = reg, \ 1062 .field_pos = field, \ 1063 .sign = s, \ 1064 .min_field_value = min_value, \ 1065 .hwcap_type = type, \ 1066 .hwcap = cap, \ 1067 } 1068 1069 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 1070 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL), 1071 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES), 1072 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1), 1073 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2), 1074 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512), 1075 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32), 1076 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS), 1077 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM), 1078 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3), 1079 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3), 1080 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4), 1081 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP), 1082 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM), 1083 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP), 1084 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP), 1085 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD), 1086 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP), 1087 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP), 1088 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT), 1089 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA), 1090 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC), 1091 #ifdef CONFIG_ARM64_SVE 1092 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE), 1093 #endif 1094 {}, 1095 }; 1096 1097 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 1098 #ifdef CONFIG_COMPAT 1099 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 1100 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 1101 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 1102 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 1103 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 1104 #endif 1105 {}, 1106 }; 1107 1108 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1109 { 1110 switch (cap->hwcap_type) { 1111 case CAP_HWCAP: 1112 elf_hwcap |= cap->hwcap; 1113 break; 1114 #ifdef CONFIG_COMPAT 1115 case CAP_COMPAT_HWCAP: 1116 compat_elf_hwcap |= (u32)cap->hwcap; 1117 break; 1118 case CAP_COMPAT_HWCAP2: 1119 compat_elf_hwcap2 |= (u32)cap->hwcap; 1120 break; 1121 #endif 1122 default: 1123 WARN_ON(1); 1124 break; 1125 } 1126 } 1127 1128 /* Check if we have a particular HWCAP enabled */ 1129 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 1130 { 1131 bool rc; 1132 1133 switch (cap->hwcap_type) { 1134 case CAP_HWCAP: 1135 rc = (elf_hwcap & cap->hwcap) != 0; 1136 break; 1137 #ifdef CONFIG_COMPAT 1138 case CAP_COMPAT_HWCAP: 1139 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 1140 break; 1141 case CAP_COMPAT_HWCAP2: 1142 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 1143 break; 1144 #endif 1145 default: 1146 WARN_ON(1); 1147 rc = false; 1148 } 1149 1150 return rc; 1151 } 1152 1153 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 1154 { 1155 /* We support emulation of accesses to CPU ID feature registers */ 1156 elf_hwcap |= HWCAP_CPUID; 1157 for (; hwcaps->matches; hwcaps++) 1158 if (hwcaps->matches(hwcaps, hwcaps->def_scope)) 1159 cap_set_elf_hwcap(hwcaps); 1160 } 1161 1162 /* 1163 * Check if the current CPU has a given feature capability. 1164 * Should be called from non-preemptible context. 1165 */ 1166 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array, 1167 unsigned int cap) 1168 { 1169 const struct arm64_cpu_capabilities *caps; 1170 1171 if (WARN_ON(preemptible())) 1172 return false; 1173 1174 for (caps = cap_array; caps->matches; caps++) 1175 if (caps->capability == cap && 1176 caps->matches(caps, SCOPE_LOCAL_CPU)) 1177 return true; 1178 return false; 1179 } 1180 1181 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, 1182 const char *info) 1183 { 1184 for (; caps->matches; caps++) { 1185 if (!caps->matches(caps, caps->def_scope)) 1186 continue; 1187 1188 if (!cpus_have_cap(caps->capability) && caps->desc) 1189 pr_info("%s %s\n", info, caps->desc); 1190 cpus_set_cap(caps->capability); 1191 } 1192 } 1193 1194 /* 1195 * Run through the enabled capabilities and enable() it on all active 1196 * CPUs 1197 */ 1198 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps) 1199 { 1200 for (; caps->matches; caps++) { 1201 unsigned int num = caps->capability; 1202 1203 if (!cpus_have_cap(num)) 1204 continue; 1205 1206 /* Ensure cpus_have_const_cap(num) works */ 1207 static_branch_enable(&cpu_hwcap_keys[num]); 1208 1209 if (caps->enable) { 1210 /* 1211 * Use stop_machine() as it schedules the work allowing 1212 * us to modify PSTATE, instead of on_each_cpu() which 1213 * uses an IPI, giving us a PSTATE that disappears when 1214 * we return. 1215 */ 1216 stop_machine(caps->enable, (void *)caps, cpu_online_mask); 1217 } 1218 } 1219 } 1220 1221 /* 1222 * Check for CPU features that are used in early boot 1223 * based on the Boot CPU value. 1224 */ 1225 static void check_early_cpu_features(void) 1226 { 1227 verify_cpu_run_el(); 1228 verify_cpu_asid_bits(); 1229 } 1230 1231 static void 1232 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 1233 { 1234 1235 for (; caps->matches; caps++) 1236 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 1237 pr_crit("CPU%d: missing HWCAP: %s\n", 1238 smp_processor_id(), caps->desc); 1239 cpu_die_early(); 1240 } 1241 } 1242 1243 static void 1244 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list) 1245 { 1246 const struct arm64_cpu_capabilities *caps = caps_list; 1247 for (; caps->matches; caps++) { 1248 if (!cpus_have_cap(caps->capability)) 1249 continue; 1250 /* 1251 * If the new CPU misses an advertised feature, we cannot proceed 1252 * further, park the cpu. 1253 */ 1254 if (!__this_cpu_has_cap(caps_list, caps->capability)) { 1255 pr_crit("CPU%d: missing feature: %s\n", 1256 smp_processor_id(), caps->desc); 1257 cpu_die_early(); 1258 } 1259 if (caps->enable) 1260 caps->enable((void *)caps); 1261 } 1262 } 1263 1264 static void verify_sve_features(void) 1265 { 1266 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1); 1267 u64 zcr = read_zcr_features(); 1268 1269 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK; 1270 unsigned int len = zcr & ZCR_ELx_LEN_MASK; 1271 1272 if (len < safe_len || sve_verify_vq_map()) { 1273 pr_crit("CPU%d: SVE: required vector length(s) missing\n", 1274 smp_processor_id()); 1275 cpu_die_early(); 1276 } 1277 1278 /* Add checks on other ZCR bits here if necessary */ 1279 } 1280 1281 /* 1282 * Run through the enabled system capabilities and enable() it on this CPU. 1283 * The capabilities were decided based on the available CPUs at the boot time. 1284 * Any new CPU should match the system wide status of the capability. If the 1285 * new CPU doesn't have a capability which the system now has enabled, we 1286 * cannot do anything to fix it up and could cause unexpected failures. So 1287 * we park the CPU. 1288 */ 1289 static void verify_local_cpu_capabilities(void) 1290 { 1291 verify_local_cpu_errata_workarounds(); 1292 verify_local_cpu_features(arm64_features); 1293 verify_local_elf_hwcaps(arm64_elf_hwcaps); 1294 1295 if (system_supports_32bit_el0()) 1296 verify_local_elf_hwcaps(compat_elf_hwcaps); 1297 1298 if (system_supports_sve()) 1299 verify_sve_features(); 1300 1301 if (system_uses_ttbr0_pan()) 1302 pr_info("Emulating Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 1303 } 1304 1305 void check_local_cpu_capabilities(void) 1306 { 1307 /* 1308 * All secondary CPUs should conform to the early CPU features 1309 * in use by the kernel based on boot CPU. 1310 */ 1311 check_early_cpu_features(); 1312 1313 /* 1314 * If we haven't finalised the system capabilities, this CPU gets 1315 * a chance to update the errata work arounds. 1316 * Otherwise, this CPU should verify that it has all the system 1317 * advertised capabilities. 1318 */ 1319 if (!sys_caps_initialised) 1320 update_cpu_errata_workarounds(); 1321 else 1322 verify_local_cpu_capabilities(); 1323 } 1324 1325 static void __init setup_feature_capabilities(void) 1326 { 1327 update_cpu_capabilities(arm64_features, "detected feature:"); 1328 enable_cpu_capabilities(arm64_features); 1329 } 1330 1331 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready); 1332 EXPORT_SYMBOL(arm64_const_caps_ready); 1333 1334 static void __init mark_const_caps_ready(void) 1335 { 1336 static_branch_enable(&arm64_const_caps_ready); 1337 } 1338 1339 extern const struct arm64_cpu_capabilities arm64_errata[]; 1340 1341 bool this_cpu_has_cap(unsigned int cap) 1342 { 1343 return (__this_cpu_has_cap(arm64_features, cap) || 1344 __this_cpu_has_cap(arm64_errata, cap)); 1345 } 1346 1347 void __init setup_cpu_features(void) 1348 { 1349 u32 cwg; 1350 int cls; 1351 1352 /* Set the CPU feature capabilies */ 1353 setup_feature_capabilities(); 1354 enable_errata_workarounds(); 1355 mark_const_caps_ready(); 1356 setup_elf_hwcaps(arm64_elf_hwcaps); 1357 1358 if (system_supports_32bit_el0()) 1359 setup_elf_hwcaps(compat_elf_hwcaps); 1360 1361 sve_setup(); 1362 1363 /* Advertise that we have computed the system capabilities */ 1364 set_sys_caps_initialised(); 1365 1366 /* 1367 * Check for sane CTR_EL0.CWG value. 1368 */ 1369 cwg = cache_type_cwg(); 1370 cls = cache_line_size(); 1371 if (!cwg) 1372 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n", 1373 cls); 1374 if (L1_CACHE_BYTES < cls) 1375 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n", 1376 L1_CACHE_BYTES, cls); 1377 } 1378 1379 static bool __maybe_unused 1380 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused) 1381 { 1382 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO)); 1383 } 1384 1385 /* 1386 * We emulate only the following system register space. 1387 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7] 1388 * See Table C5-6 System instruction encodings for System register accesses, 1389 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 1390 */ 1391 static inline bool __attribute_const__ is_emulated(u32 id) 1392 { 1393 return (sys_reg_Op0(id) == 0x3 && 1394 sys_reg_CRn(id) == 0x0 && 1395 sys_reg_Op1(id) == 0x0 && 1396 (sys_reg_CRm(id) == 0 || 1397 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7)))); 1398 } 1399 1400 /* 1401 * With CRm == 0, reg should be one of : 1402 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 1403 */ 1404 static inline int emulate_id_reg(u32 id, u64 *valp) 1405 { 1406 switch (id) { 1407 case SYS_MIDR_EL1: 1408 *valp = read_cpuid_id(); 1409 break; 1410 case SYS_MPIDR_EL1: 1411 *valp = SYS_MPIDR_SAFE_VAL; 1412 break; 1413 case SYS_REVIDR_EL1: 1414 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 1415 *valp = 0; 1416 break; 1417 default: 1418 return -EINVAL; 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int emulate_sys_reg(u32 id, u64 *valp) 1425 { 1426 struct arm64_ftr_reg *regp; 1427 1428 if (!is_emulated(id)) 1429 return -EINVAL; 1430 1431 if (sys_reg_CRm(id) == 0) 1432 return emulate_id_reg(id, valp); 1433 1434 regp = get_arm64_ftr_reg(id); 1435 if (regp) 1436 *valp = arm64_ftr_reg_user_value(regp); 1437 else 1438 /* 1439 * The untracked registers are either IMPLEMENTATION DEFINED 1440 * (e.g, ID_AFR0_EL1) or reserved RAZ. 1441 */ 1442 *valp = 0; 1443 return 0; 1444 } 1445 1446 static int emulate_mrs(struct pt_regs *regs, u32 insn) 1447 { 1448 int rc; 1449 u32 sys_reg, dst; 1450 u64 val; 1451 1452 /* 1453 * sys_reg values are defined as used in mrs/msr instruction. 1454 * shift the imm value to get the encoding. 1455 */ 1456 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 1457 rc = emulate_sys_reg(sys_reg, &val); 1458 if (!rc) { 1459 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 1460 pt_regs_write_reg(regs, dst, val); 1461 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 1462 } 1463 1464 return rc; 1465 } 1466 1467 static struct undef_hook mrs_hook = { 1468 .instr_mask = 0xfff00000, 1469 .instr_val = 0xd5300000, 1470 .pstate_mask = COMPAT_PSR_MODE_MASK, 1471 .pstate_val = PSR_MODE_EL0t, 1472 .fn = emulate_mrs, 1473 }; 1474 1475 static int __init enable_mrs_emulation(void) 1476 { 1477 register_undef_hook(&mrs_hook); 1478 return 0; 1479 } 1480 1481 core_initcall(enable_mrs_emulation); 1482 1483 int cpu_clear_disr(void *__unused) 1484 { 1485 /* Firmware may have left a deferred SError in this register. */ 1486 write_sysreg_s(0, SYS_DISR_EL1); 1487 1488 return 0; 1489 } 1490