1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/hypervisor.h> 90 #include <asm/processor.h> 91 #include <asm/smp.h> 92 #include <asm/sysreg.h> 93 #include <asm/traps.h> 94 #include <asm/vectors.h> 95 #include <asm/virt.h> 96 97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 99 100 #ifdef CONFIG_COMPAT 101 #define COMPAT_ELF_HWCAP_DEFAULT \ 102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 105 COMPAT_HWCAP_LPAE) 106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 107 unsigned int compat_elf_hwcap2 __read_mostly; 108 unsigned int compat_elf_hwcap3 __read_mostly; 109 #endif 110 111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 112 EXPORT_SYMBOL(system_cpucaps); 113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 114 115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 116 117 /* 118 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 119 * ends up in the .bss section where it is initialized in early_map_kernel() 120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 122 * may end up generating an incorrect idmap page table attributes. 123 */ 124 bool arm64_use_ng_mappings __read_mostly = false; 125 EXPORT_SYMBOL(arm64_use_ng_mappings); 126 127 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 128 129 /* 130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 131 * support it? 132 */ 133 static bool __read_mostly allow_mismatched_32bit_el0; 134 135 /* 136 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 137 * seen at least one CPU capable of 32-bit EL0. 138 */ 139 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 140 141 /* 142 * Mask of CPUs supporting 32-bit EL0. 143 * Only valid if arm64_mismatched_32bit_el0 is enabled. 144 */ 145 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 151 } 152 153 #define __ARM64_MAX_POSITIVE(reg, field) \ 154 ((reg##_##field##_SIGNED ? \ 155 BIT(reg##_##field##_WIDTH - 1) : \ 156 BIT(reg##_##field##_WIDTH)) - 1) 157 158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 159 160 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 161 .sys_reg = SYS_##reg, \ 162 .field_pos = reg##_##field##_SHIFT, \ 163 .field_width = reg##_##field##_WIDTH, \ 164 .sign = reg##_##field##_SIGNED, \ 165 .min_field_value = min_value, \ 166 .max_field_value = max_value, 167 168 /* 169 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 170 * an implicit maximum that depends on the sign-ess of the field. 171 * 172 * An unsigned field will be capped at all ones, while a signed field 173 * will be limited to the positive half only. 174 */ 175 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 176 __ARM64_CPUID_FIELDS(reg, field, \ 177 SYS_FIELD_VALUE(reg, field, min_value), \ 178 __ARM64_MAX_POSITIVE(reg, field)) 179 180 /* 181 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 182 * implicit minimal value to max_value. This should be used when 183 * matching a non-implemented property. 184 */ 185 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 186 __ARM64_CPUID_FIELDS(reg, field, \ 187 __ARM64_MIN_NEGATIVE(reg, field), \ 188 SYS_FIELD_VALUE(reg, field, max_value)) 189 190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 191 { \ 192 .sign = SIGNED, \ 193 .visible = VISIBLE, \ 194 .strict = STRICT, \ 195 .type = TYPE, \ 196 .shift = SHIFT, \ 197 .width = WIDTH, \ 198 .safe_val = SAFE_VAL, \ 199 } 200 201 /* Define a feature with unsigned values */ 202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 204 205 /* Define a feature with a signed value */ 206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 #define ARM64_FTR_END \ 210 { \ 211 .width = 0, \ 212 } 213 214 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 215 216 static bool __system_matches_cap(unsigned int n); 217 218 /* 219 * NOTE: Any changes to the visibility of features should be kept in 220 * sync with the documentation of the CPU feature register ABI. 221 */ 222 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 237 ARM64_FTR_END, 238 }; 239 240 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 276 ARM64_FTR_END, 277 }; 278 279 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 296 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 297 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 308 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 314 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 315 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 318 ARM64_FTR_END, 319 }; 320 321 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 322 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 323 ARM64_FTR_END, 324 }; 325 326 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 327 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 328 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 329 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 330 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 332 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 333 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 334 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 335 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 336 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 337 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 338 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 351 ARM64_FTR_END, 352 }; 353 354 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 356 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 358 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 360 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 362 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 363 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 364 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 365 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 366 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 401 ARM64_FTR_END, 402 }; 403 404 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 405 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 406 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 413 ARM64_FTR_END, 414 }; 415 416 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 417 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 420 /* 421 * Page size not being supported at Stage-2 is not fatal. You 422 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 423 * your favourite nesting hypervisor. 424 * 425 * There is a small corner case where the hypervisor explicitly 426 * advertises a given granule size at Stage-2 (value 2) on some 427 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 428 * vCPUs. Although this is not forbidden by the architecture, it 429 * indicates that the hypervisor is being silly (or buggy). 430 * 431 * We make no effort to cope with this and pretend that if these 432 * fields are inconsistent across vCPUs, then it isn't worth 433 * trying to bring KVM up. 434 */ 435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 438 /* 439 * We already refuse to boot CPUs that don't support our configured 440 * page size, so we can only detect mismatches for a page size other 441 * than the one we're currently using. Unfortunately, SoCs like this 442 * exist in the wild so, even though we don't like it, we'll have to go 443 * along with it and treat them as non-strict. 444 */ 445 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 446 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 448 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 450 /* Linux shouldn't care about secure memory */ 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 454 /* 455 * Differing PARange is fine as long as all peripherals and memory are mapped 456 * within the minimum PARange of all CPUs 457 */ 458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 459 ARM64_FTR_END, 460 }; 461 462 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 477 ARM64_FTR_END, 478 }; 479 480 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 496 ARM64_FTR_END, 497 }; 498 499 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 500 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 501 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 504 ARM64_FTR_END, 505 }; 506 507 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 508 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_ctr[] = { 514 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 520 /* 521 * Linux can handle differing I-cache policies. Userspace JITs will 522 * make use of *minLine. 523 * If we have differing I-cache policies, report it as the weakest - VIPT. 524 */ 525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 527 ARM64_FTR_END, 528 }; 529 530 static struct arm64_ftr_override __ro_after_init no_override = { }; 531 532 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 533 .name = "SYS_CTR_EL0", 534 .ftr_bits = ftr_ctr, 535 .override = &no_override, 536 }; 537 538 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 539 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 544 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 547 ARM64_FTR_END, 548 }; 549 550 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 551 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 556 /* 557 * We can instantiate multiple PMU instances with different levels 558 * of support. 559 */ 560 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 562 ARM64_FTR_END, 563 }; 564 565 static const struct arm64_ftr_bits ftr_mvfr0[] = { 566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 574 ARM64_FTR_END, 575 }; 576 577 static const struct arm64_ftr_bits ftr_mvfr1[] = { 578 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 579 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 586 ARM64_FTR_END, 587 }; 588 589 static const struct arm64_ftr_bits ftr_mvfr2[] = { 590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 592 ARM64_FTR_END, 593 }; 594 595 static const struct arm64_ftr_bits ftr_dczid[] = { 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 598 ARM64_FTR_END, 599 }; 600 601 static const struct arm64_ftr_bits ftr_gmid[] = { 602 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 603 ARM64_FTR_END, 604 }; 605 606 static const struct arm64_ftr_bits ftr_id_isar0[] = { 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_id_isar5[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 619 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 624 ARM64_FTR_END, 625 }; 626 627 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 635 636 /* 637 * SpecSEI = 1 indicates that the PE might generate an SError on an 638 * external abort on speculative read. It is safe to assume that an 639 * SError might be generated than it will not be. Hence it has been 640 * classified as FTR_HIGHER_SAFE. 641 */ 642 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 643 ARM64_FTR_END, 644 }; 645 646 static const struct arm64_ftr_bits ftr_id_isar4[] = { 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 655 ARM64_FTR_END, 656 }; 657 658 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 659 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 660 ARM64_FTR_END, 661 }; 662 663 static const struct arm64_ftr_bits ftr_id_isar6[] = { 664 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 681 ARM64_FTR_END, 682 }; 683 684 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 693 ARM64_FTR_END, 694 }; 695 696 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 697 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 698 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 699 ARM64_FTR_END, 700 }; 701 702 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 703 /* [31:28] TraceFilt */ 704 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 711 ARM64_FTR_END, 712 }; 713 714 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 715 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 716 ARM64_FTR_END, 717 }; 718 719 static const struct arm64_ftr_bits ftr_mpamidr[] = { 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 724 ARM64_FTR_END, 725 }; 726 727 /* 728 * Common ftr bits for a 32bit register with all hidden, strict 729 * attributes, with 4bit feature fields and a default safe value of 730 * 0. Covers the following 32bit registers: 731 * id_isar[1-3], id_mmfr[1-3] 732 */ 733 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 734 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 742 ARM64_FTR_END, 743 }; 744 745 /* Table for a single 32bit feature value */ 746 static const struct arm64_ftr_bits ftr_single32[] = { 747 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 748 ARM64_FTR_END, 749 }; 750 751 static const struct arm64_ftr_bits ftr_raz[] = { 752 ARM64_FTR_END, 753 }; 754 755 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 756 .sys_id = id, \ 757 .reg = &(struct arm64_ftr_reg){ \ 758 .name = id_str, \ 759 .override = (ovr), \ 760 .ftr_bits = &((table)[0]), \ 761 }} 762 763 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 764 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 765 766 #define ARM64_FTR_REG(id, table) \ 767 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 768 769 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 770 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 771 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 772 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 773 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 774 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 775 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 776 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 777 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 778 779 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 780 781 static const struct __ftr_reg_entry { 782 u32 sys_id; 783 struct arm64_ftr_reg *reg; 784 } arm64_ftr_regs[] = { 785 786 /* Op1 = 0, CRn = 0, CRm = 1 */ 787 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 788 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 789 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 790 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 791 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 792 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 793 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 794 795 /* Op1 = 0, CRn = 0, CRm = 2 */ 796 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 797 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 798 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 799 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 801 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 802 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 803 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 804 805 /* Op1 = 0, CRn = 0, CRm = 3 */ 806 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 807 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 808 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 809 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 810 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 811 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 812 813 /* Op1 = 0, CRn = 0, CRm = 4 */ 814 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 815 &id_aa64pfr0_override), 816 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 817 &id_aa64pfr1_override), 818 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 819 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 820 &id_aa64zfr0_override), 821 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 822 &id_aa64smfr0_override), 823 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 824 825 /* Op1 = 0, CRn = 0, CRm = 5 */ 826 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 827 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 828 829 /* Op1 = 0, CRn = 0, CRm = 6 */ 830 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 832 &id_aa64isar1_override), 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 834 &id_aa64isar2_override), 835 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 836 837 /* Op1 = 0, CRn = 0, CRm = 7 */ 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 839 &id_aa64mmfr0_override), 840 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 841 &id_aa64mmfr1_override), 842 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 843 &id_aa64mmfr2_override), 844 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 845 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 846 847 /* Op1 = 0, CRn = 10, CRm = 4 */ 848 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 849 850 /* Op1 = 1, CRn = 0, CRm = 0 */ 851 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 852 853 /* Op1 = 3, CRn = 0, CRm = 0 */ 854 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 855 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 856 857 /* Op1 = 3, CRn = 14, CRm = 0 */ 858 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 859 }; 860 861 static int search_cmp_ftr_reg(const void *id, const void *regp) 862 { 863 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 864 } 865 866 /* 867 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 868 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 869 * ascending order of sys_id, we use binary search to find a matching 870 * entry. 871 * 872 * returns - Upon success, matching ftr_reg entry for id. 873 * - NULL on failure. It is upto the caller to decide 874 * the impact of a failure. 875 */ 876 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 877 { 878 const struct __ftr_reg_entry *ret; 879 880 ret = bsearch((const void *)(unsigned long)sys_id, 881 arm64_ftr_regs, 882 ARRAY_SIZE(arm64_ftr_regs), 883 sizeof(arm64_ftr_regs[0]), 884 search_cmp_ftr_reg); 885 if (ret) 886 return ret->reg; 887 return NULL; 888 } 889 890 /* 891 * get_arm64_ftr_reg - Looks up a feature register entry using 892 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 893 * 894 * returns - Upon success, matching ftr_reg entry for id. 895 * - NULL on failure but with an WARN_ON(). 896 */ 897 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 898 { 899 struct arm64_ftr_reg *reg; 900 901 reg = get_arm64_ftr_reg_nowarn(sys_id); 902 903 /* 904 * Requesting a non-existent register search is an error. Warn 905 * and let the caller handle it. 906 */ 907 WARN_ON(!reg); 908 return reg; 909 } 910 911 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 912 s64 ftr_val) 913 { 914 u64 mask = arm64_ftr_mask(ftrp); 915 916 reg &= ~mask; 917 reg |= (ftr_val << ftrp->shift) & mask; 918 return reg; 919 } 920 921 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 922 s64 cur) 923 { 924 s64 ret = 0; 925 926 switch (ftrp->type) { 927 case FTR_EXACT: 928 ret = ftrp->safe_val; 929 break; 930 case FTR_LOWER_SAFE: 931 ret = min(new, cur); 932 break; 933 case FTR_HIGHER_OR_ZERO_SAFE: 934 if (!cur || !new) 935 break; 936 fallthrough; 937 case FTR_HIGHER_SAFE: 938 ret = max(new, cur); 939 break; 940 default: 941 BUG(); 942 } 943 944 return ret; 945 } 946 947 static void __init sort_ftr_regs(void) 948 { 949 unsigned int i; 950 951 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 952 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 953 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 954 unsigned int j = 0; 955 956 /* 957 * Features here must be sorted in descending order with respect 958 * to their shift values and should not overlap with each other. 959 */ 960 for (; ftr_bits->width != 0; ftr_bits++, j++) { 961 unsigned int width = ftr_reg->ftr_bits[j].width; 962 unsigned int shift = ftr_reg->ftr_bits[j].shift; 963 unsigned int prev_shift; 964 965 WARN((shift + width) > 64, 966 "%s has invalid feature at shift %d\n", 967 ftr_reg->name, shift); 968 969 /* 970 * Skip the first feature. There is nothing to 971 * compare against for now. 972 */ 973 if (j == 0) 974 continue; 975 976 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 977 WARN((shift + width) > prev_shift, 978 "%s has feature overlap at shift %d\n", 979 ftr_reg->name, shift); 980 } 981 982 /* 983 * Skip the first register. There is nothing to 984 * compare against for now. 985 */ 986 if (i == 0) 987 continue; 988 /* 989 * Registers here must be sorted in ascending order with respect 990 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 991 * to work correctly. 992 */ 993 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 994 } 995 } 996 997 /* 998 * Initialise the CPU feature register from Boot CPU values. 999 * Also initiliases the strict_mask for the register. 1000 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1001 * RES0 for the system-wide value, and must strictly match. 1002 */ 1003 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1004 { 1005 u64 val = 0; 1006 u64 strict_mask = ~0x0ULL; 1007 u64 user_mask = 0; 1008 u64 valid_mask = 0; 1009 1010 const struct arm64_ftr_bits *ftrp; 1011 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1012 1013 if (!reg) 1014 return; 1015 1016 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1017 u64 ftr_mask = arm64_ftr_mask(ftrp); 1018 s64 ftr_new = arm64_ftr_value(ftrp, new); 1019 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1020 1021 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1022 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1023 char *str = NULL; 1024 1025 if (ftr_ovr != tmp) { 1026 /* Unsafe, remove the override */ 1027 reg->override->mask &= ~ftr_mask; 1028 reg->override->val &= ~ftr_mask; 1029 tmp = ftr_ovr; 1030 str = "ignoring override"; 1031 } else if (ftr_new != tmp) { 1032 /* Override was valid */ 1033 ftr_new = tmp; 1034 str = "forced"; 1035 } else { 1036 /* Override was the safe value */ 1037 str = "already set"; 1038 } 1039 1040 pr_warn("%s[%d:%d]: %s to %llx\n", 1041 reg->name, 1042 ftrp->shift + ftrp->width - 1, 1043 ftrp->shift, str, 1044 tmp & (BIT(ftrp->width) - 1)); 1045 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1046 reg->override->val &= ~ftr_mask; 1047 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1048 reg->name, 1049 ftrp->shift + ftrp->width - 1, 1050 ftrp->shift); 1051 } 1052 1053 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1054 1055 valid_mask |= ftr_mask; 1056 if (!ftrp->strict) 1057 strict_mask &= ~ftr_mask; 1058 if (ftrp->visible) 1059 user_mask |= ftr_mask; 1060 else 1061 reg->user_val = arm64_ftr_set_value(ftrp, 1062 reg->user_val, 1063 ftrp->safe_val); 1064 } 1065 1066 val &= valid_mask; 1067 1068 reg->sys_val = val; 1069 reg->strict_mask = strict_mask; 1070 reg->user_mask = user_mask; 1071 } 1072 1073 extern const struct arm64_cpu_capabilities arm64_errata[]; 1074 static const struct arm64_cpu_capabilities arm64_features[]; 1075 1076 static void __init 1077 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1078 { 1079 for (; caps->matches; caps++) { 1080 if (WARN(caps->capability >= ARM64_NCAPS, 1081 "Invalid capability %d\n", caps->capability)) 1082 continue; 1083 if (WARN(cpucap_ptrs[caps->capability], 1084 "Duplicate entry for capability %d\n", 1085 caps->capability)) 1086 continue; 1087 cpucap_ptrs[caps->capability] = caps; 1088 } 1089 } 1090 1091 static void __init init_cpucap_indirect_list(void) 1092 { 1093 init_cpucap_indirect_list_from_array(arm64_features); 1094 init_cpucap_indirect_list_from_array(arm64_errata); 1095 } 1096 1097 static void __init setup_boot_cpu_capabilities(void); 1098 1099 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1100 { 1101 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1102 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1103 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1104 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1105 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1106 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1107 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1108 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1109 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1110 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1111 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1112 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1113 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1114 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1115 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1116 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1117 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1118 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1119 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1120 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1121 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1122 } 1123 1124 #ifdef CONFIG_ARM64_PSEUDO_NMI 1125 static bool enable_pseudo_nmi; 1126 1127 static int __init early_enable_pseudo_nmi(char *p) 1128 { 1129 return kstrtobool(p, &enable_pseudo_nmi); 1130 } 1131 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1132 1133 static __init void detect_system_supports_pseudo_nmi(void) 1134 { 1135 struct device_node *np; 1136 1137 if (!enable_pseudo_nmi) 1138 return; 1139 1140 /* 1141 * Detect broken MediaTek firmware that doesn't properly save and 1142 * restore GIC priorities. 1143 */ 1144 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1145 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1146 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1147 enable_pseudo_nmi = false; 1148 } 1149 of_node_put(np); 1150 } 1151 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1152 static inline void detect_system_supports_pseudo_nmi(void) { } 1153 #endif 1154 1155 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1156 { 1157 /* Before we start using the tables, make sure it is sorted */ 1158 sort_ftr_regs(); 1159 1160 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1161 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1162 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1163 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1164 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1165 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1166 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1167 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1168 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1169 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1170 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1171 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1172 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1173 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1174 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1175 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1176 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1177 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1178 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1179 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1180 1181 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1182 init_32bit_cpu_features(&info->aarch32); 1183 1184 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1185 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1186 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1187 1188 vec_init_vq_map(ARM64_VEC_SVE); 1189 1190 cpacr_restore(cpacr); 1191 } 1192 1193 if (IS_ENABLED(CONFIG_ARM64_SME) && 1194 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1195 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1196 1197 vec_init_vq_map(ARM64_VEC_SME); 1198 1199 cpacr_restore(cpacr); 1200 } 1201 1202 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) 1203 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1204 1205 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1206 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1207 } 1208 1209 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1210 { 1211 const struct arm64_ftr_bits *ftrp; 1212 1213 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1214 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1215 s64 ftr_new = arm64_ftr_value(ftrp, new); 1216 1217 if (ftr_cur == ftr_new) 1218 continue; 1219 /* Find a safe value */ 1220 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1221 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1222 } 1223 1224 } 1225 1226 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1227 { 1228 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1229 1230 if (!regp) 1231 return 0; 1232 1233 update_cpu_ftr_reg(regp, val); 1234 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1235 return 0; 1236 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1237 regp->name, boot, cpu, val); 1238 return 1; 1239 } 1240 1241 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1242 { 1243 const struct arm64_ftr_bits *ftrp; 1244 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1245 1246 if (!regp) 1247 return; 1248 1249 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1250 if (ftrp->shift == field) { 1251 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1252 break; 1253 } 1254 } 1255 1256 /* Bogus field? */ 1257 WARN_ON(!ftrp->width); 1258 } 1259 1260 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1261 struct cpuinfo_arm64 *boot) 1262 { 1263 static bool boot_cpu_32bit_regs_overridden = false; 1264 1265 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1266 return; 1267 1268 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1269 return; 1270 1271 boot->aarch32 = info->aarch32; 1272 init_32bit_cpu_features(&boot->aarch32); 1273 boot_cpu_32bit_regs_overridden = true; 1274 } 1275 1276 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1277 struct cpuinfo_32bit *boot) 1278 { 1279 int taint = 0; 1280 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1281 1282 /* 1283 * If we don't have AArch32 at EL1, then relax the strictness of 1284 * EL1-dependent register fields to avoid spurious sanity check fails. 1285 */ 1286 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1287 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1288 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1289 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1290 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1291 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1292 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1293 } 1294 1295 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1296 info->reg_id_dfr0, boot->reg_id_dfr0); 1297 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1298 info->reg_id_dfr1, boot->reg_id_dfr1); 1299 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1300 info->reg_id_isar0, boot->reg_id_isar0); 1301 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1302 info->reg_id_isar1, boot->reg_id_isar1); 1303 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1304 info->reg_id_isar2, boot->reg_id_isar2); 1305 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1306 info->reg_id_isar3, boot->reg_id_isar3); 1307 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1308 info->reg_id_isar4, boot->reg_id_isar4); 1309 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1310 info->reg_id_isar5, boot->reg_id_isar5); 1311 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1312 info->reg_id_isar6, boot->reg_id_isar6); 1313 1314 /* 1315 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1316 * ACTLR formats could differ across CPUs and therefore would have to 1317 * be trapped for virtualization anyway. 1318 */ 1319 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1320 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1321 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1322 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1323 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1324 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1325 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1326 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1327 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1328 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1329 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1330 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1331 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1332 info->reg_id_pfr0, boot->reg_id_pfr0); 1333 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1334 info->reg_id_pfr1, boot->reg_id_pfr1); 1335 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1336 info->reg_id_pfr2, boot->reg_id_pfr2); 1337 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1338 info->reg_mvfr0, boot->reg_mvfr0); 1339 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1340 info->reg_mvfr1, boot->reg_mvfr1); 1341 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1342 info->reg_mvfr2, boot->reg_mvfr2); 1343 1344 return taint; 1345 } 1346 1347 /* 1348 * Update system wide CPU feature registers with the values from a 1349 * non-boot CPU. Also performs SANITY checks to make sure that there 1350 * aren't any insane variations from that of the boot CPU. 1351 */ 1352 void update_cpu_features(int cpu, 1353 struct cpuinfo_arm64 *info, 1354 struct cpuinfo_arm64 *boot) 1355 { 1356 int taint = 0; 1357 1358 /* 1359 * The kernel can handle differing I-cache policies, but otherwise 1360 * caches should look identical. Userspace JITs will make use of 1361 * *minLine. 1362 */ 1363 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1364 info->reg_ctr, boot->reg_ctr); 1365 1366 /* 1367 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1368 * could result in too much or too little memory being zeroed if a 1369 * process is preempted and migrated between CPUs. 1370 */ 1371 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1372 info->reg_dczid, boot->reg_dczid); 1373 1374 /* If different, timekeeping will be broken (especially with KVM) */ 1375 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1376 info->reg_cntfrq, boot->reg_cntfrq); 1377 1378 /* 1379 * The kernel uses self-hosted debug features and expects CPUs to 1380 * support identical debug features. We presently need CTX_CMPs, WRPs, 1381 * and BRPs to be identical. 1382 * ID_AA64DFR1 is currently RES0. 1383 */ 1384 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1385 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1386 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1387 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1388 /* 1389 * Even in big.LITTLE, processors should be identical instruction-set 1390 * wise. 1391 */ 1392 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1393 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1394 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1395 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1396 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1397 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1398 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1399 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1400 1401 /* 1402 * Differing PARange support is fine as long as all peripherals and 1403 * memory are mapped within the minimum PARange of all CPUs. 1404 * Linux should not care about secure memory. 1405 */ 1406 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1407 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1408 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1409 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1410 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1411 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1412 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1413 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1414 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1415 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1416 1417 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1418 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1419 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1420 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1421 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1422 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1423 1424 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1425 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1426 1427 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1428 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1429 1430 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1431 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1432 1433 /* Probe vector lengths */ 1434 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1435 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1436 if (!system_capabilities_finalized()) { 1437 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1438 1439 vec_update_vq_map(ARM64_VEC_SVE); 1440 1441 cpacr_restore(cpacr); 1442 } 1443 } 1444 1445 if (IS_ENABLED(CONFIG_ARM64_SME) && 1446 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1447 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1448 1449 /* Probe vector lengths */ 1450 if (!system_capabilities_finalized()) 1451 vec_update_vq_map(ARM64_VEC_SME); 1452 1453 cpacr_restore(cpacr); 1454 } 1455 1456 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { 1457 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1458 info->reg_mpamidr, boot->reg_mpamidr); 1459 } 1460 1461 /* 1462 * The kernel uses the LDGM/STGM instructions and the number of tags 1463 * they read/write depends on the GMID_EL1.BS field. Check that the 1464 * value is the same on all CPUs. 1465 */ 1466 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1467 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1468 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1469 info->reg_gmid, boot->reg_gmid); 1470 } 1471 1472 /* 1473 * If we don't have AArch32 at all then skip the checks entirely 1474 * as the register values may be UNKNOWN and we're not going to be 1475 * using them for anything. 1476 * 1477 * This relies on a sanitised view of the AArch64 ID registers 1478 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1479 */ 1480 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1481 lazy_init_32bit_cpu_features(info, boot); 1482 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1483 &boot->aarch32); 1484 } 1485 1486 /* 1487 * Mismatched CPU features are a recipe for disaster. Don't even 1488 * pretend to support them. 1489 */ 1490 if (taint) { 1491 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1492 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1493 } 1494 } 1495 1496 u64 read_sanitised_ftr_reg(u32 id) 1497 { 1498 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1499 1500 if (!regp) 1501 return 0; 1502 return regp->sys_val; 1503 } 1504 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1505 1506 #define read_sysreg_case(r) \ 1507 case r: val = read_sysreg_s(r); break; 1508 1509 /* 1510 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1511 * Read the system register on the current CPU 1512 */ 1513 u64 __read_sysreg_by_encoding(u32 sys_id) 1514 { 1515 struct arm64_ftr_reg *regp; 1516 u64 val; 1517 1518 switch (sys_id) { 1519 read_sysreg_case(SYS_ID_PFR0_EL1); 1520 read_sysreg_case(SYS_ID_PFR1_EL1); 1521 read_sysreg_case(SYS_ID_PFR2_EL1); 1522 read_sysreg_case(SYS_ID_DFR0_EL1); 1523 read_sysreg_case(SYS_ID_DFR1_EL1); 1524 read_sysreg_case(SYS_ID_MMFR0_EL1); 1525 read_sysreg_case(SYS_ID_MMFR1_EL1); 1526 read_sysreg_case(SYS_ID_MMFR2_EL1); 1527 read_sysreg_case(SYS_ID_MMFR3_EL1); 1528 read_sysreg_case(SYS_ID_MMFR4_EL1); 1529 read_sysreg_case(SYS_ID_MMFR5_EL1); 1530 read_sysreg_case(SYS_ID_ISAR0_EL1); 1531 read_sysreg_case(SYS_ID_ISAR1_EL1); 1532 read_sysreg_case(SYS_ID_ISAR2_EL1); 1533 read_sysreg_case(SYS_ID_ISAR3_EL1); 1534 read_sysreg_case(SYS_ID_ISAR4_EL1); 1535 read_sysreg_case(SYS_ID_ISAR5_EL1); 1536 read_sysreg_case(SYS_ID_ISAR6_EL1); 1537 read_sysreg_case(SYS_MVFR0_EL1); 1538 read_sysreg_case(SYS_MVFR1_EL1); 1539 read_sysreg_case(SYS_MVFR2_EL1); 1540 1541 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1542 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1543 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1544 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1545 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1546 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1547 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1548 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1549 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1550 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1551 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1552 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1553 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1554 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1555 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1556 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1557 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1558 1559 read_sysreg_case(SYS_CNTFRQ_EL0); 1560 read_sysreg_case(SYS_CTR_EL0); 1561 read_sysreg_case(SYS_DCZID_EL0); 1562 1563 default: 1564 BUG(); 1565 return 0; 1566 } 1567 1568 regp = get_arm64_ftr_reg(sys_id); 1569 if (regp) { 1570 val &= ~regp->override->mask; 1571 val |= (regp->override->val & regp->override->mask); 1572 } 1573 1574 return val; 1575 } 1576 1577 #include <linux/irqchip/arm-gic-v3.h> 1578 1579 static bool 1580 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1581 { 1582 return true; 1583 } 1584 1585 static bool 1586 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1587 { 1588 int val, min, max; 1589 u64 tmp; 1590 1591 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1592 entry->field_width, 1593 entry->sign); 1594 1595 tmp = entry->min_field_value; 1596 tmp <<= entry->field_pos; 1597 1598 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1599 entry->field_width, 1600 entry->sign); 1601 1602 tmp = entry->max_field_value; 1603 tmp <<= entry->field_pos; 1604 1605 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1606 entry->field_width, 1607 entry->sign); 1608 1609 return val >= min && val <= max; 1610 } 1611 1612 static u64 1613 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1614 { 1615 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1616 if (scope == SCOPE_SYSTEM) 1617 return read_sanitised_ftr_reg(entry->sys_reg); 1618 else 1619 return __read_sysreg_by_encoding(entry->sys_reg); 1620 } 1621 1622 static bool 1623 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1624 { 1625 int mask; 1626 struct arm64_ftr_reg *regp; 1627 u64 val = read_scoped_sysreg(entry, scope); 1628 1629 regp = get_arm64_ftr_reg(entry->sys_reg); 1630 if (!regp) 1631 return false; 1632 1633 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1634 entry->field_pos, 1635 entry->field_width); 1636 if (!mask) 1637 return false; 1638 1639 return feature_matches(val, entry); 1640 } 1641 1642 static bool 1643 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1644 { 1645 u64 val = read_scoped_sysreg(entry, scope); 1646 return feature_matches(val, entry); 1647 } 1648 1649 const struct cpumask *system_32bit_el0_cpumask(void) 1650 { 1651 if (!system_supports_32bit_el0()) 1652 return cpu_none_mask; 1653 1654 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1655 return cpu_32bit_el0_mask; 1656 1657 return cpu_possible_mask; 1658 } 1659 1660 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1661 { 1662 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1663 } 1664 1665 static int __init parse_32bit_el0_param(char *str) 1666 { 1667 allow_mismatched_32bit_el0 = true; 1668 return 0; 1669 } 1670 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1671 1672 static ssize_t aarch32_el0_show(struct device *dev, 1673 struct device_attribute *attr, char *buf) 1674 { 1675 const struct cpumask *mask = system_32bit_el0_cpumask(); 1676 1677 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1678 } 1679 static const DEVICE_ATTR_RO(aarch32_el0); 1680 1681 static int __init aarch32_el0_sysfs_init(void) 1682 { 1683 struct device *dev_root; 1684 int ret = 0; 1685 1686 if (!allow_mismatched_32bit_el0) 1687 return 0; 1688 1689 dev_root = bus_get_dev_root(&cpu_subsys); 1690 if (dev_root) { 1691 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1692 put_device(dev_root); 1693 } 1694 return ret; 1695 } 1696 device_initcall(aarch32_el0_sysfs_init); 1697 1698 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1699 { 1700 if (!has_cpuid_feature(entry, scope)) 1701 return allow_mismatched_32bit_el0; 1702 1703 if (scope == SCOPE_SYSTEM) 1704 pr_info("detected: 32-bit EL0 Support\n"); 1705 1706 return true; 1707 } 1708 1709 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1710 { 1711 bool has_sre; 1712 1713 if (!has_cpuid_feature(entry, scope)) 1714 return false; 1715 1716 has_sre = gic_enable_sre(); 1717 if (!has_sre) 1718 pr_warn_once("%s present but disabled by higher exception level\n", 1719 entry->desc); 1720 1721 return has_sre; 1722 } 1723 1724 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1725 int scope) 1726 { 1727 u64 ctr; 1728 1729 if (scope == SCOPE_SYSTEM) 1730 ctr = arm64_ftr_reg_ctrel0.sys_val; 1731 else 1732 ctr = read_cpuid_effective_cachetype(); 1733 1734 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1735 } 1736 1737 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1738 { 1739 /* 1740 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1741 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1742 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1743 * value. 1744 */ 1745 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1746 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1747 } 1748 1749 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1750 int scope) 1751 { 1752 u64 ctr; 1753 1754 if (scope == SCOPE_SYSTEM) 1755 ctr = arm64_ftr_reg_ctrel0.sys_val; 1756 else 1757 ctr = read_cpuid_cachetype(); 1758 1759 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1760 } 1761 1762 static bool __maybe_unused 1763 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1764 { 1765 /* 1766 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1767 * may share TLB entries with a CPU stuck in the crashed 1768 * kernel. 1769 */ 1770 if (is_kdump_kernel()) 1771 return false; 1772 1773 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1774 return false; 1775 1776 return has_cpuid_feature(entry, scope); 1777 } 1778 1779 static bool __meltdown_safe = true; 1780 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1781 1782 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1783 int scope) 1784 { 1785 /* List of CPUs that are not vulnerable and don't need KPTI */ 1786 static const struct midr_range kpti_safe_list[] = { 1787 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1788 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1789 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1790 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1791 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1792 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1793 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1794 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1795 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1796 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1797 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1798 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1799 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1800 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1801 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1802 { /* sentinel */ } 1803 }; 1804 char const *str = "kpti command line option"; 1805 bool meltdown_safe; 1806 1807 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1808 1809 /* Defer to CPU feature registers */ 1810 if (has_cpuid_feature(entry, scope)) 1811 meltdown_safe = true; 1812 1813 if (!meltdown_safe) 1814 __meltdown_safe = false; 1815 1816 /* 1817 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1818 * ThunderX leads to apparent I-cache corruption of kernel text, which 1819 * ends as well as you might imagine. Don't even try. We cannot rely 1820 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1821 * because cpucap detection order may change. However, since we know 1822 * affected CPUs are always in a homogeneous configuration, it is 1823 * safe to rely on this_cpu_has_cap() here. 1824 */ 1825 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1826 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1827 __kpti_forced = -1; 1828 } 1829 1830 /* Useful for KASLR robustness */ 1831 if (kaslr_enabled() && kaslr_requires_kpti()) { 1832 if (!__kpti_forced) { 1833 str = "KASLR"; 1834 __kpti_forced = 1; 1835 } 1836 } 1837 1838 if (cpu_mitigations_off() && !__kpti_forced) { 1839 str = "mitigations=off"; 1840 __kpti_forced = -1; 1841 } 1842 1843 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1844 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1845 return false; 1846 } 1847 1848 /* Forced? */ 1849 if (__kpti_forced) { 1850 pr_info_once("kernel page table isolation forced %s by %s\n", 1851 __kpti_forced > 0 ? "ON" : "OFF", str); 1852 return __kpti_forced > 0; 1853 } 1854 1855 return !meltdown_safe; 1856 } 1857 1858 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1859 { 1860 /* 1861 * Although the Apple M2 family appears to support NV1, the 1862 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1863 * that it doesn't support NV1 at all. 1864 */ 1865 static const struct midr_range nv1_ni_list[] = { 1866 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1867 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1868 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1869 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1870 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1871 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1872 {} 1873 }; 1874 1875 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1876 !(has_cpuid_feature(entry, scope) || 1877 is_midr_in_range_list(nv1_ni_list))); 1878 } 1879 1880 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1881 static bool has_lpa2_at_stage1(u64 mmfr0) 1882 { 1883 unsigned int tgran; 1884 1885 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1886 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1887 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1888 } 1889 1890 static bool has_lpa2_at_stage2(u64 mmfr0) 1891 { 1892 unsigned int tgran; 1893 1894 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1895 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1896 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1897 } 1898 1899 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1900 { 1901 u64 mmfr0; 1902 1903 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1904 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1905 } 1906 #else 1907 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1908 { 1909 return false; 1910 } 1911 #endif 1912 1913 #ifdef CONFIG_HW_PERF_EVENTS 1914 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1915 { 1916 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1917 unsigned int pmuver; 1918 1919 /* 1920 * PMUVer follows the standard ID scheme for an unsigned field with the 1921 * exception of 0xF (IMP_DEF) which is treated specially and implies 1922 * FEAT_PMUv3 is not implemented. 1923 * 1924 * See DDI0487L.a D24.1.3.2 for more details. 1925 */ 1926 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1927 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1928 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1929 return false; 1930 1931 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1932 } 1933 #endif 1934 1935 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1936 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1937 1938 extern 1939 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1940 phys_addr_t size, pgprot_t prot, 1941 phys_addr_t (*pgtable_alloc)(int), int flags); 1942 1943 static phys_addr_t __initdata kpti_ng_temp_alloc; 1944 1945 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1946 { 1947 kpti_ng_temp_alloc -= PAGE_SIZE; 1948 return kpti_ng_temp_alloc; 1949 } 1950 1951 static int __init __kpti_install_ng_mappings(void *__unused) 1952 { 1953 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1954 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1955 kpti_remap_fn *remap_fn; 1956 1957 int cpu = smp_processor_id(); 1958 int levels = CONFIG_PGTABLE_LEVELS; 1959 int order = order_base_2(levels); 1960 u64 kpti_ng_temp_pgd_pa = 0; 1961 pgd_t *kpti_ng_temp_pgd; 1962 u64 alloc = 0; 1963 1964 if (levels == 5 && !pgtable_l5_enabled()) 1965 levels = 4; 1966 else if (levels == 4 && !pgtable_l4_enabled()) 1967 levels = 3; 1968 1969 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1970 1971 if (!cpu) { 1972 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1973 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1974 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1975 1976 // 1977 // Create a minimal page table hierarchy that permits us to map 1978 // the swapper page tables temporarily as we traverse them. 1979 // 1980 // The physical pages are laid out as follows: 1981 // 1982 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1983 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1984 // +--------+-\-------+-\------ +-\------ +-///--------+ 1985 // ^ 1986 // The first page is mapped into this hierarchy at a PMD_SHIFT 1987 // aligned virtual address, so that we can manipulate the PTE 1988 // level entries while the mapping is active. The first entry 1989 // covers the PTE[] page itself, the remaining entries are free 1990 // to be used as a ad-hoc fixmap. 1991 // 1992 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1993 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1994 kpti_ng_pgd_alloc, 0); 1995 } 1996 1997 cpu_install_idmap(); 1998 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 1999 cpu_uninstall_idmap(); 2000 2001 if (!cpu) { 2002 free_pages(alloc, order); 2003 arm64_use_ng_mappings = true; 2004 } 2005 2006 return 0; 2007 } 2008 2009 static void __init kpti_install_ng_mappings(void) 2010 { 2011 /* Check whether KPTI is going to be used */ 2012 if (!arm64_kernel_unmapped_at_el0()) 2013 return; 2014 2015 /* 2016 * We don't need to rewrite the page-tables if either we've done 2017 * it already or we have KASLR enabled and therefore have not 2018 * created any global mappings at all. 2019 */ 2020 if (arm64_use_ng_mappings) 2021 return; 2022 2023 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 2024 } 2025 2026 #else 2027 static inline void kpti_install_ng_mappings(void) 2028 { 2029 } 2030 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 2031 2032 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 2033 { 2034 if (__this_cpu_read(this_cpu_vector) == vectors) { 2035 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2036 2037 __this_cpu_write(this_cpu_vector, v); 2038 } 2039 2040 } 2041 2042 static int __init parse_kpti(char *str) 2043 { 2044 bool enabled; 2045 int ret = kstrtobool(str, &enabled); 2046 2047 if (ret) 2048 return ret; 2049 2050 __kpti_forced = enabled ? 1 : -1; 2051 return 0; 2052 } 2053 early_param("kpti", parse_kpti); 2054 2055 #ifdef CONFIG_ARM64_HW_AFDBM 2056 static struct cpumask dbm_cpus __read_mostly; 2057 2058 static inline void __cpu_enable_hw_dbm(void) 2059 { 2060 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2061 2062 write_sysreg(tcr, tcr_el1); 2063 isb(); 2064 local_flush_tlb_all(); 2065 } 2066 2067 static bool cpu_has_broken_dbm(void) 2068 { 2069 /* List of CPUs which have broken DBM support. */ 2070 static const struct midr_range cpus[] = { 2071 #ifdef CONFIG_ARM64_ERRATUM_1024718 2072 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2073 /* Kryo4xx Silver (rdpe => r1p0) */ 2074 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2075 #endif 2076 #ifdef CONFIG_ARM64_ERRATUM_2051678 2077 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2078 #endif 2079 {}, 2080 }; 2081 2082 return is_midr_in_range_list(cpus); 2083 } 2084 2085 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2086 { 2087 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2088 !cpu_has_broken_dbm(); 2089 } 2090 2091 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2092 { 2093 if (cpu_can_use_dbm(cap)) { 2094 __cpu_enable_hw_dbm(); 2095 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2096 } 2097 } 2098 2099 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2100 int __unused) 2101 { 2102 /* 2103 * DBM is a non-conflicting feature. i.e, the kernel can safely 2104 * run a mix of CPUs with and without the feature. So, we 2105 * unconditionally enable the capability to allow any late CPU 2106 * to use the feature. We only enable the control bits on the 2107 * CPU, if it is supported. 2108 */ 2109 2110 return true; 2111 } 2112 2113 #endif 2114 2115 #ifdef CONFIG_ARM64_AMU_EXTN 2116 2117 /* 2118 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2119 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2120 * information regarding all the events that it supports. When a CPU bit is 2121 * set in the cpumask, the user of this feature can only rely on the presence 2122 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2123 * counters are enabled or access to these counters is enabled by code 2124 * executed at higher exception levels (firmware). 2125 */ 2126 static struct cpumask amu_cpus __read_mostly; 2127 2128 bool cpu_has_amu_feat(int cpu) 2129 { 2130 return cpumask_test_cpu(cpu, &amu_cpus); 2131 } 2132 2133 int get_cpu_with_amu_feat(void) 2134 { 2135 return cpumask_any(&amu_cpus); 2136 } 2137 2138 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2139 { 2140 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2141 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2142 2143 /* 0 reference values signal broken/disabled counters */ 2144 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2145 update_freq_counters_refs(); 2146 } 2147 } 2148 2149 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2150 int __unused) 2151 { 2152 /* 2153 * The AMU extension is a non-conflicting feature: the kernel can 2154 * safely run a mix of CPUs with and without support for the 2155 * activity monitors extension. Therefore, unconditionally enable 2156 * the capability to allow any late CPU to use the feature. 2157 * 2158 * With this feature unconditionally enabled, the cpu_enable 2159 * function will be called for all CPUs that match the criteria, 2160 * including secondary and hotplugged, marking this feature as 2161 * present on that respective CPU. The enable function will also 2162 * print a detection message. 2163 */ 2164 2165 return true; 2166 } 2167 #else 2168 int get_cpu_with_amu_feat(void) 2169 { 2170 return nr_cpu_ids; 2171 } 2172 #endif 2173 2174 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2175 { 2176 return is_kernel_in_hyp_mode(); 2177 } 2178 2179 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2180 { 2181 /* 2182 * Copy register values that aren't redirected by hardware. 2183 * 2184 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2185 * this value to tpidr_el2 before we patch the code. Once we've done 2186 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2187 * do anything here. 2188 */ 2189 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2190 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2191 } 2192 2193 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2194 int scope) 2195 { 2196 if (kvm_get_mode() != KVM_MODE_NV) 2197 return false; 2198 2199 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2200 pr_warn("unavailable: %s\n", cap->desc); 2201 return false; 2202 } 2203 2204 return true; 2205 } 2206 2207 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2208 int __unused) 2209 { 2210 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2211 } 2212 2213 #ifdef CONFIG_ARM64_PAN 2214 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2215 { 2216 /* 2217 * We modify PSTATE. This won't work from irq context as the PSTATE 2218 * is discarded once we return from the exception. 2219 */ 2220 WARN_ON_ONCE(in_interrupt()); 2221 2222 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2223 set_pstate_pan(1); 2224 } 2225 #endif /* CONFIG_ARM64_PAN */ 2226 2227 #ifdef CONFIG_ARM64_RAS_EXTN 2228 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2229 { 2230 /* Firmware may have left a deferred SError in this register. */ 2231 write_sysreg_s(0, SYS_DISR_EL1); 2232 } 2233 #endif /* CONFIG_ARM64_RAS_EXTN */ 2234 2235 #ifdef CONFIG_ARM64_PTR_AUTH 2236 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2237 { 2238 int boot_val, sec_val; 2239 2240 /* We don't expect to be called with SCOPE_SYSTEM */ 2241 WARN_ON(scope == SCOPE_SYSTEM); 2242 /* 2243 * The ptr-auth feature levels are not intercompatible with lower 2244 * levels. Hence we must match ptr-auth feature level of the secondary 2245 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2246 * from the sanitised register whereas direct register read is done for 2247 * the secondary CPUs. 2248 * The sanitised feature state is guaranteed to match that of the 2249 * boot CPU as a mismatched secondary CPU is parked before it gets 2250 * a chance to update the state, with the capability. 2251 */ 2252 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2253 entry->field_pos, entry->sign); 2254 if (scope & SCOPE_BOOT_CPU) 2255 return boot_val >= entry->min_field_value; 2256 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2257 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2258 entry->field_pos, entry->sign); 2259 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2260 } 2261 2262 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2263 int scope) 2264 { 2265 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2266 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2267 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2268 2269 return apa || apa3 || api; 2270 } 2271 2272 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2273 int __unused) 2274 { 2275 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2276 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2277 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2278 2279 return gpa || gpa3 || gpi; 2280 } 2281 #endif /* CONFIG_ARM64_PTR_AUTH */ 2282 2283 #ifdef CONFIG_ARM64_E0PD 2284 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2285 { 2286 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2287 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2288 } 2289 #endif /* CONFIG_ARM64_E0PD */ 2290 2291 #ifdef CONFIG_ARM64_PSEUDO_NMI 2292 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2293 int scope) 2294 { 2295 /* 2296 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2297 * feature, so will be detected earlier. 2298 */ 2299 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2300 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2301 return false; 2302 2303 return enable_pseudo_nmi; 2304 } 2305 2306 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2307 int scope) 2308 { 2309 /* 2310 * If we're not using priority masking then we won't be poking PMR_EL1, 2311 * and there's no need to relax synchronization of writes to it, and 2312 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2313 * that. 2314 * 2315 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2316 * feature, so will be detected earlier. 2317 */ 2318 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2319 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2320 return false; 2321 2322 /* 2323 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2324 * hint for interrupt distribution, a DSB is not necessary when 2325 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2326 * 2327 * Linux itself doesn't use 1:N distribution, so has no need to 2328 * set PMHE. The only reason to have it set is if EL3 requires it 2329 * (and we can't change it). 2330 */ 2331 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2332 } 2333 #endif 2334 2335 #ifdef CONFIG_ARM64_BTI 2336 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2337 { 2338 /* 2339 * Use of X16/X17 for tail-calls and trampolines that jump to 2340 * function entry points using BR is a requirement for 2341 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2342 * So, be strict and forbid other BRs using other registers to 2343 * jump onto a PACIxSP instruction: 2344 */ 2345 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2346 isb(); 2347 } 2348 #endif /* CONFIG_ARM64_BTI */ 2349 2350 #ifdef CONFIG_ARM64_MTE 2351 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2352 { 2353 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2354 2355 mte_cpu_setup(); 2356 2357 /* 2358 * Clear the tags in the zero page. This needs to be done via the 2359 * linear map which has the Tagged attribute. 2360 */ 2361 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2362 mte_clear_page_tags(lm_alias(empty_zero_page)); 2363 set_page_mte_tagged(ZERO_PAGE(0)); 2364 } 2365 2366 kasan_init_hw_tags_cpu(); 2367 } 2368 #endif /* CONFIG_ARM64_MTE */ 2369 2370 static void user_feature_fixup(void) 2371 { 2372 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2373 struct arm64_ftr_reg *regp; 2374 2375 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2376 if (regp) 2377 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2378 } 2379 2380 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2381 struct arm64_ftr_reg *regp; 2382 2383 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2384 if (regp) 2385 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2386 } 2387 } 2388 2389 static void elf_hwcap_fixup(void) 2390 { 2391 #ifdef CONFIG_COMPAT 2392 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2393 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2394 #endif /* CONFIG_COMPAT */ 2395 } 2396 2397 #ifdef CONFIG_KVM 2398 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2399 { 2400 return kvm_get_mode() == KVM_MODE_PROTECTED; 2401 } 2402 #endif /* CONFIG_KVM */ 2403 2404 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2405 { 2406 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2407 } 2408 2409 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2410 { 2411 set_pstate_dit(1); 2412 } 2413 2414 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2415 { 2416 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2417 } 2418 2419 #ifdef CONFIG_ARM64_POE 2420 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2421 { 2422 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2423 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2424 } 2425 #endif 2426 2427 #ifdef CONFIG_ARM64_GCS 2428 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2429 { 2430 /* GCSPR_EL0 is always readable */ 2431 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2432 } 2433 #endif 2434 2435 /* Internal helper functions to match cpu capability type */ 2436 static bool 2437 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2438 { 2439 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2440 } 2441 2442 static bool 2443 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2444 { 2445 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2446 } 2447 2448 static bool 2449 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2450 { 2451 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2452 } 2453 2454 static bool 2455 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2456 { 2457 if (!has_cpuid_feature(entry, scope)) 2458 return false; 2459 2460 /* Check firmware actually enabled MPAM on this cpu. */ 2461 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2462 } 2463 2464 static void 2465 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2466 { 2467 /* 2468 * Access by the kernel (at EL1) should use the reserved PARTID 2469 * which is configured unrestricted. This avoids priority-inversion 2470 * where latency sensitive tasks have to wait for a task that has 2471 * been throttled to release the lock. 2472 */ 2473 write_sysreg_s(0, SYS_MPAM1_EL1); 2474 } 2475 2476 static bool 2477 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2478 { 2479 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2480 2481 return idr & MPAMIDR_EL1_HAS_HCR; 2482 } 2483 2484 static const struct arm64_cpu_capabilities arm64_features[] = { 2485 { 2486 .capability = ARM64_ALWAYS_BOOT, 2487 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2488 .matches = has_always, 2489 }, 2490 { 2491 .capability = ARM64_ALWAYS_SYSTEM, 2492 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2493 .matches = has_always, 2494 }, 2495 { 2496 .desc = "GIC system register CPU interface", 2497 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2498 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2499 .matches = has_useable_gicv3_cpuif, 2500 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2501 }, 2502 { 2503 .desc = "Enhanced Counter Virtualization", 2504 .capability = ARM64_HAS_ECV, 2505 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2506 .matches = has_cpuid_feature, 2507 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2508 }, 2509 { 2510 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2511 .capability = ARM64_HAS_ECV_CNTPOFF, 2512 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2513 .matches = has_cpuid_feature, 2514 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2515 }, 2516 #ifdef CONFIG_ARM64_PAN 2517 { 2518 .desc = "Privileged Access Never", 2519 .capability = ARM64_HAS_PAN, 2520 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2521 .matches = has_cpuid_feature, 2522 .cpu_enable = cpu_enable_pan, 2523 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2524 }, 2525 #endif /* CONFIG_ARM64_PAN */ 2526 #ifdef CONFIG_ARM64_EPAN 2527 { 2528 .desc = "Enhanced Privileged Access Never", 2529 .capability = ARM64_HAS_EPAN, 2530 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2531 .matches = has_cpuid_feature, 2532 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2533 }, 2534 #endif /* CONFIG_ARM64_EPAN */ 2535 #ifdef CONFIG_ARM64_LSE_ATOMICS 2536 { 2537 .desc = "LSE atomic instructions", 2538 .capability = ARM64_HAS_LSE_ATOMICS, 2539 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2540 .matches = has_cpuid_feature, 2541 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2542 }, 2543 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2544 { 2545 .desc = "Virtualization Host Extensions", 2546 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2547 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2548 .matches = runs_at_el2, 2549 .cpu_enable = cpu_copy_el2regs, 2550 }, 2551 { 2552 .desc = "Nested Virtualization Support", 2553 .capability = ARM64_HAS_NESTED_VIRT, 2554 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2555 .matches = has_nested_virt_support, 2556 .match_list = (const struct arm64_cpu_capabilities []){ 2557 { 2558 .matches = has_cpuid_feature, 2559 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2560 }, 2561 { 2562 .matches = has_cpuid_feature, 2563 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2564 }, 2565 { /* Sentinel */ } 2566 }, 2567 }, 2568 { 2569 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2570 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2571 .matches = has_32bit_el0, 2572 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2573 }, 2574 #ifdef CONFIG_KVM 2575 { 2576 .desc = "32-bit EL1 Support", 2577 .capability = ARM64_HAS_32BIT_EL1, 2578 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2579 .matches = has_cpuid_feature, 2580 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2581 }, 2582 { 2583 .desc = "Protected KVM", 2584 .capability = ARM64_KVM_PROTECTED_MODE, 2585 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2586 .matches = is_kvm_protected_mode, 2587 }, 2588 { 2589 .desc = "HCRX_EL2 register", 2590 .capability = ARM64_HAS_HCX, 2591 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2592 .matches = has_cpuid_feature, 2593 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2594 }, 2595 #endif 2596 { 2597 .desc = "Kernel page table isolation (KPTI)", 2598 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2599 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2600 .cpu_enable = cpu_enable_kpti, 2601 .matches = unmap_kernel_at_el0, 2602 /* 2603 * The ID feature fields below are used to indicate that 2604 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2605 * more details. 2606 */ 2607 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2608 }, 2609 { 2610 .capability = ARM64_HAS_FPSIMD, 2611 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2612 .matches = has_cpuid_feature, 2613 .cpu_enable = cpu_enable_fpsimd, 2614 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2615 }, 2616 #ifdef CONFIG_ARM64_PMEM 2617 { 2618 .desc = "Data cache clean to Point of Persistence", 2619 .capability = ARM64_HAS_DCPOP, 2620 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2621 .matches = has_cpuid_feature, 2622 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2623 }, 2624 { 2625 .desc = "Data cache clean to Point of Deep Persistence", 2626 .capability = ARM64_HAS_DCPODP, 2627 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2628 .matches = has_cpuid_feature, 2629 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2630 }, 2631 #endif 2632 #ifdef CONFIG_ARM64_SVE 2633 { 2634 .desc = "Scalable Vector Extension", 2635 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2636 .capability = ARM64_SVE, 2637 .cpu_enable = cpu_enable_sve, 2638 .matches = has_cpuid_feature, 2639 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2640 }, 2641 #endif /* CONFIG_ARM64_SVE */ 2642 #ifdef CONFIG_ARM64_RAS_EXTN 2643 { 2644 .desc = "RAS Extension Support", 2645 .capability = ARM64_HAS_RAS_EXTN, 2646 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2647 .matches = has_cpuid_feature, 2648 .cpu_enable = cpu_clear_disr, 2649 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2650 }, 2651 #endif /* CONFIG_ARM64_RAS_EXTN */ 2652 #ifdef CONFIG_ARM64_AMU_EXTN 2653 { 2654 .desc = "Activity Monitors Unit (AMU)", 2655 .capability = ARM64_HAS_AMU_EXTN, 2656 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2657 .matches = has_amu, 2658 .cpu_enable = cpu_amu_enable, 2659 .cpus = &amu_cpus, 2660 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2661 }, 2662 #endif /* CONFIG_ARM64_AMU_EXTN */ 2663 { 2664 .desc = "Data cache clean to the PoU not required for I/D coherence", 2665 .capability = ARM64_HAS_CACHE_IDC, 2666 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2667 .matches = has_cache_idc, 2668 .cpu_enable = cpu_emulate_effective_ctr, 2669 }, 2670 { 2671 .desc = "Instruction cache invalidation not required for I/D coherence", 2672 .capability = ARM64_HAS_CACHE_DIC, 2673 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2674 .matches = has_cache_dic, 2675 }, 2676 { 2677 .desc = "Stage-2 Force Write-Back", 2678 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2679 .capability = ARM64_HAS_STAGE2_FWB, 2680 .matches = has_cpuid_feature, 2681 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2682 }, 2683 { 2684 .desc = "ARMv8.4 Translation Table Level", 2685 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2686 .capability = ARM64_HAS_ARMv8_4_TTL, 2687 .matches = has_cpuid_feature, 2688 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2689 }, 2690 { 2691 .desc = "TLB range maintenance instructions", 2692 .capability = ARM64_HAS_TLB_RANGE, 2693 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2694 .matches = has_cpuid_feature, 2695 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2696 }, 2697 #ifdef CONFIG_ARM64_HW_AFDBM 2698 { 2699 .desc = "Hardware dirty bit management", 2700 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2701 .capability = ARM64_HW_DBM, 2702 .matches = has_hw_dbm, 2703 .cpu_enable = cpu_enable_hw_dbm, 2704 .cpus = &dbm_cpus, 2705 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2706 }, 2707 #endif 2708 #ifdef CONFIG_ARM64_HAFT 2709 { 2710 .desc = "Hardware managed Access Flag for Table Descriptors", 2711 /* 2712 * Contrary to the page/block access flag, the table access flag 2713 * cannot be emulated in software (no access fault will occur). 2714 * Therefore this should be used only if it's supported system 2715 * wide. 2716 */ 2717 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2718 .capability = ARM64_HAFT, 2719 .matches = has_cpuid_feature, 2720 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2721 }, 2722 #endif 2723 { 2724 .desc = "CRC32 instructions", 2725 .capability = ARM64_HAS_CRC32, 2726 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2727 .matches = has_cpuid_feature, 2728 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2729 }, 2730 { 2731 .desc = "Speculative Store Bypassing Safe (SSBS)", 2732 .capability = ARM64_SSBS, 2733 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2734 .matches = has_cpuid_feature, 2735 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2736 }, 2737 #ifdef CONFIG_ARM64_CNP 2738 { 2739 .desc = "Common not Private translations", 2740 .capability = ARM64_HAS_CNP, 2741 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2742 .matches = has_useable_cnp, 2743 .cpu_enable = cpu_enable_cnp, 2744 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2745 }, 2746 #endif 2747 { 2748 .desc = "Speculation barrier (SB)", 2749 .capability = ARM64_HAS_SB, 2750 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2751 .matches = has_cpuid_feature, 2752 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2753 }, 2754 #ifdef CONFIG_ARM64_PTR_AUTH 2755 { 2756 .desc = "Address authentication (architected QARMA5 algorithm)", 2757 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2758 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2759 .matches = has_address_auth_cpucap, 2760 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2761 }, 2762 { 2763 .desc = "Address authentication (architected QARMA3 algorithm)", 2764 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2765 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2766 .matches = has_address_auth_cpucap, 2767 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2768 }, 2769 { 2770 .desc = "Address authentication (IMP DEF algorithm)", 2771 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2772 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2773 .matches = has_address_auth_cpucap, 2774 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2775 }, 2776 { 2777 .capability = ARM64_HAS_ADDRESS_AUTH, 2778 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2779 .matches = has_address_auth_metacap, 2780 }, 2781 { 2782 .desc = "Generic authentication (architected QARMA5 algorithm)", 2783 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2784 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2785 .matches = has_cpuid_feature, 2786 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2787 }, 2788 { 2789 .desc = "Generic authentication (architected QARMA3 algorithm)", 2790 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2791 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2792 .matches = has_cpuid_feature, 2793 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2794 }, 2795 { 2796 .desc = "Generic authentication (IMP DEF algorithm)", 2797 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2798 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2799 .matches = has_cpuid_feature, 2800 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2801 }, 2802 { 2803 .capability = ARM64_HAS_GENERIC_AUTH, 2804 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2805 .matches = has_generic_auth, 2806 }, 2807 #endif /* CONFIG_ARM64_PTR_AUTH */ 2808 #ifdef CONFIG_ARM64_PSEUDO_NMI 2809 { 2810 /* 2811 * Depends on having GICv3 2812 */ 2813 .desc = "IRQ priority masking", 2814 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2815 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2816 .matches = can_use_gic_priorities, 2817 }, 2818 { 2819 /* 2820 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2821 */ 2822 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2823 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2824 .matches = has_gic_prio_relaxed_sync, 2825 }, 2826 #endif 2827 #ifdef CONFIG_ARM64_E0PD 2828 { 2829 .desc = "E0PD", 2830 .capability = ARM64_HAS_E0PD, 2831 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2832 .cpu_enable = cpu_enable_e0pd, 2833 .matches = has_cpuid_feature, 2834 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2835 }, 2836 #endif 2837 { 2838 .desc = "Random Number Generator", 2839 .capability = ARM64_HAS_RNG, 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .matches = has_cpuid_feature, 2842 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2843 }, 2844 #ifdef CONFIG_ARM64_BTI 2845 { 2846 .desc = "Branch Target Identification", 2847 .capability = ARM64_BTI, 2848 #ifdef CONFIG_ARM64_BTI_KERNEL 2849 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2850 #else 2851 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2852 #endif 2853 .matches = has_cpuid_feature, 2854 .cpu_enable = bti_enable, 2855 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2856 }, 2857 #endif 2858 #ifdef CONFIG_ARM64_MTE 2859 { 2860 .desc = "Memory Tagging Extension", 2861 .capability = ARM64_MTE, 2862 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2863 .matches = has_cpuid_feature, 2864 .cpu_enable = cpu_enable_mte, 2865 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2866 }, 2867 { 2868 .desc = "Asymmetric MTE Tag Check Fault", 2869 .capability = ARM64_MTE_ASYMM, 2870 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2871 .matches = has_cpuid_feature, 2872 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2873 }, 2874 #endif /* CONFIG_ARM64_MTE */ 2875 { 2876 .desc = "RCpc load-acquire (LDAPR)", 2877 .capability = ARM64_HAS_LDAPR, 2878 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2879 .matches = has_cpuid_feature, 2880 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2881 }, 2882 { 2883 .desc = "Fine Grained Traps", 2884 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2885 .capability = ARM64_HAS_FGT, 2886 .matches = has_cpuid_feature, 2887 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2888 }, 2889 { 2890 .desc = "Fine Grained Traps 2", 2891 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2892 .capability = ARM64_HAS_FGT2, 2893 .matches = has_cpuid_feature, 2894 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2895 }, 2896 #ifdef CONFIG_ARM64_SME 2897 { 2898 .desc = "Scalable Matrix Extension", 2899 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2900 .capability = ARM64_SME, 2901 .matches = has_cpuid_feature, 2902 .cpu_enable = cpu_enable_sme, 2903 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2904 }, 2905 /* FA64 should be sorted after the base SME capability */ 2906 { 2907 .desc = "FA64", 2908 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2909 .capability = ARM64_SME_FA64, 2910 .matches = has_cpuid_feature, 2911 .cpu_enable = cpu_enable_fa64, 2912 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2913 }, 2914 { 2915 .desc = "SME2", 2916 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2917 .capability = ARM64_SME2, 2918 .matches = has_cpuid_feature, 2919 .cpu_enable = cpu_enable_sme2, 2920 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2921 }, 2922 #endif /* CONFIG_ARM64_SME */ 2923 { 2924 .desc = "WFx with timeout", 2925 .capability = ARM64_HAS_WFXT, 2926 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2927 .matches = has_cpuid_feature, 2928 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2929 }, 2930 { 2931 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2932 .capability = ARM64_HAS_TIDCP1, 2933 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2934 .matches = has_cpuid_feature, 2935 .cpu_enable = cpu_trap_el0_impdef, 2936 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2937 }, 2938 { 2939 .desc = "Data independent timing control (DIT)", 2940 .capability = ARM64_HAS_DIT, 2941 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2942 .matches = has_cpuid_feature, 2943 .cpu_enable = cpu_enable_dit, 2944 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2945 }, 2946 { 2947 .desc = "Memory Copy and Memory Set instructions", 2948 .capability = ARM64_HAS_MOPS, 2949 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2950 .matches = has_cpuid_feature, 2951 .cpu_enable = cpu_enable_mops, 2952 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2953 }, 2954 { 2955 .capability = ARM64_HAS_TCR2, 2956 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2957 .matches = has_cpuid_feature, 2958 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 2959 }, 2960 { 2961 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 2962 .capability = ARM64_HAS_S1PIE, 2963 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2964 .matches = has_cpuid_feature, 2965 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 2966 }, 2967 { 2968 .desc = "VHE for hypervisor only", 2969 .capability = ARM64_KVM_HVHE, 2970 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2971 .matches = hvhe_possible, 2972 }, 2973 { 2974 .desc = "Enhanced Virtualization Traps", 2975 .capability = ARM64_HAS_EVT, 2976 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2977 .matches = has_cpuid_feature, 2978 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 2979 }, 2980 { 2981 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 2982 .capability = ARM64_HAS_LPA2, 2983 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2984 .matches = has_lpa2, 2985 }, 2986 { 2987 .desc = "FPMR", 2988 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2989 .capability = ARM64_HAS_FPMR, 2990 .matches = has_cpuid_feature, 2991 .cpu_enable = cpu_enable_fpmr, 2992 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 2993 }, 2994 #ifdef CONFIG_ARM64_VA_BITS_52 2995 { 2996 .capability = ARM64_HAS_VA52, 2997 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2998 .matches = has_cpuid_feature, 2999 #ifdef CONFIG_ARM64_64K_PAGES 3000 .desc = "52-bit Virtual Addressing (LVA)", 3001 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3002 #else 3003 .desc = "52-bit Virtual Addressing (LPA2)", 3004 #ifdef CONFIG_ARM64_4K_PAGES 3005 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3006 #else 3007 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3008 #endif 3009 #endif 3010 }, 3011 #endif 3012 { 3013 .desc = "Memory Partitioning And Monitoring", 3014 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3015 .capability = ARM64_MPAM, 3016 .matches = test_has_mpam, 3017 .cpu_enable = cpu_enable_mpam, 3018 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3019 }, 3020 { 3021 .desc = "Memory Partitioning And Monitoring Virtualisation", 3022 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3023 .capability = ARM64_MPAM_HCR, 3024 .matches = test_has_mpam_hcr, 3025 }, 3026 { 3027 .desc = "NV1", 3028 .capability = ARM64_HAS_HCR_NV1, 3029 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3030 .matches = has_nv1, 3031 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3032 }, 3033 #ifdef CONFIG_ARM64_POE 3034 { 3035 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3036 .capability = ARM64_HAS_S1POE, 3037 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3038 .matches = has_cpuid_feature, 3039 .cpu_enable = cpu_enable_poe, 3040 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3041 }, 3042 #endif 3043 #ifdef CONFIG_ARM64_GCS 3044 { 3045 .desc = "Guarded Control Stack (GCS)", 3046 .capability = ARM64_HAS_GCS, 3047 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3048 .cpu_enable = cpu_enable_gcs, 3049 .matches = has_cpuid_feature, 3050 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3051 }, 3052 #endif 3053 #ifdef CONFIG_HW_PERF_EVENTS 3054 { 3055 .desc = "PMUv3", 3056 .capability = ARM64_HAS_PMUV3, 3057 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3058 .matches = has_pmuv3, 3059 }, 3060 #endif 3061 {}, 3062 }; 3063 3064 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3065 .matches = has_user_cpuid_feature, \ 3066 ARM64_CPUID_FIELDS(reg, field, min_value) 3067 3068 #define __HWCAP_CAP(name, cap_type, cap) \ 3069 .desc = name, \ 3070 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3071 .hwcap_type = cap_type, \ 3072 .hwcap = cap, \ 3073 3074 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3075 { \ 3076 __HWCAP_CAP(#cap, cap_type, cap) \ 3077 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3078 } 3079 3080 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3081 { \ 3082 __HWCAP_CAP(#cap, cap_type, cap) \ 3083 .matches = cpucap_multi_entry_cap_matches, \ 3084 .match_list = list, \ 3085 } 3086 3087 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3088 { \ 3089 __HWCAP_CAP(#cap, cap_type, cap) \ 3090 .matches = match, \ 3091 } 3092 3093 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3094 { \ 3095 __HWCAP_CAP(#cap, cap_type, cap) \ 3096 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3097 .matches = match, \ 3098 } 3099 3100 #ifdef CONFIG_ARM64_PTR_AUTH 3101 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3102 { 3103 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3104 }, 3105 { 3106 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3107 }, 3108 { 3109 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3110 }, 3111 {}, 3112 }; 3113 3114 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3115 { 3116 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3117 }, 3118 { 3119 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3120 }, 3121 { 3122 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3123 }, 3124 {}, 3125 }; 3126 #endif 3127 3128 #ifdef CONFIG_ARM64_SVE 3129 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3130 { 3131 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3132 } 3133 #endif 3134 3135 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3136 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3137 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3138 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3139 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3140 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3141 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3142 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3143 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3144 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3145 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3146 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3147 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3148 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3149 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3150 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3151 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3152 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3153 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3154 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3155 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3156 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3157 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3158 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3159 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3160 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3161 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3162 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3163 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3164 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3165 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3166 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3167 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3168 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3169 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3170 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3171 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3172 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3173 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3174 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3175 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3176 #ifdef CONFIG_ARM64_SVE 3177 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3178 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3179 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3180 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3181 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3182 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3183 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3184 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3185 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3186 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3187 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3188 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3189 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3190 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3191 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3192 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3193 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3194 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3195 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3196 #endif 3197 #ifdef CONFIG_ARM64_GCS 3198 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3199 #endif 3200 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3201 #ifdef CONFIG_ARM64_BTI 3202 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3203 #endif 3204 #ifdef CONFIG_ARM64_PTR_AUTH 3205 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3206 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3207 #endif 3208 #ifdef CONFIG_ARM64_MTE 3209 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3210 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3211 #endif /* CONFIG_ARM64_MTE */ 3212 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3213 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3214 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3215 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3216 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3217 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3218 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3219 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3220 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3221 #ifdef CONFIG_ARM64_SME 3222 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3223 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3224 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3225 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3226 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3227 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3228 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3229 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3230 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3231 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3232 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3233 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3234 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3235 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3236 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3237 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3238 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3239 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3240 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3241 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3242 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3243 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3244 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3245 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3246 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3247 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3248 #endif /* CONFIG_ARM64_SME */ 3249 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3250 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3251 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3252 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3253 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3254 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3255 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3256 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3257 #ifdef CONFIG_ARM64_POE 3258 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3259 #endif 3260 {}, 3261 }; 3262 3263 #ifdef CONFIG_COMPAT 3264 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3265 { 3266 /* 3267 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3268 * in line with that of arm32 as in vfp_init(). We make sure that the 3269 * check is future proof, by making sure value is non-zero. 3270 */ 3271 u32 mvfr1; 3272 3273 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3274 if (scope == SCOPE_SYSTEM) 3275 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3276 else 3277 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3278 3279 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3280 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3281 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3282 } 3283 #endif 3284 3285 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3286 #ifdef CONFIG_COMPAT 3287 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3288 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3289 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3290 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3291 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3292 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3293 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3294 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3295 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3296 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3297 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3298 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3299 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3300 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3301 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3302 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3303 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3304 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3305 #endif 3306 {}, 3307 }; 3308 3309 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3310 { 3311 switch (cap->hwcap_type) { 3312 case CAP_HWCAP: 3313 cpu_set_feature(cap->hwcap); 3314 break; 3315 #ifdef CONFIG_COMPAT 3316 case CAP_COMPAT_HWCAP: 3317 compat_elf_hwcap |= (u32)cap->hwcap; 3318 break; 3319 case CAP_COMPAT_HWCAP2: 3320 compat_elf_hwcap2 |= (u32)cap->hwcap; 3321 break; 3322 #endif 3323 default: 3324 WARN_ON(1); 3325 break; 3326 } 3327 } 3328 3329 /* Check if we have a particular HWCAP enabled */ 3330 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3331 { 3332 bool rc; 3333 3334 switch (cap->hwcap_type) { 3335 case CAP_HWCAP: 3336 rc = cpu_have_feature(cap->hwcap); 3337 break; 3338 #ifdef CONFIG_COMPAT 3339 case CAP_COMPAT_HWCAP: 3340 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3341 break; 3342 case CAP_COMPAT_HWCAP2: 3343 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3344 break; 3345 #endif 3346 default: 3347 WARN_ON(1); 3348 rc = false; 3349 } 3350 3351 return rc; 3352 } 3353 3354 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3355 { 3356 /* We support emulation of accesses to CPU ID feature registers */ 3357 cpu_set_named_feature(CPUID); 3358 for (; hwcaps->matches; hwcaps++) 3359 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3360 cap_set_elf_hwcap(hwcaps); 3361 } 3362 3363 static void update_cpu_capabilities(u16 scope_mask) 3364 { 3365 int i; 3366 const struct arm64_cpu_capabilities *caps; 3367 3368 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3369 for (i = 0; i < ARM64_NCAPS; i++) { 3370 caps = cpucap_ptrs[i]; 3371 if (!caps || !(caps->type & scope_mask) || 3372 cpus_have_cap(caps->capability) || 3373 !caps->matches(caps, cpucap_default_scope(caps))) 3374 continue; 3375 3376 if (caps->desc && !caps->cpus) 3377 pr_info("detected: %s\n", caps->desc); 3378 3379 __set_bit(caps->capability, system_cpucaps); 3380 3381 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) 3382 set_bit(caps->capability, boot_cpucaps); 3383 } 3384 } 3385 3386 /* 3387 * Enable all the available capabilities on this CPU. The capabilities 3388 * with BOOT_CPU scope are handled separately and hence skipped here. 3389 */ 3390 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3391 { 3392 int i; 3393 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3394 3395 for_each_available_cap(i) { 3396 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3397 3398 if (WARN_ON(!cap)) 3399 continue; 3400 3401 if (!(cap->type & non_boot_scope)) 3402 continue; 3403 3404 if (cap->cpu_enable) 3405 cap->cpu_enable(cap); 3406 } 3407 return 0; 3408 } 3409 3410 /* 3411 * Run through the enabled capabilities and enable() it on all active 3412 * CPUs 3413 */ 3414 static void __init enable_cpu_capabilities(u16 scope_mask) 3415 { 3416 int i; 3417 const struct arm64_cpu_capabilities *caps; 3418 bool boot_scope; 3419 3420 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3421 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3422 3423 for (i = 0; i < ARM64_NCAPS; i++) { 3424 caps = cpucap_ptrs[i]; 3425 if (!caps || !(caps->type & scope_mask) || 3426 !cpus_have_cap(caps->capability)) 3427 continue; 3428 3429 if (boot_scope && caps->cpu_enable) 3430 /* 3431 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3432 * before any secondary CPU boots. Thus, each secondary 3433 * will enable the capability as appropriate via 3434 * check_local_cpu_capabilities(). The only exception is 3435 * the boot CPU, for which the capability must be 3436 * enabled here. This approach avoids costly 3437 * stop_machine() calls for this case. 3438 */ 3439 caps->cpu_enable(caps); 3440 } 3441 3442 /* 3443 * For all non-boot scope capabilities, use stop_machine() 3444 * as it schedules the work allowing us to modify PSTATE, 3445 * instead of on_each_cpu() which uses an IPI, giving us a 3446 * PSTATE that disappears when we return. 3447 */ 3448 if (!boot_scope) 3449 stop_machine(cpu_enable_non_boot_scope_capabilities, 3450 NULL, cpu_online_mask); 3451 } 3452 3453 /* 3454 * Run through the list of capabilities to check for conflicts. 3455 * If the system has already detected a capability, take necessary 3456 * action on this CPU. 3457 */ 3458 static void verify_local_cpu_caps(u16 scope_mask) 3459 { 3460 int i; 3461 bool cpu_has_cap, system_has_cap; 3462 const struct arm64_cpu_capabilities *caps; 3463 3464 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3465 3466 for (i = 0; i < ARM64_NCAPS; i++) { 3467 caps = cpucap_ptrs[i]; 3468 if (!caps || !(caps->type & scope_mask)) 3469 continue; 3470 3471 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3472 system_has_cap = cpus_have_cap(caps->capability); 3473 3474 if (system_has_cap) { 3475 /* 3476 * Check if the new CPU misses an advertised feature, 3477 * which is not safe to miss. 3478 */ 3479 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3480 break; 3481 /* 3482 * We have to issue cpu_enable() irrespective of 3483 * whether the CPU has it or not, as it is enabeld 3484 * system wide. It is upto the call back to take 3485 * appropriate action on this CPU. 3486 */ 3487 if (caps->cpu_enable) 3488 caps->cpu_enable(caps); 3489 } else { 3490 /* 3491 * Check if the CPU has this capability if it isn't 3492 * safe to have when the system doesn't. 3493 */ 3494 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3495 break; 3496 } 3497 } 3498 3499 if (i < ARM64_NCAPS) { 3500 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3501 smp_processor_id(), caps->capability, 3502 caps->desc, system_has_cap, cpu_has_cap); 3503 3504 if (cpucap_panic_on_conflict(caps)) 3505 cpu_panic_kernel(); 3506 else 3507 cpu_die_early(); 3508 } 3509 } 3510 3511 /* 3512 * Check for CPU features that are used in early boot 3513 * based on the Boot CPU value. 3514 */ 3515 static void check_early_cpu_features(void) 3516 { 3517 verify_cpu_asid_bits(); 3518 3519 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3520 } 3521 3522 static void 3523 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3524 { 3525 3526 for (; caps->matches; caps++) 3527 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3528 pr_crit("CPU%d: missing HWCAP: %s\n", 3529 smp_processor_id(), caps->desc); 3530 cpu_die_early(); 3531 } 3532 } 3533 3534 static void verify_local_elf_hwcaps(void) 3535 { 3536 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3537 3538 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3539 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3540 } 3541 3542 static void verify_sve_features(void) 3543 { 3544 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3545 3546 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3547 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3548 smp_processor_id()); 3549 cpu_die_early(); 3550 } 3551 3552 cpacr_restore(cpacr); 3553 } 3554 3555 static void verify_sme_features(void) 3556 { 3557 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3558 3559 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3560 pr_crit("CPU%d: SME: vector length support mismatch\n", 3561 smp_processor_id()); 3562 cpu_die_early(); 3563 } 3564 3565 cpacr_restore(cpacr); 3566 } 3567 3568 static void verify_hyp_capabilities(void) 3569 { 3570 u64 safe_mmfr1, mmfr0, mmfr1; 3571 int parange, ipa_max; 3572 unsigned int safe_vmid_bits, vmid_bits; 3573 3574 if (!IS_ENABLED(CONFIG_KVM)) 3575 return; 3576 3577 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3578 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3579 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3580 3581 /* Verify VMID bits */ 3582 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3583 vmid_bits = get_vmid_bits(mmfr1); 3584 if (vmid_bits < safe_vmid_bits) { 3585 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3586 cpu_die_early(); 3587 } 3588 3589 /* Verify IPA range */ 3590 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3591 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3592 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3593 if (ipa_max < get_kvm_ipa_limit()) { 3594 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3595 cpu_die_early(); 3596 } 3597 } 3598 3599 static void verify_mpam_capabilities(void) 3600 { 3601 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3602 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3603 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3604 3605 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3606 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3607 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3608 cpu_die_early(); 3609 } 3610 3611 cpu_idr = read_cpuid(MPAMIDR_EL1); 3612 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3613 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3614 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3615 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3616 cpu_die_early(); 3617 } 3618 3619 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3620 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3621 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3622 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3623 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3624 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3625 cpu_die_early(); 3626 } 3627 } 3628 3629 /* 3630 * Run through the enabled system capabilities and enable() it on this CPU. 3631 * The capabilities were decided based on the available CPUs at the boot time. 3632 * Any new CPU should match the system wide status of the capability. If the 3633 * new CPU doesn't have a capability which the system now has enabled, we 3634 * cannot do anything to fix it up and could cause unexpected failures. So 3635 * we park the CPU. 3636 */ 3637 static void verify_local_cpu_capabilities(void) 3638 { 3639 /* 3640 * The capabilities with SCOPE_BOOT_CPU are checked from 3641 * check_early_cpu_features(), as they need to be verified 3642 * on all secondary CPUs. 3643 */ 3644 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3645 verify_local_elf_hwcaps(); 3646 3647 if (system_supports_sve()) 3648 verify_sve_features(); 3649 3650 if (system_supports_sme()) 3651 verify_sme_features(); 3652 3653 if (is_hyp_mode_available()) 3654 verify_hyp_capabilities(); 3655 3656 if (system_supports_mpam()) 3657 verify_mpam_capabilities(); 3658 } 3659 3660 void check_local_cpu_capabilities(void) 3661 { 3662 /* 3663 * All secondary CPUs should conform to the early CPU features 3664 * in use by the kernel based on boot CPU. 3665 */ 3666 check_early_cpu_features(); 3667 3668 /* 3669 * If we haven't finalised the system capabilities, this CPU gets 3670 * a chance to update the errata work arounds and local features. 3671 * Otherwise, this CPU should verify that it has all the system 3672 * advertised capabilities. 3673 */ 3674 if (!system_capabilities_finalized()) 3675 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3676 else 3677 verify_local_cpu_capabilities(); 3678 } 3679 3680 bool this_cpu_has_cap(unsigned int n) 3681 { 3682 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3683 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3684 3685 if (cap) 3686 return cap->matches(cap, SCOPE_LOCAL_CPU); 3687 } 3688 3689 return false; 3690 } 3691 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3692 3693 /* 3694 * This helper function is used in a narrow window when, 3695 * - The system wide safe registers are set with all the SMP CPUs and, 3696 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3697 */ 3698 static bool __maybe_unused __system_matches_cap(unsigned int n) 3699 { 3700 if (n < ARM64_NCAPS) { 3701 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3702 3703 if (cap) 3704 return cap->matches(cap, SCOPE_SYSTEM); 3705 } 3706 return false; 3707 } 3708 3709 void cpu_set_feature(unsigned int num) 3710 { 3711 set_bit(num, elf_hwcap); 3712 } 3713 3714 bool cpu_have_feature(unsigned int num) 3715 { 3716 return test_bit(num, elf_hwcap); 3717 } 3718 EXPORT_SYMBOL_GPL(cpu_have_feature); 3719 3720 unsigned long cpu_get_elf_hwcap(void) 3721 { 3722 /* 3723 * We currently only populate the first 32 bits of AT_HWCAP. Please 3724 * note that for userspace compatibility we guarantee that bits 62 3725 * and 63 will always be returned as 0. 3726 */ 3727 return elf_hwcap[0]; 3728 } 3729 3730 unsigned long cpu_get_elf_hwcap2(void) 3731 { 3732 return elf_hwcap[1]; 3733 } 3734 3735 unsigned long cpu_get_elf_hwcap3(void) 3736 { 3737 return elf_hwcap[2]; 3738 } 3739 3740 static void __init setup_boot_cpu_capabilities(void) 3741 { 3742 kvm_arm_target_impl_cpu_init(); 3743 /* 3744 * The boot CPU's feature register values have been recorded. Detect 3745 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3746 * patch alternatives for the available boot cpucaps. 3747 */ 3748 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3749 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3750 apply_boot_alternatives(); 3751 } 3752 3753 void __init setup_boot_cpu_features(void) 3754 { 3755 /* 3756 * Initialize the indirect array of CPU capabilities pointers before we 3757 * handle the boot CPU. 3758 */ 3759 init_cpucap_indirect_list(); 3760 3761 /* 3762 * Detect broken pseudo-NMI. Must be called _before_ the call to 3763 * setup_boot_cpu_capabilities() since it interacts with 3764 * can_use_gic_priorities(). 3765 */ 3766 detect_system_supports_pseudo_nmi(); 3767 3768 setup_boot_cpu_capabilities(); 3769 } 3770 3771 static void __init setup_system_capabilities(void) 3772 { 3773 /* 3774 * The system-wide safe feature register values have been finalized. 3775 * Detect, enable, and patch alternatives for the available system 3776 * cpucaps. 3777 */ 3778 update_cpu_capabilities(SCOPE_SYSTEM); 3779 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3780 apply_alternatives_all(); 3781 3782 /* 3783 * Log any cpucaps with a cpumask as these aren't logged by 3784 * update_cpu_capabilities(). 3785 */ 3786 for (int i = 0; i < ARM64_NCAPS; i++) { 3787 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3788 3789 if (caps && caps->cpus && caps->desc && 3790 cpumask_any(caps->cpus) < nr_cpu_ids) 3791 pr_info("detected: %s on CPU%*pbl\n", 3792 caps->desc, cpumask_pr_args(caps->cpus)); 3793 } 3794 3795 /* 3796 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3797 */ 3798 if (system_uses_ttbr0_pan()) 3799 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3800 } 3801 3802 void __init setup_system_features(void) 3803 { 3804 setup_system_capabilities(); 3805 3806 kpti_install_ng_mappings(); 3807 3808 sve_setup(); 3809 sme_setup(); 3810 3811 /* 3812 * Check for sane CTR_EL0.CWG value. 3813 */ 3814 if (!cache_type_cwg()) 3815 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3816 ARCH_DMA_MINALIGN); 3817 } 3818 3819 void __init setup_user_features(void) 3820 { 3821 user_feature_fixup(); 3822 3823 setup_elf_hwcaps(arm64_elf_hwcaps); 3824 3825 if (system_supports_32bit_el0()) { 3826 setup_elf_hwcaps(compat_elf_hwcaps); 3827 elf_hwcap_fixup(); 3828 } 3829 3830 minsigstksz_setup(); 3831 } 3832 3833 static int enable_mismatched_32bit_el0(unsigned int cpu) 3834 { 3835 /* 3836 * The first 32-bit-capable CPU we detected and so can no longer 3837 * be offlined by userspace. -1 indicates we haven't yet onlined 3838 * a 32-bit-capable CPU. 3839 */ 3840 static int lucky_winner = -1; 3841 3842 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3843 bool cpu_32bit = false; 3844 3845 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3846 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3847 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3848 else 3849 cpu_32bit = true; 3850 } 3851 3852 if (cpu_32bit) { 3853 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3854 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3855 } 3856 3857 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3858 return 0; 3859 3860 if (lucky_winner >= 0) 3861 return 0; 3862 3863 /* 3864 * We've detected a mismatch. We need to keep one of our CPUs with 3865 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3866 * every CPU in the system for a 32-bit task. 3867 */ 3868 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3869 cpu_active_mask); 3870 get_cpu_device(lucky_winner)->offline_disabled = true; 3871 setup_elf_hwcaps(compat_elf_hwcaps); 3872 elf_hwcap_fixup(); 3873 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3874 cpu, lucky_winner); 3875 return 0; 3876 } 3877 3878 static int __init init_32bit_el0_mask(void) 3879 { 3880 if (!allow_mismatched_32bit_el0) 3881 return 0; 3882 3883 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3884 return -ENOMEM; 3885 3886 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3887 "arm64/mismatched_32bit_el0:online", 3888 enable_mismatched_32bit_el0, NULL); 3889 } 3890 subsys_initcall_sync(init_32bit_el0_mask); 3891 3892 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3893 { 3894 cpu_enable_swapper_cnp(); 3895 } 3896 3897 /* 3898 * We emulate only the following system register space. 3899 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3900 * See Table C5-6 System instruction encodings for System register accesses, 3901 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3902 */ 3903 static inline bool __attribute_const__ is_emulated(u32 id) 3904 { 3905 return (sys_reg_Op0(id) == 0x3 && 3906 sys_reg_CRn(id) == 0x0 && 3907 sys_reg_Op1(id) == 0x0 && 3908 (sys_reg_CRm(id) == 0 || 3909 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3910 } 3911 3912 /* 3913 * With CRm == 0, reg should be one of : 3914 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 3915 */ 3916 static inline int emulate_id_reg(u32 id, u64 *valp) 3917 { 3918 switch (id) { 3919 case SYS_MIDR_EL1: 3920 *valp = read_cpuid_id(); 3921 break; 3922 case SYS_MPIDR_EL1: 3923 *valp = SYS_MPIDR_SAFE_VAL; 3924 break; 3925 case SYS_REVIDR_EL1: 3926 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 3927 *valp = 0; 3928 break; 3929 default: 3930 return -EINVAL; 3931 } 3932 3933 return 0; 3934 } 3935 3936 static int emulate_sys_reg(u32 id, u64 *valp) 3937 { 3938 struct arm64_ftr_reg *regp; 3939 3940 if (!is_emulated(id)) 3941 return -EINVAL; 3942 3943 if (sys_reg_CRm(id) == 0) 3944 return emulate_id_reg(id, valp); 3945 3946 regp = get_arm64_ftr_reg_nowarn(id); 3947 if (regp) 3948 *valp = arm64_ftr_reg_user_value(regp); 3949 else 3950 /* 3951 * The untracked registers are either IMPLEMENTATION DEFINED 3952 * (e.g, ID_AFR0_EL1) or reserved RAZ. 3953 */ 3954 *valp = 0; 3955 return 0; 3956 } 3957 3958 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 3959 { 3960 int rc; 3961 u64 val; 3962 3963 rc = emulate_sys_reg(sys_reg, &val); 3964 if (!rc) { 3965 pt_regs_write_reg(regs, rt, val); 3966 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 3967 } 3968 return rc; 3969 } 3970 3971 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 3972 { 3973 u32 sys_reg, rt; 3974 3975 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 3976 return false; 3977 3978 /* 3979 * sys_reg values are defined as used in mrs/msr instruction. 3980 * shift the imm value to get the encoding. 3981 */ 3982 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 3983 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 3984 return do_emulate_mrs(regs, sys_reg, rt) == 0; 3985 } 3986 3987 enum mitigation_state arm64_get_meltdown_state(void) 3988 { 3989 if (__meltdown_safe) 3990 return SPECTRE_UNAFFECTED; 3991 3992 if (arm64_kernel_unmapped_at_el0()) 3993 return SPECTRE_MITIGATED; 3994 3995 return SPECTRE_VULNERABLE; 3996 } 3997 3998 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 3999 char *buf) 4000 { 4001 switch (arm64_get_meltdown_state()) { 4002 case SPECTRE_UNAFFECTED: 4003 return sprintf(buf, "Not affected\n"); 4004 4005 case SPECTRE_MITIGATED: 4006 return sprintf(buf, "Mitigation: PTI\n"); 4007 4008 default: 4009 return sprintf(buf, "Vulnerable\n"); 4010 } 4011 } 4012