1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/cpu.h> 81 #include <asm/cpufeature.h> 82 #include <asm/cpu_ops.h> 83 #include <asm/fpsimd.h> 84 #include <asm/hwcap.h> 85 #include <asm/insn.h> 86 #include <asm/kvm_host.h> 87 #include <asm/mmu_context.h> 88 #include <asm/mte.h> 89 #include <asm/hypervisor.h> 90 #include <asm/processor.h> 91 #include <asm/smp.h> 92 #include <asm/sysreg.h> 93 #include <asm/traps.h> 94 #include <asm/vectors.h> 95 #include <asm/virt.h> 96 97 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 98 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 99 100 #ifdef CONFIG_COMPAT 101 #define COMPAT_ELF_HWCAP_DEFAULT \ 102 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 103 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 104 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 105 COMPAT_HWCAP_LPAE) 106 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 107 unsigned int compat_elf_hwcap2 __read_mostly; 108 unsigned int compat_elf_hwcap3 __read_mostly; 109 #endif 110 111 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 112 EXPORT_SYMBOL(system_cpucaps); 113 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 114 115 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 116 117 /* 118 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 119 * ends up in the .bss section where it is initialized in early_map_kernel() 120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 122 * may end up generating an incorrect idmap page table attributes. 123 */ 124 bool arm64_use_ng_mappings __read_mostly = false; 125 EXPORT_SYMBOL(arm64_use_ng_mappings); 126 127 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 128 129 /* 130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 131 * support it? 132 */ 133 static bool __read_mostly allow_mismatched_32bit_el0; 134 135 /* 136 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 137 * seen at least one CPU capable of 32-bit EL0. 138 */ 139 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 140 141 /* 142 * Mask of CPUs supporting 32-bit EL0. 143 * Only valid if arm64_mismatched_32bit_el0 is enabled. 144 */ 145 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 146 147 void dump_cpu_features(void) 148 { 149 /* file-wide pr_fmt adds "CPU features: " prefix */ 150 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 151 } 152 153 #define __ARM64_MAX_POSITIVE(reg, field) \ 154 ((reg##_##field##_SIGNED ? \ 155 BIT(reg##_##field##_WIDTH - 1) : \ 156 BIT(reg##_##field##_WIDTH)) - 1) 157 158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 159 160 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 161 .sys_reg = SYS_##reg, \ 162 .field_pos = reg##_##field##_SHIFT, \ 163 .field_width = reg##_##field##_WIDTH, \ 164 .sign = reg##_##field##_SIGNED, \ 165 .min_field_value = min_value, \ 166 .max_field_value = max_value, 167 168 /* 169 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 170 * an implicit maximum that depends on the sign-ess of the field. 171 * 172 * An unsigned field will be capped at all ones, while a signed field 173 * will be limited to the positive half only. 174 */ 175 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 176 __ARM64_CPUID_FIELDS(reg, field, \ 177 SYS_FIELD_VALUE(reg, field, min_value), \ 178 __ARM64_MAX_POSITIVE(reg, field)) 179 180 /* 181 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 182 * implicit minimal value to max_value. This should be used when 183 * matching a non-implemented property. 184 */ 185 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 186 __ARM64_CPUID_FIELDS(reg, field, \ 187 __ARM64_MIN_NEGATIVE(reg, field), \ 188 SYS_FIELD_VALUE(reg, field, max_value)) 189 190 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 191 { \ 192 .sign = SIGNED, \ 193 .visible = VISIBLE, \ 194 .strict = STRICT, \ 195 .type = TYPE, \ 196 .shift = SHIFT, \ 197 .width = WIDTH, \ 198 .safe_val = SAFE_VAL, \ 199 } 200 201 /* Define a feature with unsigned values */ 202 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 203 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 204 205 /* Define a feature with a signed value */ 206 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 #define ARM64_FTR_END \ 210 { \ 211 .width = 0, \ 212 } 213 214 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 215 216 static bool __system_matches_cap(unsigned int n); 217 218 /* 219 * NOTE: Any changes to the visibility of features should be kept in 220 * sync with the documentation of the CPU feature register ABI. 221 */ 222 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 237 ARM64_FTR_END, 238 }; 239 240 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 260 ARM64_FTR_END, 261 }; 262 263 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 276 ARM64_FTR_END, 277 }; 278 279 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 292 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 296 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 297 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 302 ARM64_FTR_END, 303 }; 304 305 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 306 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 308 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 309 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 310 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 313 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 314 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 315 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 316 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 317 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 318 ARM64_FTR_END, 319 }; 320 321 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 322 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 324 ARM64_FTR_END, 325 }; 326 327 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 328 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 330 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 334 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 336 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 352 ARM64_FTR_END, 353 }; 354 355 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 357 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 362 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 363 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 364 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 402 ARM64_FTR_END, 403 }; 404 405 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 406 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 408 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 414 ARM64_FTR_END, 415 }; 416 417 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 419 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 421 /* 422 * Page size not being supported at Stage-2 is not fatal. You 423 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 424 * your favourite nesting hypervisor. 425 * 426 * There is a small corner case where the hypervisor explicitly 427 * advertises a given granule size at Stage-2 (value 2) on some 428 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 429 * vCPUs. Although this is not forbidden by the architecture, it 430 * indicates that the hypervisor is being silly (or buggy). 431 * 432 * We make no effort to cope with this and pretend that if these 433 * fields are inconsistent across vCPUs, then it isn't worth 434 * trying to bring KVM up. 435 */ 436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 438 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 439 /* 440 * We already refuse to boot CPUs that don't support our configured 441 * page size, so we can only detect mismatches for a page size other 442 * than the one we're currently using. Unfortunately, SoCs like this 443 * exist in the wild so, even though we don't like it, we'll have to go 444 * along with it and treat them as non-strict. 445 */ 446 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 447 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 449 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 451 /* Linux shouldn't care about secure memory */ 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 455 /* 456 * Differing PARange is fine as long as all peripherals and memory are mapped 457 * within the minimum PARange of all CPUs 458 */ 459 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 460 ARM64_FTR_END, 461 }; 462 463 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 478 ARM64_FTR_END, 479 }; 480 481 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 497 ARM64_FTR_END, 498 }; 499 500 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 501 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 502 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 505 ARM64_FTR_END, 506 }; 507 508 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 509 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_ctr[] = { 515 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 520 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 521 /* 522 * Linux can handle differing I-cache policies. Userspace JITs will 523 * make use of *minLine. 524 * If we have differing I-cache policies, report it as the weakest - VIPT. 525 */ 526 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 527 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 528 ARM64_FTR_END, 529 }; 530 531 static struct arm64_ftr_override __ro_after_init no_override = { }; 532 533 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 534 .name = "SYS_CTR_EL0", 535 .ftr_bits = ftr_ctr, 536 .override = &no_override, 537 }; 538 539 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 540 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 545 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 546 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 547 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 548 ARM64_FTR_END, 549 }; 550 551 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 552 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 557 /* 558 * We can instantiate multiple PMU instances with different levels 559 * of support. 560 */ 561 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 563 ARM64_FTR_END, 564 }; 565 566 static const struct arm64_ftr_bits ftr_mvfr0[] = { 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 572 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 575 ARM64_FTR_END, 576 }; 577 578 static const struct arm64_ftr_bits ftr_mvfr1[] = { 579 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 580 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 581 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 587 ARM64_FTR_END, 588 }; 589 590 static const struct arm64_ftr_bits ftr_mvfr2[] = { 591 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 592 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 593 ARM64_FTR_END, 594 }; 595 596 static const struct arm64_ftr_bits ftr_dczid[] = { 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 599 ARM64_FTR_END, 600 }; 601 602 static const struct arm64_ftr_bits ftr_gmid[] = { 603 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 604 ARM64_FTR_END, 605 }; 606 607 static const struct arm64_ftr_bits ftr_id_isar0[] = { 608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 613 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 614 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 615 ARM64_FTR_END, 616 }; 617 618 static const struct arm64_ftr_bits ftr_id_isar5[] = { 619 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 620 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 621 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 622 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 625 ARM64_FTR_END, 626 }; 627 628 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 636 637 /* 638 * SpecSEI = 1 indicates that the PE might generate an SError on an 639 * external abort on speculative read. It is safe to assume that an 640 * SError might be generated than it will not be. Hence it has been 641 * classified as FTR_HIGHER_SAFE. 642 */ 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 644 ARM64_FTR_END, 645 }; 646 647 static const struct arm64_ftr_bits ftr_id_isar4[] = { 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 654 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 655 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 656 ARM64_FTR_END, 657 }; 658 659 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 660 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 661 ARM64_FTR_END, 662 }; 663 664 static const struct arm64_ftr_bits ftr_id_isar6[] = { 665 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 671 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 672 ARM64_FTR_END, 673 }; 674 675 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 682 ARM64_FTR_END, 683 }; 684 685 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 694 ARM64_FTR_END, 695 }; 696 697 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 698 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 699 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 700 ARM64_FTR_END, 701 }; 702 703 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 704 /* [31:28] TraceFilt */ 705 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 710 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 711 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 712 ARM64_FTR_END, 713 }; 714 715 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 716 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 717 ARM64_FTR_END, 718 }; 719 720 static const struct arm64_ftr_bits ftr_mpamidr[] = { 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 725 ARM64_FTR_END, 726 }; 727 728 /* 729 * Common ftr bits for a 32bit register with all hidden, strict 730 * attributes, with 4bit feature fields and a default safe value of 731 * 0. Covers the following 32bit registers: 732 * id_isar[1-3], id_mmfr[1-3] 733 */ 734 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 741 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 742 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 743 ARM64_FTR_END, 744 }; 745 746 /* Table for a single 32bit feature value */ 747 static const struct arm64_ftr_bits ftr_single32[] = { 748 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 749 ARM64_FTR_END, 750 }; 751 752 static const struct arm64_ftr_bits ftr_raz[] = { 753 ARM64_FTR_END, 754 }; 755 756 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 757 .sys_id = id, \ 758 .reg = &(struct arm64_ftr_reg){ \ 759 .name = id_str, \ 760 .override = (ovr), \ 761 .ftr_bits = &((table)[0]), \ 762 }} 763 764 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 765 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 766 767 #define ARM64_FTR_REG(id, table) \ 768 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 769 770 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 771 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 772 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 773 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 774 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 775 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 776 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 777 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 778 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 779 780 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 781 782 static const struct __ftr_reg_entry { 783 u32 sys_id; 784 struct arm64_ftr_reg *reg; 785 } arm64_ftr_regs[] = { 786 787 /* Op1 = 0, CRn = 0, CRm = 1 */ 788 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 789 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 790 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 791 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 792 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 793 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 794 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 795 796 /* Op1 = 0, CRn = 0, CRm = 2 */ 797 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 798 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 799 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 800 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 801 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 802 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 803 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 804 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 805 806 /* Op1 = 0, CRn = 0, CRm = 3 */ 807 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 808 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 809 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 810 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 811 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 812 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 813 814 /* Op1 = 0, CRn = 0, CRm = 4 */ 815 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 816 &id_aa64pfr0_override), 817 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 818 &id_aa64pfr1_override), 819 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 820 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 821 &id_aa64zfr0_override), 822 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 823 &id_aa64smfr0_override), 824 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 825 826 /* Op1 = 0, CRn = 0, CRm = 5 */ 827 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 828 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 829 830 /* Op1 = 0, CRn = 0, CRm = 6 */ 831 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 832 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 833 &id_aa64isar1_override), 834 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 835 &id_aa64isar2_override), 836 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 837 838 /* Op1 = 0, CRn = 0, CRm = 7 */ 839 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 840 &id_aa64mmfr0_override), 841 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 842 &id_aa64mmfr1_override), 843 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 844 &id_aa64mmfr2_override), 845 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 846 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 847 848 /* Op1 = 0, CRn = 10, CRm = 4 */ 849 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 850 851 /* Op1 = 1, CRn = 0, CRm = 0 */ 852 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 853 854 /* Op1 = 3, CRn = 0, CRm = 0 */ 855 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 856 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 857 858 /* Op1 = 3, CRn = 14, CRm = 0 */ 859 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 860 }; 861 862 static int search_cmp_ftr_reg(const void *id, const void *regp) 863 { 864 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 865 } 866 867 /* 868 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 869 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 870 * ascending order of sys_id, we use binary search to find a matching 871 * entry. 872 * 873 * returns - Upon success, matching ftr_reg entry for id. 874 * - NULL on failure. It is upto the caller to decide 875 * the impact of a failure. 876 */ 877 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 878 { 879 const struct __ftr_reg_entry *ret; 880 881 ret = bsearch((const void *)(unsigned long)sys_id, 882 arm64_ftr_regs, 883 ARRAY_SIZE(arm64_ftr_regs), 884 sizeof(arm64_ftr_regs[0]), 885 search_cmp_ftr_reg); 886 if (ret) 887 return ret->reg; 888 return NULL; 889 } 890 891 /* 892 * get_arm64_ftr_reg - Looks up a feature register entry using 893 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 894 * 895 * returns - Upon success, matching ftr_reg entry for id. 896 * - NULL on failure but with an WARN_ON(). 897 */ 898 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 899 { 900 struct arm64_ftr_reg *reg; 901 902 reg = get_arm64_ftr_reg_nowarn(sys_id); 903 904 /* 905 * Requesting a non-existent register search is an error. Warn 906 * and let the caller handle it. 907 */ 908 WARN_ON(!reg); 909 return reg; 910 } 911 912 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 913 s64 ftr_val) 914 { 915 u64 mask = arm64_ftr_mask(ftrp); 916 917 reg &= ~mask; 918 reg |= (ftr_val << ftrp->shift) & mask; 919 return reg; 920 } 921 922 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 923 s64 cur) 924 { 925 s64 ret = 0; 926 927 switch (ftrp->type) { 928 case FTR_EXACT: 929 ret = ftrp->safe_val; 930 break; 931 case FTR_LOWER_SAFE: 932 ret = min(new, cur); 933 break; 934 case FTR_HIGHER_OR_ZERO_SAFE: 935 if (!cur || !new) 936 break; 937 fallthrough; 938 case FTR_HIGHER_SAFE: 939 ret = max(new, cur); 940 break; 941 default: 942 BUG(); 943 } 944 945 return ret; 946 } 947 948 static void __init sort_ftr_regs(void) 949 { 950 unsigned int i; 951 952 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 953 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 954 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 955 unsigned int j = 0; 956 957 /* 958 * Features here must be sorted in descending order with respect 959 * to their shift values and should not overlap with each other. 960 */ 961 for (; ftr_bits->width != 0; ftr_bits++, j++) { 962 unsigned int width = ftr_reg->ftr_bits[j].width; 963 unsigned int shift = ftr_reg->ftr_bits[j].shift; 964 unsigned int prev_shift; 965 966 WARN((shift + width) > 64, 967 "%s has invalid feature at shift %d\n", 968 ftr_reg->name, shift); 969 970 /* 971 * Skip the first feature. There is nothing to 972 * compare against for now. 973 */ 974 if (j == 0) 975 continue; 976 977 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 978 WARN((shift + width) > prev_shift, 979 "%s has feature overlap at shift %d\n", 980 ftr_reg->name, shift); 981 } 982 983 /* 984 * Skip the first register. There is nothing to 985 * compare against for now. 986 */ 987 if (i == 0) 988 continue; 989 /* 990 * Registers here must be sorted in ascending order with respect 991 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 992 * to work correctly. 993 */ 994 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 995 } 996 } 997 998 /* 999 * Initialise the CPU feature register from Boot CPU values. 1000 * Also initiliases the strict_mask for the register. 1001 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1002 * RES0 for the system-wide value, and must strictly match. 1003 */ 1004 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1005 { 1006 u64 val = 0; 1007 u64 strict_mask = ~0x0ULL; 1008 u64 user_mask = 0; 1009 u64 valid_mask = 0; 1010 1011 const struct arm64_ftr_bits *ftrp; 1012 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1013 1014 if (!reg) 1015 return; 1016 1017 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1018 u64 ftr_mask = arm64_ftr_mask(ftrp); 1019 s64 ftr_new = arm64_ftr_value(ftrp, new); 1020 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1021 1022 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1023 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1024 char *str = NULL; 1025 1026 if (ftr_ovr != tmp) { 1027 /* Unsafe, remove the override */ 1028 reg->override->mask &= ~ftr_mask; 1029 reg->override->val &= ~ftr_mask; 1030 tmp = ftr_ovr; 1031 str = "ignoring override"; 1032 } else if (ftr_new != tmp) { 1033 /* Override was valid */ 1034 ftr_new = tmp; 1035 str = "forced"; 1036 } else { 1037 /* Override was the safe value */ 1038 str = "already set"; 1039 } 1040 1041 pr_warn("%s[%d:%d]: %s to %llx\n", 1042 reg->name, 1043 ftrp->shift + ftrp->width - 1, 1044 ftrp->shift, str, 1045 tmp & (BIT(ftrp->width) - 1)); 1046 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1047 reg->override->val &= ~ftr_mask; 1048 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1049 reg->name, 1050 ftrp->shift + ftrp->width - 1, 1051 ftrp->shift); 1052 } 1053 1054 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1055 1056 valid_mask |= ftr_mask; 1057 if (!ftrp->strict) 1058 strict_mask &= ~ftr_mask; 1059 if (ftrp->visible) 1060 user_mask |= ftr_mask; 1061 else 1062 reg->user_val = arm64_ftr_set_value(ftrp, 1063 reg->user_val, 1064 ftrp->safe_val); 1065 } 1066 1067 val &= valid_mask; 1068 1069 reg->sys_val = val; 1070 reg->strict_mask = strict_mask; 1071 reg->user_mask = user_mask; 1072 } 1073 1074 extern const struct arm64_cpu_capabilities arm64_errata[]; 1075 static const struct arm64_cpu_capabilities arm64_features[]; 1076 1077 static void __init 1078 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1079 { 1080 for (; caps->matches; caps++) { 1081 if (WARN(caps->capability >= ARM64_NCAPS, 1082 "Invalid capability %d\n", caps->capability)) 1083 continue; 1084 if (WARN(cpucap_ptrs[caps->capability], 1085 "Duplicate entry for capability %d\n", 1086 caps->capability)) 1087 continue; 1088 cpucap_ptrs[caps->capability] = caps; 1089 } 1090 } 1091 1092 static void __init init_cpucap_indirect_list(void) 1093 { 1094 init_cpucap_indirect_list_from_array(arm64_features); 1095 init_cpucap_indirect_list_from_array(arm64_errata); 1096 } 1097 1098 static void __init setup_boot_cpu_capabilities(void); 1099 1100 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1101 { 1102 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1103 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1104 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1105 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1106 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1107 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1108 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1109 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1110 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1111 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1112 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1113 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1114 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1115 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1116 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1117 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1118 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1119 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1120 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1121 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1122 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1123 } 1124 1125 #ifdef CONFIG_ARM64_PSEUDO_NMI 1126 static bool enable_pseudo_nmi; 1127 1128 static int __init early_enable_pseudo_nmi(char *p) 1129 { 1130 return kstrtobool(p, &enable_pseudo_nmi); 1131 } 1132 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1133 1134 static __init void detect_system_supports_pseudo_nmi(void) 1135 { 1136 struct device_node *np; 1137 1138 if (!enable_pseudo_nmi) 1139 return; 1140 1141 /* 1142 * Detect broken MediaTek firmware that doesn't properly save and 1143 * restore GIC priorities. 1144 */ 1145 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1146 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1147 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1148 enable_pseudo_nmi = false; 1149 } 1150 of_node_put(np); 1151 } 1152 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1153 static inline void detect_system_supports_pseudo_nmi(void) { } 1154 #endif 1155 1156 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1157 { 1158 /* Before we start using the tables, make sure it is sorted */ 1159 sort_ftr_regs(); 1160 1161 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1162 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1163 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1164 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1165 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1166 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1167 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1168 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1169 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1170 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1171 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1172 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1173 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1174 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1175 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1176 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1177 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1178 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1179 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1180 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1181 1182 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1183 init_32bit_cpu_features(&info->aarch32); 1184 1185 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1186 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1187 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1188 1189 vec_init_vq_map(ARM64_VEC_SVE); 1190 1191 cpacr_restore(cpacr); 1192 } 1193 1194 if (IS_ENABLED(CONFIG_ARM64_SME) && 1195 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1196 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1197 1198 vec_init_vq_map(ARM64_VEC_SME); 1199 1200 cpacr_restore(cpacr); 1201 } 1202 1203 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1204 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1205 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1206 } 1207 1208 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1209 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1210 } 1211 1212 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1213 { 1214 const struct arm64_ftr_bits *ftrp; 1215 1216 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1217 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1218 s64 ftr_new = arm64_ftr_value(ftrp, new); 1219 1220 if (ftr_cur == ftr_new) 1221 continue; 1222 /* Find a safe value */ 1223 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1224 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1225 } 1226 1227 } 1228 1229 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1230 { 1231 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1232 1233 if (!regp) 1234 return 0; 1235 1236 update_cpu_ftr_reg(regp, val); 1237 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1238 return 0; 1239 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1240 regp->name, boot, cpu, val); 1241 return 1; 1242 } 1243 1244 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1245 { 1246 const struct arm64_ftr_bits *ftrp; 1247 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1248 1249 if (!regp) 1250 return; 1251 1252 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1253 if (ftrp->shift == field) { 1254 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1255 break; 1256 } 1257 } 1258 1259 /* Bogus field? */ 1260 WARN_ON(!ftrp->width); 1261 } 1262 1263 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1264 struct cpuinfo_arm64 *boot) 1265 { 1266 static bool boot_cpu_32bit_regs_overridden = false; 1267 1268 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1269 return; 1270 1271 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1272 return; 1273 1274 boot->aarch32 = info->aarch32; 1275 init_32bit_cpu_features(&boot->aarch32); 1276 boot_cpu_32bit_regs_overridden = true; 1277 } 1278 1279 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1280 struct cpuinfo_32bit *boot) 1281 { 1282 int taint = 0; 1283 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1284 1285 /* 1286 * If we don't have AArch32 at EL1, then relax the strictness of 1287 * EL1-dependent register fields to avoid spurious sanity check fails. 1288 */ 1289 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1290 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1291 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1292 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1293 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1294 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1295 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1296 } 1297 1298 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1299 info->reg_id_dfr0, boot->reg_id_dfr0); 1300 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1301 info->reg_id_dfr1, boot->reg_id_dfr1); 1302 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1303 info->reg_id_isar0, boot->reg_id_isar0); 1304 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1305 info->reg_id_isar1, boot->reg_id_isar1); 1306 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1307 info->reg_id_isar2, boot->reg_id_isar2); 1308 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1309 info->reg_id_isar3, boot->reg_id_isar3); 1310 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1311 info->reg_id_isar4, boot->reg_id_isar4); 1312 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1313 info->reg_id_isar5, boot->reg_id_isar5); 1314 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1315 info->reg_id_isar6, boot->reg_id_isar6); 1316 1317 /* 1318 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1319 * ACTLR formats could differ across CPUs and therefore would have to 1320 * be trapped for virtualization anyway. 1321 */ 1322 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1323 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1324 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1325 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1326 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1327 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1328 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1329 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1330 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1331 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1332 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1333 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1334 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1335 info->reg_id_pfr0, boot->reg_id_pfr0); 1336 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1337 info->reg_id_pfr1, boot->reg_id_pfr1); 1338 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1339 info->reg_id_pfr2, boot->reg_id_pfr2); 1340 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1341 info->reg_mvfr0, boot->reg_mvfr0); 1342 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1343 info->reg_mvfr1, boot->reg_mvfr1); 1344 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1345 info->reg_mvfr2, boot->reg_mvfr2); 1346 1347 return taint; 1348 } 1349 1350 /* 1351 * Update system wide CPU feature registers with the values from a 1352 * non-boot CPU. Also performs SANITY checks to make sure that there 1353 * aren't any insane variations from that of the boot CPU. 1354 */ 1355 void update_cpu_features(int cpu, 1356 struct cpuinfo_arm64 *info, 1357 struct cpuinfo_arm64 *boot) 1358 { 1359 int taint = 0; 1360 1361 /* 1362 * The kernel can handle differing I-cache policies, but otherwise 1363 * caches should look identical. Userspace JITs will make use of 1364 * *minLine. 1365 */ 1366 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1367 info->reg_ctr, boot->reg_ctr); 1368 1369 /* 1370 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1371 * could result in too much or too little memory being zeroed if a 1372 * process is preempted and migrated between CPUs. 1373 */ 1374 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1375 info->reg_dczid, boot->reg_dczid); 1376 1377 /* If different, timekeeping will be broken (especially with KVM) */ 1378 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1379 info->reg_cntfrq, boot->reg_cntfrq); 1380 1381 /* 1382 * The kernel uses self-hosted debug features and expects CPUs to 1383 * support identical debug features. We presently need CTX_CMPs, WRPs, 1384 * and BRPs to be identical. 1385 * ID_AA64DFR1 is currently RES0. 1386 */ 1387 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1388 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1389 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1390 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1391 /* 1392 * Even in big.LITTLE, processors should be identical instruction-set 1393 * wise. 1394 */ 1395 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1396 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1397 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1398 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1399 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1400 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1401 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1402 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1403 1404 /* 1405 * Differing PARange support is fine as long as all peripherals and 1406 * memory are mapped within the minimum PARange of all CPUs. 1407 * Linux should not care about secure memory. 1408 */ 1409 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1410 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1411 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1412 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1413 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1414 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1415 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1416 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1417 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1418 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1419 1420 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1421 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1423 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1424 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1425 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1426 1427 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1428 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1429 1430 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1431 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1432 1433 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1434 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1435 1436 /* Probe vector lengths */ 1437 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1438 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1439 if (!system_capabilities_finalized()) { 1440 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1441 1442 vec_update_vq_map(ARM64_VEC_SVE); 1443 1444 cpacr_restore(cpacr); 1445 } 1446 } 1447 1448 if (IS_ENABLED(CONFIG_ARM64_SME) && 1449 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1450 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1451 1452 /* Probe vector lengths */ 1453 if (!system_capabilities_finalized()) 1454 vec_update_vq_map(ARM64_VEC_SME); 1455 1456 cpacr_restore(cpacr); 1457 } 1458 1459 if (id_aa64pfr0_mpam(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1460 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1461 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1462 info->reg_mpamidr, boot->reg_mpamidr); 1463 } 1464 1465 /* 1466 * The kernel uses the LDGM/STGM instructions and the number of tags 1467 * they read/write depends on the GMID_EL1.BS field. Check that the 1468 * value is the same on all CPUs. 1469 */ 1470 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1471 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1472 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1473 info->reg_gmid, boot->reg_gmid); 1474 } 1475 1476 /* 1477 * If we don't have AArch32 at all then skip the checks entirely 1478 * as the register values may be UNKNOWN and we're not going to be 1479 * using them for anything. 1480 * 1481 * This relies on a sanitised view of the AArch64 ID registers 1482 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1483 */ 1484 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1485 lazy_init_32bit_cpu_features(info, boot); 1486 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1487 &boot->aarch32); 1488 } 1489 1490 /* 1491 * Mismatched CPU features are a recipe for disaster. Don't even 1492 * pretend to support them. 1493 */ 1494 if (taint) { 1495 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1496 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1497 } 1498 } 1499 1500 u64 read_sanitised_ftr_reg(u32 id) 1501 { 1502 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1503 1504 if (!regp) 1505 return 0; 1506 return regp->sys_val; 1507 } 1508 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1509 1510 #define read_sysreg_case(r) \ 1511 case r: val = read_sysreg_s(r); break; 1512 1513 /* 1514 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1515 * Read the system register on the current CPU 1516 */ 1517 u64 __read_sysreg_by_encoding(u32 sys_id) 1518 { 1519 struct arm64_ftr_reg *regp; 1520 u64 val; 1521 1522 switch (sys_id) { 1523 read_sysreg_case(SYS_ID_PFR0_EL1); 1524 read_sysreg_case(SYS_ID_PFR1_EL1); 1525 read_sysreg_case(SYS_ID_PFR2_EL1); 1526 read_sysreg_case(SYS_ID_DFR0_EL1); 1527 read_sysreg_case(SYS_ID_DFR1_EL1); 1528 read_sysreg_case(SYS_ID_MMFR0_EL1); 1529 read_sysreg_case(SYS_ID_MMFR1_EL1); 1530 read_sysreg_case(SYS_ID_MMFR2_EL1); 1531 read_sysreg_case(SYS_ID_MMFR3_EL1); 1532 read_sysreg_case(SYS_ID_MMFR4_EL1); 1533 read_sysreg_case(SYS_ID_MMFR5_EL1); 1534 read_sysreg_case(SYS_ID_ISAR0_EL1); 1535 read_sysreg_case(SYS_ID_ISAR1_EL1); 1536 read_sysreg_case(SYS_ID_ISAR2_EL1); 1537 read_sysreg_case(SYS_ID_ISAR3_EL1); 1538 read_sysreg_case(SYS_ID_ISAR4_EL1); 1539 read_sysreg_case(SYS_ID_ISAR5_EL1); 1540 read_sysreg_case(SYS_ID_ISAR6_EL1); 1541 read_sysreg_case(SYS_MVFR0_EL1); 1542 read_sysreg_case(SYS_MVFR1_EL1); 1543 read_sysreg_case(SYS_MVFR2_EL1); 1544 1545 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1546 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1547 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1548 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1549 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1550 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1551 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1552 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1553 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1554 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1555 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1556 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1557 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1558 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1559 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1560 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1561 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1562 1563 read_sysreg_case(SYS_CNTFRQ_EL0); 1564 read_sysreg_case(SYS_CTR_EL0); 1565 read_sysreg_case(SYS_DCZID_EL0); 1566 1567 default: 1568 BUG(); 1569 return 0; 1570 } 1571 1572 regp = get_arm64_ftr_reg(sys_id); 1573 if (regp) { 1574 val &= ~regp->override->mask; 1575 val |= (regp->override->val & regp->override->mask); 1576 } 1577 1578 return val; 1579 } 1580 1581 #include <linux/irqchip/arm-gic-v3.h> 1582 1583 static bool 1584 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1585 { 1586 return true; 1587 } 1588 1589 static bool 1590 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1591 { 1592 int val, min, max; 1593 u64 tmp; 1594 1595 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1596 entry->field_width, 1597 entry->sign); 1598 1599 tmp = entry->min_field_value; 1600 tmp <<= entry->field_pos; 1601 1602 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1603 entry->field_width, 1604 entry->sign); 1605 1606 tmp = entry->max_field_value; 1607 tmp <<= entry->field_pos; 1608 1609 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1610 entry->field_width, 1611 entry->sign); 1612 1613 return val >= min && val <= max; 1614 } 1615 1616 static u64 1617 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1618 { 1619 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1620 if (scope == SCOPE_SYSTEM) 1621 return read_sanitised_ftr_reg(entry->sys_reg); 1622 else 1623 return __read_sysreg_by_encoding(entry->sys_reg); 1624 } 1625 1626 static bool 1627 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1628 { 1629 int mask; 1630 struct arm64_ftr_reg *regp; 1631 u64 val = read_scoped_sysreg(entry, scope); 1632 1633 regp = get_arm64_ftr_reg(entry->sys_reg); 1634 if (!regp) 1635 return false; 1636 1637 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1638 entry->field_pos, 1639 entry->field_width); 1640 if (!mask) 1641 return false; 1642 1643 return feature_matches(val, entry); 1644 } 1645 1646 static bool 1647 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1648 { 1649 u64 val = read_scoped_sysreg(entry, scope); 1650 return feature_matches(val, entry); 1651 } 1652 1653 const struct cpumask *system_32bit_el0_cpumask(void) 1654 { 1655 if (!system_supports_32bit_el0()) 1656 return cpu_none_mask; 1657 1658 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1659 return cpu_32bit_el0_mask; 1660 1661 return cpu_possible_mask; 1662 } 1663 1664 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1665 { 1666 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_TICK)); 1667 } 1668 1669 static int __init parse_32bit_el0_param(char *str) 1670 { 1671 allow_mismatched_32bit_el0 = true; 1672 return 0; 1673 } 1674 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1675 1676 static ssize_t aarch32_el0_show(struct device *dev, 1677 struct device_attribute *attr, char *buf) 1678 { 1679 const struct cpumask *mask = system_32bit_el0_cpumask(); 1680 1681 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1682 } 1683 static const DEVICE_ATTR_RO(aarch32_el0); 1684 1685 static int __init aarch32_el0_sysfs_init(void) 1686 { 1687 struct device *dev_root; 1688 int ret = 0; 1689 1690 if (!allow_mismatched_32bit_el0) 1691 return 0; 1692 1693 dev_root = bus_get_dev_root(&cpu_subsys); 1694 if (dev_root) { 1695 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1696 put_device(dev_root); 1697 } 1698 return ret; 1699 } 1700 device_initcall(aarch32_el0_sysfs_init); 1701 1702 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1703 { 1704 if (!has_cpuid_feature(entry, scope)) 1705 return allow_mismatched_32bit_el0; 1706 1707 if (scope == SCOPE_SYSTEM) 1708 pr_info("detected: 32-bit EL0 Support\n"); 1709 1710 return true; 1711 } 1712 1713 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1714 { 1715 bool has_sre; 1716 1717 if (!has_cpuid_feature(entry, scope)) 1718 return false; 1719 1720 has_sre = gic_enable_sre(); 1721 if (!has_sre) 1722 pr_warn_once("%s present but disabled by higher exception level\n", 1723 entry->desc); 1724 1725 return has_sre; 1726 } 1727 1728 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1729 int scope) 1730 { 1731 u64 ctr; 1732 1733 if (scope == SCOPE_SYSTEM) 1734 ctr = arm64_ftr_reg_ctrel0.sys_val; 1735 else 1736 ctr = read_cpuid_effective_cachetype(); 1737 1738 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1739 } 1740 1741 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1742 { 1743 /* 1744 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1745 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1746 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1747 * value. 1748 */ 1749 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1750 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1751 } 1752 1753 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1754 int scope) 1755 { 1756 u64 ctr; 1757 1758 if (scope == SCOPE_SYSTEM) 1759 ctr = arm64_ftr_reg_ctrel0.sys_val; 1760 else 1761 ctr = read_cpuid_cachetype(); 1762 1763 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1764 } 1765 1766 static bool __maybe_unused 1767 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1768 { 1769 /* 1770 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1771 * may share TLB entries with a CPU stuck in the crashed 1772 * kernel. 1773 */ 1774 if (is_kdump_kernel()) 1775 return false; 1776 1777 if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP)) 1778 return false; 1779 1780 return has_cpuid_feature(entry, scope); 1781 } 1782 1783 static bool __meltdown_safe = true; 1784 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1785 1786 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1787 int scope) 1788 { 1789 /* List of CPUs that are not vulnerable and don't need KPTI */ 1790 static const struct midr_range kpti_safe_list[] = { 1791 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1792 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1793 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1794 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1795 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1796 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1797 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1798 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1799 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1800 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1801 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1802 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1803 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1804 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1805 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1806 { /* sentinel */ } 1807 }; 1808 char const *str = "kpti command line option"; 1809 bool meltdown_safe; 1810 1811 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1812 1813 /* Defer to CPU feature registers */ 1814 if (has_cpuid_feature(entry, scope)) 1815 meltdown_safe = true; 1816 1817 if (!meltdown_safe) 1818 __meltdown_safe = false; 1819 1820 /* 1821 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1822 * ThunderX leads to apparent I-cache corruption of kernel text, which 1823 * ends as well as you might imagine. Don't even try. We cannot rely 1824 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1825 * because cpucap detection order may change. However, since we know 1826 * affected CPUs are always in a homogeneous configuration, it is 1827 * safe to rely on this_cpu_has_cap() here. 1828 */ 1829 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1830 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1831 __kpti_forced = -1; 1832 } 1833 1834 /* Useful for KASLR robustness */ 1835 if (kaslr_enabled() && kaslr_requires_kpti()) { 1836 if (!__kpti_forced) { 1837 str = "KASLR"; 1838 __kpti_forced = 1; 1839 } 1840 } 1841 1842 if (cpu_mitigations_off() && !__kpti_forced) { 1843 str = "mitigations=off"; 1844 __kpti_forced = -1; 1845 } 1846 1847 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1848 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1849 return false; 1850 } 1851 1852 /* Forced? */ 1853 if (__kpti_forced) { 1854 pr_info_once("kernel page table isolation forced %s by %s\n", 1855 __kpti_forced > 0 ? "ON" : "OFF", str); 1856 return __kpti_forced > 0; 1857 } 1858 1859 return !meltdown_safe; 1860 } 1861 1862 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1863 { 1864 /* 1865 * Although the Apple M2 family appears to support NV1, the 1866 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1867 * that it doesn't support NV1 at all. 1868 */ 1869 static const struct midr_range nv1_ni_list[] = { 1870 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1871 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1872 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1873 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1874 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1875 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1876 {} 1877 }; 1878 1879 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1880 !(has_cpuid_feature(entry, scope) || 1881 is_midr_in_range_list(nv1_ni_list))); 1882 } 1883 1884 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1885 static bool has_lpa2_at_stage1(u64 mmfr0) 1886 { 1887 unsigned int tgran; 1888 1889 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1890 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1891 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1892 } 1893 1894 static bool has_lpa2_at_stage2(u64 mmfr0) 1895 { 1896 unsigned int tgran; 1897 1898 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1899 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1900 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1901 } 1902 1903 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1904 { 1905 u64 mmfr0; 1906 1907 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1908 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1909 } 1910 #else 1911 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1912 { 1913 return false; 1914 } 1915 #endif 1916 1917 #ifdef CONFIG_HW_PERF_EVENTS 1918 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1919 { 1920 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1921 unsigned int pmuver; 1922 1923 /* 1924 * PMUVer follows the standard ID scheme for an unsigned field with the 1925 * exception of 0xF (IMP_DEF) which is treated specially and implies 1926 * FEAT_PMUv3 is not implemented. 1927 * 1928 * See DDI0487L.a D24.1.3.2 for more details. 1929 */ 1930 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1931 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1932 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 1933 return false; 1934 1935 return pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP; 1936 } 1937 #endif 1938 1939 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1940 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT)) 1941 1942 extern 1943 void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt, 1944 phys_addr_t size, pgprot_t prot, 1945 phys_addr_t (*pgtable_alloc)(int), int flags); 1946 1947 static phys_addr_t __initdata kpti_ng_temp_alloc; 1948 1949 static phys_addr_t __init kpti_ng_pgd_alloc(int shift) 1950 { 1951 kpti_ng_temp_alloc -= PAGE_SIZE; 1952 return kpti_ng_temp_alloc; 1953 } 1954 1955 static int __init __kpti_install_ng_mappings(void *__unused) 1956 { 1957 typedef void (kpti_remap_fn)(int, int, phys_addr_t, unsigned long); 1958 extern kpti_remap_fn idmap_kpti_install_ng_mappings; 1959 kpti_remap_fn *remap_fn; 1960 1961 int cpu = smp_processor_id(); 1962 int levels = CONFIG_PGTABLE_LEVELS; 1963 int order = order_base_2(levels); 1964 u64 kpti_ng_temp_pgd_pa = 0; 1965 pgd_t *kpti_ng_temp_pgd; 1966 u64 alloc = 0; 1967 1968 if (levels == 5 && !pgtable_l5_enabled()) 1969 levels = 4; 1970 else if (levels == 4 && !pgtable_l4_enabled()) 1971 levels = 3; 1972 1973 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings); 1974 1975 if (!cpu) { 1976 alloc = __get_free_pages(GFP_ATOMIC | __GFP_ZERO, order); 1977 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); 1978 kpti_ng_temp_alloc = kpti_ng_temp_pgd_pa = __pa(kpti_ng_temp_pgd); 1979 1980 // 1981 // Create a minimal page table hierarchy that permits us to map 1982 // the swapper page tables temporarily as we traverse them. 1983 // 1984 // The physical pages are laid out as follows: 1985 // 1986 // +--------+-/-------+-/------ +-/------ +-\\\--------+ 1987 // : PTE[] : | PMD[] : | PUD[] : | P4D[] : ||| PGD[] : 1988 // +--------+-\-------+-\------ +-\------ +-///--------+ 1989 // ^ 1990 // The first page is mapped into this hierarchy at a PMD_SHIFT 1991 // aligned virtual address, so that we can manipulate the PTE 1992 // level entries while the mapping is active. The first entry 1993 // covers the PTE[] page itself, the remaining entries are free 1994 // to be used as a ad-hoc fixmap. 1995 // 1996 create_kpti_ng_temp_pgd(kpti_ng_temp_pgd, __pa(alloc), 1997 KPTI_NG_TEMP_VA, PAGE_SIZE, PAGE_KERNEL, 1998 kpti_ng_pgd_alloc, 0); 1999 } 2000 2001 cpu_install_idmap(); 2002 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); 2003 cpu_uninstall_idmap(); 2004 2005 if (!cpu) { 2006 free_pages(alloc, order); 2007 arm64_use_ng_mappings = true; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static void __init kpti_install_ng_mappings(void) 2014 { 2015 /* Check whether KPTI is going to be used */ 2016 if (!arm64_kernel_unmapped_at_el0()) 2017 return; 2018 2019 /* 2020 * We don't need to rewrite the page-tables if either we've done 2021 * it already or we have KASLR enabled and therefore have not 2022 * created any global mappings at all. 2023 */ 2024 if (arm64_use_ng_mappings) 2025 return; 2026 2027 stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); 2028 } 2029 2030 #else 2031 static inline void kpti_install_ng_mappings(void) 2032 { 2033 } 2034 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 2035 2036 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 2037 { 2038 if (__this_cpu_read(this_cpu_vector) == vectors) { 2039 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 2040 2041 __this_cpu_write(this_cpu_vector, v); 2042 } 2043 2044 } 2045 2046 static int __init parse_kpti(char *str) 2047 { 2048 bool enabled; 2049 int ret = kstrtobool(str, &enabled); 2050 2051 if (ret) 2052 return ret; 2053 2054 __kpti_forced = enabled ? 1 : -1; 2055 return 0; 2056 } 2057 early_param("kpti", parse_kpti); 2058 2059 #ifdef CONFIG_ARM64_HW_AFDBM 2060 static struct cpumask dbm_cpus __read_mostly; 2061 2062 static inline void __cpu_enable_hw_dbm(void) 2063 { 2064 u64 tcr = read_sysreg(tcr_el1) | TCR_HD; 2065 2066 write_sysreg(tcr, tcr_el1); 2067 isb(); 2068 local_flush_tlb_all(); 2069 } 2070 2071 static bool cpu_has_broken_dbm(void) 2072 { 2073 /* List of CPUs which have broken DBM support. */ 2074 static const struct midr_range cpus[] = { 2075 #ifdef CONFIG_ARM64_ERRATUM_1024718 2076 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 2077 /* Kryo4xx Silver (rdpe => r1p0) */ 2078 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 2079 #endif 2080 #ifdef CONFIG_ARM64_ERRATUM_2051678 2081 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2082 #endif 2083 {}, 2084 }; 2085 2086 return is_midr_in_range_list(cpus); 2087 } 2088 2089 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2090 { 2091 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2092 !cpu_has_broken_dbm(); 2093 } 2094 2095 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2096 { 2097 if (cpu_can_use_dbm(cap)) { 2098 __cpu_enable_hw_dbm(); 2099 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2100 } 2101 } 2102 2103 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2104 int __unused) 2105 { 2106 /* 2107 * DBM is a non-conflicting feature. i.e, the kernel can safely 2108 * run a mix of CPUs with and without the feature. So, we 2109 * unconditionally enable the capability to allow any late CPU 2110 * to use the feature. We only enable the control bits on the 2111 * CPU, if it is supported. 2112 */ 2113 2114 return true; 2115 } 2116 2117 #endif 2118 2119 #ifdef CONFIG_ARM64_AMU_EXTN 2120 2121 /* 2122 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2123 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2124 * information regarding all the events that it supports. When a CPU bit is 2125 * set in the cpumask, the user of this feature can only rely on the presence 2126 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2127 * counters are enabled or access to these counters is enabled by code 2128 * executed at higher exception levels (firmware). 2129 */ 2130 static struct cpumask amu_cpus __read_mostly; 2131 2132 bool cpu_has_amu_feat(int cpu) 2133 { 2134 return cpumask_test_cpu(cpu, &amu_cpus); 2135 } 2136 2137 int get_cpu_with_amu_feat(void) 2138 { 2139 return cpumask_any(&amu_cpus); 2140 } 2141 2142 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2143 { 2144 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2145 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2146 2147 /* 0 reference values signal broken/disabled counters */ 2148 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2149 update_freq_counters_refs(); 2150 } 2151 } 2152 2153 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2154 int __unused) 2155 { 2156 /* 2157 * The AMU extension is a non-conflicting feature: the kernel can 2158 * safely run a mix of CPUs with and without support for the 2159 * activity monitors extension. Therefore, unconditionally enable 2160 * the capability to allow any late CPU to use the feature. 2161 * 2162 * With this feature unconditionally enabled, the cpu_enable 2163 * function will be called for all CPUs that match the criteria, 2164 * including secondary and hotplugged, marking this feature as 2165 * present on that respective CPU. The enable function will also 2166 * print a detection message. 2167 */ 2168 2169 return true; 2170 } 2171 #else 2172 int get_cpu_with_amu_feat(void) 2173 { 2174 return nr_cpu_ids; 2175 } 2176 #endif 2177 2178 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2179 { 2180 return is_kernel_in_hyp_mode(); 2181 } 2182 2183 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2184 { 2185 /* 2186 * Copy register values that aren't redirected by hardware. 2187 * 2188 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2189 * this value to tpidr_el2 before we patch the code. Once we've done 2190 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2191 * do anything here. 2192 */ 2193 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2194 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2195 } 2196 2197 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2198 int scope) 2199 { 2200 if (kvm_get_mode() != KVM_MODE_NV) 2201 return false; 2202 2203 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2204 pr_warn("unavailable: %s\n", cap->desc); 2205 return false; 2206 } 2207 2208 return true; 2209 } 2210 2211 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2212 int __unused) 2213 { 2214 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2215 } 2216 2217 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2218 { 2219 /* 2220 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2221 * as possible. This list is therefore an allow-list of known-good 2222 * implementations that both support BBML2 and additionally, fulfill the 2223 * extra constraint of never generating TLB conflict aborts when using 2224 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2225 * kernel contexts difficult to prove safe against recursive aborts). 2226 * 2227 * Note that implementations can only be considered "known-good" if their 2228 * implementors attest to the fact that the implementation never raises 2229 * TLB conflict aborts for BBML2 mapping granularity changes. 2230 */ 2231 static const struct midr_range supports_bbml2_noabort_list[] = { 2232 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2233 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2234 {} 2235 }; 2236 2237 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2238 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2239 return false; 2240 2241 /* 2242 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2243 * about whether the MIDR check passes. 2244 */ 2245 2246 return true; 2247 } 2248 2249 #ifdef CONFIG_ARM64_PAN 2250 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2251 { 2252 /* 2253 * We modify PSTATE. This won't work from irq context as the PSTATE 2254 * is discarded once we return from the exception. 2255 */ 2256 WARN_ON_ONCE(in_interrupt()); 2257 2258 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2259 set_pstate_pan(1); 2260 } 2261 #endif /* CONFIG_ARM64_PAN */ 2262 2263 #ifdef CONFIG_ARM64_RAS_EXTN 2264 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2265 { 2266 /* Firmware may have left a deferred SError in this register. */ 2267 write_sysreg_s(0, SYS_DISR_EL1); 2268 } 2269 #endif /* CONFIG_ARM64_RAS_EXTN */ 2270 2271 #ifdef CONFIG_ARM64_PTR_AUTH 2272 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2273 { 2274 int boot_val, sec_val; 2275 2276 /* We don't expect to be called with SCOPE_SYSTEM */ 2277 WARN_ON(scope == SCOPE_SYSTEM); 2278 /* 2279 * The ptr-auth feature levels are not intercompatible with lower 2280 * levels. Hence we must match ptr-auth feature level of the secondary 2281 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2282 * from the sanitised register whereas direct register read is done for 2283 * the secondary CPUs. 2284 * The sanitised feature state is guaranteed to match that of the 2285 * boot CPU as a mismatched secondary CPU is parked before it gets 2286 * a chance to update the state, with the capability. 2287 */ 2288 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2289 entry->field_pos, entry->sign); 2290 if (scope & SCOPE_BOOT_CPU) 2291 return boot_val >= entry->min_field_value; 2292 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2293 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2294 entry->field_pos, entry->sign); 2295 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2296 } 2297 2298 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2299 int scope) 2300 { 2301 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2302 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2303 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2304 2305 return apa || apa3 || api; 2306 } 2307 2308 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2309 int __unused) 2310 { 2311 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2312 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2313 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2314 2315 return gpa || gpa3 || gpi; 2316 } 2317 #endif /* CONFIG_ARM64_PTR_AUTH */ 2318 2319 #ifdef CONFIG_ARM64_E0PD 2320 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2321 { 2322 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2323 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1); 2324 } 2325 #endif /* CONFIG_ARM64_E0PD */ 2326 2327 #ifdef CONFIG_ARM64_PSEUDO_NMI 2328 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2329 int scope) 2330 { 2331 /* 2332 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU 2333 * feature, so will be detected earlier. 2334 */ 2335 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS); 2336 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) 2337 return false; 2338 2339 return enable_pseudo_nmi; 2340 } 2341 2342 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2343 int scope) 2344 { 2345 /* 2346 * If we're not using priority masking then we won't be poking PMR_EL1, 2347 * and there's no need to relax synchronization of writes to it, and 2348 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2349 * that. 2350 * 2351 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2352 * feature, so will be detected earlier. 2353 */ 2354 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2355 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2356 return false; 2357 2358 /* 2359 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2360 * hint for interrupt distribution, a DSB is not necessary when 2361 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2362 * 2363 * Linux itself doesn't use 1:N distribution, so has no need to 2364 * set PMHE. The only reason to have it set is if EL3 requires it 2365 * (and we can't change it). 2366 */ 2367 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2368 } 2369 #endif 2370 2371 #ifdef CONFIG_ARM64_BTI 2372 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2373 { 2374 /* 2375 * Use of X16/X17 for tail-calls and trampolines that jump to 2376 * function entry points using BR is a requirement for 2377 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2378 * So, be strict and forbid other BRs using other registers to 2379 * jump onto a PACIxSP instruction: 2380 */ 2381 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2382 isb(); 2383 } 2384 #endif /* CONFIG_ARM64_BTI */ 2385 2386 #ifdef CONFIG_ARM64_MTE 2387 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2388 { 2389 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2390 2391 mte_cpu_setup(); 2392 2393 /* 2394 * Clear the tags in the zero page. This needs to be done via the 2395 * linear map which has the Tagged attribute. 2396 */ 2397 if (try_page_mte_tagging(ZERO_PAGE(0))) { 2398 mte_clear_page_tags(lm_alias(empty_zero_page)); 2399 set_page_mte_tagged(ZERO_PAGE(0)); 2400 } 2401 2402 kasan_init_hw_tags_cpu(); 2403 } 2404 #endif /* CONFIG_ARM64_MTE */ 2405 2406 static void user_feature_fixup(void) 2407 { 2408 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2409 struct arm64_ftr_reg *regp; 2410 2411 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2412 if (regp) 2413 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2414 } 2415 2416 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2417 struct arm64_ftr_reg *regp; 2418 2419 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2420 if (regp) 2421 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2422 } 2423 } 2424 2425 static void elf_hwcap_fixup(void) 2426 { 2427 #ifdef CONFIG_COMPAT 2428 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2429 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2430 #endif /* CONFIG_COMPAT */ 2431 } 2432 2433 #ifdef CONFIG_KVM 2434 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2435 { 2436 return kvm_get_mode() == KVM_MODE_PROTECTED; 2437 } 2438 #endif /* CONFIG_KVM */ 2439 2440 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2441 { 2442 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2443 } 2444 2445 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2446 { 2447 set_pstate_dit(1); 2448 } 2449 2450 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2451 { 2452 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2453 } 2454 2455 #ifdef CONFIG_ARM64_POE 2456 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2457 { 2458 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2459 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2460 } 2461 #endif 2462 2463 #ifdef CONFIG_ARM64_GCS 2464 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2465 { 2466 /* GCSPR_EL0 is always readable */ 2467 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2468 } 2469 #endif 2470 2471 /* Internal helper functions to match cpu capability type */ 2472 static bool 2473 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2474 { 2475 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2476 } 2477 2478 static bool 2479 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2480 { 2481 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2482 } 2483 2484 static bool 2485 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2486 { 2487 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2488 } 2489 2490 static bool 2491 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2492 { 2493 if (!has_cpuid_feature(entry, scope)) 2494 return false; 2495 2496 /* Check firmware actually enabled MPAM on this cpu. */ 2497 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2498 } 2499 2500 static void 2501 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2502 { 2503 /* 2504 * Access by the kernel (at EL1) should use the reserved PARTID 2505 * which is configured unrestricted. This avoids priority-inversion 2506 * where latency sensitive tasks have to wait for a task that has 2507 * been throttled to release the lock. 2508 */ 2509 write_sysreg_s(0, SYS_MPAM1_EL1); 2510 } 2511 2512 static bool 2513 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2514 { 2515 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2516 2517 return idr & MPAMIDR_EL1_HAS_HCR; 2518 } 2519 2520 static const struct arm64_cpu_capabilities arm64_features[] = { 2521 { 2522 .capability = ARM64_ALWAYS_BOOT, 2523 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2524 .matches = has_always, 2525 }, 2526 { 2527 .capability = ARM64_ALWAYS_SYSTEM, 2528 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2529 .matches = has_always, 2530 }, 2531 { 2532 .desc = "GIC system register CPU interface", 2533 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS, 2534 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2535 .matches = has_useable_gicv3_cpuif, 2536 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2537 }, 2538 { 2539 .desc = "Enhanced Counter Virtualization", 2540 .capability = ARM64_HAS_ECV, 2541 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2542 .matches = has_cpuid_feature, 2543 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2544 }, 2545 { 2546 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2547 .capability = ARM64_HAS_ECV_CNTPOFF, 2548 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2549 .matches = has_cpuid_feature, 2550 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2551 }, 2552 #ifdef CONFIG_ARM64_PAN 2553 { 2554 .desc = "Privileged Access Never", 2555 .capability = ARM64_HAS_PAN, 2556 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2557 .matches = has_cpuid_feature, 2558 .cpu_enable = cpu_enable_pan, 2559 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2560 }, 2561 #endif /* CONFIG_ARM64_PAN */ 2562 #ifdef CONFIG_ARM64_EPAN 2563 { 2564 .desc = "Enhanced Privileged Access Never", 2565 .capability = ARM64_HAS_EPAN, 2566 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2567 .matches = has_cpuid_feature, 2568 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2569 }, 2570 #endif /* CONFIG_ARM64_EPAN */ 2571 #ifdef CONFIG_ARM64_LSE_ATOMICS 2572 { 2573 .desc = "LSE atomic instructions", 2574 .capability = ARM64_HAS_LSE_ATOMICS, 2575 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2576 .matches = has_cpuid_feature, 2577 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2578 }, 2579 #endif /* CONFIG_ARM64_LSE_ATOMICS */ 2580 { 2581 .desc = "Virtualization Host Extensions", 2582 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2583 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2584 .matches = runs_at_el2, 2585 .cpu_enable = cpu_copy_el2regs, 2586 }, 2587 { 2588 .desc = "Nested Virtualization Support", 2589 .capability = ARM64_HAS_NESTED_VIRT, 2590 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2591 .matches = has_nested_virt_support, 2592 .match_list = (const struct arm64_cpu_capabilities []){ 2593 { 2594 .matches = has_cpuid_feature, 2595 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2596 }, 2597 { 2598 .matches = has_cpuid_feature, 2599 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2600 }, 2601 { /* Sentinel */ } 2602 }, 2603 }, 2604 { 2605 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2606 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2607 .matches = has_32bit_el0, 2608 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2609 }, 2610 #ifdef CONFIG_KVM 2611 { 2612 .desc = "32-bit EL1 Support", 2613 .capability = ARM64_HAS_32BIT_EL1, 2614 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2615 .matches = has_cpuid_feature, 2616 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2617 }, 2618 { 2619 .desc = "Protected KVM", 2620 .capability = ARM64_KVM_PROTECTED_MODE, 2621 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2622 .matches = is_kvm_protected_mode, 2623 }, 2624 { 2625 .desc = "HCRX_EL2 register", 2626 .capability = ARM64_HAS_HCX, 2627 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2628 .matches = has_cpuid_feature, 2629 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2630 }, 2631 #endif 2632 { 2633 .desc = "Kernel page table isolation (KPTI)", 2634 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2635 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2636 .cpu_enable = cpu_enable_kpti, 2637 .matches = unmap_kernel_at_el0, 2638 /* 2639 * The ID feature fields below are used to indicate that 2640 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2641 * more details. 2642 */ 2643 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2644 }, 2645 { 2646 .capability = ARM64_HAS_FPSIMD, 2647 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2648 .matches = has_cpuid_feature, 2649 .cpu_enable = cpu_enable_fpsimd, 2650 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2651 }, 2652 #ifdef CONFIG_ARM64_PMEM 2653 { 2654 .desc = "Data cache clean to Point of Persistence", 2655 .capability = ARM64_HAS_DCPOP, 2656 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2657 .matches = has_cpuid_feature, 2658 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2659 }, 2660 { 2661 .desc = "Data cache clean to Point of Deep Persistence", 2662 .capability = ARM64_HAS_DCPODP, 2663 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2664 .matches = has_cpuid_feature, 2665 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2666 }, 2667 #endif 2668 #ifdef CONFIG_ARM64_SVE 2669 { 2670 .desc = "Scalable Vector Extension", 2671 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2672 .capability = ARM64_SVE, 2673 .cpu_enable = cpu_enable_sve, 2674 .matches = has_cpuid_feature, 2675 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2676 }, 2677 #endif /* CONFIG_ARM64_SVE */ 2678 #ifdef CONFIG_ARM64_RAS_EXTN 2679 { 2680 .desc = "RAS Extension Support", 2681 .capability = ARM64_HAS_RAS_EXTN, 2682 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2683 .matches = has_cpuid_feature, 2684 .cpu_enable = cpu_clear_disr, 2685 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2686 }, 2687 #endif /* CONFIG_ARM64_RAS_EXTN */ 2688 #ifdef CONFIG_ARM64_AMU_EXTN 2689 { 2690 .desc = "Activity Monitors Unit (AMU)", 2691 .capability = ARM64_HAS_AMU_EXTN, 2692 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2693 .matches = has_amu, 2694 .cpu_enable = cpu_amu_enable, 2695 .cpus = &amu_cpus, 2696 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2697 }, 2698 #endif /* CONFIG_ARM64_AMU_EXTN */ 2699 { 2700 .desc = "Data cache clean to the PoU not required for I/D coherence", 2701 .capability = ARM64_HAS_CACHE_IDC, 2702 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2703 .matches = has_cache_idc, 2704 .cpu_enable = cpu_emulate_effective_ctr, 2705 }, 2706 { 2707 .desc = "Instruction cache invalidation not required for I/D coherence", 2708 .capability = ARM64_HAS_CACHE_DIC, 2709 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2710 .matches = has_cache_dic, 2711 }, 2712 { 2713 .desc = "Stage-2 Force Write-Back", 2714 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2715 .capability = ARM64_HAS_STAGE2_FWB, 2716 .matches = has_cpuid_feature, 2717 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2718 }, 2719 { 2720 .desc = "ARMv8.4 Translation Table Level", 2721 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2722 .capability = ARM64_HAS_ARMv8_4_TTL, 2723 .matches = has_cpuid_feature, 2724 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2725 }, 2726 { 2727 .desc = "TLB range maintenance instructions", 2728 .capability = ARM64_HAS_TLB_RANGE, 2729 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2730 .matches = has_cpuid_feature, 2731 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2732 }, 2733 #ifdef CONFIG_ARM64_HW_AFDBM 2734 { 2735 .desc = "Hardware dirty bit management", 2736 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2737 .capability = ARM64_HW_DBM, 2738 .matches = has_hw_dbm, 2739 .cpu_enable = cpu_enable_hw_dbm, 2740 .cpus = &dbm_cpus, 2741 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2742 }, 2743 #endif 2744 #ifdef CONFIG_ARM64_HAFT 2745 { 2746 .desc = "Hardware managed Access Flag for Table Descriptors", 2747 /* 2748 * Contrary to the page/block access flag, the table access flag 2749 * cannot be emulated in software (no access fault will occur). 2750 * Therefore this should be used only if it's supported system 2751 * wide. 2752 */ 2753 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2754 .capability = ARM64_HAFT, 2755 .matches = has_cpuid_feature, 2756 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2757 }, 2758 #endif 2759 { 2760 .desc = "CRC32 instructions", 2761 .capability = ARM64_HAS_CRC32, 2762 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2763 .matches = has_cpuid_feature, 2764 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2765 }, 2766 { 2767 .desc = "Speculative Store Bypassing Safe (SSBS)", 2768 .capability = ARM64_SSBS, 2769 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2770 .matches = has_cpuid_feature, 2771 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2772 }, 2773 #ifdef CONFIG_ARM64_CNP 2774 { 2775 .desc = "Common not Private translations", 2776 .capability = ARM64_HAS_CNP, 2777 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2778 .matches = has_useable_cnp, 2779 .cpu_enable = cpu_enable_cnp, 2780 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2781 }, 2782 #endif 2783 { 2784 .desc = "Speculation barrier (SB)", 2785 .capability = ARM64_HAS_SB, 2786 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2787 .matches = has_cpuid_feature, 2788 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2789 }, 2790 #ifdef CONFIG_ARM64_PTR_AUTH 2791 { 2792 .desc = "Address authentication (architected QARMA5 algorithm)", 2793 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2794 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2795 .matches = has_address_auth_cpucap, 2796 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2797 }, 2798 { 2799 .desc = "Address authentication (architected QARMA3 algorithm)", 2800 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2801 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2802 .matches = has_address_auth_cpucap, 2803 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2804 }, 2805 { 2806 .desc = "Address authentication (IMP DEF algorithm)", 2807 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2808 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2809 .matches = has_address_auth_cpucap, 2810 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2811 }, 2812 { 2813 .capability = ARM64_HAS_ADDRESS_AUTH, 2814 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2815 .matches = has_address_auth_metacap, 2816 }, 2817 { 2818 .desc = "Generic authentication (architected QARMA5 algorithm)", 2819 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2820 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2821 .matches = has_cpuid_feature, 2822 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2823 }, 2824 { 2825 .desc = "Generic authentication (architected QARMA3 algorithm)", 2826 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2827 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2828 .matches = has_cpuid_feature, 2829 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2830 }, 2831 { 2832 .desc = "Generic authentication (IMP DEF algorithm)", 2833 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2834 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2835 .matches = has_cpuid_feature, 2836 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2837 }, 2838 { 2839 .capability = ARM64_HAS_GENERIC_AUTH, 2840 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2841 .matches = has_generic_auth, 2842 }, 2843 #endif /* CONFIG_ARM64_PTR_AUTH */ 2844 #ifdef CONFIG_ARM64_PSEUDO_NMI 2845 { 2846 /* 2847 * Depends on having GICv3 2848 */ 2849 .desc = "IRQ priority masking", 2850 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2851 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2852 .matches = can_use_gic_priorities, 2853 }, 2854 { 2855 /* 2856 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2857 */ 2858 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2859 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2860 .matches = has_gic_prio_relaxed_sync, 2861 }, 2862 #endif 2863 #ifdef CONFIG_ARM64_E0PD 2864 { 2865 .desc = "E0PD", 2866 .capability = ARM64_HAS_E0PD, 2867 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2868 .cpu_enable = cpu_enable_e0pd, 2869 .matches = has_cpuid_feature, 2870 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2871 }, 2872 #endif 2873 { 2874 .desc = "Random Number Generator", 2875 .capability = ARM64_HAS_RNG, 2876 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2877 .matches = has_cpuid_feature, 2878 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2879 }, 2880 #ifdef CONFIG_ARM64_BTI 2881 { 2882 .desc = "Branch Target Identification", 2883 .capability = ARM64_BTI, 2884 #ifdef CONFIG_ARM64_BTI_KERNEL 2885 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2886 #else 2887 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2888 #endif 2889 .matches = has_cpuid_feature, 2890 .cpu_enable = bti_enable, 2891 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2892 }, 2893 #endif 2894 #ifdef CONFIG_ARM64_MTE 2895 { 2896 .desc = "Memory Tagging Extension", 2897 .capability = ARM64_MTE, 2898 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2899 .matches = has_cpuid_feature, 2900 .cpu_enable = cpu_enable_mte, 2901 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2902 }, 2903 { 2904 .desc = "Asymmetric MTE Tag Check Fault", 2905 .capability = ARM64_MTE_ASYMM, 2906 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2907 .matches = has_cpuid_feature, 2908 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2909 }, 2910 { 2911 .desc = "FAR on MTE Tag Check Fault", 2912 .capability = ARM64_MTE_FAR, 2913 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2914 .matches = has_cpuid_feature, 2915 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2916 }, 2917 #endif /* CONFIG_ARM64_MTE */ 2918 { 2919 .desc = "RCpc load-acquire (LDAPR)", 2920 .capability = ARM64_HAS_LDAPR, 2921 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2922 .matches = has_cpuid_feature, 2923 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2924 }, 2925 { 2926 .desc = "Fine Grained Traps", 2927 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2928 .capability = ARM64_HAS_FGT, 2929 .matches = has_cpuid_feature, 2930 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2931 }, 2932 { 2933 .desc = "Fine Grained Traps 2", 2934 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2935 .capability = ARM64_HAS_FGT2, 2936 .matches = has_cpuid_feature, 2937 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2938 }, 2939 #ifdef CONFIG_ARM64_SME 2940 { 2941 .desc = "Scalable Matrix Extension", 2942 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2943 .capability = ARM64_SME, 2944 .matches = has_cpuid_feature, 2945 .cpu_enable = cpu_enable_sme, 2946 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2947 }, 2948 /* FA64 should be sorted after the base SME capability */ 2949 { 2950 .desc = "FA64", 2951 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2952 .capability = ARM64_SME_FA64, 2953 .matches = has_cpuid_feature, 2954 .cpu_enable = cpu_enable_fa64, 2955 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2956 }, 2957 { 2958 .desc = "SME2", 2959 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2960 .capability = ARM64_SME2, 2961 .matches = has_cpuid_feature, 2962 .cpu_enable = cpu_enable_sme2, 2963 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 2964 }, 2965 #endif /* CONFIG_ARM64_SME */ 2966 { 2967 .desc = "WFx with timeout", 2968 .capability = ARM64_HAS_WFXT, 2969 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2970 .matches = has_cpuid_feature, 2971 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 2972 }, 2973 { 2974 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 2975 .capability = ARM64_HAS_TIDCP1, 2976 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2977 .matches = has_cpuid_feature, 2978 .cpu_enable = cpu_trap_el0_impdef, 2979 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 2980 }, 2981 { 2982 .desc = "Data independent timing control (DIT)", 2983 .capability = ARM64_HAS_DIT, 2984 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2985 .matches = has_cpuid_feature, 2986 .cpu_enable = cpu_enable_dit, 2987 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 2988 }, 2989 { 2990 .desc = "Memory Copy and Memory Set instructions", 2991 .capability = ARM64_HAS_MOPS, 2992 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2993 .matches = has_cpuid_feature, 2994 .cpu_enable = cpu_enable_mops, 2995 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 2996 }, 2997 { 2998 .capability = ARM64_HAS_TCR2, 2999 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3000 .matches = has_cpuid_feature, 3001 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3002 }, 3003 { 3004 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3005 .capability = ARM64_HAS_S1PIE, 3006 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3007 .matches = has_cpuid_feature, 3008 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3009 }, 3010 { 3011 .desc = "VHE for hypervisor only", 3012 .capability = ARM64_KVM_HVHE, 3013 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3014 .matches = hvhe_possible, 3015 }, 3016 { 3017 .desc = "Enhanced Virtualization Traps", 3018 .capability = ARM64_HAS_EVT, 3019 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3020 .matches = has_cpuid_feature, 3021 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3022 }, 3023 { 3024 .desc = "BBM Level 2 without TLB conflict abort", 3025 .capability = ARM64_HAS_BBML2_NOABORT, 3026 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3027 .matches = has_bbml2_noabort, 3028 }, 3029 { 3030 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3031 .capability = ARM64_HAS_LPA2, 3032 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3033 .matches = has_lpa2, 3034 }, 3035 { 3036 .desc = "FPMR", 3037 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3038 .capability = ARM64_HAS_FPMR, 3039 .matches = has_cpuid_feature, 3040 .cpu_enable = cpu_enable_fpmr, 3041 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3042 }, 3043 #ifdef CONFIG_ARM64_VA_BITS_52 3044 { 3045 .capability = ARM64_HAS_VA52, 3046 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3047 .matches = has_cpuid_feature, 3048 #ifdef CONFIG_ARM64_64K_PAGES 3049 .desc = "52-bit Virtual Addressing (LVA)", 3050 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3051 #else 3052 .desc = "52-bit Virtual Addressing (LPA2)", 3053 #ifdef CONFIG_ARM64_4K_PAGES 3054 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3055 #else 3056 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3057 #endif 3058 #endif 3059 }, 3060 #endif 3061 { 3062 .desc = "Memory Partitioning And Monitoring", 3063 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3064 .capability = ARM64_MPAM, 3065 .matches = test_has_mpam, 3066 .cpu_enable = cpu_enable_mpam, 3067 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, MPAM, 1) 3068 }, 3069 { 3070 .desc = "Memory Partitioning And Monitoring Virtualisation", 3071 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3072 .capability = ARM64_MPAM_HCR, 3073 .matches = test_has_mpam_hcr, 3074 }, 3075 { 3076 .desc = "NV1", 3077 .capability = ARM64_HAS_HCR_NV1, 3078 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3079 .matches = has_nv1, 3080 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3081 }, 3082 #ifdef CONFIG_ARM64_POE 3083 { 3084 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3085 .capability = ARM64_HAS_S1POE, 3086 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3087 .matches = has_cpuid_feature, 3088 .cpu_enable = cpu_enable_poe, 3089 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3090 }, 3091 #endif 3092 #ifdef CONFIG_ARM64_GCS 3093 { 3094 .desc = "Guarded Control Stack (GCS)", 3095 .capability = ARM64_HAS_GCS, 3096 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3097 .cpu_enable = cpu_enable_gcs, 3098 .matches = has_cpuid_feature, 3099 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3100 }, 3101 #endif 3102 #ifdef CONFIG_HW_PERF_EVENTS 3103 { 3104 .desc = "PMUv3", 3105 .capability = ARM64_HAS_PMUV3, 3106 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3107 .matches = has_pmuv3, 3108 }, 3109 #endif 3110 {}, 3111 }; 3112 3113 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3114 .matches = has_user_cpuid_feature, \ 3115 ARM64_CPUID_FIELDS(reg, field, min_value) 3116 3117 #define __HWCAP_CAP(name, cap_type, cap) \ 3118 .desc = name, \ 3119 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3120 .hwcap_type = cap_type, \ 3121 .hwcap = cap, \ 3122 3123 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3124 { \ 3125 __HWCAP_CAP(#cap, cap_type, cap) \ 3126 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3127 } 3128 3129 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3130 { \ 3131 __HWCAP_CAP(#cap, cap_type, cap) \ 3132 .matches = cpucap_multi_entry_cap_matches, \ 3133 .match_list = list, \ 3134 } 3135 3136 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3137 { \ 3138 __HWCAP_CAP(#cap, cap_type, cap) \ 3139 .matches = match, \ 3140 } 3141 3142 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3143 { \ 3144 __HWCAP_CAP(#cap, cap_type, cap) \ 3145 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3146 .matches = match, \ 3147 } 3148 3149 #ifdef CONFIG_ARM64_PTR_AUTH 3150 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3151 { 3152 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3153 }, 3154 { 3155 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3156 }, 3157 { 3158 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3159 }, 3160 {}, 3161 }; 3162 3163 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3164 { 3165 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3166 }, 3167 { 3168 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3169 }, 3170 { 3171 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3172 }, 3173 {}, 3174 }; 3175 #endif 3176 3177 #ifdef CONFIG_ARM64_SVE 3178 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3179 { 3180 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3181 } 3182 #endif 3183 3184 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3185 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3186 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3187 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3188 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3189 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3190 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3191 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3192 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3193 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3194 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3195 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3196 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3197 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3198 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3199 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3200 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3201 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3202 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3203 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3204 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3205 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3206 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3207 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3208 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3209 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3210 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3211 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3212 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3213 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3214 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3215 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3216 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3217 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3218 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3219 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3220 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3221 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3222 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3223 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3224 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3225 #ifdef CONFIG_ARM64_SVE 3226 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3227 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3228 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3229 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3230 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3231 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3232 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3233 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3234 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3235 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3236 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3237 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3238 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3239 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3240 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3241 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3242 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3243 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3244 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3245 #endif 3246 #ifdef CONFIG_ARM64_GCS 3247 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3248 #endif 3249 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3250 #ifdef CONFIG_ARM64_BTI 3251 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3252 #endif 3253 #ifdef CONFIG_ARM64_PTR_AUTH 3254 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3255 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3256 #endif 3257 #ifdef CONFIG_ARM64_MTE 3258 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3259 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3260 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3261 #endif /* CONFIG_ARM64_MTE */ 3262 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3263 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3264 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3265 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3266 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3267 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3268 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3269 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3270 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3271 #ifdef CONFIG_ARM64_SME 3272 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3273 HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3274 HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3275 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3276 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3277 HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3278 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3279 HWCAP_CAP(ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3280 HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3281 HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3282 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3283 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3284 HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3285 HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3286 HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3287 HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3288 HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3289 HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3290 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3291 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3292 HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3293 HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3294 HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3295 HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3296 HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3297 HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3298 #endif /* CONFIG_ARM64_SME */ 3299 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3300 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3301 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3302 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3303 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3304 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3305 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3306 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3307 #ifdef CONFIG_ARM64_POE 3308 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3309 #endif 3310 {}, 3311 }; 3312 3313 #ifdef CONFIG_COMPAT 3314 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3315 { 3316 /* 3317 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3318 * in line with that of arm32 as in vfp_init(). We make sure that the 3319 * check is future proof, by making sure value is non-zero. 3320 */ 3321 u32 mvfr1; 3322 3323 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3324 if (scope == SCOPE_SYSTEM) 3325 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3326 else 3327 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3328 3329 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3330 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3331 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3332 } 3333 #endif 3334 3335 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3336 #ifdef CONFIG_COMPAT 3337 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3338 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3339 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3340 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3341 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3342 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3343 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3344 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3345 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3346 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3347 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3348 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3349 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3350 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3351 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3352 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3353 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3354 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3355 #endif 3356 {}, 3357 }; 3358 3359 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3360 { 3361 switch (cap->hwcap_type) { 3362 case CAP_HWCAP: 3363 cpu_set_feature(cap->hwcap); 3364 break; 3365 #ifdef CONFIG_COMPAT 3366 case CAP_COMPAT_HWCAP: 3367 compat_elf_hwcap |= (u32)cap->hwcap; 3368 break; 3369 case CAP_COMPAT_HWCAP2: 3370 compat_elf_hwcap2 |= (u32)cap->hwcap; 3371 break; 3372 #endif 3373 default: 3374 WARN_ON(1); 3375 break; 3376 } 3377 } 3378 3379 /* Check if we have a particular HWCAP enabled */ 3380 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3381 { 3382 bool rc; 3383 3384 switch (cap->hwcap_type) { 3385 case CAP_HWCAP: 3386 rc = cpu_have_feature(cap->hwcap); 3387 break; 3388 #ifdef CONFIG_COMPAT 3389 case CAP_COMPAT_HWCAP: 3390 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3391 break; 3392 case CAP_COMPAT_HWCAP2: 3393 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3394 break; 3395 #endif 3396 default: 3397 WARN_ON(1); 3398 rc = false; 3399 } 3400 3401 return rc; 3402 } 3403 3404 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3405 { 3406 /* We support emulation of accesses to CPU ID feature registers */ 3407 cpu_set_named_feature(CPUID); 3408 for (; hwcaps->matches; hwcaps++) 3409 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3410 cap_set_elf_hwcap(hwcaps); 3411 } 3412 3413 static void update_cpu_capabilities(u16 scope_mask) 3414 { 3415 int i; 3416 const struct arm64_cpu_capabilities *caps; 3417 3418 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3419 for (i = 0; i < ARM64_NCAPS; i++) { 3420 bool match_all = false; 3421 bool caps_set = false; 3422 bool boot_cpu = false; 3423 3424 caps = cpucap_ptrs[i]; 3425 if (!caps || !(caps->type & scope_mask)) 3426 continue; 3427 3428 match_all = cpucap_match_all_early_cpus(caps); 3429 caps_set = cpus_have_cap(caps->capability); 3430 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3431 3432 /* 3433 * Unless it's a match-all CPUs feature, avoid probing if 3434 * already detected. 3435 */ 3436 if (!match_all && caps_set) 3437 continue; 3438 3439 /* 3440 * A match-all CPUs capability is only set when probing the 3441 * boot CPU. It may be cleared subsequently if not detected on 3442 * secondary ones. 3443 */ 3444 if (match_all && !caps_set && !boot_cpu) 3445 continue; 3446 3447 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3448 if (match_all) 3449 __clear_bit(caps->capability, system_cpucaps); 3450 continue; 3451 } 3452 3453 /* 3454 * Match-all CPUs capabilities are logged later when the 3455 * system capabilities are finalised. 3456 */ 3457 if (!match_all && caps->desc && !caps->cpus) 3458 pr_info("detected: %s\n", caps->desc); 3459 3460 __set_bit(caps->capability, system_cpucaps); 3461 3462 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3463 set_bit(caps->capability, boot_cpucaps); 3464 } 3465 } 3466 3467 /* 3468 * Enable all the available capabilities on this CPU. The capabilities 3469 * with BOOT_CPU scope are handled separately and hence skipped here. 3470 */ 3471 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3472 { 3473 int i; 3474 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3475 3476 for_each_available_cap(i) { 3477 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3478 3479 if (WARN_ON(!cap)) 3480 continue; 3481 3482 if (!(cap->type & non_boot_scope)) 3483 continue; 3484 3485 if (cap->cpu_enable) 3486 cap->cpu_enable(cap); 3487 } 3488 return 0; 3489 } 3490 3491 /* 3492 * Run through the enabled capabilities and enable() it on all active 3493 * CPUs 3494 */ 3495 static void __init enable_cpu_capabilities(u16 scope_mask) 3496 { 3497 int i; 3498 const struct arm64_cpu_capabilities *caps; 3499 bool boot_scope; 3500 3501 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3502 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3503 3504 for (i = 0; i < ARM64_NCAPS; i++) { 3505 caps = cpucap_ptrs[i]; 3506 if (!caps || !(caps->type & scope_mask) || 3507 !cpus_have_cap(caps->capability)) 3508 continue; 3509 3510 if (boot_scope && caps->cpu_enable) 3511 /* 3512 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3513 * before any secondary CPU boots. Thus, each secondary 3514 * will enable the capability as appropriate via 3515 * check_local_cpu_capabilities(). The only exception is 3516 * the boot CPU, for which the capability must be 3517 * enabled here. This approach avoids costly 3518 * stop_machine() calls for this case. 3519 */ 3520 caps->cpu_enable(caps); 3521 } 3522 3523 /* 3524 * For all non-boot scope capabilities, use stop_machine() 3525 * as it schedules the work allowing us to modify PSTATE, 3526 * instead of on_each_cpu() which uses an IPI, giving us a 3527 * PSTATE that disappears when we return. 3528 */ 3529 if (!boot_scope) 3530 stop_machine(cpu_enable_non_boot_scope_capabilities, 3531 NULL, cpu_online_mask); 3532 } 3533 3534 /* 3535 * Run through the list of capabilities to check for conflicts. 3536 * If the system has already detected a capability, take necessary 3537 * action on this CPU. 3538 */ 3539 static void verify_local_cpu_caps(u16 scope_mask) 3540 { 3541 int i; 3542 bool cpu_has_cap, system_has_cap; 3543 const struct arm64_cpu_capabilities *caps; 3544 3545 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3546 3547 for (i = 0; i < ARM64_NCAPS; i++) { 3548 caps = cpucap_ptrs[i]; 3549 if (!caps || !(caps->type & scope_mask)) 3550 continue; 3551 3552 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3553 system_has_cap = cpus_have_cap(caps->capability); 3554 3555 if (system_has_cap) { 3556 /* 3557 * Check if the new CPU misses an advertised feature, 3558 * which is not safe to miss. 3559 */ 3560 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3561 break; 3562 /* 3563 * We have to issue cpu_enable() irrespective of 3564 * whether the CPU has it or not, as it is enabeld 3565 * system wide. It is upto the call back to take 3566 * appropriate action on this CPU. 3567 */ 3568 if (caps->cpu_enable) 3569 caps->cpu_enable(caps); 3570 } else { 3571 /* 3572 * Check if the CPU has this capability if it isn't 3573 * safe to have when the system doesn't. 3574 */ 3575 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3576 break; 3577 } 3578 } 3579 3580 if (i < ARM64_NCAPS) { 3581 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3582 smp_processor_id(), caps->capability, 3583 caps->desc, system_has_cap, cpu_has_cap); 3584 3585 if (cpucap_panic_on_conflict(caps)) 3586 cpu_panic_kernel(); 3587 else 3588 cpu_die_early(); 3589 } 3590 } 3591 3592 /* 3593 * Check for CPU features that are used in early boot 3594 * based on the Boot CPU value. 3595 */ 3596 static void check_early_cpu_features(void) 3597 { 3598 verify_cpu_asid_bits(); 3599 3600 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3601 } 3602 3603 static void 3604 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3605 { 3606 3607 for (; caps->matches; caps++) 3608 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3609 pr_crit("CPU%d: missing HWCAP: %s\n", 3610 smp_processor_id(), caps->desc); 3611 cpu_die_early(); 3612 } 3613 } 3614 3615 static void verify_local_elf_hwcaps(void) 3616 { 3617 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3618 3619 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3620 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3621 } 3622 3623 static void verify_sve_features(void) 3624 { 3625 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3626 3627 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3628 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3629 smp_processor_id()); 3630 cpu_die_early(); 3631 } 3632 3633 cpacr_restore(cpacr); 3634 } 3635 3636 static void verify_sme_features(void) 3637 { 3638 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3639 3640 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3641 pr_crit("CPU%d: SME: vector length support mismatch\n", 3642 smp_processor_id()); 3643 cpu_die_early(); 3644 } 3645 3646 cpacr_restore(cpacr); 3647 } 3648 3649 static void verify_hyp_capabilities(void) 3650 { 3651 u64 safe_mmfr1, mmfr0, mmfr1; 3652 int parange, ipa_max; 3653 unsigned int safe_vmid_bits, vmid_bits; 3654 3655 if (!IS_ENABLED(CONFIG_KVM)) 3656 return; 3657 3658 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3659 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3660 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3661 3662 /* Verify VMID bits */ 3663 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3664 vmid_bits = get_vmid_bits(mmfr1); 3665 if (vmid_bits < safe_vmid_bits) { 3666 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3667 cpu_die_early(); 3668 } 3669 3670 /* Verify IPA range */ 3671 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3672 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3673 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3674 if (ipa_max < get_kvm_ipa_limit()) { 3675 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3676 cpu_die_early(); 3677 } 3678 } 3679 3680 static void verify_mpam_capabilities(void) 3681 { 3682 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3683 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3684 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3685 3686 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3687 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3688 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3689 cpu_die_early(); 3690 } 3691 3692 cpu_idr = read_cpuid(MPAMIDR_EL1); 3693 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3694 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3695 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3696 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3697 cpu_die_early(); 3698 } 3699 3700 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3701 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3702 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3703 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3704 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3705 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3706 cpu_die_early(); 3707 } 3708 } 3709 3710 /* 3711 * Run through the enabled system capabilities and enable() it on this CPU. 3712 * The capabilities were decided based on the available CPUs at the boot time. 3713 * Any new CPU should match the system wide status of the capability. If the 3714 * new CPU doesn't have a capability which the system now has enabled, we 3715 * cannot do anything to fix it up and could cause unexpected failures. So 3716 * we park the CPU. 3717 */ 3718 static void verify_local_cpu_capabilities(void) 3719 { 3720 /* 3721 * The capabilities with SCOPE_BOOT_CPU are checked from 3722 * check_early_cpu_features(), as they need to be verified 3723 * on all secondary CPUs. 3724 */ 3725 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3726 verify_local_elf_hwcaps(); 3727 3728 if (system_supports_sve()) 3729 verify_sve_features(); 3730 3731 if (system_supports_sme()) 3732 verify_sme_features(); 3733 3734 if (is_hyp_mode_available()) 3735 verify_hyp_capabilities(); 3736 3737 if (system_supports_mpam()) 3738 verify_mpam_capabilities(); 3739 } 3740 3741 void check_local_cpu_capabilities(void) 3742 { 3743 /* 3744 * All secondary CPUs should conform to the early CPU features 3745 * in use by the kernel based on boot CPU. 3746 */ 3747 check_early_cpu_features(); 3748 3749 /* 3750 * If we haven't finalised the system capabilities, this CPU gets 3751 * a chance to update the errata work arounds and local features. 3752 * Otherwise, this CPU should verify that it has all the system 3753 * advertised capabilities. 3754 */ 3755 if (!system_capabilities_finalized()) 3756 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3757 else 3758 verify_local_cpu_capabilities(); 3759 } 3760 3761 bool this_cpu_has_cap(unsigned int n) 3762 { 3763 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3764 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3765 3766 if (cap) 3767 return cap->matches(cap, SCOPE_LOCAL_CPU); 3768 } 3769 3770 return false; 3771 } 3772 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3773 3774 /* 3775 * This helper function is used in a narrow window when, 3776 * - The system wide safe registers are set with all the SMP CPUs and, 3777 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3778 */ 3779 static bool __maybe_unused __system_matches_cap(unsigned int n) 3780 { 3781 if (n < ARM64_NCAPS) { 3782 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3783 3784 if (cap) 3785 return cap->matches(cap, SCOPE_SYSTEM); 3786 } 3787 return false; 3788 } 3789 3790 void cpu_set_feature(unsigned int num) 3791 { 3792 set_bit(num, elf_hwcap); 3793 } 3794 3795 bool cpu_have_feature(unsigned int num) 3796 { 3797 return test_bit(num, elf_hwcap); 3798 } 3799 EXPORT_SYMBOL_GPL(cpu_have_feature); 3800 3801 unsigned long cpu_get_elf_hwcap(void) 3802 { 3803 /* 3804 * We currently only populate the first 32 bits of AT_HWCAP. Please 3805 * note that for userspace compatibility we guarantee that bits 62 3806 * and 63 will always be returned as 0. 3807 */ 3808 return elf_hwcap[0]; 3809 } 3810 3811 unsigned long cpu_get_elf_hwcap2(void) 3812 { 3813 return elf_hwcap[1]; 3814 } 3815 3816 unsigned long cpu_get_elf_hwcap3(void) 3817 { 3818 return elf_hwcap[2]; 3819 } 3820 3821 static void __init setup_boot_cpu_capabilities(void) 3822 { 3823 kvm_arm_target_impl_cpu_init(); 3824 /* 3825 * The boot CPU's feature register values have been recorded. Detect 3826 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3827 * patch alternatives for the available boot cpucaps. 3828 */ 3829 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3830 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3831 apply_boot_alternatives(); 3832 } 3833 3834 void __init setup_boot_cpu_features(void) 3835 { 3836 /* 3837 * Initialize the indirect array of CPU capabilities pointers before we 3838 * handle the boot CPU. 3839 */ 3840 init_cpucap_indirect_list(); 3841 3842 /* 3843 * Detect broken pseudo-NMI. Must be called _before_ the call to 3844 * setup_boot_cpu_capabilities() since it interacts with 3845 * can_use_gic_priorities(). 3846 */ 3847 detect_system_supports_pseudo_nmi(); 3848 3849 setup_boot_cpu_capabilities(); 3850 } 3851 3852 static void __init setup_system_capabilities(void) 3853 { 3854 /* 3855 * The system-wide safe feature register values have been finalized. 3856 * Detect, enable, and patch alternatives for the available system 3857 * cpucaps. 3858 */ 3859 update_cpu_capabilities(SCOPE_SYSTEM); 3860 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3861 apply_alternatives_all(); 3862 3863 for (int i = 0; i < ARM64_NCAPS; i++) { 3864 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3865 3866 if (!caps || !caps->desc) 3867 continue; 3868 3869 /* 3870 * Log any cpucaps with a cpumask as these aren't logged by 3871 * update_cpu_capabilities(). 3872 */ 3873 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3874 pr_info("detected: %s on CPU%*pbl\n", 3875 caps->desc, cpumask_pr_args(caps->cpus)); 3876 3877 /* Log match-all CPUs capabilities */ 3878 if (cpucap_match_all_early_cpus(caps) && 3879 cpus_have_cap(caps->capability)) 3880 pr_info("detected: %s\n", caps->desc); 3881 } 3882 3883 /* 3884 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3885 */ 3886 if (system_uses_ttbr0_pan()) 3887 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3888 } 3889 3890 void __init setup_system_features(void) 3891 { 3892 setup_system_capabilities(); 3893 3894 kpti_install_ng_mappings(); 3895 3896 sve_setup(); 3897 sme_setup(); 3898 3899 /* 3900 * Check for sane CTR_EL0.CWG value. 3901 */ 3902 if (!cache_type_cwg()) 3903 pr_warn("No Cache Writeback Granule information, assuming %d\n", 3904 ARCH_DMA_MINALIGN); 3905 } 3906 3907 void __init setup_user_features(void) 3908 { 3909 user_feature_fixup(); 3910 3911 setup_elf_hwcaps(arm64_elf_hwcaps); 3912 3913 if (system_supports_32bit_el0()) { 3914 setup_elf_hwcaps(compat_elf_hwcaps); 3915 elf_hwcap_fixup(); 3916 } 3917 3918 minsigstksz_setup(); 3919 } 3920 3921 static int enable_mismatched_32bit_el0(unsigned int cpu) 3922 { 3923 /* 3924 * The first 32-bit-capable CPU we detected and so can no longer 3925 * be offlined by userspace. -1 indicates we haven't yet onlined 3926 * a 32-bit-capable CPU. 3927 */ 3928 static int lucky_winner = -1; 3929 3930 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 3931 bool cpu_32bit = false; 3932 3933 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 3934 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) 3935 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); 3936 else 3937 cpu_32bit = true; 3938 } 3939 3940 if (cpu_32bit) { 3941 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 3942 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 3943 } 3944 3945 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 3946 return 0; 3947 3948 if (lucky_winner >= 0) 3949 return 0; 3950 3951 /* 3952 * We've detected a mismatch. We need to keep one of our CPUs with 3953 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 3954 * every CPU in the system for a 32-bit task. 3955 */ 3956 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 3957 cpu_active_mask); 3958 get_cpu_device(lucky_winner)->offline_disabled = true; 3959 setup_elf_hwcaps(compat_elf_hwcaps); 3960 elf_hwcap_fixup(); 3961 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 3962 cpu, lucky_winner); 3963 return 0; 3964 } 3965 3966 static int __init init_32bit_el0_mask(void) 3967 { 3968 if (!allow_mismatched_32bit_el0) 3969 return 0; 3970 3971 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 3972 return -ENOMEM; 3973 3974 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 3975 "arm64/mismatched_32bit_el0:online", 3976 enable_mismatched_32bit_el0, NULL); 3977 } 3978 subsys_initcall_sync(init_32bit_el0_mask); 3979 3980 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 3981 { 3982 cpu_enable_swapper_cnp(); 3983 } 3984 3985 /* 3986 * We emulate only the following system register space. 3987 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 3988 * See Table C5-6 System instruction encodings for System register accesses, 3989 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 3990 */ 3991 static inline bool __attribute_const__ is_emulated(u32 id) 3992 { 3993 return (sys_reg_Op0(id) == 0x3 && 3994 sys_reg_CRn(id) == 0x0 && 3995 sys_reg_Op1(id) == 0x0 && 3996 (sys_reg_CRm(id) == 0 || 3997 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 3998 } 3999 4000 /* 4001 * With CRm == 0, reg should be one of : 4002 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4003 */ 4004 static inline int emulate_id_reg(u32 id, u64 *valp) 4005 { 4006 switch (id) { 4007 case SYS_MIDR_EL1: 4008 *valp = read_cpuid_id(); 4009 break; 4010 case SYS_MPIDR_EL1: 4011 *valp = SYS_MPIDR_SAFE_VAL; 4012 break; 4013 case SYS_REVIDR_EL1: 4014 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4015 *valp = 0; 4016 break; 4017 default: 4018 return -EINVAL; 4019 } 4020 4021 return 0; 4022 } 4023 4024 static int emulate_sys_reg(u32 id, u64 *valp) 4025 { 4026 struct arm64_ftr_reg *regp; 4027 4028 if (!is_emulated(id)) 4029 return -EINVAL; 4030 4031 if (sys_reg_CRm(id) == 0) 4032 return emulate_id_reg(id, valp); 4033 4034 regp = get_arm64_ftr_reg_nowarn(id); 4035 if (regp) 4036 *valp = arm64_ftr_reg_user_value(regp); 4037 else 4038 /* 4039 * The untracked registers are either IMPLEMENTATION DEFINED 4040 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4041 */ 4042 *valp = 0; 4043 return 0; 4044 } 4045 4046 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4047 { 4048 int rc; 4049 u64 val; 4050 4051 rc = emulate_sys_reg(sys_reg, &val); 4052 if (!rc) { 4053 pt_regs_write_reg(regs, rt, val); 4054 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4055 } 4056 return rc; 4057 } 4058 4059 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4060 { 4061 u32 sys_reg, rt; 4062 4063 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4064 return false; 4065 4066 /* 4067 * sys_reg values are defined as used in mrs/msr instruction. 4068 * shift the imm value to get the encoding. 4069 */ 4070 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4071 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4072 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4073 } 4074 4075 enum mitigation_state arm64_get_meltdown_state(void) 4076 { 4077 if (__meltdown_safe) 4078 return SPECTRE_UNAFFECTED; 4079 4080 if (arm64_kernel_unmapped_at_el0()) 4081 return SPECTRE_MITIGATED; 4082 4083 return SPECTRE_VULNERABLE; 4084 } 4085 4086 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4087 char *buf) 4088 { 4089 switch (arm64_get_meltdown_state()) { 4090 case SPECTRE_UNAFFECTED: 4091 return sprintf(buf, "Not affected\n"); 4092 4093 case SPECTRE_MITIGATED: 4094 return sprintf(buf, "Mitigation: PTI\n"); 4095 4096 default: 4097 return sprintf(buf, "Vulnerable\n"); 4098 } 4099 } 4100