1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 121 /* 122 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 123 * ends up in the .bss section where it is initialized in early_map_kernel() 124 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 125 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 126 * may end up generating an incorrect idmap page table attributes. 127 */ 128 bool arm64_use_ng_mappings __read_mostly = false; 129 EXPORT_SYMBOL(arm64_use_ng_mappings); 130 131 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 132 133 /* 134 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 135 * support it? 136 */ 137 static bool __read_mostly allow_mismatched_32bit_el0; 138 139 /* 140 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 141 * seen at least one CPU capable of 32-bit EL0. 142 */ 143 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 144 145 /* 146 * Mask of CPUs supporting 32-bit EL0. 147 * Only valid if arm64_mismatched_32bit_el0 is enabled. 148 */ 149 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 150 151 void dump_cpu_features(void) 152 { 153 /* file-wide pr_fmt adds "CPU features: " prefix */ 154 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 155 } 156 157 #define __ARM64_MAX_POSITIVE(reg, field) \ 158 ((reg##_##field##_SIGNED ? \ 159 BIT(reg##_##field##_WIDTH - 1) : \ 160 BIT(reg##_##field##_WIDTH)) - 1) 161 162 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 163 164 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 165 .sys_reg = SYS_##reg, \ 166 .field_pos = reg##_##field##_SHIFT, \ 167 .field_width = reg##_##field##_WIDTH, \ 168 .sign = reg##_##field##_SIGNED, \ 169 .min_field_value = min_value, \ 170 .max_field_value = max_value, 171 172 /* 173 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 174 * an implicit maximum that depends on the sign-ess of the field. 175 * 176 * An unsigned field will be capped at all ones, while a signed field 177 * will be limited to the positive half only. 178 */ 179 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 180 __ARM64_CPUID_FIELDS(reg, field, \ 181 SYS_FIELD_VALUE(reg, field, min_value), \ 182 __ARM64_MAX_POSITIVE(reg, field)) 183 184 /* 185 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 186 * implicit minimal value to max_value. This should be used when 187 * matching a non-implemented property. 188 */ 189 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 190 __ARM64_CPUID_FIELDS(reg, field, \ 191 __ARM64_MIN_NEGATIVE(reg, field), \ 192 SYS_FIELD_VALUE(reg, field, max_value)) 193 194 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 { \ 196 .sign = SIGNED, \ 197 .visible = VISIBLE, \ 198 .strict = STRICT, \ 199 .type = TYPE, \ 200 .shift = SHIFT, \ 201 .width = WIDTH, \ 202 .safe_val = SAFE_VAL, \ 203 } 204 205 /* Define a feature with unsigned values */ 206 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 /* Define a feature with a signed value */ 210 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 211 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 212 213 #define ARM64_FTR_END \ 214 { \ 215 .width = 0, \ 216 } 217 218 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 219 220 static bool __system_matches_cap(unsigned int n); 221 222 /* 223 * NOTE: Any changes to the visibility of features should be kept in 224 * sync with the documentation of the CPU feature register ABI. 225 */ 226 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 269 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_ATS1A_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 276 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 277 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 278 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 279 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 282 ARM64_FTR_END, 283 }; 284 285 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 286 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 289 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 290 ARM64_FTR_END, 291 }; 292 293 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 300 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 301 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 304 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 305 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 309 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 310 ARM64_FTR_END, 311 }; 312 313 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 314 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 315 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 316 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 317 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 318 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 319 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 322 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 323 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 325 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 326 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 327 ARM64_FTR_END, 328 }; 329 330 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 331 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 334 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 335 ARM64_FTR_END, 336 }; 337 338 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 339 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 340 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 341 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 342 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 343 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 344 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 345 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 346 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 347 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 348 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 349 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 350 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 351 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 352 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 353 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 354 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 355 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 356 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 357 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 358 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 359 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 360 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 361 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 362 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 363 ARM64_FTR_END, 364 }; 365 366 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 367 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 368 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 369 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 370 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), 371 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 372 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 373 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 374 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 375 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 376 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 377 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 378 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 379 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 380 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 381 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 382 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 383 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 384 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 385 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 386 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 387 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 388 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 389 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 390 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 391 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 392 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 393 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 394 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 395 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 396 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 397 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 398 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 399 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 400 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 401 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 402 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 403 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 404 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 405 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 406 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 407 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 408 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 409 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 410 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 411 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 412 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 413 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 414 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 415 ARM64_FTR_END, 416 }; 417 418 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM2_SHIFT, 1, 0), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 427 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 428 ARM64_FTR_END, 429 }; 430 431 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 435 /* 436 * Page size not being supported at Stage-2 is not fatal. You 437 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 438 * your favourite nesting hypervisor. 439 * 440 * There is a small corner case where the hypervisor explicitly 441 * advertises a given granule size at Stage-2 (value 2) on some 442 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 443 * vCPUs. Although this is not forbidden by the architecture, it 444 * indicates that the hypervisor is being silly (or buggy). 445 * 446 * We make no effort to cope with this and pretend that if these 447 * fields are inconsistent across vCPUs, then it isn't worth 448 * trying to bring KVM up. 449 */ 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 453 /* 454 * We already refuse to boot CPUs that don't support our configured 455 * page size, so we can only detect mismatches for a page size other 456 * than the one we're currently using. Unfortunately, SoCs like this 457 * exist in the wild so, even though we don't like it, we'll have to go 458 * along with it and treat them as non-strict. 459 */ 460 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 461 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 463 464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 465 /* Linux shouldn't care about secure memory */ 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 469 /* 470 * Differing PARange is fine as long as all peripherals and memory are mapped 471 * within the minimum PARange of all CPUs 472 */ 473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 474 ARM64_FTR_END, 475 }; 476 477 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 492 ARM64_FTR_END, 493 }; 494 495 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 511 ARM64_FTR_END, 512 }; 513 514 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 515 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 516 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 520 ARM64_FTR_END, 521 }; 522 523 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 524 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 526 ARM64_FTR_END, 527 }; 528 529 static const struct arm64_ftr_bits ftr_ctr[] = { 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 535 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 536 /* 537 * Linux can handle differing I-cache policies. Userspace JITs will 538 * make use of *minLine. 539 * If we have differing I-cache policies, report it as the weakest - VIPT. 540 */ 541 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 542 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 543 ARM64_FTR_END, 544 }; 545 546 static struct arm64_ftr_override __ro_after_init no_override = { }; 547 548 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 549 .name = "SYS_CTR_EL0", 550 .ftr_bits = ftr_ctr, 551 .override = &no_override, 552 }; 553 554 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 555 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 560 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 562 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 563 ARM64_FTR_END, 564 }; 565 566 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 567 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 572 /* 573 * We can instantiate multiple PMU instances with different levels 574 * of support. 575 */ 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 577 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 578 ARM64_FTR_END, 579 }; 580 581 static const struct arm64_ftr_bits ftr_mvfr0[] = { 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 590 ARM64_FTR_END, 591 }; 592 593 static const struct arm64_ftr_bits ftr_mvfr1[] = { 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 602 ARM64_FTR_END, 603 }; 604 605 static const struct arm64_ftr_bits ftr_mvfr2[] = { 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 608 ARM64_FTR_END, 609 }; 610 611 static const struct arm64_ftr_bits ftr_dczid[] = { 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 613 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 614 ARM64_FTR_END, 615 }; 616 617 static const struct arm64_ftr_bits ftr_gmid[] = { 618 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 619 ARM64_FTR_END, 620 }; 621 622 static const struct arm64_ftr_bits ftr_id_isar0[] = { 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 630 ARM64_FTR_END, 631 }; 632 633 static const struct arm64_ftr_bits ftr_id_isar5[] = { 634 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 639 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 640 ARM64_FTR_END, 641 }; 642 643 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 651 652 /* 653 * SpecSEI = 1 indicates that the PE might generate an SError on an 654 * external abort on speculative read. It is safe to assume that an 655 * SError might be generated than it will not be. Hence it has been 656 * classified as FTR_HIGHER_SAFE. 657 */ 658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 659 ARM64_FTR_END, 660 }; 661 662 static const struct arm64_ftr_bits ftr_id_isar4[] = { 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 670 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 671 ARM64_FTR_END, 672 }; 673 674 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 676 ARM64_FTR_END, 677 }; 678 679 static const struct arm64_ftr_bits ftr_id_isar6[] = { 680 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 687 ARM64_FTR_END, 688 }; 689 690 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 696 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 697 ARM64_FTR_END, 698 }; 699 700 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 709 ARM64_FTR_END, 710 }; 711 712 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 713 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 714 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 715 ARM64_FTR_END, 716 }; 717 718 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 719 /* [31:28] TraceFilt */ 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 726 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 727 ARM64_FTR_END, 728 }; 729 730 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 731 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 732 ARM64_FTR_END, 733 }; 734 735 static const struct arm64_ftr_bits ftr_mpamidr[] = { 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 740 ARM64_FTR_END, 741 }; 742 743 /* 744 * Common ftr bits for a 32bit register with all hidden, strict 745 * attributes, with 4bit feature fields and a default safe value of 746 * 0. Covers the following 32bit registers: 747 * id_isar[1-3], id_mmfr[1-3] 748 */ 749 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 750 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 756 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 757 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 758 ARM64_FTR_END, 759 }; 760 761 /* Table for a single 32bit feature value */ 762 static const struct arm64_ftr_bits ftr_single32[] = { 763 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 764 ARM64_FTR_END, 765 }; 766 767 static const struct arm64_ftr_bits ftr_raz[] = { 768 ARM64_FTR_END, 769 }; 770 771 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 772 .sys_id = id, \ 773 .reg = &(struct arm64_ftr_reg){ \ 774 .name = id_str, \ 775 .override = (ovr), \ 776 .ftr_bits = &((table)[0]), \ 777 }} 778 779 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 780 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 781 782 #define ARM64_FTR_REG(id, table) \ 783 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 784 785 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 786 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 787 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 788 struct arm64_ftr_override __read_mostly id_aa64mmfr4_override; 789 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 790 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 791 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 792 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 793 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 794 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 795 796 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 797 798 static const struct __ftr_reg_entry { 799 u32 sys_id; 800 struct arm64_ftr_reg *reg; 801 } arm64_ftr_regs[] = { 802 803 /* Op1 = 0, CRn = 0, CRm = 1 */ 804 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 805 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 806 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 807 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 808 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 809 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 810 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 811 812 /* Op1 = 0, CRn = 0, CRm = 2 */ 813 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 814 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 815 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 816 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 817 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 818 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 819 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 820 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 821 822 /* Op1 = 0, CRn = 0, CRm = 3 */ 823 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 824 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 825 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 826 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 827 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 828 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 829 830 /* Op1 = 0, CRn = 0, CRm = 4 */ 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 832 &id_aa64pfr0_override), 833 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 834 &id_aa64pfr1_override), 835 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 836 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 837 &id_aa64zfr0_override), 838 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 839 &id_aa64smfr0_override), 840 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 841 842 /* Op1 = 0, CRn = 0, CRm = 5 */ 843 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 844 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 845 846 /* Op1 = 0, CRn = 0, CRm = 6 */ 847 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 848 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 849 &id_aa64isar1_override), 850 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 851 &id_aa64isar2_override), 852 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 853 854 /* Op1 = 0, CRn = 0, CRm = 7 */ 855 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 856 &id_aa64mmfr0_override), 857 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 858 &id_aa64mmfr1_override), 859 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 860 &id_aa64mmfr2_override), 861 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 862 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4, 863 &id_aa64mmfr4_override), 864 865 /* Op1 = 0, CRn = 10, CRm = 4 */ 866 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 867 868 /* Op1 = 1, CRn = 0, CRm = 0 */ 869 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 870 871 /* Op1 = 3, CRn = 0, CRm = 0 */ 872 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 873 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 874 875 /* Op1 = 3, CRn = 14, CRm = 0 */ 876 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 877 }; 878 879 static int search_cmp_ftr_reg(const void *id, const void *regp) 880 { 881 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 882 } 883 884 /* 885 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 886 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 887 * ascending order of sys_id, we use binary search to find a matching 888 * entry. 889 * 890 * returns - Upon success, matching ftr_reg entry for id. 891 * - NULL on failure. It is upto the caller to decide 892 * the impact of a failure. 893 */ 894 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 895 { 896 const struct __ftr_reg_entry *ret; 897 898 ret = bsearch((const void *)(unsigned long)sys_id, 899 arm64_ftr_regs, 900 ARRAY_SIZE(arm64_ftr_regs), 901 sizeof(arm64_ftr_regs[0]), 902 search_cmp_ftr_reg); 903 if (ret) 904 return ret->reg; 905 return NULL; 906 } 907 908 /* 909 * get_arm64_ftr_reg - Looks up a feature register entry using 910 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 911 * 912 * returns - Upon success, matching ftr_reg entry for id. 913 * - NULL on failure but with an WARN_ON(). 914 */ 915 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 916 { 917 struct arm64_ftr_reg *reg; 918 919 reg = get_arm64_ftr_reg_nowarn(sys_id); 920 921 /* 922 * Requesting a non-existent register search is an error. Warn 923 * and let the caller handle it. 924 */ 925 WARN_ON(!reg); 926 return reg; 927 } 928 929 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 930 s64 ftr_val) 931 { 932 u64 mask = arm64_ftr_mask(ftrp); 933 934 reg &= ~mask; 935 reg |= (ftr_val << ftrp->shift) & mask; 936 return reg; 937 } 938 939 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 940 s64 cur) 941 { 942 s64 ret = 0; 943 944 switch (ftrp->type) { 945 case FTR_EXACT: 946 ret = ftrp->safe_val; 947 break; 948 case FTR_LOWER_SAFE: 949 ret = min(new, cur); 950 break; 951 case FTR_HIGHER_OR_ZERO_SAFE: 952 if (!cur || !new) 953 break; 954 fallthrough; 955 case FTR_HIGHER_SAFE: 956 ret = max(new, cur); 957 break; 958 default: 959 BUG(); 960 } 961 962 return ret; 963 } 964 965 static void __init sort_ftr_regs(void) 966 { 967 unsigned int i; 968 969 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 970 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 971 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 972 unsigned int j = 0; 973 974 /* 975 * Features here must be sorted in descending order with respect 976 * to their shift values and should not overlap with each other. 977 */ 978 for (; ftr_bits->width != 0; ftr_bits++, j++) { 979 unsigned int width = ftr_reg->ftr_bits[j].width; 980 unsigned int shift = ftr_reg->ftr_bits[j].shift; 981 unsigned int prev_shift; 982 983 WARN((shift + width) > 64, 984 "%s has invalid feature at shift %d\n", 985 ftr_reg->name, shift); 986 987 /* 988 * Skip the first feature. There is nothing to 989 * compare against for now. 990 */ 991 if (j == 0) 992 continue; 993 994 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 995 WARN((shift + width) > prev_shift, 996 "%s has feature overlap at shift %d\n", 997 ftr_reg->name, shift); 998 } 999 1000 /* 1001 * Skip the first register. There is nothing to 1002 * compare against for now. 1003 */ 1004 if (i == 0) 1005 continue; 1006 /* 1007 * Registers here must be sorted in ascending order with respect 1008 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1009 * to work correctly. 1010 */ 1011 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1012 } 1013 } 1014 1015 /* 1016 * Initialise the CPU feature register from Boot CPU values. 1017 * Also initialises the strict_mask for the register. 1018 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1019 * RES0 for the system-wide value, and must strictly match. 1020 */ 1021 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1022 { 1023 u64 val = 0; 1024 u64 strict_mask = ~0x0ULL; 1025 u64 user_mask = 0; 1026 u64 valid_mask = 0; 1027 1028 const struct arm64_ftr_bits *ftrp; 1029 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1030 1031 if (!reg) 1032 return; 1033 1034 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1035 u64 ftr_mask = arm64_ftr_mask(ftrp); 1036 s64 ftr_new = arm64_ftr_value(ftrp, new); 1037 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1038 1039 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1040 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1041 char *str = NULL; 1042 1043 if (ftr_ovr != tmp) { 1044 /* Unsafe, remove the override */ 1045 reg->override->mask &= ~ftr_mask; 1046 reg->override->val &= ~ftr_mask; 1047 tmp = ftr_ovr; 1048 str = "ignoring override"; 1049 } else if (ftr_new != tmp) { 1050 /* Override was valid */ 1051 ftr_new = tmp; 1052 str = "forced"; 1053 } else { 1054 /* Override was the safe value */ 1055 str = "already set"; 1056 } 1057 1058 pr_warn("%s[%d:%d]: %s to %llx\n", 1059 reg->name, 1060 ftrp->shift + ftrp->width - 1, 1061 ftrp->shift, str, 1062 tmp & (BIT(ftrp->width) - 1)); 1063 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1064 reg->override->val &= ~ftr_mask; 1065 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1066 reg->name, 1067 ftrp->shift + ftrp->width - 1, 1068 ftrp->shift); 1069 } 1070 1071 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1072 1073 valid_mask |= ftr_mask; 1074 if (!ftrp->strict) 1075 strict_mask &= ~ftr_mask; 1076 if (ftrp->visible) 1077 user_mask |= ftr_mask; 1078 else 1079 reg->user_val = arm64_ftr_set_value(ftrp, 1080 reg->user_val, 1081 ftrp->safe_val); 1082 } 1083 1084 val &= valid_mask; 1085 1086 reg->sys_val = val; 1087 reg->strict_mask = strict_mask; 1088 reg->user_mask = user_mask; 1089 } 1090 1091 extern const struct arm64_cpu_capabilities arm64_errata[]; 1092 static const struct arm64_cpu_capabilities arm64_features[]; 1093 1094 static void __init 1095 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1096 { 1097 for (; caps->matches; caps++) { 1098 if (WARN(caps->capability >= ARM64_NCAPS, 1099 "Invalid capability %d\n", caps->capability)) 1100 continue; 1101 if (WARN(cpucap_ptrs[caps->capability], 1102 "Duplicate entry for capability %d\n", 1103 caps->capability)) 1104 continue; 1105 cpucap_ptrs[caps->capability] = caps; 1106 } 1107 } 1108 1109 static void __init init_cpucap_indirect_list(void) 1110 { 1111 init_cpucap_indirect_list_from_array(arm64_features); 1112 init_cpucap_indirect_list_from_array(arm64_errata); 1113 } 1114 1115 static void __init setup_boot_cpu_capabilities(void); 1116 1117 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1118 { 1119 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1120 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1121 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1122 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1123 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1124 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1125 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1126 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1127 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1128 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1129 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1130 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1131 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1132 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1133 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1134 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1135 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1136 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1137 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1138 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1139 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1140 } 1141 1142 #ifdef CONFIG_ARM64_PSEUDO_NMI 1143 static bool enable_pseudo_nmi; 1144 1145 static int __init early_enable_pseudo_nmi(char *p) 1146 { 1147 return kstrtobool(p, &enable_pseudo_nmi); 1148 } 1149 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1150 1151 static __init void detect_system_supports_pseudo_nmi(void) 1152 { 1153 struct device_node *np; 1154 1155 if (!enable_pseudo_nmi) 1156 return; 1157 1158 /* 1159 * Detect broken MediaTek firmware that doesn't properly save and 1160 * restore GIC priorities. 1161 */ 1162 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1163 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1164 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1165 enable_pseudo_nmi = false; 1166 } 1167 of_node_put(np); 1168 } 1169 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1170 static inline void detect_system_supports_pseudo_nmi(void) { } 1171 #endif 1172 1173 static bool detect_ftr_has_mpam(void) 1174 { 1175 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1176 u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1177 1178 return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); 1179 } 1180 1181 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1182 { 1183 /* Before we start using the tables, make sure it is sorted */ 1184 sort_ftr_regs(); 1185 1186 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1187 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1188 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1189 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1190 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1191 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1192 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1193 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1194 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1195 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1196 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1197 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1198 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1199 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1200 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1201 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1202 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1203 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1204 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1205 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1206 1207 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1208 init_32bit_cpu_features(&info->aarch32); 1209 1210 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1211 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1212 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1213 1214 vec_init_vq_map(ARM64_VEC_SVE); 1215 1216 cpacr_restore(cpacr); 1217 } 1218 1219 if (IS_ENABLED(CONFIG_ARM64_SME) && 1220 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1221 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1222 1223 vec_init_vq_map(ARM64_VEC_SME); 1224 1225 cpacr_restore(cpacr); 1226 } 1227 1228 if (detect_ftr_has_mpam()) { 1229 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1230 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1231 } 1232 1233 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1234 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1235 } 1236 1237 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1238 { 1239 const struct arm64_ftr_bits *ftrp; 1240 1241 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1242 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1243 s64 ftr_new = arm64_ftr_value(ftrp, new); 1244 1245 if (ftr_cur == ftr_new) 1246 continue; 1247 /* Find a safe value */ 1248 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1249 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1250 } 1251 1252 } 1253 1254 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1255 { 1256 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1257 1258 if (!regp) 1259 return 0; 1260 1261 update_cpu_ftr_reg(regp, val); 1262 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1263 return 0; 1264 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1265 regp->name, boot, cpu, val); 1266 return 1; 1267 } 1268 1269 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1270 { 1271 const struct arm64_ftr_bits *ftrp; 1272 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1273 1274 if (!regp) 1275 return; 1276 1277 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1278 if (ftrp->shift == field) { 1279 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1280 break; 1281 } 1282 } 1283 1284 /* Bogus field? */ 1285 WARN_ON(!ftrp->width); 1286 } 1287 1288 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1289 struct cpuinfo_arm64 *boot) 1290 { 1291 static bool boot_cpu_32bit_regs_overridden = false; 1292 1293 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1294 return; 1295 1296 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1297 return; 1298 1299 boot->aarch32 = info->aarch32; 1300 init_32bit_cpu_features(&boot->aarch32); 1301 boot_cpu_32bit_regs_overridden = true; 1302 } 1303 1304 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1305 struct cpuinfo_32bit *boot) 1306 { 1307 int taint = 0; 1308 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1309 1310 /* 1311 * If we don't have AArch32 at EL1, then relax the strictness of 1312 * EL1-dependent register fields to avoid spurious sanity check fails. 1313 */ 1314 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1315 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1316 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1317 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1318 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1319 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1320 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1321 } 1322 1323 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1324 info->reg_id_dfr0, boot->reg_id_dfr0); 1325 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1326 info->reg_id_dfr1, boot->reg_id_dfr1); 1327 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1328 info->reg_id_isar0, boot->reg_id_isar0); 1329 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1330 info->reg_id_isar1, boot->reg_id_isar1); 1331 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1332 info->reg_id_isar2, boot->reg_id_isar2); 1333 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1334 info->reg_id_isar3, boot->reg_id_isar3); 1335 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1336 info->reg_id_isar4, boot->reg_id_isar4); 1337 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1338 info->reg_id_isar5, boot->reg_id_isar5); 1339 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1340 info->reg_id_isar6, boot->reg_id_isar6); 1341 1342 /* 1343 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1344 * ACTLR formats could differ across CPUs and therefore would have to 1345 * be trapped for virtualization anyway. 1346 */ 1347 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1348 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1349 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1350 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1351 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1352 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1353 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1354 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1355 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1356 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1357 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1358 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1359 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1360 info->reg_id_pfr0, boot->reg_id_pfr0); 1361 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1362 info->reg_id_pfr1, boot->reg_id_pfr1); 1363 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1364 info->reg_id_pfr2, boot->reg_id_pfr2); 1365 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1366 info->reg_mvfr0, boot->reg_mvfr0); 1367 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1368 info->reg_mvfr1, boot->reg_mvfr1); 1369 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1370 info->reg_mvfr2, boot->reg_mvfr2); 1371 1372 return taint; 1373 } 1374 1375 /* 1376 * Update system wide CPU feature registers with the values from a 1377 * non-boot CPU. Also performs SANITY checks to make sure that there 1378 * aren't any insane variations from that of the boot CPU. 1379 */ 1380 void update_cpu_features(int cpu, 1381 struct cpuinfo_arm64 *info, 1382 struct cpuinfo_arm64 *boot) 1383 { 1384 int taint = 0; 1385 1386 /* 1387 * The kernel can handle differing I-cache policies, but otherwise 1388 * caches should look identical. Userspace JITs will make use of 1389 * *minLine. 1390 */ 1391 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1392 info->reg_ctr, boot->reg_ctr); 1393 1394 /* 1395 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1396 * could result in too much or too little memory being zeroed if a 1397 * process is preempted and migrated between CPUs. 1398 */ 1399 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1400 info->reg_dczid, boot->reg_dczid); 1401 1402 /* If different, timekeeping will be broken (especially with KVM) */ 1403 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1404 info->reg_cntfrq, boot->reg_cntfrq); 1405 1406 /* 1407 * The kernel uses self-hosted debug features and expects CPUs to 1408 * support identical debug features. We presently need CTX_CMPs, WRPs, 1409 * and BRPs to be identical. 1410 * ID_AA64DFR1 is currently RES0. 1411 */ 1412 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1413 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1414 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1415 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1416 /* 1417 * Even in big.LITTLE, processors should be identical instruction-set 1418 * wise. 1419 */ 1420 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1421 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1422 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1423 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1424 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1425 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1426 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1427 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1428 1429 /* 1430 * Differing PARange support is fine as long as all peripherals and 1431 * memory are mapped within the minimum PARange of all CPUs. 1432 * Linux should not care about secure memory. 1433 */ 1434 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1435 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1436 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1437 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1438 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1439 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1440 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1441 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1442 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1443 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1444 1445 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1446 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1447 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1448 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1449 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1450 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1451 1452 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1453 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1454 1455 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1456 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1457 1458 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1459 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1460 1461 /* Probe vector lengths */ 1462 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1463 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1464 if (!system_capabilities_finalized()) { 1465 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1466 1467 vec_update_vq_map(ARM64_VEC_SVE); 1468 1469 cpacr_restore(cpacr); 1470 } 1471 } 1472 1473 if (IS_ENABLED(CONFIG_ARM64_SME) && 1474 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1475 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1476 1477 /* Probe vector lengths */ 1478 if (!system_capabilities_finalized()) 1479 vec_update_vq_map(ARM64_VEC_SME); 1480 1481 cpacr_restore(cpacr); 1482 } 1483 1484 if (detect_ftr_has_mpam()) { 1485 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1486 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1487 info->reg_mpamidr, boot->reg_mpamidr); 1488 } 1489 1490 /* 1491 * The kernel uses the LDGM/STGM instructions and the number of tags 1492 * they read/write depends on the GMID_EL1.BS field. Check that the 1493 * value is the same on all CPUs. 1494 */ 1495 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1496 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1497 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1498 info->reg_gmid, boot->reg_gmid); 1499 } 1500 1501 /* 1502 * If we don't have AArch32 at all then skip the checks entirely 1503 * as the register values may be UNKNOWN and we're not going to be 1504 * using them for anything. 1505 * 1506 * This relies on a sanitised view of the AArch64 ID registers 1507 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1508 */ 1509 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1510 lazy_init_32bit_cpu_features(info, boot); 1511 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1512 &boot->aarch32); 1513 } 1514 1515 /* 1516 * Mismatched CPU features are a recipe for disaster. Don't even 1517 * pretend to support them. 1518 */ 1519 if (taint) { 1520 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1521 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1522 } 1523 } 1524 1525 u64 read_sanitised_ftr_reg(u32 id) 1526 { 1527 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1528 1529 if (!regp) 1530 return 0; 1531 return regp->sys_val; 1532 } 1533 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1534 1535 #define read_sysreg_case(r) \ 1536 case r: val = read_sysreg_s(r); break; 1537 1538 /* 1539 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1540 * Read the system register on the current CPU 1541 */ 1542 u64 __read_sysreg_by_encoding(u32 sys_id) 1543 { 1544 struct arm64_ftr_reg *regp; 1545 u64 val; 1546 1547 switch (sys_id) { 1548 read_sysreg_case(SYS_ID_PFR0_EL1); 1549 read_sysreg_case(SYS_ID_PFR1_EL1); 1550 read_sysreg_case(SYS_ID_PFR2_EL1); 1551 read_sysreg_case(SYS_ID_DFR0_EL1); 1552 read_sysreg_case(SYS_ID_DFR1_EL1); 1553 read_sysreg_case(SYS_ID_MMFR0_EL1); 1554 read_sysreg_case(SYS_ID_MMFR1_EL1); 1555 read_sysreg_case(SYS_ID_MMFR2_EL1); 1556 read_sysreg_case(SYS_ID_MMFR3_EL1); 1557 read_sysreg_case(SYS_ID_MMFR4_EL1); 1558 read_sysreg_case(SYS_ID_MMFR5_EL1); 1559 read_sysreg_case(SYS_ID_ISAR0_EL1); 1560 read_sysreg_case(SYS_ID_ISAR1_EL1); 1561 read_sysreg_case(SYS_ID_ISAR2_EL1); 1562 read_sysreg_case(SYS_ID_ISAR3_EL1); 1563 read_sysreg_case(SYS_ID_ISAR4_EL1); 1564 read_sysreg_case(SYS_ID_ISAR5_EL1); 1565 read_sysreg_case(SYS_ID_ISAR6_EL1); 1566 read_sysreg_case(SYS_MVFR0_EL1); 1567 read_sysreg_case(SYS_MVFR1_EL1); 1568 read_sysreg_case(SYS_MVFR2_EL1); 1569 1570 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1571 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1572 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1573 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1574 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1575 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1576 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1577 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1578 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1579 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1580 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1581 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1582 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1583 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1584 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1585 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1586 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1587 1588 read_sysreg_case(SYS_CNTFRQ_EL0); 1589 read_sysreg_case(SYS_CTR_EL0); 1590 read_sysreg_case(SYS_DCZID_EL0); 1591 1592 default: 1593 BUG(); 1594 return 0; 1595 } 1596 1597 regp = get_arm64_ftr_reg(sys_id); 1598 if (regp) { 1599 val &= ~regp->override->mask; 1600 val |= (regp->override->val & regp->override->mask); 1601 } 1602 1603 return val; 1604 } 1605 1606 #include <linux/irqchip/arm-gic-v3.h> 1607 1608 static bool 1609 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1610 { 1611 return true; 1612 } 1613 1614 static bool 1615 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1616 { 1617 int val, min, max; 1618 u64 tmp; 1619 1620 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1621 entry->field_width, 1622 entry->sign); 1623 1624 tmp = entry->min_field_value; 1625 tmp <<= entry->field_pos; 1626 1627 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1628 entry->field_width, 1629 entry->sign); 1630 1631 tmp = entry->max_field_value; 1632 tmp <<= entry->field_pos; 1633 1634 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1635 entry->field_width, 1636 entry->sign); 1637 1638 return val >= min && val <= max; 1639 } 1640 1641 static u64 1642 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1643 { 1644 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1645 if (scope == SCOPE_SYSTEM) 1646 return read_sanitised_ftr_reg(entry->sys_reg); 1647 else 1648 return __read_sysreg_by_encoding(entry->sys_reg); 1649 } 1650 1651 static bool 1652 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1653 { 1654 int mask; 1655 struct arm64_ftr_reg *regp; 1656 u64 val = read_scoped_sysreg(entry, scope); 1657 1658 regp = get_arm64_ftr_reg(entry->sys_reg); 1659 if (!regp) 1660 return false; 1661 1662 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1663 entry->field_pos, 1664 entry->field_width); 1665 if (!mask) 1666 return false; 1667 1668 return feature_matches(val, entry); 1669 } 1670 1671 static bool 1672 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1673 { 1674 u64 val = read_scoped_sysreg(entry, scope); 1675 return feature_matches(val, entry); 1676 } 1677 1678 const struct cpumask *system_32bit_el0_cpumask(void) 1679 { 1680 if (!system_supports_32bit_el0()) 1681 return cpu_none_mask; 1682 1683 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1684 return cpu_32bit_el0_mask; 1685 1686 return cpu_possible_mask; 1687 } 1688 1689 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1690 { 1691 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1692 } 1693 1694 static int __init parse_32bit_el0_param(char *str) 1695 { 1696 allow_mismatched_32bit_el0 = true; 1697 return 0; 1698 } 1699 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1700 1701 static ssize_t aarch32_el0_show(struct device *dev, 1702 struct device_attribute *attr, char *buf) 1703 { 1704 const struct cpumask *mask = system_32bit_el0_cpumask(); 1705 1706 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1707 } 1708 static const DEVICE_ATTR_RO(aarch32_el0); 1709 1710 static int __init aarch32_el0_sysfs_init(void) 1711 { 1712 struct device *dev_root; 1713 int ret = 0; 1714 1715 if (!allow_mismatched_32bit_el0) 1716 return 0; 1717 1718 dev_root = bus_get_dev_root(&cpu_subsys); 1719 if (dev_root) { 1720 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1721 put_device(dev_root); 1722 } 1723 return ret; 1724 } 1725 device_initcall(aarch32_el0_sysfs_init); 1726 1727 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1728 { 1729 if (!has_cpuid_feature(entry, scope)) 1730 return allow_mismatched_32bit_el0; 1731 1732 if (scope == SCOPE_SYSTEM) 1733 pr_info("detected: 32-bit EL0 Support\n"); 1734 1735 return true; 1736 } 1737 1738 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1739 { 1740 bool has_sre; 1741 1742 if (!has_cpuid_feature(entry, scope)) 1743 return false; 1744 1745 has_sre = gic_enable_sre(); 1746 if (!has_sre) 1747 pr_warn_once("%s present but disabled by higher exception level\n", 1748 entry->desc); 1749 1750 return has_sre; 1751 } 1752 1753 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1754 int scope) 1755 { 1756 u64 ctr; 1757 1758 if (scope == SCOPE_SYSTEM) 1759 ctr = arm64_ftr_reg_ctrel0.sys_val; 1760 else 1761 ctr = read_cpuid_effective_cachetype(); 1762 1763 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1764 } 1765 1766 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1767 { 1768 /* 1769 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1770 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1771 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1772 * value. 1773 */ 1774 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1775 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1776 } 1777 1778 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1779 int scope) 1780 { 1781 u64 ctr; 1782 1783 if (scope == SCOPE_SYSTEM) 1784 ctr = arm64_ftr_reg_ctrel0.sys_val; 1785 else 1786 ctr = read_cpuid_cachetype(); 1787 1788 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1789 } 1790 1791 static bool __maybe_unused 1792 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1793 { 1794 /* 1795 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1796 * may share TLB entries with a CPU stuck in the crashed 1797 * kernel. 1798 */ 1799 if (is_kdump_kernel()) 1800 return false; 1801 1802 if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) 1803 return false; 1804 1805 return has_cpuid_feature(entry, scope); 1806 } 1807 1808 static bool __meltdown_safe = true; 1809 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1810 1811 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1812 int scope) 1813 { 1814 /* List of CPUs that are not vulnerable and don't need KPTI */ 1815 static const struct midr_range kpti_safe_list[] = { 1816 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1817 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1818 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1819 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1820 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1821 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1822 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1823 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1824 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1825 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1826 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1827 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1828 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1829 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1830 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1831 { /* sentinel */ } 1832 }; 1833 char const *str = "kpti command line option"; 1834 bool meltdown_safe; 1835 1836 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1837 1838 /* Defer to CPU feature registers */ 1839 if (has_cpuid_feature(entry, scope)) 1840 meltdown_safe = true; 1841 1842 if (!meltdown_safe) 1843 __meltdown_safe = false; 1844 1845 /* 1846 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1847 * ThunderX leads to apparent I-cache corruption of kernel text, which 1848 * ends as well as you might imagine. Don't even try. We cannot rely 1849 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1850 * because cpucap detection order may change. However, since we know 1851 * affected CPUs are always in a homogeneous configuration, it is 1852 * safe to rely on this_cpu_has_cap() here. 1853 */ 1854 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1855 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1856 __kpti_forced = -1; 1857 } 1858 1859 /* Useful for KASLR robustness */ 1860 if (kaslr_enabled() && kaslr_requires_kpti()) { 1861 if (!__kpti_forced) { 1862 str = "KASLR"; 1863 __kpti_forced = 1; 1864 } 1865 } 1866 1867 if (cpu_mitigations_off() && !__kpti_forced) { 1868 str = "mitigations=off"; 1869 __kpti_forced = -1; 1870 } 1871 1872 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1873 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1874 return false; 1875 } 1876 1877 /* Forced? */ 1878 if (__kpti_forced) { 1879 pr_info_once("kernel page table isolation forced %s by %s\n", 1880 __kpti_forced > 0 ? "ON" : "OFF", str); 1881 return __kpti_forced > 0; 1882 } 1883 1884 return !meltdown_safe; 1885 } 1886 1887 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1888 { 1889 /* 1890 * Although the Apple M2 family appears to support NV1, the 1891 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1892 * that it doesn't support NV1 at all. 1893 */ 1894 static const struct midr_range nv1_ni_list[] = { 1895 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1896 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1897 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1898 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1899 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1900 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1901 {} 1902 }; 1903 1904 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1905 !(has_cpuid_feature(entry, scope) || 1906 is_midr_in_range_list(nv1_ni_list))); 1907 } 1908 1909 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1910 static bool has_lpa2_at_stage1(u64 mmfr0) 1911 { 1912 unsigned int tgran; 1913 1914 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1915 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1916 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1917 } 1918 1919 static bool has_lpa2_at_stage2(u64 mmfr0) 1920 { 1921 unsigned int tgran; 1922 1923 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1924 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1925 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1926 } 1927 1928 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1929 { 1930 u64 mmfr0; 1931 1932 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1933 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1934 } 1935 #else 1936 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1937 { 1938 return false; 1939 } 1940 #endif 1941 1942 #ifdef CONFIG_HW_PERF_EVENTS 1943 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1944 { 1945 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1946 unsigned int pmuver; 1947 1948 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1949 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1950 1951 return pmuv3_implemented(pmuver); 1952 } 1953 #endif 1954 1955 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1956 { 1957 if (__this_cpu_read(this_cpu_vector) == vectors) { 1958 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1959 1960 __this_cpu_write(this_cpu_vector, v); 1961 } 1962 1963 } 1964 1965 static int __init parse_kpti(char *str) 1966 { 1967 bool enabled; 1968 int ret = kstrtobool(str, &enabled); 1969 1970 if (ret) 1971 return ret; 1972 1973 __kpti_forced = enabled ? 1 : -1; 1974 return 0; 1975 } 1976 early_param("kpti", parse_kpti); 1977 1978 #ifdef CONFIG_ARM64_HW_AFDBM 1979 static struct cpumask dbm_cpus __read_mostly; 1980 1981 static inline void __cpu_enable_hw_dbm(void) 1982 { 1983 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1984 1985 write_sysreg(tcr, tcr_el1); 1986 isb(); 1987 local_flush_tlb_all(); 1988 } 1989 1990 static bool cpu_has_broken_dbm(void) 1991 { 1992 /* List of CPUs which have broken DBM support. */ 1993 static const struct midr_range cpus[] = { 1994 #ifdef CONFIG_ARM64_ERRATUM_1024718 1995 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1996 /* Kryo4xx Silver (rdpe => r1p0) */ 1997 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1998 #endif 1999 #ifdef CONFIG_ARM64_ERRATUM_2051678 2000 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 2001 #endif 2002 {}, 2003 }; 2004 2005 return is_midr_in_range_list(cpus); 2006 } 2007 2008 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2009 { 2010 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2011 !cpu_has_broken_dbm(); 2012 } 2013 2014 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2015 { 2016 if (cpu_can_use_dbm(cap)) { 2017 __cpu_enable_hw_dbm(); 2018 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2019 } 2020 } 2021 2022 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2023 int __unused) 2024 { 2025 /* 2026 * DBM is a non-conflicting feature. i.e, the kernel can safely 2027 * run a mix of CPUs with and without the feature. So, we 2028 * unconditionally enable the capability to allow any late CPU 2029 * to use the feature. We only enable the control bits on the 2030 * CPU, if it is supported. 2031 */ 2032 2033 return true; 2034 } 2035 2036 #endif 2037 2038 #ifdef CONFIG_ARM64_AMU_EXTN 2039 2040 /* 2041 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2042 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2043 * information regarding all the events that it supports. When a CPU bit is 2044 * set in the cpumask, the user of this feature can only rely on the presence 2045 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2046 * counters are enabled or access to these counters is enabled by code 2047 * executed at higher exception levels (firmware). 2048 */ 2049 static struct cpumask amu_cpus __read_mostly; 2050 2051 bool cpu_has_amu_feat(int cpu) 2052 { 2053 return cpumask_test_cpu(cpu, &amu_cpus); 2054 } 2055 2056 int get_cpu_with_amu_feat(void) 2057 { 2058 return cpumask_any(&amu_cpus); 2059 } 2060 2061 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2062 { 2063 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2064 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2065 2066 /* 0 reference values signal broken/disabled counters */ 2067 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2068 update_freq_counters_refs(); 2069 } 2070 } 2071 2072 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2073 int __unused) 2074 { 2075 /* 2076 * The AMU extension is a non-conflicting feature: the kernel can 2077 * safely run a mix of CPUs with and without support for the 2078 * activity monitors extension. Therefore, unconditionally enable 2079 * the capability to allow any late CPU to use the feature. 2080 * 2081 * With this feature unconditionally enabled, the cpu_enable 2082 * function will be called for all CPUs that match the criteria, 2083 * including secondary and hotplugged, marking this feature as 2084 * present on that respective CPU. The enable function will also 2085 * print a detection message. 2086 */ 2087 2088 return true; 2089 } 2090 #else 2091 int get_cpu_with_amu_feat(void) 2092 { 2093 return nr_cpu_ids; 2094 } 2095 #endif 2096 2097 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2098 { 2099 return is_kernel_in_hyp_mode(); 2100 } 2101 2102 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2103 { 2104 /* 2105 * Copy register values that aren't redirected by hardware. 2106 * 2107 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2108 * this value to tpidr_el2 before we patch the code. Once we've done 2109 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2110 * do anything here. 2111 */ 2112 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2113 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2114 } 2115 2116 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2117 int scope) 2118 { 2119 if (kvm_get_mode() != KVM_MODE_NV) 2120 return false; 2121 2122 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2123 pr_warn("unavailable: %s\n", cap->desc); 2124 return false; 2125 } 2126 2127 return true; 2128 } 2129 2130 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2131 int __unused) 2132 { 2133 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2134 } 2135 2136 bool cpu_supports_bbml3(void) 2137 { 2138 /* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */ 2139 static const struct midr_range supports_bbml3_list[] = { 2140 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2141 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2142 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2143 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2144 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2145 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2146 MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), 2147 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 2148 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 2149 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 2150 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 2151 MIDR_ALL_VERSIONS(MIDR_C1_NANO), 2152 MIDR_ALL_VERSIONS(MIDR_C1_PRO), 2153 /* Erratum 3683289 fixed in r1p1 */ 2154 MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), 2155 MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), 2156 {} 2157 }; 2158 u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); 2159 2160 if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >= ID_AA64MMFR2_EL1_BBM_3) 2161 return true; 2162 2163 return is_midr_in_range_list(supports_bbml3_list); 2164 } 2165 2166 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) 2167 { 2168 return cpu_supports_bbml3(); 2169 } 2170 2171 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2172 { 2173 /* 2174 * We modify PSTATE. This won't work from irq context as the PSTATE 2175 * is discarded once we return from the exception. 2176 */ 2177 WARN_ON_ONCE(in_interrupt()); 2178 2179 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2180 set_pstate_pan(1); 2181 } 2182 2183 #ifdef CONFIG_ARM64_RAS_EXTN 2184 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2185 { 2186 /* Firmware may have left a deferred SError in this register. */ 2187 write_sysreg_s(0, SYS_DISR_EL1); 2188 } 2189 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2190 { 2191 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2192 { 2193 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2194 }, 2195 { 2196 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2197 }, 2198 { 2199 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2200 }, 2201 }; 2202 2203 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2204 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2205 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2206 } 2207 #endif /* CONFIG_ARM64_RAS_EXTN */ 2208 2209 #ifdef CONFIG_ARM64_PTR_AUTH 2210 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2211 { 2212 int boot_val, sec_val; 2213 2214 /* We don't expect to be called with SCOPE_SYSTEM */ 2215 WARN_ON(scope == SCOPE_SYSTEM); 2216 /* 2217 * The ptr-auth feature levels are not intercompatible with lower 2218 * levels. Hence we must match ptr-auth feature level of the secondary 2219 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2220 * from the sanitised register whereas direct register read is done for 2221 * the secondary CPUs. 2222 * The sanitised feature state is guaranteed to match that of the 2223 * boot CPU as a mismatched secondary CPU is parked before it gets 2224 * a chance to update the state, with the capability. 2225 */ 2226 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2227 entry->field_pos, entry->sign); 2228 if (scope & SCOPE_BOOT_CPU) 2229 return boot_val >= entry->min_field_value; 2230 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2231 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2232 entry->field_pos, entry->sign); 2233 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2234 } 2235 2236 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2237 int scope) 2238 { 2239 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2240 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2241 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2242 2243 return apa || apa3 || api; 2244 } 2245 2246 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2247 int __unused) 2248 { 2249 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2250 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2251 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2252 2253 return gpa || gpa3 || gpi; 2254 } 2255 #endif /* CONFIG_ARM64_PTR_AUTH */ 2256 2257 #ifdef CONFIG_ARM64_E0PD 2258 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2259 { 2260 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2261 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2262 } 2263 #endif /* CONFIG_ARM64_E0PD */ 2264 2265 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2266 { 2267 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2268 } 2269 2270 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2271 { 2272 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2273 } 2274 2275 #ifdef CONFIG_ARM64_PSEUDO_NMI 2276 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2277 int scope) 2278 { 2279 /* 2280 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2281 * feature, so will be detected earlier. 2282 */ 2283 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2284 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2285 return false; 2286 2287 return enable_pseudo_nmi; 2288 } 2289 2290 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2291 int scope) 2292 { 2293 /* 2294 * If we're not using priority masking then we won't be poking PMR_EL1, 2295 * and there's no need to relax synchronization of writes to it, and 2296 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2297 * that. 2298 * 2299 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2300 * feature, so will be detected earlier. 2301 */ 2302 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2303 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2304 return false; 2305 2306 /* 2307 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2308 * hint for interrupt distribution, a DSB is not necessary when 2309 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2310 * 2311 * Linux itself doesn't use 1:N distribution, so has no need to 2312 * set PMHE. The only reason to have it set is if EL3 requires it 2313 * (and we can't change it). 2314 */ 2315 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2316 } 2317 #endif 2318 2319 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2320 int scope) 2321 { 2322 static const struct midr_range has_vgic_v3[] = { 2323 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2324 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2325 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2326 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2327 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2328 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2329 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2330 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2331 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2332 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2333 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2334 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2335 {}, 2336 }; 2337 struct arm_smccc_res res = {}; 2338 2339 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2340 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2341 if (!is_hyp_mode_available()) 2342 return false; 2343 2344 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2345 return true; 2346 2347 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2348 !is_midr_in_range_list(has_vgic_v3)) 2349 return false; 2350 2351 /* 2352 * pKVM prevents late onlining of CPUs. This means that whatever 2353 * state the capability is in after deprivilege cannot be affected 2354 * by a new CPU booting -- this is garanteed to be a CPU we have 2355 * already seen, and the cap is therefore unchanged. 2356 */ 2357 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2358 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2359 2360 if (is_kernel_in_hyp_mode()) 2361 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2362 else 2363 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2364 2365 if (res.a0 == HVC_STUB_ERR) 2366 return false; 2367 2368 return res.a1 & ICH_VTR_EL2_TDS; 2369 } 2370 2371 #ifdef CONFIG_ARM64_BTI 2372 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2373 { 2374 /* 2375 * Use of X16/X17 for tail-calls and trampolines that jump to 2376 * function entry points using BR is a requirement for 2377 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2378 * So, be strict and forbid other BRs using other registers to 2379 * jump onto a PACIxSP instruction: 2380 */ 2381 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2382 isb(); 2383 } 2384 #endif /* CONFIG_ARM64_BTI */ 2385 2386 #ifdef CONFIG_ARM64_MTE 2387 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2388 { 2389 static bool cleared_zero_page = false; 2390 2391 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2392 2393 mte_cpu_setup(); 2394 2395 /* 2396 * Clear the tags in the zero page. This needs to be done via the 2397 * linear map which has the Tagged attribute. Since this page is 2398 * always mapped as pte_special(), set_pte_at() will not attempt to 2399 * clear the tags or set PG_mte_tagged. 2400 */ 2401 if (!cleared_zero_page) { 2402 cleared_zero_page = true; 2403 mte_clear_page_tags(lm_alias(empty_zero_page)); 2404 } 2405 2406 kasan_init_hw_tags_cpu(); 2407 } 2408 #endif /* CONFIG_ARM64_MTE */ 2409 2410 static void user_feature_fixup(void) 2411 { 2412 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2413 struct arm64_ftr_reg *regp; 2414 2415 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2416 if (regp) 2417 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2418 } 2419 2420 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2421 struct arm64_ftr_reg *regp; 2422 2423 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2424 if (regp) 2425 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2426 } 2427 } 2428 2429 static void elf_hwcap_fixup(void) 2430 { 2431 #ifdef CONFIG_COMPAT 2432 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2433 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2434 #endif /* CONFIG_COMPAT */ 2435 } 2436 2437 #ifdef CONFIG_KVM 2438 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2439 { 2440 return kvm_get_mode() == KVM_MODE_PROTECTED; 2441 } 2442 #endif /* CONFIG_KVM */ 2443 2444 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2445 { 2446 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2447 } 2448 2449 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2450 { 2451 set_pstate_dit(1); 2452 } 2453 2454 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2455 { 2456 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2457 } 2458 2459 #ifdef CONFIG_ARM64_POE 2460 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2461 { 2462 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2463 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2464 } 2465 #endif 2466 2467 #ifdef CONFIG_ARM64_GCS 2468 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2469 { 2470 /* GCSPR_EL0 is always readable */ 2471 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2472 } 2473 #endif 2474 2475 /* Internal helper functions to match cpu capability type */ 2476 static bool 2477 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2478 { 2479 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2480 } 2481 2482 static bool 2483 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2484 { 2485 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2486 } 2487 2488 static bool 2489 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2490 { 2491 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2492 } 2493 2494 static bool 2495 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2496 { 2497 if (!detect_ftr_has_mpam()) 2498 return false; 2499 2500 /* Check firmware actually enabled MPAM on this cpu. */ 2501 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2502 } 2503 2504 static void 2505 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2506 { 2507 int cpu = smp_processor_id(); 2508 u64 regval = 0; 2509 2510 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2511 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2512 2513 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2514 if (cpus_have_cap(ARM64_SME)) 2515 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2516 isb(); 2517 2518 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2519 write_sysreg_s(regval, SYS_MPAM0_EL1); 2520 } 2521 2522 static bool 2523 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2524 { 2525 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2526 2527 return idr & MPAMIDR_EL1_HAS_HCR; 2528 } 2529 2530 static bool 2531 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2532 { 2533 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2534 return false; 2535 2536 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2537 } 2538 2539 static const struct arm64_cpu_capabilities arm64_features[] = { 2540 { 2541 .capability = ARM64_ALWAYS_BOOT, 2542 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2543 .matches = has_always, 2544 }, 2545 { 2546 .capability = ARM64_ALWAYS_SYSTEM, 2547 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2548 .matches = has_always, 2549 }, 2550 { 2551 .desc = "GICv3 CPU interface", 2552 .capability = ARM64_HAS_GICV3_CPUIF, 2553 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2554 .matches = has_useable_gicv3_cpuif, 2555 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2556 }, 2557 { 2558 .desc = "Enhanced Counter Virtualization", 2559 .capability = ARM64_HAS_ECV, 2560 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2561 .matches = has_cpuid_feature, 2562 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2563 }, 2564 { 2565 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2566 .capability = ARM64_HAS_ECV_CNTPOFF, 2567 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2568 .matches = has_cpuid_feature, 2569 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2570 }, 2571 { 2572 .desc = "Privileged Access Never", 2573 .capability = ARM64_HAS_PAN, 2574 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2575 .matches = has_cpuid_feature, 2576 .cpu_enable = cpu_enable_pan, 2577 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2578 }, 2579 #ifdef CONFIG_ARM64_EPAN 2580 { 2581 .desc = "Enhanced Privileged Access Never", 2582 .capability = ARM64_HAS_EPAN, 2583 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2584 .matches = has_cpuid_feature, 2585 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2586 }, 2587 #endif /* CONFIG_ARM64_EPAN */ 2588 { 2589 .desc = "LSE atomic instructions", 2590 .capability = ARM64_HAS_LSE_ATOMICS, 2591 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2592 .matches = has_cpuid_feature, 2593 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2594 }, 2595 { 2596 .desc = "Virtualization Host Extensions", 2597 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2598 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2599 .matches = runs_at_el2, 2600 .cpu_enable = cpu_copy_el2regs, 2601 }, 2602 { 2603 .desc = "Nested Virtualization Support", 2604 .capability = ARM64_HAS_NESTED_VIRT, 2605 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2606 .matches = has_nested_virt_support, 2607 .match_list = (const struct arm64_cpu_capabilities []){ 2608 { 2609 .matches = has_cpuid_feature, 2610 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2611 }, 2612 { 2613 .matches = has_cpuid_feature, 2614 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2615 }, 2616 { /* Sentinel */ } 2617 }, 2618 }, 2619 { 2620 .desc = "FEAT_NV2p1", 2621 .capability = ARM64_HAS_NV2P1, 2622 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2623 .matches = has_cpuid_feature, 2624 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2P1) 2625 }, 2626 { 2627 .desc = "FEAT_NV3", 2628 .capability = ARM64_HAS_NV3, 2629 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2630 .matches = has_cpuid_feature, 2631 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV3) 2632 }, 2633 { 2634 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2635 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2636 .matches = has_32bit_el0, 2637 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2638 }, 2639 #ifdef CONFIG_KVM 2640 { 2641 .desc = "32-bit EL1 Support", 2642 .capability = ARM64_HAS_32BIT_EL1, 2643 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2644 .matches = has_cpuid_feature, 2645 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2646 }, 2647 { 2648 .desc = "Protected KVM", 2649 .capability = ARM64_KVM_PROTECTED_MODE, 2650 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2651 .matches = is_kvm_protected_mode, 2652 }, 2653 { 2654 .desc = "HCRX_EL2 register", 2655 .capability = ARM64_HAS_HCX, 2656 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2657 .matches = has_cpuid_feature, 2658 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2659 }, 2660 #endif 2661 { 2662 .desc = "Kernel page table isolation (KPTI)", 2663 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2664 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2665 .cpu_enable = cpu_enable_kpti, 2666 .matches = unmap_kernel_at_el0, 2667 /* 2668 * The ID feature fields below are used to indicate that 2669 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2670 * more details. 2671 */ 2672 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2673 }, 2674 { 2675 .capability = ARM64_HAS_FPSIMD, 2676 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2677 .matches = has_cpuid_feature, 2678 .cpu_enable = cpu_enable_fpsimd, 2679 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2680 }, 2681 #ifdef CONFIG_ARM64_PMEM 2682 { 2683 .desc = "Data cache clean to Point of Persistence", 2684 .capability = ARM64_HAS_DCPOP, 2685 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2686 .matches = has_cpuid_feature, 2687 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2688 }, 2689 { 2690 .desc = "Data cache clean to Point of Deep Persistence", 2691 .capability = ARM64_HAS_DCPODP, 2692 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2693 .matches = has_cpuid_feature, 2694 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2695 }, 2696 #endif 2697 #ifdef CONFIG_ARM64_SVE 2698 { 2699 .desc = "Scalable Vector Extension", 2700 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2701 .capability = ARM64_SVE, 2702 .cpu_enable = cpu_enable_sve, 2703 .matches = has_cpuid_feature, 2704 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2705 }, 2706 #endif /* CONFIG_ARM64_SVE */ 2707 #ifdef CONFIG_ARM64_RAS_EXTN 2708 { 2709 .desc = "RAS Extension Support", 2710 .capability = ARM64_HAS_RAS_EXTN, 2711 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2712 .matches = has_cpuid_feature, 2713 .cpu_enable = cpu_clear_disr, 2714 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2715 }, 2716 { 2717 .desc = "RASv1p1 Extension Support", 2718 .capability = ARM64_HAS_RASV1P1_EXTN, 2719 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2720 .matches = has_rasv1p1, 2721 }, 2722 #endif /* CONFIG_ARM64_RAS_EXTN */ 2723 #ifdef CONFIG_ARM64_AMU_EXTN 2724 { 2725 .desc = "Activity Monitors Unit (AMU)", 2726 .capability = ARM64_HAS_AMU_EXTN, 2727 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2728 .matches = has_amu, 2729 .cpu_enable = cpu_amu_enable, 2730 .cpus = &amu_cpus, 2731 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2732 }, 2733 #endif /* CONFIG_ARM64_AMU_EXTN */ 2734 { 2735 .desc = "Data cache clean to the PoU not required for I/D coherence", 2736 .capability = ARM64_HAS_CACHE_IDC, 2737 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2738 .matches = has_cache_idc, 2739 .cpu_enable = cpu_emulate_effective_ctr, 2740 }, 2741 { 2742 .desc = "Instruction cache invalidation not required for I/D coherence", 2743 .capability = ARM64_HAS_CACHE_DIC, 2744 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2745 .matches = has_cache_dic, 2746 }, 2747 { 2748 .desc = "Stage-2 Force Write-Back", 2749 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2750 .capability = ARM64_HAS_STAGE2_FWB, 2751 .matches = has_cpuid_feature, 2752 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2753 }, 2754 { 2755 .desc = "ARMv8.4 Translation Table Level", 2756 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2757 .capability = ARM64_HAS_ARMv8_4_TTL, 2758 .matches = has_cpuid_feature, 2759 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2760 }, 2761 { 2762 .desc = "TLB range maintenance instructions", 2763 .capability = ARM64_HAS_TLB_RANGE, 2764 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2765 .matches = has_cpuid_feature, 2766 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2767 }, 2768 #ifdef CONFIG_ARM64_HW_AFDBM 2769 { 2770 .desc = "Hardware dirty bit management", 2771 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2772 .capability = ARM64_HW_DBM, 2773 .matches = has_hw_dbm, 2774 .cpu_enable = cpu_enable_hw_dbm, 2775 .cpus = &dbm_cpus, 2776 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2777 }, 2778 #endif 2779 #ifdef CONFIG_ARM64_HAFT 2780 { 2781 .desc = "Hardware managed Access Flag for Table Descriptors", 2782 /* 2783 * Contrary to the page/block access flag, the table access flag 2784 * cannot be emulated in software (no access fault will occur). 2785 * Therefore this should be used only if it's supported system 2786 * wide. 2787 */ 2788 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2789 .capability = ARM64_HAFT, 2790 .matches = has_cpuid_feature, 2791 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2792 }, 2793 #endif 2794 { 2795 .desc = "CRC32 instructions", 2796 .capability = ARM64_HAS_CRC32, 2797 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2798 .matches = has_cpuid_feature, 2799 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2800 }, 2801 { 2802 .desc = "Speculative Store Bypassing Safe (SSBS)", 2803 .capability = ARM64_SSBS, 2804 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2805 .matches = has_cpuid_feature, 2806 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2807 }, 2808 #ifdef CONFIG_ARM64_CNP 2809 { 2810 .desc = "Common not Private translations", 2811 .capability = ARM64_HAS_CNP, 2812 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2813 .matches = has_useable_cnp, 2814 .cpu_enable = cpu_enable_cnp, 2815 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2816 }, 2817 #endif 2818 { 2819 .desc = "Speculation barrier (SB)", 2820 .capability = ARM64_HAS_SB, 2821 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2822 .matches = has_cpuid_feature, 2823 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2824 }, 2825 #ifdef CONFIG_ARM64_PTR_AUTH 2826 { 2827 .desc = "Address authentication (architected QARMA5 algorithm)", 2828 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2829 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2830 .matches = has_address_auth_cpucap, 2831 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2832 }, 2833 { 2834 .desc = "Address authentication (architected QARMA3 algorithm)", 2835 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2836 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2837 .matches = has_address_auth_cpucap, 2838 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2839 }, 2840 { 2841 .desc = "Address authentication (IMP DEF algorithm)", 2842 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2843 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2844 .matches = has_address_auth_cpucap, 2845 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2846 }, 2847 { 2848 .capability = ARM64_HAS_ADDRESS_AUTH, 2849 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2850 .matches = has_address_auth_metacap, 2851 }, 2852 { 2853 .desc = "Generic authentication (architected QARMA5 algorithm)", 2854 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2855 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2856 .matches = has_cpuid_feature, 2857 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2858 }, 2859 { 2860 .desc = "Generic authentication (architected QARMA3 algorithm)", 2861 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2862 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2863 .matches = has_cpuid_feature, 2864 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2865 }, 2866 { 2867 .desc = "Generic authentication (IMP DEF algorithm)", 2868 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2869 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2870 .matches = has_cpuid_feature, 2871 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2872 }, 2873 { 2874 .capability = ARM64_HAS_GENERIC_AUTH, 2875 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2876 .matches = has_generic_auth, 2877 }, 2878 #endif /* CONFIG_ARM64_PTR_AUTH */ 2879 #ifdef CONFIG_ARM64_PSEUDO_NMI 2880 { 2881 /* 2882 * Depends on having GICv3 2883 */ 2884 .desc = "IRQ priority masking", 2885 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2886 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2887 .matches = can_use_gic_priorities, 2888 }, 2889 { 2890 /* 2891 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2892 */ 2893 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2894 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2895 .matches = has_gic_prio_relaxed_sync, 2896 }, 2897 #endif 2898 { 2899 /* 2900 * Depends on having GICv3 2901 */ 2902 .desc = "ICV_DIR_EL1 trapping", 2903 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2904 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2905 .matches = can_trap_icv_dir_el1, 2906 }, 2907 #ifdef CONFIG_ARM64_E0PD 2908 { 2909 .desc = "E0PD", 2910 .capability = ARM64_HAS_E0PD, 2911 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2912 .cpu_enable = cpu_enable_e0pd, 2913 .matches = has_cpuid_feature, 2914 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2915 }, 2916 #endif 2917 { 2918 .desc = "Random Number Generator", 2919 .capability = ARM64_HAS_RNG, 2920 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2921 .matches = has_cpuid_feature, 2922 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2923 }, 2924 #ifdef CONFIG_ARM64_BTI 2925 { 2926 .desc = "Branch Target Identification", 2927 .capability = ARM64_BTI, 2928 #ifdef CONFIG_ARM64_BTI_KERNEL 2929 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2930 #else 2931 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2932 #endif 2933 .matches = has_cpuid_feature, 2934 .cpu_enable = bti_enable, 2935 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2936 }, 2937 #endif 2938 #ifdef CONFIG_ARM64_MTE 2939 { 2940 .desc = "Memory Tagging Extension", 2941 .capability = ARM64_MTE, 2942 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2943 .matches = has_cpuid_feature, 2944 .cpu_enable = cpu_enable_mte, 2945 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2946 }, 2947 { 2948 .desc = "Asymmetric MTE Tag Check Fault", 2949 .capability = ARM64_MTE_ASYMM, 2950 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2951 .matches = has_cpuid_feature, 2952 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2953 }, 2954 { 2955 .desc = "FAR on MTE Tag Check Fault", 2956 .capability = ARM64_MTE_FAR, 2957 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2958 .matches = has_cpuid_feature, 2959 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2960 }, 2961 { 2962 .desc = "Store Only MTE Tag Check", 2963 .capability = ARM64_MTE_STORE_ONLY, 2964 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2965 .matches = has_cpuid_feature, 2966 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2967 }, 2968 #endif /* CONFIG_ARM64_MTE */ 2969 { 2970 .desc = "RCpc load-acquire (LDAPR)", 2971 .capability = ARM64_HAS_LDAPR, 2972 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2973 .matches = has_cpuid_feature, 2974 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2975 }, 2976 { 2977 .desc = "Fine Grained Traps", 2978 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2979 .capability = ARM64_HAS_FGT, 2980 .matches = has_cpuid_feature, 2981 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2982 }, 2983 { 2984 .desc = "Fine Grained Traps 2", 2985 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2986 .capability = ARM64_HAS_FGT2, 2987 .matches = has_cpuid_feature, 2988 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2989 }, 2990 #ifdef CONFIG_ARM64_SME 2991 { 2992 .desc = "Scalable Matrix Extension", 2993 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2994 .capability = ARM64_SME, 2995 .matches = has_cpuid_feature, 2996 .cpu_enable = cpu_enable_sme, 2997 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2998 }, 2999 /* FA64 should be sorted after the base SME capability */ 3000 { 3001 .desc = "FA64", 3002 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3003 .capability = ARM64_SME_FA64, 3004 .matches = has_cpuid_feature, 3005 .cpu_enable = cpu_enable_fa64, 3006 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 3007 }, 3008 { 3009 .desc = "SME2", 3010 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3011 .capability = ARM64_SME2, 3012 .matches = has_cpuid_feature, 3013 .cpu_enable = cpu_enable_sme2, 3014 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 3015 }, 3016 #endif /* CONFIG_ARM64_SME */ 3017 { 3018 .desc = "WFx with timeout", 3019 .capability = ARM64_HAS_WFXT, 3020 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3021 .matches = has_cpuid_feature, 3022 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 3023 }, 3024 { 3025 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 3026 .capability = ARM64_HAS_TIDCP1, 3027 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3028 .matches = has_cpuid_feature, 3029 .cpu_enable = cpu_trap_el0_impdef, 3030 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3031 }, 3032 { 3033 .desc = "Data independent timing control (DIT)", 3034 .capability = ARM64_HAS_DIT, 3035 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3036 .matches = has_cpuid_feature, 3037 .cpu_enable = cpu_enable_dit, 3038 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3039 }, 3040 { 3041 .desc = "Memory Copy and Memory Set instructions", 3042 .capability = ARM64_HAS_MOPS, 3043 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3044 .matches = has_cpuid_feature, 3045 .cpu_enable = cpu_enable_mops, 3046 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3047 }, 3048 { 3049 .capability = ARM64_HAS_TCR2, 3050 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3051 .matches = has_cpuid_feature, 3052 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3053 }, 3054 { 3055 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3056 .capability = ARM64_HAS_S1PIE, 3057 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3058 .matches = has_cpuid_feature, 3059 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3060 }, 3061 { 3062 .desc = "VHE for hypervisor only", 3063 .capability = ARM64_KVM_HVHE, 3064 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3065 .matches = hvhe_possible, 3066 }, 3067 { 3068 .desc = "Enhanced Virtualization Traps", 3069 .capability = ARM64_HAS_EVT, 3070 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3071 .matches = has_cpuid_feature, 3072 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3073 }, 3074 { 3075 .desc = "BBM Level 3", 3076 .capability = ARM64_HAS_BBML3, 3077 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3078 .matches = has_bbml3, 3079 }, 3080 { 3081 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3082 .capability = ARM64_HAS_LPA2, 3083 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3084 .matches = has_lpa2, 3085 }, 3086 { 3087 .desc = "FPMR", 3088 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3089 .capability = ARM64_HAS_FPMR, 3090 .matches = has_cpuid_feature, 3091 .cpu_enable = cpu_enable_fpmr, 3092 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3093 }, 3094 #ifdef CONFIG_ARM64_VA_BITS_52 3095 { 3096 .capability = ARM64_HAS_VA52, 3097 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3098 .matches = has_cpuid_feature, 3099 #ifdef CONFIG_ARM64_64K_PAGES 3100 .desc = "52-bit Virtual Addressing (LVA)", 3101 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3102 #else 3103 .desc = "52-bit Virtual Addressing (LPA2)", 3104 #ifdef CONFIG_ARM64_4K_PAGES 3105 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3106 #else 3107 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3108 #endif 3109 #endif 3110 }, 3111 #endif 3112 { 3113 .desc = "Memory Partitioning And Monitoring", 3114 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3115 .capability = ARM64_MPAM, 3116 .matches = test_has_mpam, 3117 .cpu_enable = cpu_enable_mpam, 3118 }, 3119 { 3120 .desc = "Memory Partitioning And Monitoring Virtualisation", 3121 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3122 .capability = ARM64_MPAM_HCR, 3123 .matches = test_has_mpam_hcr, 3124 }, 3125 { 3126 .desc = "NV1", 3127 .capability = ARM64_HAS_HCR_NV1, 3128 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3129 .matches = has_nv1, 3130 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3131 }, 3132 #ifdef CONFIG_ARM64_POE 3133 { 3134 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3135 .capability = ARM64_HAS_S1POE, 3136 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3137 .matches = has_cpuid_feature, 3138 .cpu_enable = cpu_enable_poe, 3139 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3140 }, 3141 #endif 3142 #ifdef CONFIG_ARM64_GCS 3143 { 3144 .desc = "Guarded Control Stack (GCS)", 3145 .capability = ARM64_HAS_GCS, 3146 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3147 .cpu_enable = cpu_enable_gcs, 3148 .matches = has_cpuid_feature, 3149 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3150 }, 3151 #endif 3152 #ifdef CONFIG_HW_PERF_EVENTS 3153 { 3154 .desc = "PMUv3", 3155 .capability = ARM64_HAS_PMUV3, 3156 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3157 .matches = has_pmuv3, 3158 }, 3159 #endif 3160 { 3161 .desc = "SCTLR2", 3162 .capability = ARM64_HAS_SCTLR2, 3163 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3164 .matches = has_cpuid_feature, 3165 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3166 }, 3167 { 3168 .desc = "GICv5 CPU interface", 3169 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3170 .capability = ARM64_HAS_GICV5_CPUIF, 3171 .matches = has_cpuid_feature, 3172 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3173 }, 3174 { 3175 .desc = "GICv5 Legacy vCPU interface", 3176 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3177 .capability = ARM64_HAS_GICV5_LEGACY, 3178 .matches = test_has_gicv5_legacy, 3179 }, 3180 { 3181 .desc = "XNX", 3182 .capability = ARM64_HAS_XNX, 3183 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3184 .matches = has_cpuid_feature, 3185 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3186 }, 3187 { 3188 .desc = "LS64", 3189 .capability = ARM64_HAS_LS64, 3190 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3191 .matches = has_cpuid_feature, 3192 .cpu_enable = cpu_enable_ls64, 3193 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3194 }, 3195 { 3196 .desc = "LS64_V", 3197 .capability = ARM64_HAS_LS64_V, 3198 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3199 .matches = has_cpuid_feature, 3200 .cpu_enable = cpu_enable_ls64_v, 3201 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3202 }, 3203 #ifdef CONFIG_ARM64_LSUI 3204 { 3205 .desc = "Unprivileged Load Store Instructions (LSUI)", 3206 .capability = ARM64_HAS_LSUI, 3207 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3208 .matches = has_cpuid_feature, 3209 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3210 }, 3211 #endif 3212 {}, 3213 }; 3214 3215 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3216 .matches = has_user_cpuid_feature, \ 3217 ARM64_CPUID_FIELDS(reg, field, min_value) 3218 3219 #define __HWCAP_CAP(name, cap_type, cap) \ 3220 .desc = name, \ 3221 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3222 .hwcap_type = cap_type, \ 3223 .hwcap = cap, \ 3224 3225 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3226 { \ 3227 __HWCAP_CAP(#cap, cap_type, cap) \ 3228 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3229 } 3230 3231 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3232 { \ 3233 __HWCAP_CAP(#cap, cap_type, cap) \ 3234 .matches = cpucap_multi_entry_cap_matches, \ 3235 .match_list = list, \ 3236 } 3237 3238 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3239 { \ 3240 __HWCAP_CAP(#cap, cap_type, cap) \ 3241 .matches = match, \ 3242 } 3243 3244 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3245 { \ 3246 __HWCAP_CAP(#cap, cap_type, cap) \ 3247 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3248 .matches = match, \ 3249 } 3250 3251 #ifdef CONFIG_ARM64_PTR_AUTH 3252 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3253 { 3254 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3255 }, 3256 { 3257 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3258 }, 3259 { 3260 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3261 }, 3262 {}, 3263 }; 3264 3265 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3266 { 3267 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3268 }, 3269 { 3270 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3271 }, 3272 { 3273 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3274 }, 3275 {}, 3276 }; 3277 #endif 3278 3279 #ifdef CONFIG_ARM64_SVE 3280 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3281 { 3282 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3283 } 3284 #endif 3285 3286 #ifdef CONFIG_ARM64_SME 3287 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3288 { 3289 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3290 } 3291 #endif 3292 3293 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3294 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3295 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3296 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3297 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3298 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3299 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3300 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3301 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3302 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3303 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3304 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3305 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3306 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3307 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3308 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F32DOT), 3309 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32MM), 3310 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3311 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3312 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3313 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3314 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3315 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3316 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3317 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3318 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3319 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3320 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3321 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3322 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3323 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3324 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3325 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3326 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3327 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3328 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3329 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3330 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3331 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3332 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3333 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3334 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3335 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3336 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3337 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3338 #ifdef CONFIG_ARM64_SVE 3339 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_SVE_LUT6), 3340 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3341 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_HWCAP, KERNEL_HWCAP_SVE2P3), 3342 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3343 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3344 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3345 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3346 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3347 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3348 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3349 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3350 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3351 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_HWCAP, KERNEL_HWCAP_SVE_B16MM), 3352 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3353 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3354 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3355 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3356 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3357 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3358 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3359 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3360 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3361 #endif 3362 #ifdef CONFIG_ARM64_GCS 3363 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3364 #endif 3365 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3366 #ifdef CONFIG_ARM64_BTI 3367 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3368 #endif 3369 #ifdef CONFIG_ARM64_PTR_AUTH 3370 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3371 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3372 #endif 3373 #ifdef CONFIG_ARM64_MTE 3374 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3375 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3376 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3377 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3378 #endif /* CONFIG_ARM64_MTE */ 3379 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3380 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3381 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3382 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3383 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3384 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3385 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3386 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3387 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3388 #ifdef CONFIG_ARM64_SME 3389 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3390 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3391 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUT6), 3392 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3393 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP_HWCAP, KERNEL_HWCAP_SME2P3), 3394 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3395 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3396 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3397 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3398 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3399 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3400 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3401 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3402 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3403 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3404 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3405 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3406 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3407 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3408 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3409 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3410 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3411 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3412 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3413 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3414 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3415 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3416 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3417 #endif /* CONFIG_ARM64_SME */ 3418 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3419 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3420 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3421 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3422 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3423 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3424 HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), 3425 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3426 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3427 #ifdef CONFIG_ARM64_POE 3428 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3429 #endif 3430 {}, 3431 }; 3432 3433 #ifdef CONFIG_COMPAT 3434 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3435 { 3436 /* 3437 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3438 * in line with that of arm32 as in vfp_init(). We make sure that the 3439 * check is future proof, by making sure value is non-zero. 3440 */ 3441 u32 mvfr1; 3442 3443 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3444 if (scope == SCOPE_SYSTEM) 3445 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3446 else 3447 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3448 3449 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3450 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3451 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3452 } 3453 #endif 3454 3455 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3456 #ifdef CONFIG_COMPAT 3457 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3458 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3459 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3460 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3461 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3462 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3463 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3464 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3465 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3466 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3467 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3468 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3469 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3470 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3471 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3472 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3473 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3474 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3475 #endif 3476 {}, 3477 }; 3478 3479 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3480 { 3481 switch (cap->hwcap_type) { 3482 case CAP_HWCAP: 3483 cpu_set_feature(cap->hwcap); 3484 break; 3485 #ifdef CONFIG_COMPAT 3486 case CAP_COMPAT_HWCAP: 3487 compat_elf_hwcap |= (u32)cap->hwcap; 3488 break; 3489 case CAP_COMPAT_HWCAP2: 3490 compat_elf_hwcap2 |= (u32)cap->hwcap; 3491 break; 3492 #endif 3493 default: 3494 WARN_ON(1); 3495 break; 3496 } 3497 } 3498 3499 /* Check if we have a particular HWCAP enabled */ 3500 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3501 { 3502 bool rc; 3503 3504 switch (cap->hwcap_type) { 3505 case CAP_HWCAP: 3506 rc = cpu_have_feature(cap->hwcap); 3507 break; 3508 #ifdef CONFIG_COMPAT 3509 case CAP_COMPAT_HWCAP: 3510 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3511 break; 3512 case CAP_COMPAT_HWCAP2: 3513 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3514 break; 3515 #endif 3516 default: 3517 WARN_ON(1); 3518 rc = false; 3519 } 3520 3521 return rc; 3522 } 3523 3524 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3525 { 3526 /* We support emulation of accesses to CPU ID feature registers */ 3527 cpu_set_named_feature(CPUID); 3528 for (; hwcaps->matches; hwcaps++) 3529 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3530 cap_set_elf_hwcap(hwcaps); 3531 } 3532 3533 static void update_cpu_capabilities(u16 scope_mask) 3534 { 3535 int i; 3536 const struct arm64_cpu_capabilities *caps; 3537 3538 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3539 for (i = 0; i < ARM64_NCAPS; i++) { 3540 bool match_all = false; 3541 bool caps_set = false; 3542 bool boot_cpu = false; 3543 3544 caps = cpucap_ptrs[i]; 3545 if (!caps || !(caps->type & scope_mask)) 3546 continue; 3547 3548 match_all = cpucap_match_all_early_cpus(caps); 3549 caps_set = cpus_have_cap(caps->capability); 3550 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3551 3552 /* 3553 * Unless it's a match-all CPUs feature, avoid probing if 3554 * already detected. 3555 */ 3556 if (!match_all && caps_set) 3557 continue; 3558 3559 /* 3560 * A match-all CPUs capability is only set when probing the 3561 * boot CPU. It may be cleared subsequently if not detected on 3562 * secondary ones. 3563 */ 3564 if (match_all && !caps_set && !boot_cpu) 3565 continue; 3566 3567 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3568 if (match_all) 3569 __clear_bit(caps->capability, system_cpucaps); 3570 continue; 3571 } 3572 3573 /* 3574 * Match-all CPUs capabilities are logged later when the 3575 * system capabilities are finalised. 3576 */ 3577 if (!match_all && caps->desc && !caps->cpus) 3578 pr_info("detected: %s\n", caps->desc); 3579 3580 __set_bit(caps->capability, system_cpucaps); 3581 3582 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3583 set_bit(caps->capability, boot_cpucaps); 3584 } 3585 } 3586 3587 /* 3588 * Enable all the available capabilities on this CPU. The capabilities 3589 * with BOOT_CPU scope are handled separately and hence skipped here. 3590 */ 3591 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3592 { 3593 int i; 3594 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3595 3596 for_each_available_cap(i) { 3597 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3598 3599 if (WARN_ON(!cap)) 3600 continue; 3601 3602 if (!(cap->type & non_boot_scope)) 3603 continue; 3604 3605 if (cap->cpu_enable) 3606 cap->cpu_enable(cap); 3607 } 3608 return 0; 3609 } 3610 3611 /* 3612 * Run through the enabled capabilities and enable() it on all active 3613 * CPUs 3614 */ 3615 static void __init enable_cpu_capabilities(u16 scope_mask) 3616 { 3617 int i; 3618 const struct arm64_cpu_capabilities *caps; 3619 bool boot_scope; 3620 3621 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3622 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3623 3624 for (i = 0; i < ARM64_NCAPS; i++) { 3625 caps = cpucap_ptrs[i]; 3626 if (!caps || !(caps->type & scope_mask) || 3627 !cpus_have_cap(caps->capability)) 3628 continue; 3629 3630 if (boot_scope && caps->cpu_enable) 3631 /* 3632 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3633 * before any secondary CPU boots. Thus, each secondary 3634 * will enable the capability as appropriate via 3635 * check_local_cpu_capabilities(). The only exception is 3636 * the boot CPU, for which the capability must be 3637 * enabled here. This approach avoids costly 3638 * stop_machine() calls for this case. 3639 */ 3640 caps->cpu_enable(caps); 3641 } 3642 3643 /* 3644 * For all non-boot scope capabilities, use stop_machine() 3645 * as it schedules the work allowing us to modify PSTATE, 3646 * instead of on_each_cpu() which uses an IPI, giving us a 3647 * PSTATE that disappears when we return. 3648 */ 3649 if (!boot_scope) 3650 stop_machine(cpu_enable_non_boot_scope_capabilities, 3651 NULL, cpu_online_mask); 3652 } 3653 3654 /* 3655 * Run through the list of capabilities to check for conflicts. 3656 * If the system has already detected a capability, take necessary 3657 * action on this CPU. 3658 */ 3659 static void verify_local_cpu_caps(u16 scope_mask) 3660 { 3661 int i; 3662 bool cpu_has_cap, system_has_cap; 3663 const struct arm64_cpu_capabilities *caps; 3664 3665 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3666 3667 for (i = 0; i < ARM64_NCAPS; i++) { 3668 caps = cpucap_ptrs[i]; 3669 if (!caps || !(caps->type & scope_mask)) 3670 continue; 3671 3672 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3673 system_has_cap = cpus_have_cap(caps->capability); 3674 3675 if (system_has_cap) { 3676 /* 3677 * Check if the new CPU misses an advertised feature, 3678 * which is not safe to miss. 3679 */ 3680 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3681 break; 3682 /* 3683 * We have to issue cpu_enable() irrespective of 3684 * whether the CPU has it or not, as it is enabeld 3685 * system wide. It is upto the call back to take 3686 * appropriate action on this CPU. 3687 */ 3688 if (caps->cpu_enable) 3689 caps->cpu_enable(caps); 3690 } else { 3691 /* 3692 * Check if the CPU has this capability if it isn't 3693 * safe to have when the system doesn't. 3694 */ 3695 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3696 break; 3697 } 3698 } 3699 3700 if (i < ARM64_NCAPS) { 3701 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3702 smp_processor_id(), caps->capability, 3703 caps->desc, system_has_cap, cpu_has_cap); 3704 3705 if (cpucap_panic_on_conflict(caps)) 3706 cpu_panic_kernel(); 3707 else 3708 cpu_die_early(); 3709 } 3710 } 3711 3712 /* 3713 * Check for CPU features that are used in early boot 3714 * based on the Boot CPU value. 3715 */ 3716 static void check_early_cpu_features(void) 3717 { 3718 verify_cpu_asid_bits(); 3719 3720 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3721 } 3722 3723 static void 3724 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3725 { 3726 3727 for (; caps->matches; caps++) 3728 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3729 pr_crit("CPU%d: missing HWCAP: %s\n", 3730 smp_processor_id(), caps->desc); 3731 cpu_die_early(); 3732 } 3733 } 3734 3735 static void verify_local_elf_hwcaps(void) 3736 { 3737 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3738 3739 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3740 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3741 } 3742 3743 static void verify_sve_features(void) 3744 { 3745 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3746 3747 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3748 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3749 smp_processor_id()); 3750 cpu_die_early(); 3751 } 3752 3753 cpacr_restore(cpacr); 3754 } 3755 3756 static void verify_sme_features(void) 3757 { 3758 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3759 3760 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3761 pr_crit("CPU%d: SME: vector length support mismatch\n", 3762 smp_processor_id()); 3763 cpu_die_early(); 3764 } 3765 3766 cpacr_restore(cpacr); 3767 } 3768 3769 static void verify_hyp_capabilities(void) 3770 { 3771 u64 safe_mmfr1, mmfr0, mmfr1; 3772 int parange, ipa_max; 3773 unsigned int safe_vmid_bits, vmid_bits; 3774 3775 if (!IS_ENABLED(CONFIG_KVM)) 3776 return; 3777 3778 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3779 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3780 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3781 3782 /* Verify VMID bits */ 3783 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3784 vmid_bits = get_vmid_bits(mmfr1); 3785 if (vmid_bits < safe_vmid_bits) { 3786 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3787 cpu_die_early(); 3788 } 3789 3790 /* Verify IPA range */ 3791 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3792 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3793 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3794 if (ipa_max < get_kvm_ipa_limit()) { 3795 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3796 cpu_die_early(); 3797 } 3798 } 3799 3800 static void verify_mpam_capabilities(void) 3801 { 3802 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3803 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3804 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3805 3806 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3807 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3808 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3809 cpu_die_early(); 3810 } 3811 3812 cpu_idr = read_cpuid(MPAMIDR_EL1); 3813 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3814 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3815 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3816 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3817 cpu_die_early(); 3818 } 3819 3820 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3821 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3822 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3823 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3824 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3825 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3826 cpu_die_early(); 3827 } 3828 } 3829 3830 /* 3831 * Run through the enabled system capabilities and enable() it on this CPU. 3832 * The capabilities were decided based on the available CPUs at the boot time. 3833 * Any new CPU should match the system wide status of the capability. If the 3834 * new CPU doesn't have a capability which the system now has enabled, we 3835 * cannot do anything to fix it up and could cause unexpected failures. So 3836 * we park the CPU. 3837 */ 3838 static void verify_local_cpu_capabilities(void) 3839 { 3840 /* 3841 * The capabilities with SCOPE_BOOT_CPU are checked from 3842 * check_early_cpu_features(), as they need to be verified 3843 * on all secondary CPUs. 3844 */ 3845 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3846 verify_local_elf_hwcaps(); 3847 3848 if (system_supports_sve()) 3849 verify_sve_features(); 3850 3851 if (system_supports_sme()) 3852 verify_sme_features(); 3853 3854 if (is_hyp_mode_available()) 3855 verify_hyp_capabilities(); 3856 3857 if (system_supports_mpam()) 3858 verify_mpam_capabilities(); 3859 } 3860 3861 void check_local_cpu_capabilities(void) 3862 { 3863 /* 3864 * All secondary CPUs should conform to the early CPU features 3865 * in use by the kernel based on boot CPU. 3866 */ 3867 check_early_cpu_features(); 3868 3869 /* 3870 * If we haven't finalised the system capabilities, this CPU gets 3871 * a chance to update the errata work arounds and local features. 3872 * Otherwise, this CPU should verify that it has all the system 3873 * advertised capabilities. 3874 */ 3875 if (!system_capabilities_finalized()) 3876 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3877 else 3878 verify_local_cpu_capabilities(); 3879 } 3880 3881 bool this_cpu_has_cap(unsigned int n) 3882 { 3883 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3884 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3885 3886 if (cap) 3887 return cap->matches(cap, SCOPE_LOCAL_CPU); 3888 } 3889 3890 return false; 3891 } 3892 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3893 3894 /* 3895 * This helper function is used in a narrow window when, 3896 * - The system wide safe registers are set with all the SMP CPUs and, 3897 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3898 */ 3899 static bool __maybe_unused __system_matches_cap(unsigned int n) 3900 { 3901 if (n < ARM64_NCAPS) { 3902 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3903 3904 if (cap) 3905 return cap->matches(cap, SCOPE_SYSTEM); 3906 } 3907 return false; 3908 } 3909 3910 void cpu_set_feature(unsigned int num) 3911 { 3912 set_bit(num, elf_hwcap); 3913 } 3914 3915 bool cpu_have_feature(unsigned int num) 3916 { 3917 return test_bit(num, elf_hwcap); 3918 } 3919 EXPORT_SYMBOL_GPL(cpu_have_feature); 3920 3921 unsigned long cpu_get_elf_hwcap(void) 3922 { 3923 /* 3924 * We currently only populate the first 32 bits of AT_HWCAP. Please 3925 * note that for userspace compatibility we guarantee that bits 62 3926 * and 63 will always be returned as 0. 3927 */ 3928 return elf_hwcap[0]; 3929 } 3930 3931 unsigned long cpu_get_elf_hwcap2(void) 3932 { 3933 return elf_hwcap[1]; 3934 } 3935 3936 unsigned long cpu_get_elf_hwcap3(void) 3937 { 3938 return elf_hwcap[2]; 3939 } 3940 3941 static void __init setup_boot_cpu_capabilities(void) 3942 { 3943 kvm_arm_target_impl_cpu_init(); 3944 /* 3945 * The boot CPU's feature register values have been recorded. Detect 3946 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3947 * patch alternatives for the available boot cpucaps. 3948 */ 3949 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3950 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3951 apply_boot_alternatives(); 3952 } 3953 3954 void __init setup_boot_cpu_features(void) 3955 { 3956 /* 3957 * Initialize the indirect array of CPU capabilities pointers before we 3958 * handle the boot CPU. 3959 */ 3960 init_cpucap_indirect_list(); 3961 3962 /* 3963 * Detect broken pseudo-NMI. Must be called _before_ the call to 3964 * setup_boot_cpu_capabilities() since it interacts with 3965 * can_use_gic_priorities(). 3966 */ 3967 detect_system_supports_pseudo_nmi(); 3968 3969 setup_boot_cpu_capabilities(); 3970 } 3971 3972 static void __init setup_system_capabilities(void) 3973 { 3974 /* 3975 * The system-wide safe feature register values have been finalized. 3976 * Detect, enable, and patch alternatives for the available system 3977 * cpucaps. 3978 */ 3979 update_cpu_capabilities(SCOPE_SYSTEM); 3980 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3981 apply_alternatives_all(); 3982 3983 for (int i = 0; i < ARM64_NCAPS; i++) { 3984 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3985 3986 if (!caps || !caps->desc) 3987 continue; 3988 3989 /* 3990 * Log any cpucaps with a cpumask as these aren't logged by 3991 * update_cpu_capabilities(). 3992 */ 3993 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3994 pr_info("detected: %s on CPU%*pbl\n", 3995 caps->desc, cpumask_pr_args(caps->cpus)); 3996 3997 /* Log match-all CPUs capabilities */ 3998 if (cpucap_match_all_early_cpus(caps) && 3999 cpus_have_cap(caps->capability)) 4000 pr_info("detected: %s\n", caps->desc); 4001 } 4002 4003 /* 4004 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 4005 */ 4006 if (system_uses_ttbr0_pan()) 4007 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 4008 4009 /* 4010 * Report Spectre mitigations status. 4011 */ 4012 spectre_print_disabled_mitigations(); 4013 } 4014 4015 void __init setup_system_features(void) 4016 { 4017 setup_system_capabilities(); 4018 4019 linear_map_maybe_split_to_ptes(); 4020 kpti_install_ng_mappings(); 4021 4022 sve_setup(); 4023 sme_setup(); 4024 4025 /* 4026 * Check for sane CTR_EL0.CWG value. 4027 */ 4028 if (!cache_type_cwg()) 4029 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4030 ARCH_DMA_MINALIGN); 4031 } 4032 4033 void __init setup_user_features(void) 4034 { 4035 user_feature_fixup(); 4036 4037 setup_elf_hwcaps(arm64_elf_hwcaps); 4038 4039 if (system_supports_32bit_el0()) { 4040 setup_elf_hwcaps(compat_elf_hwcaps); 4041 elf_hwcap_fixup(); 4042 } 4043 4044 minsigstksz_setup(); 4045 } 4046 4047 static int enable_mismatched_32bit_el0(unsigned int cpu) 4048 { 4049 /* 4050 * The first 32-bit-capable CPU we detected and so can no longer 4051 * be offlined by userspace. -1 indicates we haven't yet onlined 4052 * a 32-bit-capable CPU. 4053 */ 4054 static int lucky_winner = -1; 4055 4056 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4057 bool cpu_32bit = false; 4058 4059 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4060 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4061 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4062 else 4063 cpu_32bit = true; 4064 } 4065 4066 if (cpu_32bit) { 4067 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4068 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4069 } 4070 4071 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4072 return 0; 4073 4074 if (lucky_winner >= 0) 4075 return 0; 4076 4077 /* 4078 * We've detected a mismatch. We need to keep one of our CPUs with 4079 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4080 * every CPU in the system for a 32-bit task. 4081 */ 4082 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4083 cpu_active_mask); 4084 dev_set_offline_disabled(get_cpu_device(lucky_winner)); 4085 setup_elf_hwcaps(compat_elf_hwcaps); 4086 elf_hwcap_fixup(); 4087 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4088 cpu, lucky_winner); 4089 return 0; 4090 } 4091 4092 static int __init init_32bit_el0_mask(void) 4093 { 4094 if (!allow_mismatched_32bit_el0) 4095 return 0; 4096 4097 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4098 return -ENOMEM; 4099 4100 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4101 "arm64/mismatched_32bit_el0:online", 4102 enable_mismatched_32bit_el0, NULL); 4103 } 4104 subsys_initcall_sync(init_32bit_el0_mask); 4105 4106 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4107 { 4108 cpu_enable_swapper_cnp(); 4109 } 4110 4111 /* 4112 * We emulate only the following system register space. 4113 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4114 * See Table C5-6 System instruction encodings for System register accesses, 4115 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4116 */ 4117 static inline bool __attribute_const__ is_emulated(u32 id) 4118 { 4119 return (sys_reg_Op0(id) == 0x3 && 4120 sys_reg_CRn(id) == 0x0 && 4121 sys_reg_Op1(id) == 0x0 && 4122 (sys_reg_CRm(id) == 0 || 4123 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4124 } 4125 4126 /* 4127 * With CRm == 0, reg should be one of : 4128 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4129 */ 4130 static inline int emulate_id_reg(u32 id, u64 *valp) 4131 { 4132 switch (id) { 4133 case SYS_MIDR_EL1: 4134 *valp = read_cpuid_id(); 4135 break; 4136 case SYS_MPIDR_EL1: 4137 *valp = SYS_MPIDR_SAFE_VAL; 4138 break; 4139 case SYS_REVIDR_EL1: 4140 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4141 *valp = 0; 4142 break; 4143 default: 4144 return -EINVAL; 4145 } 4146 4147 return 0; 4148 } 4149 4150 static int emulate_sys_reg(u32 id, u64 *valp) 4151 { 4152 struct arm64_ftr_reg *regp; 4153 4154 if (!is_emulated(id)) 4155 return -EINVAL; 4156 4157 if (sys_reg_CRm(id) == 0) 4158 return emulate_id_reg(id, valp); 4159 4160 regp = get_arm64_ftr_reg_nowarn(id); 4161 if (regp) 4162 *valp = arm64_ftr_reg_user_value(regp); 4163 else 4164 /* 4165 * The untracked registers are either IMPLEMENTATION DEFINED 4166 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4167 */ 4168 *valp = 0; 4169 return 0; 4170 } 4171 4172 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4173 { 4174 int rc; 4175 u64 val; 4176 4177 rc = emulate_sys_reg(sys_reg, &val); 4178 if (!rc) { 4179 pt_regs_write_reg(regs, rt, val); 4180 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4181 } 4182 return rc; 4183 } 4184 4185 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4186 { 4187 u32 sys_reg, rt; 4188 4189 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4190 return false; 4191 4192 /* 4193 * sys_reg values are defined as used in mrs/msr instruction. 4194 * shift the imm value to get the encoding. 4195 */ 4196 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4197 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4198 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4199 } 4200 4201 enum mitigation_state arm64_get_meltdown_state(void) 4202 { 4203 if (__meltdown_safe) 4204 return SPECTRE_UNAFFECTED; 4205 4206 if (arm64_kernel_unmapped_at_el0()) 4207 return SPECTRE_MITIGATED; 4208 4209 return SPECTRE_VULNERABLE; 4210 } 4211 4212 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4213 char *buf) 4214 { 4215 switch (arm64_get_meltdown_state()) { 4216 case SPECTRE_UNAFFECTED: 4217 return sprintf(buf, "Not affected\n"); 4218 4219 case SPECTRE_MITIGATED: 4220 return sprintf(buf, "Mitigation: PTI\n"); 4221 4222 default: 4223 return sprintf(buf, "Vulnerable\n"); 4224 } 4225 } 4226