1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/kvm_asm.h> 15 #include <asm/smp_plat.h> 16 17 static bool __maybe_unused 18 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 19 { 20 const struct arm64_midr_revidr *fix; 21 u32 midr = read_cpuid_id(), revidr; 22 23 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 24 if (!is_midr_in_range(midr, &entry->midr_range)) 25 return false; 26 27 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 28 revidr = read_cpuid(REVIDR_EL1); 29 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 30 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 31 return false; 32 33 return true; 34 } 35 36 static bool __maybe_unused 37 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 38 int scope) 39 { 40 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 41 return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list); 42 } 43 44 static bool __maybe_unused 45 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 46 { 47 u32 model; 48 49 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 50 51 model = read_cpuid_id(); 52 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 53 MIDR_ARCHITECTURE_MASK; 54 55 return model == entry->midr_range.model; 56 } 57 58 static bool 59 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 60 int scope) 61 { 62 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 63 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 64 u64 ctr_raw, ctr_real; 65 66 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 67 68 /* 69 * We want to make sure that all the CPUs in the system expose 70 * a consistent CTR_EL0 to make sure that applications behaves 71 * correctly with migration. 72 * 73 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 74 * 75 * 1) It is safe if the system doesn't support IDC, as CPU anyway 76 * reports IDC = 0, consistent with the rest. 77 * 78 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 79 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 80 * 81 * So, we need to make sure either the raw CTR_EL0 or the effective 82 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 83 */ 84 ctr_raw = read_cpuid_cachetype() & mask; 85 ctr_real = read_cpuid_effective_cachetype() & mask; 86 87 return (ctr_real != sys) && (ctr_raw != sys); 88 } 89 90 static void 91 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 92 { 93 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 94 bool enable_uct_trap = false; 95 96 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 97 if ((read_cpuid_cachetype() & mask) != 98 (arm64_ftr_reg_ctrel0.sys_val & mask)) 99 enable_uct_trap = true; 100 101 /* ... or if the system is affected by an erratum */ 102 if (cap->capability == ARM64_WORKAROUND_1542419) 103 enable_uct_trap = true; 104 105 if (enable_uct_trap) 106 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 107 } 108 109 #ifdef CONFIG_ARM64_ERRATUM_1463225 110 static bool 111 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 112 int scope) 113 { 114 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 115 } 116 #endif 117 118 static void __maybe_unused 119 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 120 { 121 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 122 } 123 124 static DEFINE_RAW_SPINLOCK(reg_user_mask_modification); 125 static void __maybe_unused 126 cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused) 127 { 128 struct arm64_ftr_reg *regp; 129 130 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 131 if (!regp) 132 return; 133 134 raw_spin_lock(®_user_mask_modification); 135 if (regp->user_mask & ID_AA64ISAR1_EL1_BF16_MASK) 136 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 137 raw_spin_unlock(®_user_mask_modification); 138 } 139 140 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 141 .matches = is_affected_midr_range, \ 142 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 143 144 #define CAP_MIDR_ALL_VERSIONS(model) \ 145 .matches = is_affected_midr_range, \ 146 .midr_range = MIDR_ALL_VERSIONS(model) 147 148 #define MIDR_FIXED(rev, revidr_mask) \ 149 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 150 151 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 152 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 153 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 154 155 #define CAP_MIDR_RANGE_LIST(list) \ 156 .matches = is_affected_midr_range_list, \ 157 .midr_range_list = list 158 159 /* Errata affecting a range of revisions of given model variant */ 160 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 161 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 162 163 /* Errata affecting a single variant/revision of a model */ 164 #define ERRATA_MIDR_REV(model, var, rev) \ 165 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 166 167 /* Errata affecting all variants/revisions of a given a model */ 168 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 169 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 170 CAP_MIDR_ALL_VERSIONS(model) 171 172 /* Errata affecting a list of midr ranges, with same work around */ 173 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 174 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 175 CAP_MIDR_RANGE_LIST(midr_list) 176 177 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 178 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 179 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 180 {}, 181 }; 182 183 static bool __maybe_unused 184 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 185 int scope) 186 { 187 int i; 188 189 if (!is_affected_midr_range_list(entry, scope) || 190 !is_hyp_mode_available()) 191 return false; 192 193 for_each_possible_cpu(i) { 194 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 195 return true; 196 } 197 198 return false; 199 } 200 201 static bool __maybe_unused 202 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 203 int scope) 204 { 205 u32 midr = read_cpuid_id(); 206 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 207 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 208 209 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 210 return is_midr_in_range(midr, &range) && has_dic; 211 } 212 213 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 214 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 215 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 216 { 217 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 218 }, 219 { 220 .midr_range.model = MIDR_QCOM_KRYO, 221 .matches = is_kryo_midr, 222 }, 223 #endif 224 #ifdef CONFIG_ARM64_ERRATUM_1286807 225 { 226 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 227 }, 228 { 229 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 230 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 231 }, 232 #endif 233 #ifdef CONFIG_ARM64_ERRATUM_2441009 234 { 235 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 236 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 237 }, 238 #endif 239 {}, 240 }; 241 #endif 242 243 #ifdef CONFIG_CAVIUM_ERRATUM_23154 244 static const struct midr_range cavium_erratum_23154_cpus[] = { 245 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 246 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 247 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 248 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 249 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 250 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 251 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 252 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 253 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 254 {}, 255 }; 256 #endif 257 258 #ifdef CONFIG_CAVIUM_ERRATUM_27456 259 const struct midr_range cavium_erratum_27456_cpus[] = { 260 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 261 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 262 /* Cavium ThunderX, T81 pass 1.0 */ 263 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 264 {}, 265 }; 266 #endif 267 268 #ifdef CONFIG_CAVIUM_ERRATUM_30115 269 static const struct midr_range cavium_erratum_30115_cpus[] = { 270 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 271 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 272 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 273 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 274 /* Cavium ThunderX, T83 pass 1.0 */ 275 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 276 {}, 277 }; 278 #endif 279 280 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 281 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 282 { 283 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 284 }, 285 { 286 .midr_range.model = MIDR_QCOM_KRYO, 287 .matches = is_kryo_midr, 288 }, 289 {}, 290 }; 291 #endif 292 293 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 294 static const struct midr_range workaround_clean_cache[] = { 295 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 296 defined(CONFIG_ARM64_ERRATUM_827319) || \ 297 defined(CONFIG_ARM64_ERRATUM_824069) 298 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 299 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 300 #endif 301 #ifdef CONFIG_ARM64_ERRATUM_819472 302 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 303 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 304 #endif 305 {}, 306 }; 307 #endif 308 309 #ifdef CONFIG_ARM64_ERRATUM_1418040 310 /* 311 * - 1188873 affects r0p0 to r2p0 312 * - 1418040 affects r0p0 to r3p1 313 */ 314 static const struct midr_range erratum_1418040_list[] = { 315 /* Cortex-A76 r0p0 to r3p1 */ 316 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 317 /* Neoverse-N1 r0p0 to r3p1 */ 318 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 319 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 320 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 321 {}, 322 }; 323 #endif 324 325 #ifdef CONFIG_ARM64_ERRATUM_845719 326 static const struct midr_range erratum_845719_list[] = { 327 /* Cortex-A53 r0p[01234] */ 328 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 329 /* Brahma-B53 r0p[0] */ 330 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 331 /* Kryo2XX Silver rAp4 */ 332 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 333 {}, 334 }; 335 #endif 336 337 #ifdef CONFIG_ARM64_ERRATUM_843419 338 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 339 { 340 /* Cortex-A53 r0p[01234] */ 341 .matches = is_affected_midr_range, 342 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 343 MIDR_FIXED(0x4, BIT(8)), 344 }, 345 { 346 /* Brahma-B53 r0p[0] */ 347 .matches = is_affected_midr_range, 348 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 349 }, 350 {}, 351 }; 352 #endif 353 354 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 355 static const struct midr_range erratum_speculative_at_list[] = { 356 #ifdef CONFIG_ARM64_ERRATUM_1165522 357 /* Cortex A76 r0p0 to r2p0 */ 358 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 359 #endif 360 #ifdef CONFIG_ARM64_ERRATUM_1319367 361 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 362 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 363 #endif 364 #ifdef CONFIG_ARM64_ERRATUM_1530923 365 /* Cortex A55 r0p0 to r2p0 */ 366 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 367 /* Kryo4xx Silver (rdpe => r1p0) */ 368 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 369 #endif 370 {}, 371 }; 372 #endif 373 374 #ifdef CONFIG_ARM64_ERRATUM_1463225 375 static const struct midr_range erratum_1463225[] = { 376 /* Cortex-A76 r0p0 - r3p1 */ 377 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 378 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 379 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 380 {}, 381 }; 382 #endif 383 384 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 385 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 386 #ifdef CONFIG_ARM64_ERRATUM_2139208 387 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 388 #endif 389 #ifdef CONFIG_ARM64_ERRATUM_2119858 390 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 391 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 392 #endif 393 {}, 394 }; 395 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 396 397 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 398 static const struct midr_range tsb_flush_fail_cpus[] = { 399 #ifdef CONFIG_ARM64_ERRATUM_2067961 400 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 401 #endif 402 #ifdef CONFIG_ARM64_ERRATUM_2054223 403 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 404 #endif 405 {}, 406 }; 407 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 408 409 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 410 static struct midr_range trbe_write_out_of_range_cpus[] = { 411 #ifdef CONFIG_ARM64_ERRATUM_2253138 412 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 413 #endif 414 #ifdef CONFIG_ARM64_ERRATUM_2224489 415 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 416 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 417 #endif 418 {}, 419 }; 420 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 421 422 #ifdef CONFIG_ARM64_ERRATUM_1742098 423 static struct midr_range broken_aarch32_aes[] = { 424 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 425 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 426 {}, 427 }; 428 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 429 430 const struct arm64_cpu_capabilities arm64_errata[] = { 431 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 432 { 433 .desc = "ARM errata 826319, 827319, 824069, or 819472", 434 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 435 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 436 .cpu_enable = cpu_enable_cache_maint_trap, 437 }, 438 #endif 439 #ifdef CONFIG_ARM64_ERRATUM_832075 440 { 441 /* Cortex-A57 r0p0 - r1p2 */ 442 .desc = "ARM erratum 832075", 443 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 444 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 445 0, 0, 446 1, 2), 447 }, 448 #endif 449 #ifdef CONFIG_ARM64_ERRATUM_834220 450 { 451 /* Cortex-A57 r0p0 - r1p2 */ 452 .desc = "ARM erratum 834220", 453 .capability = ARM64_WORKAROUND_834220, 454 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 455 0, 0, 456 1, 2), 457 }, 458 #endif 459 #ifdef CONFIG_ARM64_ERRATUM_843419 460 { 461 .desc = "ARM erratum 843419", 462 .capability = ARM64_WORKAROUND_843419, 463 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 464 .matches = cpucap_multi_entry_cap_matches, 465 .match_list = erratum_843419_list, 466 }, 467 #endif 468 #ifdef CONFIG_ARM64_ERRATUM_845719 469 { 470 .desc = "ARM erratum 845719", 471 .capability = ARM64_WORKAROUND_845719, 472 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 473 }, 474 #endif 475 #ifdef CONFIG_CAVIUM_ERRATUM_23154 476 { 477 .desc = "Cavium errata 23154 and 38545", 478 .capability = ARM64_WORKAROUND_CAVIUM_23154, 479 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 480 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 481 }, 482 #endif 483 #ifdef CONFIG_CAVIUM_ERRATUM_27456 484 { 485 .desc = "Cavium erratum 27456", 486 .capability = ARM64_WORKAROUND_CAVIUM_27456, 487 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 488 }, 489 #endif 490 #ifdef CONFIG_CAVIUM_ERRATUM_30115 491 { 492 .desc = "Cavium erratum 30115", 493 .capability = ARM64_WORKAROUND_CAVIUM_30115, 494 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 495 }, 496 #endif 497 { 498 .desc = "Mismatched cache type (CTR_EL0)", 499 .capability = ARM64_MISMATCHED_CACHE_TYPE, 500 .matches = has_mismatched_cache_type, 501 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 502 .cpu_enable = cpu_enable_trap_ctr_access, 503 }, 504 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 505 { 506 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 507 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 508 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 509 .matches = cpucap_multi_entry_cap_matches, 510 .match_list = qcom_erratum_1003_list, 511 }, 512 #endif 513 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 514 { 515 .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009", 516 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 517 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 518 .matches = cpucap_multi_entry_cap_matches, 519 .match_list = arm64_repeat_tlbi_list, 520 }, 521 #endif 522 #ifdef CONFIG_ARM64_ERRATUM_858921 523 { 524 /* Cortex-A73 all versions */ 525 .desc = "ARM erratum 858921", 526 .capability = ARM64_WORKAROUND_858921, 527 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 528 }, 529 #endif 530 { 531 .desc = "Spectre-v2", 532 .capability = ARM64_SPECTRE_V2, 533 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 534 .matches = has_spectre_v2, 535 .cpu_enable = spectre_v2_enable_mitigation, 536 }, 537 #ifdef CONFIG_RANDOMIZE_BASE 538 { 539 /* Must come after the Spectre-v2 entry */ 540 .desc = "Spectre-v3a", 541 .capability = ARM64_SPECTRE_V3A, 542 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 543 .matches = has_spectre_v3a, 544 .cpu_enable = spectre_v3a_enable_mitigation, 545 }, 546 #endif 547 { 548 .desc = "Spectre-v4", 549 .capability = ARM64_SPECTRE_V4, 550 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 551 .matches = has_spectre_v4, 552 .cpu_enable = spectre_v4_enable_mitigation, 553 }, 554 { 555 .desc = "Spectre-BHB", 556 .capability = ARM64_SPECTRE_BHB, 557 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 558 .matches = is_spectre_bhb_affected, 559 .cpu_enable = spectre_bhb_enable_mitigation, 560 }, 561 #ifdef CONFIG_ARM64_ERRATUM_1418040 562 { 563 .desc = "ARM erratum 1418040", 564 .capability = ARM64_WORKAROUND_1418040, 565 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 566 /* 567 * We need to allow affected CPUs to come in late, but 568 * also need the non-affected CPUs to be able to come 569 * in at any point in time. Wonderful. 570 */ 571 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 572 }, 573 #endif 574 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 575 { 576 .desc = "ARM errata 1165522, 1319367, or 1530923", 577 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 578 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 579 }, 580 #endif 581 #ifdef CONFIG_ARM64_ERRATUM_1463225 582 { 583 .desc = "ARM erratum 1463225", 584 .capability = ARM64_WORKAROUND_1463225, 585 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 586 .matches = has_cortex_a76_erratum_1463225, 587 .midr_range_list = erratum_1463225, 588 }, 589 #endif 590 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 591 { 592 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 593 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 594 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 595 .matches = needs_tx2_tvm_workaround, 596 }, 597 { 598 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 599 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 600 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 601 }, 602 #endif 603 #ifdef CONFIG_ARM64_ERRATUM_1542419 604 { 605 /* we depend on the firmware portion for correctness */ 606 .desc = "ARM erratum 1542419 (kernel portion)", 607 .capability = ARM64_WORKAROUND_1542419, 608 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 609 .matches = has_neoverse_n1_erratum_1542419, 610 .cpu_enable = cpu_enable_trap_ctr_access, 611 }, 612 #endif 613 #ifdef CONFIG_ARM64_ERRATUM_1508412 614 { 615 /* we depend on the firmware portion for correctness */ 616 .desc = "ARM erratum 1508412 (kernel portion)", 617 .capability = ARM64_WORKAROUND_1508412, 618 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 619 0, 0, 620 1, 0), 621 }, 622 #endif 623 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 624 { 625 /* NVIDIA Carmel */ 626 .desc = "NVIDIA Carmel CNP erratum", 627 .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP, 628 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 629 }, 630 #endif 631 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 632 { 633 /* 634 * The erratum work around is handled within the TRBE 635 * driver and can be applied per-cpu. So, we can allow 636 * a late CPU to come online with this erratum. 637 */ 638 .desc = "ARM erratum 2119858 or 2139208", 639 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 640 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 641 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 642 }, 643 #endif 644 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 645 { 646 .desc = "ARM erratum 2067961 or 2054223", 647 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 648 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 649 }, 650 #endif 651 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 652 { 653 .desc = "ARM erratum 2253138 or 2224489", 654 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 655 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 656 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 657 }, 658 #endif 659 #ifdef CONFIG_ARM64_ERRATUM_2077057 660 { 661 .desc = "ARM erratum 2077057", 662 .capability = ARM64_WORKAROUND_2077057, 663 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 664 }, 665 #endif 666 #ifdef CONFIG_ARM64_ERRATUM_2064142 667 { 668 .desc = "ARM erratum 2064142", 669 .capability = ARM64_WORKAROUND_2064142, 670 671 /* Cortex-A510 r0p0 - r0p2 */ 672 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 673 }, 674 #endif 675 #ifdef CONFIG_ARM64_ERRATUM_2457168 676 { 677 .desc = "ARM erratum 2457168", 678 .capability = ARM64_WORKAROUND_2457168, 679 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 680 681 /* Cortex-A510 r0p0-r1p1 */ 682 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) 683 }, 684 #endif 685 #ifdef CONFIG_ARM64_ERRATUM_2038923 686 { 687 .desc = "ARM erratum 2038923", 688 .capability = ARM64_WORKAROUND_2038923, 689 690 /* Cortex-A510 r0p0 - r0p2 */ 691 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 692 }, 693 #endif 694 #ifdef CONFIG_ARM64_ERRATUM_1902691 695 { 696 .desc = "ARM erratum 1902691", 697 .capability = ARM64_WORKAROUND_1902691, 698 699 /* Cortex-A510 r0p0 - r0p1 */ 700 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 701 }, 702 #endif 703 #ifdef CONFIG_ARM64_ERRATUM_1742098 704 { 705 .desc = "ARM erratum 1742098", 706 .capability = ARM64_WORKAROUND_1742098, 707 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 708 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 709 }, 710 #endif 711 #ifdef CONFIG_ARM64_ERRATUM_2658417 712 { 713 .desc = "ARM erratum 2658417", 714 .capability = ARM64_WORKAROUND_2658417, 715 /* Cortex-A510 r0p0 - r1p1 */ 716 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 717 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), 718 .cpu_enable = cpu_clear_bf16_from_user_emulation, 719 }, 720 #endif 721 { 722 } 723 }; 724