1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/types.h> 10 #include <linux/cpu.h> 11 #include <asm/cpu.h> 12 #include <asm/cputype.h> 13 #include <asm/cpufeature.h> 14 #include <asm/fpsimd.h> 15 #include <asm/kvm_asm.h> 16 #include <asm/smp_plat.h> 17 18 static u64 target_impl_cpu_num; 19 static struct target_impl_cpu *target_impl_cpus; 20 21 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus) 22 { 23 if (target_impl_cpu_num || !num || !impl_cpus) 24 return false; 25 26 target_impl_cpu_num = num; 27 target_impl_cpus = impl_cpus; 28 return true; 29 } 30 31 static inline bool is_midr_in_range(struct midr_range const *range) 32 { 33 int i; 34 35 if (!target_impl_cpu_num) 36 return midr_is_cpu_model_range(read_cpuid_id(), range->model, 37 range->rv_min, range->rv_max); 38 39 for (i = 0; i < target_impl_cpu_num; i++) { 40 if (midr_is_cpu_model_range(target_impl_cpus[i].midr, 41 range->model, 42 range->rv_min, range->rv_max)) 43 return true; 44 } 45 return false; 46 } 47 48 bool is_midr_in_range_list(struct midr_range const *ranges) 49 { 50 while (ranges->model) 51 if (is_midr_in_range(ranges++)) 52 return true; 53 return false; 54 } 55 EXPORT_SYMBOL_GPL(is_midr_in_range_list); 56 57 static bool __maybe_unused 58 __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, 59 u32 midr, u32 revidr) 60 { 61 const struct arm64_midr_revidr *fix; 62 if (!is_midr_in_range(&entry->midr_range)) 63 return false; 64 65 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 66 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 67 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 68 return false; 69 return true; 70 } 71 72 static bool __maybe_unused 73 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 74 { 75 int i; 76 77 if (!target_impl_cpu_num) { 78 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 79 return __is_affected_midr_range(entry, read_cpuid_id(), 80 read_cpuid(REVIDR_EL1)); 81 } 82 83 for (i = 0; i < target_impl_cpu_num; i++) { 84 if (__is_affected_midr_range(entry, target_impl_cpus[i].midr, 85 target_impl_cpus[i].midr)) 86 return true; 87 } 88 return false; 89 } 90 91 static bool __maybe_unused 92 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 93 int scope) 94 { 95 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 96 return is_midr_in_range_list(entry->midr_range_list); 97 } 98 99 static bool __maybe_unused 100 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 101 { 102 u32 model; 103 104 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 105 106 model = read_cpuid_id(); 107 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 108 MIDR_ARCHITECTURE_MASK; 109 110 return model == entry->midr_range.model; 111 } 112 113 static bool 114 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 115 int scope) 116 { 117 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 118 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 119 u64 ctr_raw, ctr_real; 120 121 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 122 123 /* 124 * We want to make sure that all the CPUs in the system expose 125 * a consistent CTR_EL0 to make sure that applications behaves 126 * correctly with migration. 127 * 128 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 129 * 130 * 1) It is safe if the system doesn't support IDC, as CPU anyway 131 * reports IDC = 0, consistent with the rest. 132 * 133 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 134 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 135 * 136 * So, we need to make sure either the raw CTR_EL0 or the effective 137 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 138 */ 139 ctr_raw = read_cpuid_cachetype() & mask; 140 ctr_real = read_cpuid_effective_cachetype() & mask; 141 142 return (ctr_real != sys) && (ctr_raw != sys); 143 } 144 145 #ifdef CONFIG_ARM64_ERRATUM_4311569 146 static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); 147 static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) 148 { 149 static_branch_enable(&arm_si_l1_workaround_4311569); 150 pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 151 152 return 0; 153 } 154 early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); 155 156 /* 157 * We have some earlier use cases to call cache maintenance operation functions, for example, 158 * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this 159 * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its 160 * safe to have the workaround off by default. 161 */ 162 static bool 163 need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope) 164 { 165 return static_branch_unlikely(&arm_si_l1_workaround_4311569); 166 } 167 #endif 168 169 static void 170 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 171 { 172 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 173 bool enable_uct_trap = false; 174 175 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 176 if ((read_cpuid_cachetype() & mask) != 177 (arm64_ftr_reg_ctrel0.sys_val & mask)) 178 enable_uct_trap = true; 179 180 /* ... or if the system is affected by an erratum */ 181 if (cap->capability == ARM64_WORKAROUND_1542419) 182 enable_uct_trap = true; 183 184 if (enable_uct_trap) 185 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 186 } 187 188 #ifdef CONFIG_ARM64_ERRATUM_1463225 189 static bool 190 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 191 int scope) 192 { 193 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 194 } 195 #endif 196 197 static void __maybe_unused 198 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 199 { 200 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 201 } 202 203 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 204 .matches = is_affected_midr_range, \ 205 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 206 207 #define CAP_MIDR_ALL_VERSIONS(model) \ 208 .matches = is_affected_midr_range, \ 209 .midr_range = MIDR_ALL_VERSIONS(model) 210 211 #define MIDR_FIXED(rev, revidr_mask) \ 212 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 213 214 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 215 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 216 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 217 218 #define CAP_MIDR_RANGE_LIST(list) \ 219 .matches = is_affected_midr_range_list, \ 220 .midr_range_list = list 221 222 /* Errata affecting a range of revisions of given model variant */ 223 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 224 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 225 226 /* Errata affecting a single variant/revision of a model */ 227 #define ERRATA_MIDR_REV(model, var, rev) \ 228 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 229 230 /* Errata affecting all variants/revisions of a given a model */ 231 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 232 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 233 CAP_MIDR_ALL_VERSIONS(model) 234 235 /* Errata affecting a list of midr ranges, with same work around */ 236 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 237 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 238 CAP_MIDR_RANGE_LIST(midr_list) 239 240 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 241 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 242 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 243 {}, 244 }; 245 246 static bool __maybe_unused 247 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 248 int scope) 249 { 250 int i; 251 252 if (!is_affected_midr_range_list(entry, scope) || 253 !is_hyp_mode_available()) 254 return false; 255 256 for_each_possible_cpu(i) { 257 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 258 return true; 259 } 260 261 return false; 262 } 263 264 static bool __maybe_unused 265 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 266 int scope) 267 { 268 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 269 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 270 271 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 272 return is_midr_in_range(&range) && has_dic; 273 } 274 275 static const struct midr_range impdef_pmuv3_cpus[] = { 276 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 277 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 278 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 279 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 280 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 281 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 282 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 283 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 284 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 285 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 286 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 287 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 288 {}, 289 }; 290 291 static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 292 { 293 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 294 unsigned int pmuver; 295 296 if (!is_kernel_in_hyp_mode()) 297 return false; 298 299 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 300 ID_AA64DFR0_EL1_PMUVer_SHIFT); 301 if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 302 return false; 303 304 return is_midr_in_range_list(impdef_pmuv3_cpus); 305 } 306 307 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused) 308 { 309 sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56)); 310 } 311 312 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 313 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 314 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 315 { 316 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 317 }, 318 { 319 .midr_range.model = MIDR_QCOM_KRYO, 320 .matches = is_kryo_midr, 321 }, 322 #endif 323 #ifdef CONFIG_ARM64_ERRATUM_1286807 324 { 325 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 326 }, 327 { 328 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 329 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 330 }, 331 #endif 332 #ifdef CONFIG_ARM64_ERRATUM_2441007 333 { 334 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 335 }, 336 #endif 337 #ifdef CONFIG_ARM64_ERRATUM_2441009 338 { 339 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 340 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 341 }, 342 #endif 343 #ifdef CONFIG_ARM64_ERRATUM_4118414 344 { 345 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 346 MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM), 347 MIDR_ALL_VERSIONS(MIDR_C1_ULTRA), 348 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 349 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), 350 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 351 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 352 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), 353 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 354 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 355 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 356 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 357 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 358 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 359 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 360 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 361 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 362 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 363 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 364 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 365 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 366 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 367 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 368 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 369 {} 370 })), 371 }, 372 #endif 373 {} 374 }; 375 #endif 376 377 #ifdef CONFIG_CAVIUM_ERRATUM_23154 378 static const struct midr_range cavium_erratum_23154_cpus[] = { 379 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 380 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 381 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 382 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 383 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 384 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 385 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 386 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 387 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 388 {}, 389 }; 390 #endif 391 392 #ifdef CONFIG_CAVIUM_ERRATUM_27456 393 static const struct midr_range cavium_erratum_27456_cpus[] = { 394 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 395 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 396 /* Cavium ThunderX, T81 pass 1.0 */ 397 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 398 {}, 399 }; 400 #endif 401 402 #ifdef CONFIG_CAVIUM_ERRATUM_30115 403 static const struct midr_range cavium_erratum_30115_cpus[] = { 404 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 405 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 406 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 407 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 408 /* Cavium ThunderX, T83 pass 1.0 */ 409 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 410 {}, 411 }; 412 #endif 413 414 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 415 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 416 { 417 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 418 }, 419 { 420 .midr_range.model = MIDR_QCOM_KRYO, 421 .matches = is_kryo_midr, 422 }, 423 {}, 424 }; 425 #endif 426 427 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 428 static const struct midr_range workaround_clean_cache[] = { 429 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 430 defined(CONFIG_ARM64_ERRATUM_827319) || \ 431 defined(CONFIG_ARM64_ERRATUM_824069) 432 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 433 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 434 #endif 435 #ifdef CONFIG_ARM64_ERRATUM_819472 436 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 437 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 438 #endif 439 {}, 440 }; 441 #endif 442 443 #ifdef CONFIG_ARM64_ERRATUM_1418040 444 /* 445 * - 1188873 affects r0p0 to r2p0 446 * - 1418040 affects r0p0 to r3p1 447 */ 448 static const struct midr_range erratum_1418040_list[] = { 449 /* Cortex-A76 r0p0 to r3p1 */ 450 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 451 /* Neoverse-N1 r0p0 to r3p1 */ 452 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 453 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 454 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 455 {}, 456 }; 457 #endif 458 459 #ifdef CONFIG_ARM64_ERRATUM_845719 460 static const struct midr_range erratum_845719_list[] = { 461 /* Cortex-A53 r0p[01234] */ 462 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 463 /* Brahma-B53 r0p[0] */ 464 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 465 /* Kryo2XX Silver rAp4 */ 466 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 467 {}, 468 }; 469 #endif 470 471 #ifdef CONFIG_ARM64_ERRATUM_843419 472 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 473 { 474 /* Cortex-A53 r0p[01234] */ 475 .matches = is_affected_midr_range, 476 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 477 MIDR_FIXED(0x4, BIT(8)), 478 }, 479 { 480 /* Brahma-B53 r0p[0] */ 481 .matches = is_affected_midr_range, 482 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 483 }, 484 {}, 485 }; 486 #endif 487 488 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 489 static const struct midr_range erratum_speculative_at_list[] = { 490 #ifdef CONFIG_ARM64_ERRATUM_1165522 491 /* Cortex A76 r0p0 to r2p0 */ 492 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 493 #endif 494 #ifdef CONFIG_ARM64_ERRATUM_1319367 495 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 496 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 497 #endif 498 #ifdef CONFIG_ARM64_ERRATUM_1530923 499 /* Cortex A55 r0p0 to r2p0 */ 500 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 501 /* Kryo4xx Silver (rdpe => r1p0) */ 502 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 503 #endif 504 {}, 505 }; 506 #endif 507 508 #ifdef CONFIG_ARM64_ERRATUM_1463225 509 static const struct midr_range erratum_1463225[] = { 510 /* Cortex-A76 r0p0 - r3p1 */ 511 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 512 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 513 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 514 {}, 515 }; 516 #endif 517 518 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 519 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 520 #ifdef CONFIG_ARM64_ERRATUM_2139208 521 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 522 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 523 #endif 524 #ifdef CONFIG_ARM64_ERRATUM_2119858 525 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 526 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 527 #endif 528 {}, 529 }; 530 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 531 532 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 533 static const struct midr_range tsb_flush_fail_cpus[] = { 534 #ifdef CONFIG_ARM64_ERRATUM_2067961 535 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 536 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 537 #endif 538 #ifdef CONFIG_ARM64_ERRATUM_2054223 539 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 540 #endif 541 {}, 542 }; 543 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 544 545 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 546 static struct midr_range trbe_write_out_of_range_cpus[] = { 547 #ifdef CONFIG_ARM64_ERRATUM_2253138 548 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 549 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 550 #endif 551 #ifdef CONFIG_ARM64_ERRATUM_2224489 552 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 553 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 554 #endif 555 {}, 556 }; 557 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 558 559 #ifdef CONFIG_ARM64_ERRATUM_1742098 560 static struct midr_range broken_aarch32_aes[] = { 561 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 562 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 563 {}, 564 }; 565 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 566 567 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 568 static const struct midr_range erratum_spec_unpriv_load_list[] = { 569 #ifdef CONFIG_ARM64_ERRATUM_3117295 570 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), 571 #endif 572 #ifdef CONFIG_ARM64_ERRATUM_2966298 573 /* Cortex-A520 r0p0 to r0p1 */ 574 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), 575 #endif 576 {}, 577 }; 578 #endif 579 580 #ifdef CONFIG_ARM64_ERRATUM_3194386 581 static const struct midr_range erratum_spec_ssbs_list[] = { 582 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 583 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 584 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 585 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 586 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 587 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 588 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), 589 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 590 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 591 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 592 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 593 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 594 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 595 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 596 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 597 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 598 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 599 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 600 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 601 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 602 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 603 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 604 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 605 {} 606 }; 607 #endif 608 609 #ifdef CONFIG_ARM64_ERRATUM_4193714 610 static bool has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities *entry, 611 int scope) 612 { 613 if (!id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) 614 return false; 615 616 return is_affected_midr_range(entry, scope); 617 } 618 619 static void cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities *__unused) 620 { 621 if (this_cpu_has_cap(ARM64_WORKAROUND_4193714)) 622 sme_enable_dvmsync(); 623 } 624 #endif 625 626 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 627 static const struct midr_range erratum_ac03_cpu_38_list[] = { 628 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 629 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 630 {}, 631 }; 632 #endif 633 634 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 635 static const struct midr_range erratum_ac04_cpu_23_list[] = { 636 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 637 {}, 638 }; 639 #endif 640 641 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 642 static const struct midr_range cnp_erratum_cpus[] = { 643 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 644 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 645 #endif 646 #ifdef CONFIG_HISILICON_ERRATUM_162100125 647 MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), 648 #endif 649 {}, 650 }; 651 #endif 652 653 const struct arm64_cpu_capabilities arm64_errata[] = { 654 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 655 { 656 .desc = "ARM errata 826319, 827319, 824069, or 819472", 657 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 658 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 659 .cpu_enable = cpu_enable_cache_maint_trap, 660 }, 661 #endif 662 #ifdef CONFIG_ARM64_ERRATUM_832075 663 { 664 /* Cortex-A57 r0p0 - r1p2 */ 665 .desc = "ARM erratum 832075", 666 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 667 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 668 0, 0, 669 1, 2), 670 }, 671 #endif 672 #ifdef CONFIG_ARM64_ERRATUM_834220 673 { 674 /* Cortex-A57 r0p0 - r1p2 */ 675 .desc = "ARM erratum 834220", 676 .capability = ARM64_WORKAROUND_834220, 677 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 678 0, 0, 679 1, 2), 680 }, 681 #endif 682 #ifdef CONFIG_ARM64_ERRATUM_843419 683 { 684 .desc = "ARM erratum 843419", 685 .capability = ARM64_WORKAROUND_843419, 686 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 687 .matches = cpucap_multi_entry_cap_matches, 688 .match_list = erratum_843419_list, 689 }, 690 #endif 691 #ifdef CONFIG_ARM64_ERRATUM_845719 692 { 693 .desc = "ARM erratum 845719", 694 .capability = ARM64_WORKAROUND_845719, 695 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 696 }, 697 #endif 698 #ifdef CONFIG_CAVIUM_ERRATUM_23154 699 { 700 .desc = "Cavium errata 23154 and 38545", 701 .capability = ARM64_WORKAROUND_CAVIUM_23154, 702 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 703 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 704 }, 705 #endif 706 #ifdef CONFIG_CAVIUM_ERRATUM_27456 707 { 708 .desc = "Cavium erratum 27456", 709 .capability = ARM64_WORKAROUND_CAVIUM_27456, 710 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 711 }, 712 #endif 713 #ifdef CONFIG_CAVIUM_ERRATUM_30115 714 { 715 .desc = "Cavium erratum 30115", 716 .capability = ARM64_WORKAROUND_CAVIUM_30115, 717 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 718 }, 719 #endif 720 { 721 .desc = "Mismatched cache type (CTR_EL0)", 722 .capability = ARM64_MISMATCHED_CACHE_TYPE, 723 .matches = has_mismatched_cache_type, 724 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 725 .cpu_enable = cpu_enable_trap_ctr_access, 726 }, 727 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 728 { 729 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 730 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 731 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 732 .matches = cpucap_multi_entry_cap_matches, 733 .match_list = qcom_erratum_1003_list, 734 }, 735 #endif 736 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI 737 { 738 .desc = "Broken broadcast TLBI completion", 739 .capability = ARM64_WORKAROUND_REPEAT_TLBI, 740 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 741 .matches = cpucap_multi_entry_cap_matches, 742 .match_list = arm64_repeat_tlbi_list, 743 }, 744 #endif 745 #ifdef CONFIG_ARM64_ERRATUM_858921 746 { 747 /* Cortex-A73 all versions */ 748 .desc = "ARM erratum 858921", 749 .capability = ARM64_WORKAROUND_858921, 750 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 751 }, 752 #endif 753 { 754 .desc = "Spectre-v2", 755 .capability = ARM64_SPECTRE_V2, 756 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 757 .matches = has_spectre_v2, 758 .cpu_enable = spectre_v2_enable_mitigation, 759 }, 760 #ifdef CONFIG_RANDOMIZE_BASE 761 { 762 /* Must come after the Spectre-v2 entry */ 763 .desc = "Spectre-v3a", 764 .capability = ARM64_SPECTRE_V3A, 765 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 766 .matches = has_spectre_v3a, 767 .cpu_enable = spectre_v3a_enable_mitigation, 768 }, 769 #endif 770 { 771 .desc = "Spectre-v4", 772 .capability = ARM64_SPECTRE_V4, 773 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 774 .matches = has_spectre_v4, 775 .cpu_enable = spectre_v4_enable_mitigation, 776 }, 777 { 778 .desc = "Spectre-BHB", 779 .capability = ARM64_SPECTRE_BHB, 780 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 781 .matches = is_spectre_bhb_affected, 782 .cpu_enable = spectre_bhb_enable_mitigation, 783 }, 784 #ifdef CONFIG_ARM64_ERRATUM_1418040 785 { 786 .desc = "ARM erratum 1418040", 787 .capability = ARM64_WORKAROUND_1418040, 788 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 789 /* 790 * We need to allow affected CPUs to come in late, but 791 * also need the non-affected CPUs to be able to come 792 * in at any point in time. Wonderful. 793 */ 794 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 795 }, 796 #endif 797 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 798 { 799 .desc = "ARM errata 1165522, 1319367, or 1530923", 800 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 801 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 802 }, 803 #endif 804 #ifdef CONFIG_ARM64_ERRATUM_1463225 805 { 806 .desc = "ARM erratum 1463225", 807 .capability = ARM64_WORKAROUND_1463225, 808 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 809 .matches = has_cortex_a76_erratum_1463225, 810 .midr_range_list = erratum_1463225, 811 }, 812 #endif 813 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 814 { 815 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 816 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 817 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 818 .matches = needs_tx2_tvm_workaround, 819 }, 820 { 821 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 822 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 823 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 824 }, 825 #endif 826 #ifdef CONFIG_ARM64_ERRATUM_1542419 827 { 828 /* we depend on the firmware portion for correctness */ 829 .desc = "ARM erratum 1542419 (kernel portion)", 830 .capability = ARM64_WORKAROUND_1542419, 831 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 832 .matches = has_neoverse_n1_erratum_1542419, 833 .cpu_enable = cpu_enable_trap_ctr_access, 834 }, 835 #endif 836 #ifdef CONFIG_ARM64_ERRATUM_1508412 837 { 838 /* we depend on the firmware portion for correctness */ 839 .desc = "ARM erratum 1508412 (kernel portion)", 840 .capability = ARM64_WORKAROUND_1508412, 841 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 842 0, 0, 843 1, 0), 844 }, 845 #endif 846 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 847 { 848 .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", 849 .capability = ARM64_WORKAROUND_DISABLE_CNP, 850 ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), 851 }, 852 #endif 853 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 854 { 855 /* 856 * The erratum work around is handled within the TRBE 857 * driver and can be applied per-cpu. So, we can allow 858 * a late CPU to come online with this erratum. 859 */ 860 .desc = "ARM erratum 2119858 or 2139208", 861 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 862 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 863 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 864 }, 865 #endif 866 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 867 { 868 .desc = "ARM erratum 2067961 or 2054223", 869 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 870 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 871 }, 872 #endif 873 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 874 { 875 .desc = "ARM erratum 2253138 or 2224489", 876 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 877 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 878 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 879 }, 880 #endif 881 #ifdef CONFIG_ARM64_ERRATUM_2645198 882 { 883 .desc = "ARM erratum 2645198", 884 .capability = ARM64_WORKAROUND_2645198, 885 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715) 886 }, 887 #endif 888 #ifdef CONFIG_ARM64_ERRATUM_2077057 889 { 890 .desc = "ARM erratum 2077057", 891 .capability = ARM64_WORKAROUND_2077057, 892 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 893 }, 894 #endif 895 #ifdef CONFIG_ARM64_ERRATUM_2064142 896 { 897 .desc = "ARM erratum 2064142", 898 .capability = ARM64_WORKAROUND_2064142, 899 900 /* Cortex-A510 r0p0 - r0p2 */ 901 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 902 }, 903 #endif 904 #ifdef CONFIG_ARM64_ERRATUM_2457168 905 { 906 .desc = "ARM erratum 2457168", 907 .capability = ARM64_WORKAROUND_2457168, 908 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 909 910 /* Cortex-A510 r0p0-r1p1 */ 911 CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1) 912 }, 913 #endif 914 #ifdef CONFIG_ARM64_ERRATUM_2038923 915 { 916 .desc = "ARM erratum 2038923", 917 .capability = ARM64_WORKAROUND_2038923, 918 919 /* Cortex-A510 r0p0 - r0p2 */ 920 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 921 }, 922 #endif 923 #ifdef CONFIG_ARM64_ERRATUM_1902691 924 { 925 .desc = "ARM erratum 1902691", 926 .capability = ARM64_WORKAROUND_1902691, 927 928 /* Cortex-A510 r0p0 - r0p1 */ 929 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 930 }, 931 #endif 932 #ifdef CONFIG_ARM64_ERRATUM_1742098 933 { 934 .desc = "ARM erratum 1742098", 935 .capability = ARM64_WORKAROUND_1742098, 936 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 937 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 938 }, 939 #endif 940 #ifdef CONFIG_ARM64_ERRATUM_2658417 941 { 942 .desc = "ARM erratum 2658417", 943 .capability = ARM64_WORKAROUND_2658417, 944 /* Cortex-A510 r0p0 - r1p1 */ 945 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 946 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), 947 }, 948 #endif 949 #ifdef CONFIG_ARM64_ERRATUM_3194386 950 { 951 .desc = "SSBS not fully self-synchronizing", 952 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, 953 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), 954 }, 955 #endif 956 #ifdef CONFIG_ARM64_ERRATUM_4311569 957 { 958 .capability = ARM64_WORKAROUND_4311569, 959 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 960 .matches = need_arm_si_l1_workaround_4311569, 961 }, 962 #endif 963 #ifdef CONFIG_ARM64_ERRATUM_4193714 964 { 965 .desc = "C1-Pro SME DVMSync early acknowledgement", 966 .capability = ARM64_WORKAROUND_4193714, 967 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 968 .matches = has_sme_dvmsync_erratum, 969 .cpu_enable = cpu_enable_sme_dvmsync, 970 /* C1-Pro r0p0 - r1p2 (the latter only when REVIDR_EL1[0]==0) */ 971 .midr_range = MIDR_RANGE(MIDR_C1_PRO, 0, 0, 1, 2), 972 MIDR_FIXED(MIDR_CPU_VAR_REV(1, 2), BIT(0)), 973 }, 974 #endif 975 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 976 { 977 .desc = "ARM errata 2966298, 3117295", 978 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, 979 /* Cortex-A520 r0p0 - r0p1 */ 980 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list), 981 }, 982 #endif 983 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 984 { 985 .desc = "AmpereOne erratum AC03_CPU_38", 986 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, 987 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list), 988 }, 989 #endif 990 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 991 { 992 .desc = "AmpereOne erratum AC04_CPU_23", 993 .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23, 994 ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list), 995 }, 996 #endif 997 { 998 .desc = "Broken CNTVOFF_EL2", 999 .capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF, 1000 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 1001 MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1), 1002 {} 1003 })), 1004 }, 1005 { 1006 .desc = "Apple IMPDEF PMUv3 Traps", 1007 .capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS, 1008 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 1009 .matches = has_impdef_pmuv3, 1010 .cpu_enable = cpu_enable_impdef_pmuv3_traps, 1011 }, 1012 { 1013 } 1014 }; 1015