1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU specific errata definitions 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/of.h> 10 #include <linux/types.h> 11 #include <linux/cpu.h> 12 #include <asm/cpu.h> 13 #include <asm/cputype.h> 14 #include <asm/cpufeature.h> 15 #include <asm/fpsimd.h> 16 #include <asm/kvm_asm.h> 17 #include <asm/kvm_host.h> 18 #include <asm/smp_plat.h> 19 20 static u64 target_impl_cpu_num; 21 static struct target_impl_cpu *target_impl_cpus; 22 23 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus) 24 { 25 if (target_impl_cpu_num || !num || !impl_cpus) 26 return false; 27 28 target_impl_cpu_num = num; 29 target_impl_cpus = impl_cpus; 30 return true; 31 } 32 33 static inline bool __is_midr_in_range(u32 midr, struct midr_range const *range) 34 { 35 return midr_is_cpu_model_range(midr, range->model, 36 range->rv_min, range->rv_max); 37 } 38 39 static inline bool is_midr_in_range(struct midr_range const *range) 40 { 41 int i; 42 43 if (!target_impl_cpu_num) 44 return __is_midr_in_range(read_cpuid_id(), range); 45 46 for (i = 0; i < target_impl_cpu_num; i++) { 47 if (__is_midr_in_range(target_impl_cpus[i].midr, range)) 48 return true; 49 } 50 return false; 51 } 52 53 bool is_midr_in_range_list(struct midr_range const *ranges) 54 { 55 while (ranges->model) 56 if (is_midr_in_range(ranges++)) 57 return true; 58 return false; 59 } 60 EXPORT_SYMBOL_GPL(is_midr_in_range_list); 61 62 static bool __maybe_unused 63 __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, 64 u32 midr, u32 revidr) 65 { 66 const struct arm64_midr_revidr *fix; 67 if (!__is_midr_in_range(midr, &entry->midr_range)) 68 return false; 69 70 midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK; 71 for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++) 72 if (midr == fix->midr_rv && (revidr & fix->revidr_mask)) 73 return false; 74 return true; 75 } 76 77 static bool __maybe_unused 78 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 79 { 80 int i; 81 82 if (!target_impl_cpu_num) { 83 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 84 return __is_affected_midr_range(entry, read_cpuid_id(), 85 read_cpuid(REVIDR_EL1)); 86 } 87 88 for (i = 0; i < target_impl_cpu_num; i++) { 89 if (__is_affected_midr_range(entry, target_impl_cpus[i].midr, 90 target_impl_cpus[i].revidr)) 91 return true; 92 } 93 return false; 94 } 95 96 static bool __maybe_unused 97 is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry, 98 int scope) 99 { 100 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 101 return is_midr_in_range_list(entry->midr_range_list); 102 } 103 104 static bool __maybe_unused 105 is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope) 106 { 107 u32 model; 108 109 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 110 111 model = read_cpuid_id(); 112 model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) | 113 MIDR_ARCHITECTURE_MASK; 114 115 return model == entry->midr_range.model; 116 } 117 118 static bool 119 has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, 120 int scope) 121 { 122 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 123 u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask; 124 u64 ctr_raw, ctr_real; 125 126 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 127 128 /* 129 * We want to make sure that all the CPUs in the system expose 130 * a consistent CTR_EL0 to make sure that applications behaves 131 * correctly with migration. 132 * 133 * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 : 134 * 135 * 1) It is safe if the system doesn't support IDC, as CPU anyway 136 * reports IDC = 0, consistent with the rest. 137 * 138 * 2) If the system has IDC, it is still safe as we trap CTR_EL0 139 * access on this CPU via the ARM64_HAS_CACHE_IDC capability. 140 * 141 * So, we need to make sure either the raw CTR_EL0 or the effective 142 * CTR_EL0 matches the system's copy to allow a secondary CPU to boot. 143 */ 144 ctr_raw = read_cpuid_cachetype() & mask; 145 ctr_real = read_cpuid_effective_cachetype() & mask; 146 147 return (ctr_real != sys) && (ctr_raw != sys); 148 } 149 150 #ifdef CONFIG_ARM64_ERRATUM_4311569 151 static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); 152 static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) 153 { 154 static_branch_enable(&arm_si_l1_workaround_4311569); 155 pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311569\n"); 156 157 return 0; 158 } 159 early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_4311569_cfg); 160 161 /* 162 * We have some earlier use cases to call cache maintenance operation functions, for example, 163 * dcache_inval_poc() and dcache_clean_poc() in head.S, before making decision to turn on this 164 * workaround. Since the scope of this workaround is limited to non-coherent DMA agents, its 165 * safe to have the workaround off by default. 166 */ 167 static bool 168 need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *entry, int scope) 169 { 170 return static_branch_unlikely(&arm_si_l1_workaround_4311569); 171 } 172 #endif 173 174 static void 175 cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) 176 { 177 u64 mask = arm64_ftr_reg_ctrel0.strict_mask; 178 bool enable_uct_trap = false; 179 180 /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */ 181 if ((read_cpuid_cachetype() & mask) != 182 (arm64_ftr_reg_ctrel0.sys_val & mask)) 183 enable_uct_trap = true; 184 185 /* ... or if the system is affected by an erratum */ 186 if (cap->capability == ARM64_WORKAROUND_1542419) 187 enable_uct_trap = true; 188 189 if (enable_uct_trap) 190 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 191 } 192 193 #ifdef CONFIG_ARM64_ERRATUM_1463225 194 static bool 195 has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry, 196 int scope) 197 { 198 return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode(); 199 } 200 #endif 201 202 static void __maybe_unused 203 cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) 204 { 205 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 206 } 207 208 #ifdef CONFIG_NXP_IMX8QM_ERRATUM_ERR050104 209 static bool 210 is_imx8qm_soc(const struct arm64_cpu_capabilities *entry, int scope) 211 { 212 static const char * const compats[] = { 213 "fsl,imx8qm", 214 "fsl,imx8qp", 215 NULL 216 }; 217 218 return of_machine_compatible_match(compats); 219 } 220 221 static void 222 cpu_enable_imx8qm_err050104(const struct arm64_cpu_capabilities *__unused) 223 { 224 /* Trap the EL0 IC IVAU so that it can be upgraded to IC IALLUIS */ 225 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0); 226 227 /* 228 * TLB maintenance cannot be guaranteed correct for guests, so 229 * disable KVM as if kvm-arm.mode=none was passed on the command line. 230 */ 231 kvm_force_disabled(); 232 } 233 #endif 234 235 #define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 236 .matches = is_affected_midr_range, \ 237 .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max) 238 239 #define CAP_MIDR_ALL_VERSIONS(model) \ 240 .matches = is_affected_midr_range, \ 241 .midr_range = MIDR_ALL_VERSIONS(model) 242 243 #define MIDR_FIXED(rev, revidr_mask) \ 244 .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}} 245 246 #define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \ 247 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 248 CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) 249 250 #define CAP_MIDR_RANGE_LIST(list) \ 251 .matches = is_affected_midr_range_list, \ 252 .midr_range_list = list 253 254 /* Errata affecting a range of revisions of given model variant */ 255 #define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max) \ 256 ERRATA_MIDR_RANGE(m, var, r_min, var, r_max) 257 258 /* Errata affecting a single variant/revision of a model */ 259 #define ERRATA_MIDR_REV(model, var, rev) \ 260 ERRATA_MIDR_RANGE(model, var, rev, var, rev) 261 262 /* Errata affecting all variants/revisions of a given a model */ 263 #define ERRATA_MIDR_ALL_VERSIONS(model) \ 264 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 265 CAP_MIDR_ALL_VERSIONS(model) 266 267 /* Errata affecting a list of midr ranges, with same work around */ 268 #define ERRATA_MIDR_RANGE_LIST(midr_list) \ 269 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, \ 270 CAP_MIDR_RANGE_LIST(midr_list) 271 272 static const __maybe_unused struct midr_range tx2_family_cpus[] = { 273 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 274 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 275 {}, 276 }; 277 278 static bool __maybe_unused 279 needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry, 280 int scope) 281 { 282 int i; 283 284 if (!is_affected_midr_range_list(entry, scope) || 285 !is_hyp_mode_available()) 286 return false; 287 288 for_each_possible_cpu(i) { 289 if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0) 290 return true; 291 } 292 293 return false; 294 } 295 296 static bool __maybe_unused 297 has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 298 int scope) 299 { 300 bool has_dic = read_cpuid_cachetype() & BIT(CTR_EL0_DIC_SHIFT); 301 const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1); 302 303 WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); 304 return is_midr_in_range(&range) && has_dic; 305 } 306 307 static const struct midr_range apple_cpus[] = { 308 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 309 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 310 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 311 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 312 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 313 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 314 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 315 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 316 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 317 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 318 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 319 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 320 {}, 321 }; 322 323 static bool has_impdef_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 324 { 325 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 326 unsigned int pmuver; 327 328 if (!is_kernel_in_hyp_mode()) 329 return false; 330 331 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 332 ID_AA64DFR0_EL1_PMUVer_SHIFT); 333 if (pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 334 return false; 335 336 return is_midr_in_range_list(apple_cpus); 337 } 338 339 static bool has_broken_gic_v3_seis(const struct arm64_cpu_capabilities *entry, int scope) 340 { 341 return (is_kernel_in_hyp_mode() && 342 is_midr_in_range_list(apple_cpus) && 343 (read_sysreg_s(SYS_ICH_VTR_EL2) & ICH_VTR_EL2_SEIS)); 344 } 345 346 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilities *__unused) 347 { 348 sysreg_clear_set_s(SYS_HACR_EL2, 0, BIT(56)); 349 } 350 351 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 352 static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 353 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 354 { 355 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0) 356 }, 357 { 358 .midr_range.model = MIDR_QCOM_KRYO, 359 .matches = is_kryo_midr, 360 }, 361 #endif 362 #ifdef CONFIG_ARM64_ERRATUM_1286807 363 { 364 ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), 365 }, 366 { 367 /* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */ 368 ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), 369 }, 370 #endif 371 #ifdef CONFIG_ARM64_ERRATUM_2441007 372 { 373 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 374 }, 375 #endif 376 #ifdef CONFIG_ARM64_ERRATUM_2441009 377 { 378 /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */ 379 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 380 }, 381 #endif 382 #ifdef CONFIG_ARM64_ERRATUM_4118414 383 { 384 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 385 MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM), 386 MIDR_ALL_VERSIONS(MIDR_C1_ULTRA), 387 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 388 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), 389 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 390 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 391 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), 392 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 393 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 394 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 395 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 396 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 397 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 398 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 399 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 400 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 401 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 402 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 403 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 404 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 405 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 406 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 407 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 408 {} 409 })), 410 }, 411 #endif 412 {} 413 }; 414 #endif 415 416 #ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 417 static const struct midr_range workaround_amu_constcnt_list[] = { 418 #ifdef CONFIG_ARM64_ERRATUM_2457168 419 /* Cortex-A510 r0p0-r1p1 */ 420 MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 421 #endif 422 #ifdef CONFIG_ARM64_ERRATUM_3821522 423 /* Cortex-A725 r0p0 - r0p2 */ 424 MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2), 425 #endif 426 {} 427 }; 428 #endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */ 429 430 #ifdef CONFIG_CAVIUM_ERRATUM_23154 431 static const struct midr_range cavium_erratum_23154_cpus[] = { 432 MIDR_ALL_VERSIONS(MIDR_THUNDERX), 433 MIDR_ALL_VERSIONS(MIDR_THUNDERX_81XX), 434 MIDR_ALL_VERSIONS(MIDR_THUNDERX_83XX), 435 MIDR_ALL_VERSIONS(MIDR_OCTX2_98XX), 436 MIDR_ALL_VERSIONS(MIDR_OCTX2_96XX), 437 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XX), 438 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXN), 439 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXMM), 440 MIDR_ALL_VERSIONS(MIDR_OCTX2_95XXO), 441 {}, 442 }; 443 #endif 444 445 #ifdef CONFIG_CAVIUM_ERRATUM_27456 446 static const struct midr_range cavium_erratum_27456_cpus[] = { 447 /* Cavium ThunderX, T88 pass 1.x - 2.1 */ 448 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1), 449 /* Cavium ThunderX, T81 pass 1.0 */ 450 MIDR_REV(MIDR_THUNDERX_81XX, 0, 0), 451 {}, 452 }; 453 #endif 454 455 #ifdef CONFIG_CAVIUM_ERRATUM_30115 456 static const struct midr_range cavium_erratum_30115_cpus[] = { 457 /* Cavium ThunderX, T88 pass 1.x - 2.2 */ 458 MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2), 459 /* Cavium ThunderX, T81 pass 1.0 - 1.2 */ 460 MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2), 461 /* Cavium ThunderX, T83 pass 1.0 */ 462 MIDR_REV(MIDR_THUNDERX_83XX, 0, 0), 463 {}, 464 }; 465 #endif 466 467 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 468 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { 469 { 470 ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0), 471 }, 472 { 473 .midr_range.model = MIDR_QCOM_KRYO, 474 .matches = is_kryo_midr, 475 }, 476 {}, 477 }; 478 #endif 479 480 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 481 static const struct midr_range workaround_clean_cache[] = { 482 #if defined(CONFIG_ARM64_ERRATUM_826319) || \ 483 defined(CONFIG_ARM64_ERRATUM_827319) || \ 484 defined(CONFIG_ARM64_ERRATUM_824069) 485 /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */ 486 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2), 487 #endif 488 #ifdef CONFIG_ARM64_ERRATUM_819472 489 /* Cortex-A53 r0p[01] : ARM errata 819472 */ 490 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1), 491 #endif 492 {}, 493 }; 494 #endif 495 496 #ifdef CONFIG_ARM64_ERRATUM_1418040 497 /* 498 * - 1188873 affects r0p0 to r2p0 499 * - 1418040 affects r0p0 to r3p1 500 */ 501 static const struct midr_range erratum_1418040_list[] = { 502 /* Cortex-A76 r0p0 to r3p1 */ 503 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 504 /* Neoverse-N1 r0p0 to r3p1 */ 505 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1), 506 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 507 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 508 {}, 509 }; 510 #endif 511 512 #ifdef CONFIG_ARM64_ERRATUM_845719 513 static const struct midr_range erratum_845719_list[] = { 514 /* Cortex-A53 r0p[01234] */ 515 MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 516 /* Brahma-B53 r0p[0] */ 517 MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 518 /* Kryo2XX Silver rAp4 */ 519 MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4), 520 {}, 521 }; 522 #endif 523 524 #ifdef CONFIG_ARM64_ERRATUM_843419 525 static const struct arm64_cpu_capabilities erratum_843419_list[] = { 526 { 527 /* Cortex-A53 r0p[01234] */ 528 .matches = is_affected_midr_range, 529 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4), 530 MIDR_FIXED(0x4, BIT(8)), 531 }, 532 { 533 /* Brahma-B53 r0p[0] */ 534 .matches = is_affected_midr_range, 535 ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0), 536 }, 537 {}, 538 }; 539 #endif 540 541 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 542 static const struct midr_range erratum_speculative_at_list[] = { 543 #ifdef CONFIG_ARM64_ERRATUM_1165522 544 /* Cortex A76 r0p0 to r2p0 */ 545 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0), 546 #endif 547 #ifdef CONFIG_ARM64_ERRATUM_1319367 548 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 549 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 550 #endif 551 #ifdef CONFIG_ARM64_ERRATUM_1530923 552 /* Cortex A55 r0p0 to r2p0 */ 553 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0), 554 /* Kryo4xx Silver (rdpe => r1p0) */ 555 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 556 #endif 557 {}, 558 }; 559 #endif 560 561 #ifdef CONFIG_ARM64_ERRATUM_1463225 562 static const struct midr_range erratum_1463225[] = { 563 /* Cortex-A76 r0p0 - r3p1 */ 564 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1), 565 /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */ 566 MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf), 567 {}, 568 }; 569 #endif 570 571 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 572 static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { 573 #ifdef CONFIG_ARM64_ERRATUM_2139208 574 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 575 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 576 #endif 577 #ifdef CONFIG_ARM64_ERRATUM_2119858 578 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 579 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 580 #endif 581 {}, 582 }; 583 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ 584 585 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 586 static const struct midr_range tsb_flush_fail_cpus[] = { 587 #ifdef CONFIG_ARM64_ERRATUM_2067961 588 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 589 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 590 #endif 591 #ifdef CONFIG_ARM64_ERRATUM_2054223 592 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 593 #endif 594 {}, 595 }; 596 #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ 597 598 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 599 static struct midr_range trbe_write_out_of_range_cpus[] = { 600 #ifdef CONFIG_ARM64_ERRATUM_2253138 601 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 602 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 603 #endif 604 #ifdef CONFIG_ARM64_ERRATUM_2224489 605 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 606 MIDR_RANGE(MIDR_CORTEX_X2, 0, 0, 2, 0), 607 #endif 608 {}, 609 }; 610 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 611 612 #ifdef CONFIG_ARM64_ERRATUM_1742098 613 static struct midr_range broken_aarch32_aes[] = { 614 MIDR_RANGE(MIDR_CORTEX_A57, 0, 1, 0xf, 0xf), 615 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 616 {}, 617 }; 618 #endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */ 619 620 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 621 static const struct midr_range erratum_spec_unpriv_load_list[] = { 622 #ifdef CONFIG_ARM64_ERRATUM_3117295 623 MIDR_ALL_VERSIONS(MIDR_CORTEX_A510), 624 #endif 625 #ifdef CONFIG_ARM64_ERRATUM_2966298 626 /* Cortex-A520 r0p0 to r0p1 */ 627 MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1), 628 #endif 629 {}, 630 }; 631 #endif 632 633 #ifdef CONFIG_ARM64_ERRATUM_3194386 634 static const struct midr_range erratum_spec_ssbs_list[] = { 635 MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), 636 MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), 637 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), 638 MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), 639 MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), 640 MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), 641 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), 642 MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), 643 MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), 644 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), 645 MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C), 646 MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), 647 MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), 648 MIDR_ALL_VERSIONS(MIDR_CORTEX_X4), 649 MIDR_ALL_VERSIONS(MIDR_CORTEX_X925), 650 MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), 651 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), 652 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), 653 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), 654 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), 655 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), 656 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), 657 MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE), 658 {} 659 }; 660 #endif 661 662 #ifdef CONFIG_ARM64_ERRATUM_4193714 663 static bool has_sme_dvmsync_erratum(const struct arm64_cpu_capabilities *entry, 664 int scope) 665 { 666 if (!id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) 667 return false; 668 669 return is_affected_midr_range(entry, scope); 670 } 671 672 static void cpu_enable_sme_dvmsync(const struct arm64_cpu_capabilities *__unused) 673 { 674 if (this_cpu_has_cap(ARM64_WORKAROUND_4193714)) 675 sme_enable_dvmsync(); 676 } 677 #endif 678 679 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 680 static const struct midr_range erratum_ac03_cpu_38_list[] = { 681 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 682 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 683 {}, 684 }; 685 #endif 686 687 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 688 static const struct midr_range erratum_ac04_cpu_23_list[] = { 689 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 690 {}, 691 }; 692 #endif 693 694 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 695 static const struct midr_range cnp_erratum_cpus[] = { 696 #ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM 697 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 698 #endif 699 #ifdef CONFIG_HISILICON_ERRATUM_162100125 700 MIDR_ALL_VERSIONS(MIDR_HISI_HIP09), 701 #endif 702 {}, 703 }; 704 #endif 705 706 const struct arm64_cpu_capabilities arm64_errata[] = { 707 #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE 708 { 709 .desc = "ARM errata 826319, 827319, 824069, or 819472", 710 .capability = ARM64_WORKAROUND_CLEAN_CACHE, 711 ERRATA_MIDR_RANGE_LIST(workaround_clean_cache), 712 .cpu_enable = cpu_enable_cache_maint_trap, 713 }, 714 #endif 715 #ifdef CONFIG_ARM64_ERRATUM_832075 716 { 717 /* Cortex-A57 r0p0 - r1p2 */ 718 .desc = "ARM erratum 832075", 719 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, 720 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 721 0, 0, 722 1, 2), 723 }, 724 #endif 725 #ifdef CONFIG_ARM64_ERRATUM_834220 726 { 727 /* Cortex-A57 r0p0 - r1p2 */ 728 .desc = "ARM erratum 834220", 729 .capability = ARM64_WORKAROUND_834220, 730 ERRATA_MIDR_RANGE(MIDR_CORTEX_A57, 731 0, 0, 732 1, 2), 733 }, 734 #endif 735 #ifdef CONFIG_ARM64_ERRATUM_843419 736 { 737 .desc = "ARM erratum 843419", 738 .capability = ARM64_WORKAROUND_843419, 739 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 740 .matches = cpucap_multi_entry_cap_matches, 741 .match_list = erratum_843419_list, 742 }, 743 #endif 744 #ifdef CONFIG_ARM64_ERRATUM_845719 745 { 746 .desc = "ARM erratum 845719", 747 .capability = ARM64_WORKAROUND_845719, 748 ERRATA_MIDR_RANGE_LIST(erratum_845719_list), 749 }, 750 #endif 751 #ifdef CONFIG_CAVIUM_ERRATUM_23154 752 { 753 .desc = "Cavium errata 23154 and 38545", 754 .capability = ARM64_WORKAROUND_CAVIUM_23154, 755 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 756 ERRATA_MIDR_RANGE_LIST(cavium_erratum_23154_cpus), 757 }, 758 #endif 759 #ifdef CONFIG_CAVIUM_ERRATUM_27456 760 { 761 .desc = "Cavium erratum 27456", 762 .capability = ARM64_WORKAROUND_CAVIUM_27456, 763 ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus), 764 }, 765 #endif 766 #ifdef CONFIG_CAVIUM_ERRATUM_30115 767 { 768 .desc = "Cavium erratum 30115", 769 .capability = ARM64_WORKAROUND_CAVIUM_30115, 770 ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus), 771 }, 772 #endif 773 { 774 .desc = "Mismatched cache type (CTR_EL0)", 775 .capability = ARM64_MISMATCHED_CACHE_TYPE, 776 .matches = has_mismatched_cache_type, 777 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 778 .cpu_enable = cpu_enable_trap_ctr_access, 779 }, 780 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 781 { 782 .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", 783 .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, 784 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 785 .matches = cpucap_multi_entry_cap_matches, 786 .match_list = qcom_erratum_1003_list, 787 }, 788 #endif 789 #ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI_SYNC 790 { 791 .desc = "Broken broadcast TLBI completion", 792 .capability = ARM64_WORKAROUND_REPEAT_TLBI_SYNC, 793 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 794 .matches = cpucap_multi_entry_cap_matches, 795 .match_list = arm64_repeat_tlbi_list, 796 }, 797 #endif 798 #ifdef CONFIG_ARM64_ERRATUM_858921 799 { 800 /* Cortex-A73 all versions */ 801 .desc = "ARM erratum 858921", 802 .capability = ARM64_WORKAROUND_858921, 803 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 804 }, 805 #endif 806 { 807 .desc = "Spectre-v2", 808 .capability = ARM64_SPECTRE_V2, 809 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 810 .matches = has_spectre_v2, 811 .cpu_enable = spectre_v2_enable_mitigation, 812 }, 813 #ifdef CONFIG_RANDOMIZE_BASE 814 { 815 /* Must come after the Spectre-v2 entry */ 816 .desc = "Spectre-v3a", 817 .capability = ARM64_SPECTRE_V3A, 818 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 819 .matches = has_spectre_v3a, 820 .cpu_enable = spectre_v3a_enable_mitigation, 821 }, 822 #endif 823 { 824 .desc = "Spectre-v4", 825 .capability = ARM64_SPECTRE_V4, 826 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 827 .matches = has_spectre_v4, 828 .cpu_enable = spectre_v4_enable_mitigation, 829 }, 830 { 831 .desc = "Spectre-BHB", 832 .capability = ARM64_SPECTRE_BHB, 833 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 834 .matches = is_spectre_bhb_affected, 835 .cpu_enable = spectre_bhb_enable_mitigation, 836 }, 837 #ifdef CONFIG_ARM64_ERRATUM_1418040 838 { 839 .desc = "ARM erratum 1418040", 840 .capability = ARM64_WORKAROUND_1418040, 841 ERRATA_MIDR_RANGE_LIST(erratum_1418040_list), 842 /* 843 * We need to allow affected CPUs to come in late, but 844 * also need the non-affected CPUs to be able to come 845 * in at any point in time. Wonderful. 846 */ 847 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 848 }, 849 #endif 850 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT 851 { 852 .desc = "ARM errata 1165522, 1319367, or 1530923", 853 .capability = ARM64_WORKAROUND_SPECULATIVE_AT, 854 ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list), 855 }, 856 #endif 857 #ifdef CONFIG_ARM64_ERRATUM_1463225 858 { 859 .desc = "ARM erratum 1463225", 860 .capability = ARM64_WORKAROUND_1463225, 861 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 862 .matches = has_cortex_a76_erratum_1463225, 863 .midr_range_list = erratum_1463225, 864 }, 865 #endif 866 #ifdef CONFIG_CAVIUM_TX2_ERRATUM_219 867 { 868 .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)", 869 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM, 870 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 871 .matches = needs_tx2_tvm_workaround, 872 }, 873 { 874 .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)", 875 .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM, 876 ERRATA_MIDR_RANGE_LIST(tx2_family_cpus), 877 }, 878 #endif 879 #ifdef CONFIG_ARM64_ERRATUM_1542419 880 { 881 /* we depend on the firmware portion for correctness */ 882 .desc = "ARM erratum 1542419 (kernel portion)", 883 .capability = ARM64_WORKAROUND_1542419, 884 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 885 .matches = has_neoverse_n1_erratum_1542419, 886 .cpu_enable = cpu_enable_trap_ctr_access, 887 }, 888 #endif 889 #ifdef CONFIG_ARM64_ERRATUM_1508412 890 { 891 /* we depend on the firmware portion for correctness */ 892 .desc = "ARM erratum 1508412 (kernel portion)", 893 .capability = ARM64_WORKAROUND_1508412, 894 ERRATA_MIDR_RANGE(MIDR_CORTEX_A77, 895 0, 0, 896 1, 0), 897 }, 898 #endif 899 #ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP 900 { 901 .desc = "NVIDIA Carmel CNP erratum, or Hisilicon erratum 162100125", 902 .capability = ARM64_WORKAROUND_DISABLE_CNP, 903 ERRATA_MIDR_RANGE_LIST(cnp_erratum_cpus), 904 }, 905 #endif 906 #ifdef CONFIG_NVIDIA_OLYMPUS_1027_ERRATUM 907 { 908 /* NVIDIA Olympus core */ 909 .desc = "NVIDIA Olympus device store/load ordering erratum", 910 .capability = ARM64_WORKAROUND_NVIDIA_OLYMPUS_1027, 911 ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 912 }, 913 #endif 914 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 915 { 916 /* 917 * The erratum work around is handled within the TRBE 918 * driver and can be applied per-cpu. So, we can allow 919 * a late CPU to come online with this erratum. 920 */ 921 .desc = "ARM erratum 2119858 or 2139208", 922 .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, 923 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 924 CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), 925 }, 926 #endif 927 #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE 928 { 929 .desc = "ARM erratum 2067961 or 2054223", 930 .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, 931 ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), 932 }, 933 #endif 934 #ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 935 { 936 .desc = "ARM erratum 2253138 or 2224489", 937 .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, 938 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 939 CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus), 940 }, 941 #endif 942 #ifdef CONFIG_ARM64_ERRATUM_2645198 943 { 944 .desc = "ARM erratum 2645198", 945 .capability = ARM64_WORKAROUND_2645198, 946 ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A715) 947 }, 948 #endif 949 #ifdef CONFIG_ARM64_ERRATUM_2077057 950 { 951 .desc = "ARM erratum 2077057", 952 .capability = ARM64_WORKAROUND_2077057, 953 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 954 }, 955 #endif 956 #ifdef CONFIG_ARM64_ERRATUM_2064142 957 { 958 .desc = "ARM erratum 2064142", 959 .capability = ARM64_WORKAROUND_2064142, 960 961 /* Cortex-A510 r0p0 - r0p2 */ 962 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 963 }, 964 #endif 965 #ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT 966 { 967 .desc = "Broken AMU AMEVCNTR01 (const counter)", 968 .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT, 969 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 970 CAP_MIDR_RANGE_LIST(workaround_amu_constcnt_list) 971 }, 972 #endif 973 #ifdef CONFIG_ARM64_ERRATUM_2038923 974 { 975 .desc = "ARM erratum 2038923", 976 .capability = ARM64_WORKAROUND_2038923, 977 978 /* Cortex-A510 r0p0 - r0p2 */ 979 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) 980 }, 981 #endif 982 #ifdef CONFIG_ARM64_ERRATUM_1902691 983 { 984 .desc = "ARM erratum 1902691", 985 .capability = ARM64_WORKAROUND_1902691, 986 987 /* Cortex-A510 r0p0 - r0p1 */ 988 ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) 989 }, 990 #endif 991 #ifdef CONFIG_ARM64_ERRATUM_1742098 992 { 993 .desc = "ARM erratum 1742098", 994 .capability = ARM64_WORKAROUND_1742098, 995 CAP_MIDR_RANGE_LIST(broken_aarch32_aes), 996 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 997 }, 998 #endif 999 #ifdef CONFIG_ARM64_ERRATUM_2658417 1000 { 1001 .desc = "ARM erratum 2658417", 1002 .capability = ARM64_WORKAROUND_2658417, 1003 /* Cortex-A510 r0p0 - r1p1 */ 1004 ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1), 1005 MIDR_FIXED(MIDR_CPU_VAR_REV(1,1), BIT(25)), 1006 }, 1007 #endif 1008 #ifdef CONFIG_ARM64_ERRATUM_3194386 1009 { 1010 .desc = "SSBS not fully self-synchronizing", 1011 .capability = ARM64_WORKAROUND_SPECULATIVE_SSBS, 1012 ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), 1013 }, 1014 #endif 1015 #ifdef CONFIG_ARM64_ERRATUM_4311569 1016 { 1017 .capability = ARM64_WORKAROUND_4311569, 1018 .type = ARM64_CPUCAP_SOC_ERRATUM, 1019 .matches = need_arm_si_l1_workaround_4311569, 1020 }, 1021 #endif 1022 #ifdef CONFIG_ARM64_ERRATUM_4193714 1023 { 1024 .desc = "C1-Pro SME DVMSync early acknowledgement", 1025 .capability = ARM64_WORKAROUND_4193714, 1026 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 1027 .matches = has_sme_dvmsync_erratum, 1028 .cpu_enable = cpu_enable_sme_dvmsync, 1029 /* C1-Pro r0p0 - r1p2 (the latter only when REVIDR_EL1[0]==0) */ 1030 .midr_range = MIDR_RANGE(MIDR_C1_PRO, 0, 0, 1, 2), 1031 MIDR_FIXED(MIDR_CPU_VAR_REV(1, 2), BIT(0)), 1032 }, 1033 #endif 1034 #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1035 { 1036 .desc = "ARM errata 2966298, 3117295", 1037 .capability = ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD, 1038 /* Cortex-A520 r0p0 - r0p1 */ 1039 ERRATA_MIDR_RANGE_LIST(erratum_spec_unpriv_load_list), 1040 }, 1041 #endif 1042 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38 1043 { 1044 .desc = "AmpereOne erratum AC03_CPU_38", 1045 .capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38, 1046 ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list), 1047 }, 1048 #endif 1049 #ifdef CONFIG_AMPERE_ERRATUM_AC04_CPU_23 1050 { 1051 .desc = "AmpereOne erratum AC04_CPU_23", 1052 .capability = ARM64_WORKAROUND_AMPERE_AC04_CPU_23, 1053 ERRATA_MIDR_RANGE_LIST(erratum_ac04_cpu_23_list), 1054 }, 1055 #endif 1056 { 1057 .desc = "Broken CNTVOFF_EL2", 1058 .capability = ARM64_WORKAROUND_QCOM_ORYON_CNTVOFF, 1059 ERRATA_MIDR_RANGE_LIST(((const struct midr_range[]) { 1060 MIDR_ALL_VERSIONS(MIDR_QCOM_ORYON_X1), 1061 {} 1062 })), 1063 }, 1064 { 1065 .desc = "Apple IMPDEF PMUv3 Traps", 1066 .capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS, 1067 .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, 1068 .matches = has_impdef_pmuv3, 1069 .cpu_enable = cpu_enable_impdef_pmuv3_traps, 1070 }, 1071 { 1072 .desc = "Known broken GICv3 SEIS implementation", 1073 .capability = ARM64_WORKAROUND_GICv3_BROKEN_SEIS, 1074 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 1075 .matches = has_broken_gic_v3_seis, 1076 }, 1077 #ifdef CONFIG_NXP_IMX8QM_ERRATUM_ERR050104 1078 { 1079 .desc = "NXP erratum ERR050104", 1080 .capability = ARM64_WORKAROUND_NXP_ERR050104, 1081 .type = ARM64_CPUCAP_SOC_ERRATUM, 1082 .matches = is_imx8qm_soc, 1083 .cpu_enable = cpu_enable_imx8qm_err050104, 1084 }, 1085 #endif 1086 { 1087 } 1088 }; 1089