1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/uapi/asm/kvm.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef __ARM_KVM_H__ 24 #define __ARM_KVM_H__ 25 26 #define KVM_SPSR_EL1 0 27 #define KVM_SPSR_SVC KVM_SPSR_EL1 28 #define KVM_SPSR_ABT 1 29 #define KVM_SPSR_UND 2 30 #define KVM_SPSR_IRQ 3 31 #define KVM_SPSR_FIQ 4 32 #define KVM_NR_SPSR 5 33 34 #ifndef __ASSEMBLER__ 35 #include <linux/psci.h> 36 #include <linux/types.h> 37 #include <asm/ptrace.h> 38 #include <asm/sve_context.h> 39 40 #define __KVM_HAVE_IRQ_LINE 41 #define __KVM_HAVE_VCPU_EVENTS 42 43 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1 44 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 45 46 struct kvm_regs { 47 struct user_pt_regs regs; /* sp = sp_el0 */ 48 49 __u64 sp_el1; 50 __u64 elr_el1; 51 52 __u64 spsr[KVM_NR_SPSR]; 53 54 struct user_fpsimd_state fp_regs; 55 }; 56 57 /* 58 * Supported CPU Targets - Adding a new target type is not recommended, 59 * unless there are some special registers not supported by the 60 * genericv8 syreg table. 61 */ 62 #define KVM_ARM_TARGET_AEM_V8 0 63 #define KVM_ARM_TARGET_FOUNDATION_V8 1 64 #define KVM_ARM_TARGET_CORTEX_A57 2 65 #define KVM_ARM_TARGET_XGENE_POTENZA 3 66 #define KVM_ARM_TARGET_CORTEX_A53 4 67 /* Generic ARM v8 target */ 68 #define KVM_ARM_TARGET_GENERIC_V8 5 69 70 #define KVM_ARM_NUM_TARGETS 6 71 72 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */ 73 #define KVM_ARM_DEVICE_TYPE_SHIFT 0 74 #define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \ 75 KVM_ARM_DEVICE_TYPE_SHIFT) 76 #define KVM_ARM_DEVICE_ID_SHIFT 16 77 #define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \ 78 KVM_ARM_DEVICE_ID_SHIFT) 79 80 /* Supported device IDs */ 81 #define KVM_ARM_DEVICE_VGIC_V2 0 82 83 /* Supported VGIC address types */ 84 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0 85 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1 86 87 #define KVM_VGIC_V2_DIST_SIZE 0x1000 88 #define KVM_VGIC_V2_CPU_SIZE 0x2000 89 90 /* Supported VGICv3 address types */ 91 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2 92 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3 93 #define KVM_VGIC_ITS_ADDR_TYPE 4 94 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5 95 96 #define KVM_VGIC_V3_DIST_SIZE SZ_64K 97 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K) 98 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K) 99 100 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */ 101 #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ 102 #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ 103 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ 104 #define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */ 105 #define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */ 106 #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */ 107 #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ 108 #define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */ 109 #define KVM_ARM_VCPU_PMU_V3_STRICT 9 /* No default PMU creation */ 110 111 struct kvm_vcpu_init { 112 __u32 target; 113 __u32 features[7]; 114 }; 115 116 struct kvm_sregs { 117 }; 118 119 struct kvm_fpu { 120 }; 121 122 /* 123 * See v8 ARM ARM D7.3: Debug Registers 124 * 125 * The architectural limit is 16 debug registers of each type although 126 * in practice there are usually less (see ID_AA64DFR0_EL1). 127 * 128 * Although the control registers are architecturally defined as 32 129 * bits wide we use a 64 bit structure here to keep parity with 130 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as 131 * 64 bit values. It also allows for the possibility of the 132 * architecture expanding the control registers without having to 133 * change the userspace ABI. 134 */ 135 #define KVM_ARM_MAX_DBG_REGS 16 136 struct kvm_guest_debug_arch { 137 __u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS]; 138 __u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS]; 139 __u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS]; 140 __u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS]; 141 }; 142 143 #define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0) 144 struct kvm_debug_exit_arch { 145 __u32 hsr; 146 __u32 hsr_high; /* ESR_EL2[61:32] */ 147 __u64 far; /* used for watchpoints */ 148 }; 149 150 /* 151 * Architecture specific defines for kvm_guest_debug->control 152 */ 153 154 #define KVM_GUESTDBG_USE_SW_BP (1 << 16) 155 #define KVM_GUESTDBG_USE_HW (1 << 17) 156 157 struct kvm_sync_regs { 158 /* Used with KVM_CAP_ARM_USER_IRQ */ 159 __u64 device_irq_level; 160 }; 161 162 /* Bits for run->s.regs.device_irq_level */ 163 #define KVM_ARM_DEV_EL1_VTIMER (1 << 0) 164 #define KVM_ARM_DEV_EL1_PTIMER (1 << 1) 165 #define KVM_ARM_DEV_PMU (1 << 2) 166 167 /* 168 * PMU filter structure. Describe a range of events with a particular 169 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER. 170 */ 171 struct kvm_pmu_event_filter { 172 __u16 base_event; 173 __u16 nevents; 174 175 #define KVM_PMU_EVENT_ALLOW 0 176 #define KVM_PMU_EVENT_DENY 1 177 178 __u8 action; 179 __u8 pad[3]; 180 }; 181 182 /* for KVM_GET/SET_VCPU_EVENTS */ 183 struct kvm_vcpu_events { 184 struct { 185 __u8 serror_pending; 186 __u8 serror_has_esr; 187 __u8 ext_dabt_pending; 188 /* Align it to 8 bytes */ 189 __u8 pad[5]; 190 __u64 serror_esr; 191 } exception; 192 __u32 reserved[12]; 193 }; 194 195 struct kvm_arm_copy_mte_tags { 196 __u64 guest_ipa; 197 __u64 length; 198 void __user *addr; 199 __u64 flags; 200 __u64 reserved[2]; 201 }; 202 203 /* 204 * Counter/Timer offset structure. Describe the virtual/physical offset. 205 * To be used with KVM_ARM_SET_COUNTER_OFFSET. 206 */ 207 struct kvm_arm_counter_offset { 208 __u64 counter_offset; 209 __u64 reserved; 210 }; 211 212 #define KVM_ARM_TAGS_TO_GUEST 0 213 #define KVM_ARM_TAGS_FROM_GUEST 1 214 215 /* If you need to interpret the index values, here is the key: */ 216 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000 217 #define KVM_REG_ARM_COPROC_SHIFT 16 218 219 /* Normal registers are mapped as coprocessor 16. */ 220 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT) 221 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32)) 222 223 /* Some registers need more space to represent values. */ 224 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT) 225 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00 226 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8 227 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT) 228 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF 229 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0 230 231 /* AArch64 system registers */ 232 #define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT) 233 #define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000 234 #define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14 235 #define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800 236 #define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11 237 #define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780 238 #define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7 239 #define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078 240 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3 241 #define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007 242 #define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0 243 244 #define ARM64_SYS_REG_SHIFT_MASK(x,n) \ 245 (((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \ 246 KVM_REG_ARM64_SYSREG_ ## n ## _MASK) 247 248 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ 249 (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \ 250 ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \ 251 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \ 252 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \ 253 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \ 254 ARM64_SYS_REG_SHIFT_MASK(op2, OP2)) 255 256 #define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64) 257 258 /* Physical Timer EL0 Registers */ 259 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1) 260 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2) 261 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1) 262 263 /* 264 * EL0 Virtual Timer Registers 265 * 266 * WARNING: 267 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined 268 * with the appropriate register encodings. Their values have been 269 * accidentally swapped. As this is set API, the definitions here 270 * must be used, rather than ones derived from the encodings. 271 */ 272 #define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1) 273 #define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2) 274 #define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2) 275 276 /* KVM-as-firmware specific pseudo-registers */ 277 #define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT) 278 #define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 279 KVM_REG_ARM_FW | ((r) & 0xffff)) 280 #define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0) 281 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1) 282 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0 283 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1 284 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2 285 286 /* 287 * Only two states can be presented by the host kernel: 288 * - NOT_REQUIRED: the guest doesn't need to do anything 289 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available) 290 * 291 * All the other values are deprecated. The host still accepts all 292 * values (they are ABI), but will narrow them to the above two. 293 */ 294 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2) 295 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0 296 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1 297 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2 298 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 299 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) 300 301 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) 302 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 303 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 304 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 305 306 /* SVE registers */ 307 #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) 308 309 /* Z- and P-regs occupy blocks at the following offsets within this range: */ 310 #define KVM_REG_ARM64_SVE_ZREG_BASE 0 311 #define KVM_REG_ARM64_SVE_PREG_BASE 0x400 312 #define KVM_REG_ARM64_SVE_FFR_BASE 0x600 313 314 #define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS 315 #define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS 316 317 #define KVM_ARM64_SVE_MAX_SLICES 32 318 319 #define KVM_REG_ARM64_SVE_ZREG(n, i) \ 320 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \ 321 KVM_REG_SIZE_U2048 | \ 322 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) | \ 323 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 324 325 #define KVM_REG_ARM64_SVE_PREG(n, i) \ 326 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \ 327 KVM_REG_SIZE_U256 | \ 328 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) | \ 329 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 330 331 #define KVM_REG_ARM64_SVE_FFR(i) \ 332 (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \ 333 KVM_REG_SIZE_U256 | \ 334 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) 335 336 /* 337 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and 338 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness- 339 * invariant layout which differs from the layout used for the FPSIMD 340 * V-registers on big-endian systems: see sigcontext.h for more explanation. 341 */ 342 343 #define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN 344 #define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX 345 346 /* Vector lengths pseudo-register: */ 347 #define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \ 348 KVM_REG_SIZE_U512 | 0xffff) 349 #define KVM_ARM64_SVE_VLS_WORDS \ 350 ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) 351 352 /* Bitmap feature firmware registers */ 353 #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) 354 #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ 355 KVM_REG_ARM_FW_FEAT_BMAP | \ 356 ((r) & 0xffff)) 357 358 #define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0) 359 360 enum { 361 KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0, 362 #ifdef __KERNEL__ 363 KVM_REG_ARM_STD_BMAP_BIT_COUNT, 364 #endif 365 }; 366 367 #define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1) 368 369 enum { 370 KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0, 371 #ifdef __KERNEL__ 372 KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT, 373 #endif 374 }; 375 376 /* Vendor hyper call function numbers 0-63 */ 377 #define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2) 378 379 enum { 380 KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0, 381 KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1, 382 #ifdef __KERNEL__ 383 KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT, 384 #endif 385 }; 386 387 /* Vendor hyper call function numbers 64-127 */ 388 #define KVM_REG_ARM_VENDOR_HYP_BMAP_2 KVM_REG_ARM_FW_FEAT_BMAP_REG(3) 389 390 enum { 391 KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_VER = 0, 392 KVM_REG_ARM_VENDOR_HYP_BIT_DISCOVER_IMPL_CPUS = 1, 393 #ifdef __KERNEL__ 394 KVM_REG_ARM_VENDOR_HYP_BMAP_2_BIT_COUNT, 395 #endif 396 }; 397 398 /* Device Control API on vm fd */ 399 #define KVM_ARM_VM_SMCCC_CTRL 0 400 #define KVM_ARM_VM_SMCCC_FILTER 0 401 402 /* Device Control API: ARM VGIC */ 403 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 404 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 405 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 406 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 407 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) 408 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32 409 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \ 410 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT) 411 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 412 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) 413 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff) 414 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 415 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 416 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 417 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6 418 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7 419 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8 420 #define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9 421 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10 422 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \ 423 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT) 424 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff 425 #define VGIC_LEVEL_INFO_LINE_LEVEL 0 426 427 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 428 #define KVM_DEV_ARM_ITS_SAVE_TABLES 1 429 #define KVM_DEV_ARM_ITS_RESTORE_TABLES 2 430 #define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3 431 #define KVM_DEV_ARM_ITS_CTRL_RESET 4 432 #define KVM_DEV_ARM_VGIC_USERSPACE_PPIS 5 433 434 /* Device Control API on vcpu fd */ 435 #define KVM_ARM_VCPU_PMU_V3_CTRL 0 436 #define KVM_ARM_VCPU_PMU_V3_IRQ 0 437 #define KVM_ARM_VCPU_PMU_V3_INIT 1 438 #define KVM_ARM_VCPU_PMU_V3_FILTER 2 439 #define KVM_ARM_VCPU_PMU_V3_SET_PMU 3 440 #define KVM_ARM_VCPU_PMU_V3_SET_NR_COUNTERS 4 441 #define KVM_ARM_VCPU_TIMER_CTRL 1 442 #define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0 443 #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 444 #define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2 445 #define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3 446 #define KVM_ARM_VCPU_PVTIME_CTRL 2 447 #define KVM_ARM_VCPU_PVTIME_IPA 0 448 449 /* KVM_IRQ_LINE irq field index values */ 450 #define KVM_ARM_IRQ_VCPU2_SHIFT 28 451 #define KVM_ARM_IRQ_VCPU2_MASK 0xf 452 #define KVM_ARM_IRQ_TYPE_SHIFT 24 453 #define KVM_ARM_IRQ_TYPE_MASK 0xf 454 #define KVM_ARM_IRQ_VCPU_SHIFT 16 455 #define KVM_ARM_IRQ_VCPU_MASK 0xff 456 #define KVM_ARM_IRQ_NUM_SHIFT 0 457 #define KVM_ARM_IRQ_NUM_MASK 0xffff 458 459 /* irq_type field */ 460 #define KVM_ARM_IRQ_TYPE_CPU 0 461 #define KVM_ARM_IRQ_TYPE_SPI 1 462 #define KVM_ARM_IRQ_TYPE_PPI 2 463 464 /* out-of-kernel GIC cpu interrupt injection irq_number field */ 465 #define KVM_ARM_IRQ_CPU_IRQ 0 466 #define KVM_ARM_IRQ_CPU_FIQ 1 467 468 /* 469 * This used to hold the highest supported SPI, but it is now obsolete 470 * and only here to provide source code level compatibility with older 471 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS. 472 */ 473 #ifndef __KERNEL__ 474 #define KVM_ARM_IRQ_GIC_MAX 127 475 #endif 476 477 /* One single KVM irqchip, ie. the VGIC */ 478 #define KVM_NR_IRQCHIPS 1 479 480 /* PSCI interface */ 481 #define KVM_PSCI_FN_BASE 0x95c1ba5e 482 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n)) 483 484 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0) 485 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1) 486 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2) 487 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3) 488 489 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS 490 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED 491 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS 492 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED 493 494 /* arm64-specific kvm_run::system_event flags */ 495 /* 496 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call. 497 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET. 498 */ 499 #define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0) 500 501 /* 502 * Shutdown caused by a PSCI v1.3 SYSTEM_OFF2 call. 503 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_SHUTDOWN. 504 */ 505 #define KVM_SYSTEM_EVENT_SHUTDOWN_FLAG_PSCI_OFF2 (1ULL << 0) 506 507 /* run->fail_entry.hardware_entry_failure_reason codes. */ 508 #define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0) 509 510 enum kvm_smccc_filter_action { 511 KVM_SMCCC_FILTER_HANDLE = 0, 512 KVM_SMCCC_FILTER_DENY, 513 KVM_SMCCC_FILTER_FWD_TO_USER, 514 515 #ifdef __KERNEL__ 516 NR_SMCCC_FILTER_ACTIONS 517 #endif 518 }; 519 520 struct kvm_smccc_filter { 521 __u32 base; 522 __u32 nr_functions; 523 __u8 action; 524 __u8 pad[15]; 525 }; 526 527 /* arm64-specific KVM_EXIT_HYPERCALL flags */ 528 #define KVM_HYPERCALL_EXIT_SMC (1U << 0) 529 #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) 530 531 /* 532 * Get feature ID registers userspace writable mask. 533 * 534 * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model 535 * Feature Register 2"): 536 * 537 * "The Feature ID space is defined as the System register space in 538 * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, 539 * op2=={0-7}." 540 * 541 * This covers all currently known R/O registers that indicate 542 * anything useful feature wise, including the ID registers. 543 * 544 * If we ever need to introduce a new range, it will be described as 545 * such in the range field. 546 */ 547 #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ 548 ({ \ 549 __u64 __op1 = (op1) & 3; \ 550 __op1 -= (__op1 == 3); \ 551 (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ 552 }) 553 554 #define KVM_ARM_FEATURE_ID_RANGE 0 555 #define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8) 556 557 struct reg_mask_range { 558 __u64 addr; /* Pointer to mask array */ 559 __u32 range; /* Requested range */ 560 __u32 reserved[13]; 561 }; 562 563 #endif 564 565 #endif /* __ARM_KVM_H__ */ 566