1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/traps.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 */ 7 #ifndef __ASM_TRAP_H 8 #define __ASM_TRAP_H 9 10 #include <linux/list.h> 11 #include <asm/esr.h> 12 #include <asm/ptrace.h> 13 #include <asm/sections.h> 14 15 #ifdef CONFIG_ARMV8_DEPRECATED 16 bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn); 17 #else 18 static inline bool 19 try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn) 20 { 21 return false; 22 } 23 #endif /* CONFIG_ARMV8_DEPRECATED */ 24 25 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err); 26 void arm64_notify_segfault(unsigned long addr); 27 void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str); 28 void arm64_force_sig_fault_pkey(unsigned long far, const char *str, int pkey); 29 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str); 30 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str); 31 32 int bug_brk_handler(struct pt_regs *regs, unsigned long esr); 33 int cfi_brk_handler(struct pt_regs *regs, unsigned long esr); 34 int reserved_fault_brk_handler(struct pt_regs *regs, unsigned long esr); 35 int kasan_brk_handler(struct pt_regs *regs, unsigned long esr); 36 int ubsan_brk_handler(struct pt_regs *regs, unsigned long esr); 37 38 int early_brk64(unsigned long addr, unsigned long esr, struct pt_regs *regs); 39 40 /* 41 * Move regs->pc to next instruction and do necessary setup before it 42 * is executed. 43 */ 44 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size); 45 46 static inline int __in_irqentry_text(unsigned long ptr) 47 { 48 return ptr >= (unsigned long)&__irqentry_text_start && 49 ptr < (unsigned long)&__irqentry_text_end; 50 } 51 52 static inline int in_entry_text(unsigned long ptr) 53 { 54 return ptr >= (unsigned long)&__entry_text_start && 55 ptr < (unsigned long)&__entry_text_end; 56 } 57 58 /* 59 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 60 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 61 * have a ISS-Valid bit in the same position. 62 * If this bit is set, we know its not a RAS SError. 63 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 64 * errors share the same encoding as an all-zeros encoding from a CPU that 65 * doesn't support RAS. 66 */ 67 static inline bool arm64_is_ras_serror(unsigned long esr) 68 { 69 WARN_ON(preemptible()); 70 71 if (esr & ESR_ELx_IDS) 72 return false; 73 74 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 75 return true; 76 else 77 return false; 78 } 79 80 /* 81 * Return the AET bits from a RAS SError's ESR. 82 * 83 * It is implementation defined whether Uncategorized errors are containable. 84 * We treat them as Uncontainable. 85 * Non-RAS SError's are reported as Uncontained/Uncategorized. 86 */ 87 static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr) 88 { 89 unsigned long aet = esr & ESR_ELx_AET; 90 91 if (!arm64_is_ras_serror(esr)) { 92 /* Not a RAS error, we can't interpret the ESR. */ 93 return ESR_ELx_AET_UC; 94 } 95 96 /* 97 * AET is RES0 if 'the value returned in the DFSC field is not 98 * [ESR_ELx_FSC_SERROR]' 99 */ 100 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 101 /* No severity information : Uncategorized */ 102 return ESR_ELx_AET_UC; 103 } 104 105 return aet; 106 } 107 108 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr); 109 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr); 110 111 static inline void arm64_mops_reset_regs(struct user_pt_regs *regs, unsigned long esr) 112 { 113 bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION; 114 bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A; 115 int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr); 116 int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr); 117 int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr); 118 unsigned long dst, size; 119 120 dst = regs->regs[dstreg]; 121 size = regs->regs[sizereg]; 122 123 /* 124 * Put the registers back in the original format suitable for a 125 * prologue instruction, using the generic return routine from the 126 * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH. 127 */ 128 if (esr & ESR_ELx_MOPS_ISS_MEM_INST) { 129 /* SET* instruction */ 130 if (option_a ^ wrong_option) { 131 /* Format is from Option A; forward set */ 132 regs->regs[dstreg] = dst + size; 133 regs->regs[sizereg] = -size; 134 } 135 } else { 136 /* CPY* instruction */ 137 unsigned long src = regs->regs[srcreg]; 138 if (!(option_a ^ wrong_option)) { 139 /* Format is from Option B */ 140 if (regs->pstate & PSR_N_BIT) { 141 /* Backward copy */ 142 regs->regs[dstreg] = dst - size; 143 regs->regs[srcreg] = src - size; 144 } 145 } else { 146 /* Format is from Option A */ 147 if (size & BIT(63)) { 148 /* Forward copy */ 149 regs->regs[dstreg] = dst + size; 150 regs->regs[srcreg] = src + size; 151 regs->regs[sizereg] = -size; 152 } 153 } 154 } 155 156 if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE) 157 regs->pc -= 8; 158 else 159 regs->pc -= 4; 160 } 161 #endif 162