1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/traps.h 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 */ 7 #ifndef __ASM_TRAP_H 8 #define __ASM_TRAP_H 9 10 #include <linux/list.h> 11 #include <asm/esr.h> 12 #include <asm/ptrace.h> 13 #include <asm/sections.h> 14 15 #ifdef CONFIG_ARMV8_DEPRECATED 16 bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn); 17 #else 18 static inline bool 19 try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn) 20 { 21 return false; 22 } 23 #endif /* CONFIG_ARMV8_DEPRECATED */ 24 25 void force_signal_inject(int signal, int code, unsigned long address, unsigned long err); 26 void arm64_notify_segfault(unsigned long addr); 27 void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str); 28 void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str); 29 void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str); 30 31 int early_brk64(unsigned long addr, unsigned long esr, struct pt_regs *regs); 32 33 /* 34 * Move regs->pc to next instruction and do necessary setup before it 35 * is executed. 36 */ 37 void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size); 38 39 static inline int __in_irqentry_text(unsigned long ptr) 40 { 41 return ptr >= (unsigned long)&__irqentry_text_start && 42 ptr < (unsigned long)&__irqentry_text_end; 43 } 44 45 static inline int in_entry_text(unsigned long ptr) 46 { 47 return ptr >= (unsigned long)&__entry_text_start && 48 ptr < (unsigned long)&__entry_text_end; 49 } 50 51 /* 52 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit 53 * to indicate whether this ESR has a RAS encoding. CPUs without this feature 54 * have a ISS-Valid bit in the same position. 55 * If this bit is set, we know its not a RAS SError. 56 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS 57 * errors share the same encoding as an all-zeros encoding from a CPU that 58 * doesn't support RAS. 59 */ 60 static inline bool arm64_is_ras_serror(unsigned long esr) 61 { 62 WARN_ON(preemptible()); 63 64 if (esr & ESR_ELx_IDS) 65 return false; 66 67 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) 68 return true; 69 else 70 return false; 71 } 72 73 /* 74 * Return the AET bits from a RAS SError's ESR. 75 * 76 * It is implementation defined whether Uncategorized errors are containable. 77 * We treat them as Uncontainable. 78 * Non-RAS SError's are reported as Uncontained/Uncategorized. 79 */ 80 static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr) 81 { 82 unsigned long aet = esr & ESR_ELx_AET; 83 84 if (!arm64_is_ras_serror(esr)) { 85 /* Not a RAS error, we can't interpret the ESR. */ 86 return ESR_ELx_AET_UC; 87 } 88 89 /* 90 * AET is RES0 if 'the value returned in the DFSC field is not 91 * [ESR_ELx_FSC_SERROR]' 92 */ 93 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) { 94 /* No severity information : Uncategorized */ 95 return ESR_ELx_AET_UC; 96 } 97 98 return aet; 99 } 100 101 bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr); 102 void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr); 103 104 static inline void arm64_mops_reset_regs(struct user_pt_regs *regs, unsigned long esr) 105 { 106 bool wrong_option = esr & ESR_ELx_MOPS_ISS_WRONG_OPTION; 107 bool option_a = esr & ESR_ELx_MOPS_ISS_OPTION_A; 108 int dstreg = ESR_ELx_MOPS_ISS_DESTREG(esr); 109 int srcreg = ESR_ELx_MOPS_ISS_SRCREG(esr); 110 int sizereg = ESR_ELx_MOPS_ISS_SIZEREG(esr); 111 unsigned long dst, src, size; 112 113 dst = regs->regs[dstreg]; 114 src = regs->regs[srcreg]; 115 size = regs->regs[sizereg]; 116 117 /* 118 * Put the registers back in the original format suitable for a 119 * prologue instruction, using the generic return routine from the 120 * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH. 121 */ 122 if (esr & ESR_ELx_MOPS_ISS_MEM_INST) { 123 /* SET* instruction */ 124 if (option_a ^ wrong_option) { 125 /* Format is from Option A; forward set */ 126 regs->regs[dstreg] = dst + size; 127 regs->regs[sizereg] = -size; 128 } 129 } else { 130 /* CPY* instruction */ 131 if (!(option_a ^ wrong_option)) { 132 /* Format is from Option B */ 133 if (regs->pstate & PSR_N_BIT) { 134 /* Backward copy */ 135 regs->regs[dstreg] = dst - size; 136 regs->regs[srcreg] = src - size; 137 } 138 } else { 139 /* Format is from Option A */ 140 if (size & BIT(63)) { 141 /* Forward copy */ 142 regs->regs[dstreg] = dst + size; 143 regs->regs[srcreg] = src + size; 144 regs->regs[sizereg] = -size; 145 } 146 } 147 } 148 149 if (esr & ESR_ELx_MOPS_ISS_FROM_EPILOGUE) 150 regs->pc -= 8; 151 else 152 regs->pc -= 4; 153 } 154 #endif 155