1 /* 2 * Based on arch/arm/include/asm/tlbflush.h 3 * 4 * Copyright (C) 1999-2003 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_TLBFLUSH_H 20 #define __ASM_TLBFLUSH_H 21 22 #ifndef __ASSEMBLY__ 23 24 #include <linux/sched.h> 25 #include <asm/cputype.h> 26 27 /* 28 * TLB Management 29 * ============== 30 * 31 * The TLB specific code is expected to perform whatever tests it needs 32 * to determine if it should invalidate the TLB for each call. Start 33 * addresses are inclusive and end addresses are exclusive; it is safe to 34 * round these addresses down. 35 * 36 * flush_tlb_all() 37 * 38 * Invalidate the entire TLB. 39 * 40 * flush_tlb_mm(mm) 41 * 42 * Invalidate all TLB entries in a particular address space. 43 * - mm - mm_struct describing address space 44 * 45 * flush_tlb_range(mm,start,end) 46 * 47 * Invalidate a range of TLB entries in the specified address 48 * space. 49 * - mm - mm_struct describing address space 50 * - start - start address (may not be aligned) 51 * - end - end address (exclusive, may not be aligned) 52 * 53 * flush_tlb_page(vaddr,vma) 54 * 55 * Invalidate the specified page in the specified address range. 56 * - vaddr - virtual address (may not be aligned) 57 * - vma - vma_struct describing address range 58 * 59 * flush_kern_tlb_page(kaddr) 60 * 61 * Invalidate the TLB entry for the specified page. The address 62 * will be in the kernels virtual memory space. Current uses 63 * only require the D-TLB to be invalidated. 64 * - kaddr - Kernel virtual memory address 65 */ 66 static inline void flush_tlb_all(void) 67 { 68 dsb(ishst); 69 asm("tlbi vmalle1is"); 70 dsb(ish); 71 isb(); 72 } 73 74 static inline void flush_tlb_mm(struct mm_struct *mm) 75 { 76 unsigned long asid = (unsigned long)ASID(mm) << 48; 77 78 dsb(ishst); 79 asm("tlbi aside1is, %0" : : "r" (asid)); 80 dsb(ish); 81 } 82 83 static inline void flush_tlb_page(struct vm_area_struct *vma, 84 unsigned long uaddr) 85 { 86 unsigned long addr = uaddr >> 12 | 87 ((unsigned long)ASID(vma->vm_mm) << 48); 88 89 dsb(ishst); 90 asm("tlbi vale1is, %0" : : "r" (addr)); 91 dsb(ish); 92 } 93 94 /* 95 * This is meant to avoid soft lock-ups on large TLB flushing ranges and not 96 * necessarily a performance improvement. 97 */ 98 #define MAX_TLB_RANGE (1024UL << PAGE_SHIFT) 99 100 static inline void __flush_tlb_range(struct vm_area_struct *vma, 101 unsigned long start, unsigned long end, 102 bool last_level) 103 { 104 unsigned long asid = (unsigned long)ASID(vma->vm_mm) << 48; 105 unsigned long addr; 106 107 if ((end - start) > MAX_TLB_RANGE) { 108 flush_tlb_mm(vma->vm_mm); 109 return; 110 } 111 112 start = asid | (start >> 12); 113 end = asid | (end >> 12); 114 115 dsb(ishst); 116 for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) { 117 if (last_level) 118 asm("tlbi vale1is, %0" : : "r"(addr)); 119 else 120 asm("tlbi vae1is, %0" : : "r"(addr)); 121 } 122 dsb(ish); 123 } 124 125 static inline void flush_tlb_range(struct vm_area_struct *vma, 126 unsigned long start, unsigned long end) 127 { 128 __flush_tlb_range(vma, start, end, false); 129 } 130 131 static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) 132 { 133 unsigned long addr; 134 135 if ((end - start) > MAX_TLB_RANGE) { 136 flush_tlb_all(); 137 return; 138 } 139 140 start >>= 12; 141 end >>= 12; 142 143 dsb(ishst); 144 for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) 145 asm("tlbi vaae1is, %0" : : "r"(addr)); 146 dsb(ish); 147 isb(); 148 } 149 150 /* 151 * Used to invalidate the TLB (walk caches) corresponding to intermediate page 152 * table levels (pgd/pud/pmd). 153 */ 154 static inline void __flush_tlb_pgtable(struct mm_struct *mm, 155 unsigned long uaddr) 156 { 157 unsigned long addr = uaddr >> 12 | ((unsigned long)ASID(mm) << 48); 158 159 dsb(ishst); 160 asm("tlbi vae1is, %0" : : "r" (addr)); 161 dsb(ish); 162 } 163 164 #endif 165 166 #endif 167