1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/const.h> 13 #include <linux/stringify.h> 14 15 /* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25 #define Op0_shift 19 26 #define Op0_mask 0x3 27 #define Op1_shift 16 28 #define Op1_mask 0x7 29 #define CRn_shift 12 30 #define CRn_mask 0xf 31 #define CRm_shift 8 32 #define CRm_mask 0xf 33 #define Op2_shift 5 34 #define Op2_mask 0x7 35 36 #define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41 #define sys_insn sys_reg 42 43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49 #ifndef CONFIG_BROKEN_GAS_INST 50 51 #ifdef __ASSEMBLY__ 52 #define __emit_inst(x) .inst (x) 53 #else 54 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 55 #endif 56 57 #else /* CONFIG_BROKEN_GAS_INST */ 58 59 #ifndef CONFIG_CPU_BIG_ENDIAN 60 #define __INSTR_BSWAP(x) (x) 61 #else /* CONFIG_CPU_BIG_ENDIAN */ 62 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 63 (((x) << 8) & 0x00ff0000) | \ 64 (((x) >> 8) & 0x0000ff00) | \ 65 (((x) >> 24) & 0x000000ff)) 66 #endif /* CONFIG_CPU_BIG_ENDIAN */ 67 68 #ifdef __ASSEMBLY__ 69 #define __emit_inst(x) .long __INSTR_BSWAP(x) 70 #else /* __ASSEMBLY__ */ 71 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 72 #endif /* __ASSEMBLY__ */ 73 74 #endif /* CONFIG_BROKEN_GAS_INST */ 75 76 /* 77 * Instructions for modifying PSTATE fields. 78 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 79 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 80 * for accessing PSTATE fields have the following encoding: 81 * Op0 = 0, CRn = 4 82 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 83 * CRm = Imm4 for the instruction. 84 * Rt = 0x1f 85 */ 86 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 87 #define PSTATE_Imm_shift CRm_shift 88 89 #define PSTATE_PAN pstate_field(0, 4) 90 #define PSTATE_UAO pstate_field(0, 3) 91 #define PSTATE_SSBS pstate_field(3, 1) 92 93 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 94 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 95 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 96 97 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 98 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 99 100 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 101 102 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 103 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 104 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 105 106 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 107 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 108 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 109 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 110 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 111 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 112 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 113 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 114 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 115 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 116 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 117 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 118 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 119 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 120 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 121 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 122 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 123 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 124 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 125 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 126 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 127 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 128 129 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 130 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 131 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 132 133 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 134 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 135 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 136 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 137 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 138 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 139 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 140 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 141 142 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 143 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 144 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 145 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 146 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 147 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 148 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 149 150 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 151 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 152 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 153 154 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 155 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 156 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 157 158 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 159 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 160 161 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 162 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 163 164 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 165 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 166 167 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 168 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 169 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 170 171 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 172 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 173 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 174 175 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 176 177 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 178 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 179 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 180 181 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 182 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 183 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 184 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 185 186 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 187 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 188 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 189 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 190 191 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 192 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 193 194 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 195 196 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 197 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 198 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 199 200 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 201 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 202 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 203 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 204 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 205 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 206 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 207 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 208 209 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 210 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 211 212 /*** Statistical Profiling Extension ***/ 213 /* ID registers */ 214 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 215 #define SYS_PMSIDR_EL1_FE_SHIFT 0 216 #define SYS_PMSIDR_EL1_FT_SHIFT 1 217 #define SYS_PMSIDR_EL1_FL_SHIFT 2 218 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 219 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 220 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 221 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 222 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 223 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 224 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 225 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 226 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 227 228 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 229 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 230 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 231 #define SYS_PMBIDR_EL1_P_SHIFT 4 232 #define SYS_PMBIDR_EL1_F_SHIFT 5 233 234 /* Sampling controls */ 235 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 236 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 237 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 238 #define SYS_PMSCR_EL1_CX_SHIFT 3 239 #define SYS_PMSCR_EL1_PA_SHIFT 4 240 #define SYS_PMSCR_EL1_TS_SHIFT 5 241 #define SYS_PMSCR_EL1_PCT_SHIFT 6 242 243 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 244 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 245 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 246 #define SYS_PMSCR_EL2_CX_SHIFT 3 247 #define SYS_PMSCR_EL2_PA_SHIFT 4 248 #define SYS_PMSCR_EL2_TS_SHIFT 5 249 #define SYS_PMSCR_EL2_PCT_SHIFT 6 250 251 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 252 253 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 254 #define SYS_PMSIRR_EL1_RND_SHIFT 0 255 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 256 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 257 258 /* Filtering controls */ 259 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 260 #define SYS_PMSFCR_EL1_FE_SHIFT 0 261 #define SYS_PMSFCR_EL1_FT_SHIFT 1 262 #define SYS_PMSFCR_EL1_FL_SHIFT 2 263 #define SYS_PMSFCR_EL1_B_SHIFT 16 264 #define SYS_PMSFCR_EL1_LD_SHIFT 17 265 #define SYS_PMSFCR_EL1_ST_SHIFT 18 266 267 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 268 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 269 270 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 271 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 272 273 /* Buffer controls */ 274 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 275 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 276 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 277 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 278 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 279 280 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 281 282 /* Buffer error reporting */ 283 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 284 #define SYS_PMBSR_EL1_COLL_SHIFT 16 285 #define SYS_PMBSR_EL1_S_SHIFT 17 286 #define SYS_PMBSR_EL1_EA_SHIFT 18 287 #define SYS_PMBSR_EL1_DL_SHIFT 19 288 #define SYS_PMBSR_EL1_EC_SHIFT 26 289 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 290 291 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 292 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 293 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 294 295 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 296 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 297 298 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 299 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 300 301 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 302 303 /*** End of Statistical Profiling Extension ***/ 304 305 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 306 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 307 308 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 309 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 310 311 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 312 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 313 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 314 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 315 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 316 317 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 318 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 319 320 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 321 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 322 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 323 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 324 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 325 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 326 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 327 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 328 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 329 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 330 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 331 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 332 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 333 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 334 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 335 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 336 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 337 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 338 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 339 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 340 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 341 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 342 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 343 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 344 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 345 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 346 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 347 348 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 349 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 350 351 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 352 353 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 354 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 355 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 356 357 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 358 359 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 360 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 361 362 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 363 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 364 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 365 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 366 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 367 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 368 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 369 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 370 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 371 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 372 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 373 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 374 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 375 376 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 377 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 378 379 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 380 381 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 382 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 383 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 384 385 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 386 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 387 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 388 389 #define __PMEV_op2(n) ((n) & 0x7) 390 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 391 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 392 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 393 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 394 395 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7) 396 397 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 398 399 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 400 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 401 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 402 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 403 404 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 405 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 406 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 407 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 408 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 409 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 410 411 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 412 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 413 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 414 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 415 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 416 417 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 418 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 419 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 420 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 421 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 422 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 423 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 424 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 425 426 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 427 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 428 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 429 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 430 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 431 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 432 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 433 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 434 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 435 436 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 437 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 438 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 439 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 440 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 441 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 442 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 443 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 444 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 445 446 /* VHE encodings for architectural EL0/1 system registers */ 447 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 448 449 /* Common SCTLR_ELx flags. */ 450 #define SCTLR_ELx_DSSBS (_BITUL(44)) 451 #define SCTLR_ELx_ENIA (_BITUL(31)) 452 #define SCTLR_ELx_ENIB (_BITUL(30)) 453 #define SCTLR_ELx_ENDA (_BITUL(27)) 454 #define SCTLR_ELx_EE (_BITUL(25)) 455 #define SCTLR_ELx_IESB (_BITUL(21)) 456 #define SCTLR_ELx_WXN (_BITUL(19)) 457 #define SCTLR_ELx_ENDB (_BITUL(13)) 458 #define SCTLR_ELx_I (_BITUL(12)) 459 #define SCTLR_ELx_SA (_BITUL(3)) 460 #define SCTLR_ELx_C (_BITUL(2)) 461 #define SCTLR_ELx_A (_BITUL(1)) 462 #define SCTLR_ELx_M (_BITUL(0)) 463 464 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 465 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 466 467 /* SCTLR_EL2 specific flags. */ 468 #define SCTLR_EL2_RES1 ((_BITUL(4)) | (_BITUL(5)) | (_BITUL(11)) | (_BITUL(16)) | \ 469 (_BITUL(18)) | (_BITUL(22)) | (_BITUL(23)) | (_BITUL(28)) | \ 470 (_BITUL(29))) 471 #define SCTLR_EL2_RES0 ((_BITUL(6)) | (_BITUL(7)) | (_BITUL(8)) | (_BITUL(9)) | \ 472 (_BITUL(10)) | (_BITUL(13)) | (_BITUL(14)) | (_BITUL(15)) | \ 473 (_BITUL(17)) | (_BITUL(20)) | (_BITUL(24)) | (_BITUL(26)) | \ 474 (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ 475 (0xffffefffUL << 32)) 476 477 #ifdef CONFIG_CPU_BIG_ENDIAN 478 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 479 #define ENDIAN_CLEAR_EL2 0 480 #else 481 #define ENDIAN_SET_EL2 0 482 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE 483 #endif 484 485 /* SCTLR_EL2 value used for the hyp-stub */ 486 #define SCTLR_EL2_SET (SCTLR_ELx_IESB | ENDIAN_SET_EL2 | SCTLR_EL2_RES1) 487 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 488 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \ 489 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0) 490 491 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL 492 #error "Inconsistent SCTLR_EL2 set/clear bits" 493 #endif 494 495 /* SCTLR_EL1 specific flags. */ 496 #define SCTLR_EL1_UCI (_BITUL(26)) 497 #define SCTLR_EL1_E0E (_BITUL(24)) 498 #define SCTLR_EL1_SPAN (_BITUL(23)) 499 #define SCTLR_EL1_NTWE (_BITUL(18)) 500 #define SCTLR_EL1_NTWI (_BITUL(16)) 501 #define SCTLR_EL1_UCT (_BITUL(15)) 502 #define SCTLR_EL1_DZE (_BITUL(14)) 503 #define SCTLR_EL1_UMA (_BITUL(9)) 504 #define SCTLR_EL1_SED (_BITUL(8)) 505 #define SCTLR_EL1_ITD (_BITUL(7)) 506 #define SCTLR_EL1_CP15BEN (_BITUL(5)) 507 #define SCTLR_EL1_SA0 (_BITUL(4)) 508 509 #define SCTLR_EL1_RES1 ((_BITUL(11)) | (_BITUL(20)) | (_BITUL(22)) | (_BITUL(28)) | \ 510 (_BITUL(29))) 511 #define SCTLR_EL1_RES0 ((_BITUL(6)) | (_BITUL(10)) | (_BITUL(13)) | (_BITUL(17)) | \ 512 (_BITUL(27)) | (_BITUL(30)) | (_BITUL(31)) | \ 513 (0xffffefffUL << 32)) 514 515 #ifdef CONFIG_CPU_BIG_ENDIAN 516 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 517 #define ENDIAN_CLEAR_EL1 0 518 #else 519 #define ENDIAN_SET_EL1 0 520 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 521 #endif 522 523 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 524 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 525 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 526 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 527 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 528 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\ 529 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\ 530 SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI | SCTLR_EL1_RES0) 531 532 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL 533 #error "Inconsistent SCTLR_EL1 set/clear bits" 534 #endif 535 536 /* id_aa64isar0 */ 537 #define ID_AA64ISAR0_TS_SHIFT 52 538 #define ID_AA64ISAR0_FHM_SHIFT 48 539 #define ID_AA64ISAR0_DP_SHIFT 44 540 #define ID_AA64ISAR0_SM4_SHIFT 40 541 #define ID_AA64ISAR0_SM3_SHIFT 36 542 #define ID_AA64ISAR0_SHA3_SHIFT 32 543 #define ID_AA64ISAR0_RDM_SHIFT 28 544 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 545 #define ID_AA64ISAR0_CRC32_SHIFT 16 546 #define ID_AA64ISAR0_SHA2_SHIFT 12 547 #define ID_AA64ISAR0_SHA1_SHIFT 8 548 #define ID_AA64ISAR0_AES_SHIFT 4 549 550 /* id_aa64isar1 */ 551 #define ID_AA64ISAR1_SB_SHIFT 36 552 #define ID_AA64ISAR1_GPI_SHIFT 28 553 #define ID_AA64ISAR1_GPA_SHIFT 24 554 #define ID_AA64ISAR1_LRCPC_SHIFT 20 555 #define ID_AA64ISAR1_FCMA_SHIFT 16 556 #define ID_AA64ISAR1_JSCVT_SHIFT 12 557 #define ID_AA64ISAR1_API_SHIFT 8 558 #define ID_AA64ISAR1_APA_SHIFT 4 559 #define ID_AA64ISAR1_DPB_SHIFT 0 560 561 #define ID_AA64ISAR1_APA_NI 0x0 562 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 563 #define ID_AA64ISAR1_API_NI 0x0 564 #define ID_AA64ISAR1_API_IMP_DEF 0x1 565 #define ID_AA64ISAR1_GPA_NI 0x0 566 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 567 #define ID_AA64ISAR1_GPI_NI 0x0 568 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 569 570 /* id_aa64pfr0 */ 571 #define ID_AA64PFR0_CSV3_SHIFT 60 572 #define ID_AA64PFR0_CSV2_SHIFT 56 573 #define ID_AA64PFR0_DIT_SHIFT 48 574 #define ID_AA64PFR0_SVE_SHIFT 32 575 #define ID_AA64PFR0_RAS_SHIFT 28 576 #define ID_AA64PFR0_GIC_SHIFT 24 577 #define ID_AA64PFR0_ASIMD_SHIFT 20 578 #define ID_AA64PFR0_FP_SHIFT 16 579 #define ID_AA64PFR0_EL3_SHIFT 12 580 #define ID_AA64PFR0_EL2_SHIFT 8 581 #define ID_AA64PFR0_EL1_SHIFT 4 582 #define ID_AA64PFR0_EL0_SHIFT 0 583 584 #define ID_AA64PFR0_SVE 0x1 585 #define ID_AA64PFR0_RAS_V1 0x1 586 #define ID_AA64PFR0_FP_NI 0xf 587 #define ID_AA64PFR0_FP_SUPPORTED 0x0 588 #define ID_AA64PFR0_ASIMD_NI 0xf 589 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 590 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 591 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 592 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 593 594 /* id_aa64pfr1 */ 595 #define ID_AA64PFR1_SSBS_SHIFT 4 596 597 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 598 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 599 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 600 601 /* id_aa64zfr0 */ 602 #define ID_AA64ZFR0_SM4_SHIFT 40 603 #define ID_AA64ZFR0_SHA3_SHIFT 32 604 #define ID_AA64ZFR0_BITPERM_SHIFT 16 605 #define ID_AA64ZFR0_AES_SHIFT 4 606 #define ID_AA64ZFR0_SVEVER_SHIFT 0 607 608 #define ID_AA64ZFR0_SM4 0x1 609 #define ID_AA64ZFR0_SHA3 0x1 610 #define ID_AA64ZFR0_BITPERM 0x1 611 #define ID_AA64ZFR0_AES 0x1 612 #define ID_AA64ZFR0_AES_PMULL 0x2 613 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 614 615 /* id_aa64mmfr0 */ 616 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 617 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 618 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 619 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 620 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 621 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 622 #define ID_AA64MMFR0_ASID_SHIFT 4 623 #define ID_AA64MMFR0_PARANGE_SHIFT 0 624 625 #define ID_AA64MMFR0_TGRAN4_NI 0xf 626 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 627 #define ID_AA64MMFR0_TGRAN64_NI 0xf 628 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 629 #define ID_AA64MMFR0_TGRAN16_NI 0x0 630 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 631 #define ID_AA64MMFR0_PARANGE_48 0x5 632 #define ID_AA64MMFR0_PARANGE_52 0x6 633 634 #ifdef CONFIG_ARM64_PA_BITS_52 635 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 636 #else 637 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 638 #endif 639 640 /* id_aa64mmfr1 */ 641 #define ID_AA64MMFR1_PAN_SHIFT 20 642 #define ID_AA64MMFR1_LOR_SHIFT 16 643 #define ID_AA64MMFR1_HPD_SHIFT 12 644 #define ID_AA64MMFR1_VHE_SHIFT 8 645 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 646 #define ID_AA64MMFR1_HADBS_SHIFT 0 647 648 #define ID_AA64MMFR1_VMIDBITS_8 0 649 #define ID_AA64MMFR1_VMIDBITS_16 2 650 651 /* id_aa64mmfr2 */ 652 #define ID_AA64MMFR2_FWB_SHIFT 40 653 #define ID_AA64MMFR2_AT_SHIFT 32 654 #define ID_AA64MMFR2_LVA_SHIFT 16 655 #define ID_AA64MMFR2_IESB_SHIFT 12 656 #define ID_AA64MMFR2_LSM_SHIFT 8 657 #define ID_AA64MMFR2_UAO_SHIFT 4 658 #define ID_AA64MMFR2_CNP_SHIFT 0 659 660 /* id_aa64dfr0 */ 661 #define ID_AA64DFR0_PMSVER_SHIFT 32 662 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 663 #define ID_AA64DFR0_WRPS_SHIFT 20 664 #define ID_AA64DFR0_BRPS_SHIFT 12 665 #define ID_AA64DFR0_PMUVER_SHIFT 8 666 #define ID_AA64DFR0_TRACEVER_SHIFT 4 667 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 668 669 #define ID_ISAR5_RDM_SHIFT 24 670 #define ID_ISAR5_CRC32_SHIFT 16 671 #define ID_ISAR5_SHA2_SHIFT 12 672 #define ID_ISAR5_SHA1_SHIFT 8 673 #define ID_ISAR5_AES_SHIFT 4 674 #define ID_ISAR5_SEVL_SHIFT 0 675 676 #define MVFR0_FPROUND_SHIFT 28 677 #define MVFR0_FPSHVEC_SHIFT 24 678 #define MVFR0_FPSQRT_SHIFT 20 679 #define MVFR0_FPDIVIDE_SHIFT 16 680 #define MVFR0_FPTRAP_SHIFT 12 681 #define MVFR0_FPDP_SHIFT 8 682 #define MVFR0_FPSP_SHIFT 4 683 #define MVFR0_SIMD_SHIFT 0 684 685 #define MVFR1_SIMDFMAC_SHIFT 28 686 #define MVFR1_FPHP_SHIFT 24 687 #define MVFR1_SIMDHP_SHIFT 20 688 #define MVFR1_SIMDSP_SHIFT 16 689 #define MVFR1_SIMDINT_SHIFT 12 690 #define MVFR1_SIMDLS_SHIFT 8 691 #define MVFR1_FPDNAN_SHIFT 4 692 #define MVFR1_FPFTZ_SHIFT 0 693 694 695 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 696 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 697 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 698 699 #define ID_AA64MMFR0_TGRAN4_NI 0xf 700 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 701 #define ID_AA64MMFR0_TGRAN64_NI 0xf 702 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 703 #define ID_AA64MMFR0_TGRAN16_NI 0x0 704 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 705 706 #if defined(CONFIG_ARM64_4K_PAGES) 707 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 708 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 709 #elif defined(CONFIG_ARM64_16K_PAGES) 710 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 711 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 712 #elif defined(CONFIG_ARM64_64K_PAGES) 713 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 714 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 715 #endif 716 717 718 /* 719 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 720 * are reserved by the SVE architecture for future expansion of the LEN 721 * field, with compatible semantics. 722 */ 723 #define ZCR_ELx_LEN_SHIFT 0 724 #define ZCR_ELx_LEN_SIZE 9 725 #define ZCR_ELx_LEN_MASK 0x1ff 726 727 #define CPACR_EL1_ZEN_EL1EN (_BITUL(16)) /* enable EL1 access */ 728 #define CPACR_EL1_ZEN_EL0EN (_BITUL(17)) /* enable EL0 access, if EL1EN set */ 729 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 730 731 732 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 733 #define SYS_MPIDR_SAFE_VAL (_BITUL(31)) 734 735 #ifdef __ASSEMBLY__ 736 737 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 738 .equ .L__reg_num_x\num, \num 739 .endr 740 .equ .L__reg_num_xzr, 31 741 742 .macro mrs_s, rt, sreg 743 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 744 .endm 745 746 .macro msr_s, sreg, rt 747 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 748 .endm 749 750 #else 751 752 #include <linux/build_bug.h> 753 #include <linux/types.h> 754 755 #define __DEFINE_MRS_MSR_S_REGNUM \ 756 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 757 " .equ .L__reg_num_x\\num, \\num\n" \ 758 " .endr\n" \ 759 " .equ .L__reg_num_xzr, 31\n" 760 761 #define DEFINE_MRS_S \ 762 __DEFINE_MRS_MSR_S_REGNUM \ 763 " .macro mrs_s, rt, sreg\n" \ 764 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 765 " .endm\n" 766 767 #define DEFINE_MSR_S \ 768 __DEFINE_MRS_MSR_S_REGNUM \ 769 " .macro msr_s, sreg, rt\n" \ 770 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 771 " .endm\n" 772 773 #define UNDEFINE_MRS_S \ 774 " .purgem mrs_s\n" 775 776 #define UNDEFINE_MSR_S \ 777 " .purgem msr_s\n" 778 779 #define __mrs_s(v, r) \ 780 DEFINE_MRS_S \ 781 " mrs_s " v ", " __stringify(r) "\n" \ 782 UNDEFINE_MRS_S 783 784 #define __msr_s(r, v) \ 785 DEFINE_MSR_S \ 786 " msr_s " __stringify(r) ", " v "\n" \ 787 UNDEFINE_MSR_S 788 789 /* 790 * Unlike read_cpuid, calls to read_sysreg are never expected to be 791 * optimized away or replaced with synthetic values. 792 */ 793 #define read_sysreg(r) ({ \ 794 u64 __val; \ 795 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 796 __val; \ 797 }) 798 799 /* 800 * The "Z" constraint normally means a zero immediate, but when combined with 801 * the "%x0" template means XZR. 802 */ 803 #define write_sysreg(v, r) do { \ 804 u64 __val = (u64)(v); \ 805 asm volatile("msr " __stringify(r) ", %x0" \ 806 : : "rZ" (__val)); \ 807 } while (0) 808 809 /* 810 * For registers without architectural names, or simply unsupported by 811 * GAS. 812 */ 813 #define read_sysreg_s(r) ({ \ 814 u64 __val; \ 815 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 816 __val; \ 817 }) 818 819 #define write_sysreg_s(v, r) do { \ 820 u64 __val = (u64)(v); \ 821 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 822 } while (0) 823 824 /* 825 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 826 * set mask are set. Other bits are left as-is. 827 */ 828 #define sysreg_clear_set(sysreg, clear, set) do { \ 829 u64 __scs_val = read_sysreg(sysreg); \ 830 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 831 if (__scs_new != __scs_val) \ 832 write_sysreg(__scs_new, sysreg); \ 833 } while (0) 834 835 #endif 836 837 #endif /* __ASM_SYSREG_H */ 838