1 /* 2 * Macros for accessing system registers with older binutils. 3 * 4 * Copyright (C) 2014 ARM Ltd. 5 * Author: Catalin Marinas <catalin.marinas@arm.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __ASM_SYSREG_H 21 #define __ASM_SYSREG_H 22 23 #include <linux/stringify.h> 24 25 /* 26 * ARMv8 ARM reserves the following encoding for system registers: 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 28 * C5.2, version:ARM DDI 0487A.f) 29 * [20-19] : Op0 30 * [18-16] : Op1 31 * [15-12] : CRn 32 * [11-8] : CRm 33 * [7-5] : Op2 34 */ 35 #define sys_reg(op0, op1, crn, crm, op2) \ 36 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 37 38 #ifndef CONFIG_BROKEN_GAS_INST 39 40 #ifdef __ASSEMBLY__ 41 #define __emit_inst(x) .inst (x) 42 #else 43 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 44 #endif 45 46 #else /* CONFIG_BROKEN_GAS_INST */ 47 48 #ifndef CONFIG_CPU_BIG_ENDIAN 49 #define __INSTR_BSWAP(x) (x) 50 #else /* CONFIG_CPU_BIG_ENDIAN */ 51 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 52 (((x) << 8) & 0x00ff0000) | \ 53 (((x) >> 8) & 0x0000ff00) | \ 54 (((x) >> 24) & 0x000000ff)) 55 #endif /* CONFIG_CPU_BIG_ENDIAN */ 56 57 #ifdef __ASSEMBLY__ 58 #define __emit_inst(x) .long __INSTR_BSWAP(x) 59 #else /* __ASSEMBLY__ */ 60 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 61 #endif /* __ASSEMBLY__ */ 62 63 #endif /* CONFIG_BROKEN_GAS_INST */ 64 65 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 66 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 67 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 68 69 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 70 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 71 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 72 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 73 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 74 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 75 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 76 77 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 78 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 79 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 80 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 81 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 82 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 83 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 84 85 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 86 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 87 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 88 89 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 90 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 91 92 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 93 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 94 95 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 96 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 97 98 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 99 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 100 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 101 102 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 103 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 104 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 105 106 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 107 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) 108 109 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \ 110 (!!x)<<8 | 0x1f) 111 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \ 112 (!!x)<<8 | 0x1f) 113 114 /* Common SCTLR_ELx flags. */ 115 #define SCTLR_ELx_EE (1 << 25) 116 #define SCTLR_ELx_I (1 << 12) 117 #define SCTLR_ELx_SA (1 << 3) 118 #define SCTLR_ELx_C (1 << 2) 119 #define SCTLR_ELx_A (1 << 1) 120 #define SCTLR_ELx_M 1 121 122 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 123 SCTLR_ELx_SA | SCTLR_ELx_I) 124 125 /* SCTLR_EL1 specific flags. */ 126 #define SCTLR_EL1_UCI (1 << 26) 127 #define SCTLR_EL1_SPAN (1 << 23) 128 #define SCTLR_EL1_UCT (1 << 15) 129 #define SCTLR_EL1_SED (1 << 8) 130 #define SCTLR_EL1_CP15BEN (1 << 5) 131 132 /* id_aa64isar0 */ 133 #define ID_AA64ISAR0_RDM_SHIFT 28 134 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 135 #define ID_AA64ISAR0_CRC32_SHIFT 16 136 #define ID_AA64ISAR0_SHA2_SHIFT 12 137 #define ID_AA64ISAR0_SHA1_SHIFT 8 138 #define ID_AA64ISAR0_AES_SHIFT 4 139 140 /* id_aa64pfr0 */ 141 #define ID_AA64PFR0_GIC_SHIFT 24 142 #define ID_AA64PFR0_ASIMD_SHIFT 20 143 #define ID_AA64PFR0_FP_SHIFT 16 144 #define ID_AA64PFR0_EL3_SHIFT 12 145 #define ID_AA64PFR0_EL2_SHIFT 8 146 #define ID_AA64PFR0_EL1_SHIFT 4 147 #define ID_AA64PFR0_EL0_SHIFT 0 148 149 #define ID_AA64PFR0_FP_NI 0xf 150 #define ID_AA64PFR0_FP_SUPPORTED 0x0 151 #define ID_AA64PFR0_ASIMD_NI 0xf 152 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 153 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 154 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 155 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 156 157 /* id_aa64mmfr0 */ 158 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 159 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 160 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 161 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 162 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 163 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 164 #define ID_AA64MMFR0_ASID_SHIFT 4 165 #define ID_AA64MMFR0_PARANGE_SHIFT 0 166 167 #define ID_AA64MMFR0_TGRAN4_NI 0xf 168 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 169 #define ID_AA64MMFR0_TGRAN64_NI 0xf 170 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 171 #define ID_AA64MMFR0_TGRAN16_NI 0x0 172 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 173 174 /* id_aa64mmfr1 */ 175 #define ID_AA64MMFR1_PAN_SHIFT 20 176 #define ID_AA64MMFR1_LOR_SHIFT 16 177 #define ID_AA64MMFR1_HPD_SHIFT 12 178 #define ID_AA64MMFR1_VHE_SHIFT 8 179 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 180 #define ID_AA64MMFR1_HADBS_SHIFT 0 181 182 #define ID_AA64MMFR1_VMIDBITS_8 0 183 #define ID_AA64MMFR1_VMIDBITS_16 2 184 185 /* id_aa64mmfr2 */ 186 #define ID_AA64MMFR2_LVA_SHIFT 16 187 #define ID_AA64MMFR2_IESB_SHIFT 12 188 #define ID_AA64MMFR2_LSM_SHIFT 8 189 #define ID_AA64MMFR2_UAO_SHIFT 4 190 #define ID_AA64MMFR2_CNP_SHIFT 0 191 192 /* id_aa64dfr0 */ 193 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 194 #define ID_AA64DFR0_WRPS_SHIFT 20 195 #define ID_AA64DFR0_BRPS_SHIFT 12 196 #define ID_AA64DFR0_PMUVER_SHIFT 8 197 #define ID_AA64DFR0_TRACEVER_SHIFT 4 198 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 199 200 #define ID_ISAR5_RDM_SHIFT 24 201 #define ID_ISAR5_CRC32_SHIFT 16 202 #define ID_ISAR5_SHA2_SHIFT 12 203 #define ID_ISAR5_SHA1_SHIFT 8 204 #define ID_ISAR5_AES_SHIFT 4 205 #define ID_ISAR5_SEVL_SHIFT 0 206 207 #define MVFR0_FPROUND_SHIFT 28 208 #define MVFR0_FPSHVEC_SHIFT 24 209 #define MVFR0_FPSQRT_SHIFT 20 210 #define MVFR0_FPDIVIDE_SHIFT 16 211 #define MVFR0_FPTRAP_SHIFT 12 212 #define MVFR0_FPDP_SHIFT 8 213 #define MVFR0_FPSP_SHIFT 4 214 #define MVFR0_SIMD_SHIFT 0 215 216 #define MVFR1_SIMDFMAC_SHIFT 28 217 #define MVFR1_FPHP_SHIFT 24 218 #define MVFR1_SIMDHP_SHIFT 20 219 #define MVFR1_SIMDSP_SHIFT 16 220 #define MVFR1_SIMDINT_SHIFT 12 221 #define MVFR1_SIMDLS_SHIFT 8 222 #define MVFR1_FPDNAN_SHIFT 4 223 #define MVFR1_FPFTZ_SHIFT 0 224 225 226 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 227 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 228 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 229 230 #define ID_AA64MMFR0_TGRAN4_NI 0xf 231 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 232 #define ID_AA64MMFR0_TGRAN64_NI 0xf 233 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 234 #define ID_AA64MMFR0_TGRAN16_NI 0x0 235 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 236 237 #if defined(CONFIG_ARM64_4K_PAGES) 238 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 239 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 240 #elif defined(CONFIG_ARM64_16K_PAGES) 241 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 242 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 243 #elif defined(CONFIG_ARM64_64K_PAGES) 244 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 245 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 246 #endif 247 248 #ifdef __ASSEMBLY__ 249 250 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 251 .equ .L__reg_num_x\num, \num 252 .endr 253 .equ .L__reg_num_xzr, 31 254 255 .macro mrs_s, rt, sreg 256 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 257 .endm 258 259 .macro msr_s, sreg, rt 260 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 261 .endm 262 263 #else 264 265 #include <linux/types.h> 266 267 asm( 268 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" 269 " .equ .L__reg_num_x\\num, \\num\n" 270 " .endr\n" 271 " .equ .L__reg_num_xzr, 31\n" 272 "\n" 273 " .macro mrs_s, rt, sreg\n" 274 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) 275 " .endm\n" 276 "\n" 277 " .macro msr_s, sreg, rt\n" 278 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) 279 " .endm\n" 280 ); 281 282 /* 283 * Unlike read_cpuid, calls to read_sysreg are never expected to be 284 * optimized away or replaced with synthetic values. 285 */ 286 #define read_sysreg(r) ({ \ 287 u64 __val; \ 288 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 289 __val; \ 290 }) 291 292 /* 293 * The "Z" constraint normally means a zero immediate, but when combined with 294 * the "%x0" template means XZR. 295 */ 296 #define write_sysreg(v, r) do { \ 297 u64 __val = (u64)v; \ 298 asm volatile("msr " __stringify(r) ", %x0" \ 299 : : "rZ" (__val)); \ 300 } while (0) 301 302 /* 303 * For registers without architectural names, or simply unsupported by 304 * GAS. 305 */ 306 #define read_sysreg_s(r) ({ \ 307 u64 __val; \ 308 asm volatile("mrs_s %0, " __stringify(r) : "=r" (__val)); \ 309 __val; \ 310 }) 311 312 #define write_sysreg_s(v, r) do { \ 313 u64 __val = (u64)v; \ 314 asm volatile("msr_s " __stringify(r) ", %x0" : : "rZ" (__val)); \ 315 } while (0) 316 317 static inline void config_sctlr_el1(u32 clear, u32 set) 318 { 319 u32 val; 320 321 val = read_sysreg(sctlr_el1); 322 val &= ~clear; 323 val |= set; 324 write_sysreg(val, sctlr_el1); 325 } 326 327 #endif 328 329 #endif /* __ASM_SYSREG_H */ 330