1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 #include <linux/kasan-tags.h> 15 #include <linux/kconfig.h> 16 17 #include <asm/gpr-num.h> 18 19 /* 20 * ARMv8 ARM reserves the following encoding for system registers: 21 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 22 * C5.2, version:ARM DDI 0487A.f) 23 * [20-19] : Op0 24 * [18-16] : Op1 25 * [15-12] : CRn 26 * [11-8] : CRm 27 * [7-5] : Op2 28 */ 29 #define Op0_shift 19 30 #define Op0_mask 0x3 31 #define Op1_shift 16 32 #define Op1_mask 0x7 33 #define CRn_shift 12 34 #define CRn_mask 0xf 35 #define CRm_shift 8 36 #define CRm_mask 0xf 37 #define Op2_shift 5 38 #define Op2_mask 0x7 39 40 #define sys_reg(op0, op1, crn, crm, op2) \ 41 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 42 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 43 ((op2) << Op2_shift)) 44 45 #define sys_insn sys_reg 46 47 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 48 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 49 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 50 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 51 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 52 53 #ifndef CONFIG_BROKEN_GAS_INST 54 55 #ifdef __ASSEMBLY__ 56 // The space separator is omitted so that __emit_inst(x) can be parsed as 57 // either an assembler directive or an assembler macro argument. 58 #define __emit_inst(x) .inst(x) 59 #else 60 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 61 #endif 62 63 #else /* CONFIG_BROKEN_GAS_INST */ 64 65 #ifndef CONFIG_CPU_BIG_ENDIAN 66 #define __INSTR_BSWAP(x) (x) 67 #else /* CONFIG_CPU_BIG_ENDIAN */ 68 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 69 (((x) << 8) & 0x00ff0000) | \ 70 (((x) >> 8) & 0x0000ff00) | \ 71 (((x) >> 24) & 0x000000ff)) 72 #endif /* CONFIG_CPU_BIG_ENDIAN */ 73 74 #ifdef __ASSEMBLY__ 75 #define __emit_inst(x) .long __INSTR_BSWAP(x) 76 #else /* __ASSEMBLY__ */ 77 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 78 #endif /* __ASSEMBLY__ */ 79 80 #endif /* CONFIG_BROKEN_GAS_INST */ 81 82 /* 83 * Instructions for modifying PSTATE fields. 84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 85 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 86 * for accessing PSTATE fields have the following encoding: 87 * Op0 = 0, CRn = 4 88 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 89 * CRm = Imm4 for the instruction. 90 * Rt = 0x1f 91 */ 92 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 93 #define PSTATE_Imm_shift CRm_shift 94 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) 95 96 #define PSTATE_PAN pstate_field(0, 4) 97 #define PSTATE_UAO pstate_field(0, 3) 98 #define PSTATE_SSBS pstate_field(3, 1) 99 #define PSTATE_DIT pstate_field(3, 2) 100 #define PSTATE_TCO pstate_field(3, 4) 101 102 #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) 103 #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) 104 #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) 105 #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) 106 #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) 107 108 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 109 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 110 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 111 #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) 112 113 /* Register-based PAN access, for save/restore purposes */ 114 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) 115 116 #define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \ 117 __emit_inst(0xd5000000 | \ 118 sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \ 119 ((Rt) & 0x1f)) 120 121 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31) 122 #define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31) 123 #define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31) 124 125 /* Data cache zero operations */ 126 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 127 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 128 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 129 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 130 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 131 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 132 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 133 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 134 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 135 136 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0) 137 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0) 138 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1) 139 140 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1) 141 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3) 142 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5) 143 144 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1) 145 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3) 146 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5) 147 148 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1) 149 150 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1) 151 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3) 152 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5) 153 154 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1) 155 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3) 156 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5) 157 158 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1) 159 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3) 160 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5) 161 162 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1) 163 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3) 164 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4) 165 166 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1) 167 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5) 168 169 /* 170 * Automatically generated definitions for system registers, the 171 * manual encodings below are in the process of being converted to 172 * come from here. The header relies on the definition of sys_reg() 173 * earlier in this file. 174 */ 175 #include "asm/sysreg-defs.h" 176 177 /* 178 * System registers, organised loosely by encoding but grouped together 179 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 180 */ 181 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 182 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 183 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 184 185 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 186 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 187 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 188 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 189 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 190 191 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 192 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) 193 #define OSLSR_EL1_OSLM_NI 0 194 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) 195 #define OSLSR_EL1_OSLK BIT(1) 196 197 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 198 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 199 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 200 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 201 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 202 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 203 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 204 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 205 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 206 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 207 208 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) 209 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) 210 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) 211 #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) 212 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) 213 #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) 214 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) 215 216 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) 217 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) 218 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) 219 220 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) 221 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) 222 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3))) 223 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6) 224 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0) 225 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0) 226 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0) 227 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2) 228 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2) 229 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0) 230 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6) 231 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6) 232 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5) 233 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5) 234 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5) 235 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0) 236 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6) 237 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7) 238 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0) 239 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0) 240 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4) 241 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7) 242 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6) 243 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6) 244 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6) 245 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6) 246 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7) 247 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7) 248 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7) 249 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7) 250 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7) 251 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7) 252 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7) 253 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6) 254 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6) 255 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7) 256 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1) 257 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4) 258 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0) 259 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1) 260 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4))) 261 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0) 262 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4) 263 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4) 264 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4) 265 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2) 266 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2) 267 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3) 268 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0) 269 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0) 270 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0) 271 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1) 272 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0) 273 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2) 274 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2) 275 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2) 276 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2) 277 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2) 278 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) 279 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) 280 281 /* ETM */ 282 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) 283 284 #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) 285 286 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 287 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 288 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 289 290 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 291 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 292 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 293 294 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 295 296 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 297 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 298 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 299 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 300 301 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 302 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 303 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 304 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 305 306 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 307 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 308 309 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 310 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 311 312 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 313 314 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 315 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 316 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 317 318 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 319 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 320 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 321 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 322 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 323 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 324 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4) 325 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5) 326 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6) 327 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 328 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 329 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2) 330 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3) 331 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 332 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 333 334 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 335 336 #define SYS_PAR_EL1_F BIT(0) 337 /* When PAR_EL1.F == 1 */ 338 #define SYS_PAR_EL1_FST GENMASK(6, 1) 339 #define SYS_PAR_EL1_PTW BIT(8) 340 #define SYS_PAR_EL1_S BIT(9) 341 #define SYS_PAR_EL1_AssuredOnly BIT(12) 342 #define SYS_PAR_EL1_TopLevel BIT(13) 343 #define SYS_PAR_EL1_Overlay BIT(14) 344 #define SYS_PAR_EL1_DirtyBit BIT(15) 345 #define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48) 346 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16)) 347 #define SYS_PAR_EL1_RES1 BIT(11) 348 /* When PAR_EL1.F == 0 */ 349 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7) 350 #define SYS_PAR_EL1_NS BIT(9) 351 #define SYS_PAR_EL1_F0_IMPDEF BIT(10) 352 #define SYS_PAR_EL1_NSE BIT(11) 353 #define SYS_PAR_EL1_PA GENMASK_ULL(51, 12) 354 #define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56) 355 #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52)) 356 357 /*** Statistical Profiling Extension ***/ 358 #define PMSEVFR_EL1_RES0_IMP \ 359 (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ 360 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) 361 #define PMSEVFR_EL1_RES0_V1P1 \ 362 (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) 363 #define PMSEVFR_EL1_RES0_V1P2 \ 364 (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) 365 366 /* Buffer error reporting */ 367 #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT 368 #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK 369 370 #define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT 371 #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK 372 373 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL 374 375 /*** End of Statistical Profiling Extension ***/ 376 377 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) 378 #define TRBSR_EL1_BSC_SHIFT 0 379 380 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 381 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 382 383 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 384 385 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 386 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 387 388 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 389 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 390 391 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 392 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 393 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 394 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 395 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 396 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 397 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 398 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 399 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 400 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 401 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 402 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 403 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 404 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 405 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 406 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 407 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 408 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 409 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 410 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 411 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 412 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 413 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 414 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 415 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 416 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 417 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 418 419 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5) 420 421 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 422 423 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 424 425 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 426 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 427 428 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 429 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 430 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 431 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 432 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 433 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 434 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 435 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 436 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 437 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 438 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 439 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 440 441 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 442 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 443 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) 444 445 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 446 447 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 448 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 449 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 450 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 451 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 452 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 453 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 454 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 455 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 456 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 457 458 /* 459 * Group 0 of activity monitors (architected): 460 * op0 op1 CRn CRm op2 461 * Counter: 11 011 1101 010:n<3> n<2:0> 462 * Type: 11 011 1101 011:n<3> n<2:0> 463 * n: 0-15 464 * 465 * Group 1 of activity monitors (auxiliary): 466 * op0 op1 CRn CRm op2 467 * Counter: 11 011 1101 110:n<3> n<2:0> 468 * Type: 11 011 1101 111:n<3> n<2:0> 469 * n: 0-15 470 */ 471 472 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 473 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 474 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 475 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 476 477 /* AMU v1: Fixed (architecturally defined) activity monitors */ 478 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 479 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 480 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 481 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 482 483 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 484 485 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) 486 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2) 487 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) 488 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) 489 490 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 491 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 492 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 493 494 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0) 495 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 496 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 497 498 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 499 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 500 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0) 501 #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0) 502 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 503 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0) 504 #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0) 505 506 #define __PMEV_op2(n) ((n) & 0x7) 507 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 508 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n)) 509 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 510 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 511 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 512 513 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 514 515 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1)) 516 517 #define __SPMEV_op2(n) ((n) & 0x7) 518 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1)) 519 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n)) 520 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n)) 521 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n)) 522 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n)) 523 524 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) 525 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) 526 527 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) 528 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) 529 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) 530 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) 531 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) 532 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) 533 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) 534 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) 535 536 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) 537 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) 538 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) 539 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) 540 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) 541 542 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 543 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 544 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 545 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) 546 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) 547 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1) 548 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2) 549 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3) 550 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 551 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) 552 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) 553 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 554 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 555 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 556 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 557 558 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 559 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) 560 561 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) 562 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) 563 564 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) 565 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) 566 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) 567 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 568 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 569 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 570 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 571 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 572 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 573 574 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 575 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 576 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 577 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 578 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 579 580 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 581 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 582 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 583 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 584 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 585 586 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 587 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 588 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 589 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 590 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 591 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 592 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 593 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 594 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 595 596 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 597 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 598 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 599 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 600 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 601 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 602 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 603 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 604 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 605 606 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) 607 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) 608 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) 609 610 #define __AMEV_op2(m) (m & 0x7) 611 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) 612 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) 613 #define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) 614 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) 615 #define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) 616 617 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) 618 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) 619 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) 620 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) 621 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) 622 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) 623 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) 624 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) 625 626 /* VHE encodings for architectural EL0/1 system registers */ 627 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) 628 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 629 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 630 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 631 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 632 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 633 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 634 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 635 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 636 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) 637 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 638 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 639 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 640 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) 641 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 642 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 643 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 644 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 645 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 646 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 647 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 648 649 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) 650 651 /* AT instructions */ 652 #define AT_Op0 1 653 #define AT_CRn 7 654 655 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0) 656 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1) 657 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2) 658 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3) 659 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0) 660 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1) 661 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2) 662 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0) 663 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1) 664 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4) 665 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5) 666 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6) 667 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7) 668 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2) 669 670 /* TLBI instructions */ 671 #define TLBI_Op0 1 672 673 #define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */ 674 #define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */ 675 676 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */ 677 #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/ 678 679 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */ 680 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */ 681 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */ 682 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */ 683 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */ 684 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */ 685 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */ 686 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */ 687 688 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0) 689 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1) 690 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2) 691 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3) 692 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5) 693 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7) 694 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1) 695 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3) 696 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5) 697 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7) 698 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0) 699 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1) 700 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2) 701 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3) 702 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5) 703 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7) 704 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1) 705 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3) 706 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5) 707 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7) 708 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1) 709 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3) 710 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5) 711 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7) 712 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0) 713 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1) 714 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2) 715 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3) 716 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5) 717 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7) 718 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0) 719 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1) 720 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2) 721 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3) 722 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5) 723 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7) 724 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1) 725 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3) 726 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5) 727 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7) 728 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0) 729 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1) 730 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2) 731 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3) 732 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5) 733 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7) 734 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1) 735 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3) 736 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5) 737 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7) 738 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1) 739 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3) 740 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5) 741 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7) 742 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0) 743 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1) 744 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2) 745 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3) 746 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5) 747 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7) 748 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1) 749 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2) 750 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5) 751 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6) 752 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0) 753 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1) 754 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4) 755 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5) 756 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6) 757 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1) 758 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5) 759 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0) 760 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1) 761 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4) 762 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5) 763 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6) 764 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0) 765 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1) 766 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2) 767 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3) 768 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4) 769 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5) 770 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6) 771 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7) 772 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1) 773 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5) 774 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1) 775 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5) 776 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0) 777 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1) 778 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4) 779 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5) 780 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6) 781 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1) 782 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2) 783 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5) 784 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6) 785 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0) 786 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1) 787 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4) 788 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5) 789 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6) 790 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1) 791 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5) 792 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0) 793 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1) 794 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4) 795 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5) 796 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6) 797 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0) 798 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1) 799 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2) 800 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3) 801 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4) 802 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5) 803 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6) 804 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7) 805 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1) 806 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5) 807 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1) 808 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5) 809 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0) 810 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1) 811 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4) 812 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) 813 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) 814 815 /* Misc instructions */ 816 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4) 817 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5) 818 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6) 819 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0) 820 821 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) 822 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) 823 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) 824 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) 825 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) 826 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) 827 828 /* Common SCTLR_ELx flags. */ 829 #define SCTLR_ELx_ENTP2 (BIT(60)) 830 #define SCTLR_ELx_DSSBS (BIT(44)) 831 #define SCTLR_ELx_ATA (BIT(43)) 832 833 #define SCTLR_ELx_EE_SHIFT 25 834 #define SCTLR_ELx_ENIA_SHIFT 31 835 836 #define SCTLR_ELx_ITFSB (BIT(37)) 837 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 838 #define SCTLR_ELx_ENIB (BIT(30)) 839 #define SCTLR_ELx_LSMAOE (BIT(29)) 840 #define SCTLR_ELx_nTLSMD (BIT(28)) 841 #define SCTLR_ELx_ENDA (BIT(27)) 842 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT)) 843 #define SCTLR_ELx_EIS (BIT(22)) 844 #define SCTLR_ELx_IESB (BIT(21)) 845 #define SCTLR_ELx_TSCXT (BIT(20)) 846 #define SCTLR_ELx_WXN (BIT(19)) 847 #define SCTLR_ELx_ENDB (BIT(13)) 848 #define SCTLR_ELx_I (BIT(12)) 849 #define SCTLR_ELx_EOS (BIT(11)) 850 #define SCTLR_ELx_SA (BIT(3)) 851 #define SCTLR_ELx_C (BIT(2)) 852 #define SCTLR_ELx_A (BIT(1)) 853 #define SCTLR_ELx_M (BIT(0)) 854 855 /* SCTLR_EL2 specific flags. */ 856 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 857 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 858 (BIT(29))) 859 860 #define SCTLR_EL2_BT (BIT(36)) 861 #ifdef CONFIG_CPU_BIG_ENDIAN 862 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 863 #else 864 #define ENDIAN_SET_EL2 0 865 #endif 866 867 #define INIT_SCTLR_EL2_MMU_ON \ 868 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 869 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ 870 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) 871 872 #define INIT_SCTLR_EL2_MMU_OFF \ 873 (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) 874 875 /* SCTLR_EL1 specific flags. */ 876 #ifdef CONFIG_CPU_BIG_ENDIAN 877 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 878 #else 879 #define ENDIAN_SET_EL1 0 880 #endif 881 882 #define INIT_SCTLR_EL1_MMU_OFF \ 883 (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ 884 SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 885 886 #define INIT_SCTLR_EL1_MMU_ON \ 887 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ 888 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ 889 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ 890 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 891 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ 892 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ 893 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 894 895 /* MAIR_ELx memory attributes (used by Linux) */ 896 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 897 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 898 #define MAIR_ATTR_NORMAL_NC UL(0x44) 899 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 900 #define MAIR_ATTR_NORMAL UL(0xff) 901 #define MAIR_ATTR_MASK UL(0xff) 902 903 /* Position the attr at the correct index */ 904 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 905 906 /* id_aa64mmfr0 */ 907 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 908 #define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 909 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 910 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 911 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 912 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 913 #define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 914 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf 915 916 #define ARM64_MIN_PARANGE_BITS 32 917 918 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 919 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 920 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 921 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 922 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 923 924 #ifdef CONFIG_ARM64_PA_BITS_52 925 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 926 #else 927 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 928 #endif 929 930 #if defined(CONFIG_ARM64_4K_PAGES) 931 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT 932 #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 933 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 934 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 935 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 936 #elif defined(CONFIG_ARM64_16K_PAGES) 937 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT 938 #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 939 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 940 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 941 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 942 #elif defined(CONFIG_ARM64_64K_PAGES) 943 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT 944 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 945 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 946 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 947 #endif 948 949 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ 950 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ 951 952 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ 953 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ 954 955 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 956 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 957 958 /* GCR_EL1 Definitions */ 959 #define SYS_GCR_EL1_RRND (BIT(16)) 960 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 961 962 #ifdef CONFIG_KASAN_HW_TAGS 963 /* 964 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it 965 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. 966 */ 967 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) 968 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) 969 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) 970 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) 971 #else 972 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK 973 #endif 974 975 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 976 977 /* RGSR_EL1 Definitions */ 978 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 979 #define SYS_RGSR_EL1_SEED_SHIFT 8 980 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 981 982 /* TFSR{,E0}_EL1 bit definitions */ 983 #define SYS_TFSR_EL1_TF0_SHIFT 0 984 #define SYS_TFSR_EL1_TF1_SHIFT 1 985 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 986 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 987 988 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 989 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 990 991 /* GIC Hypervisor interface registers */ 992 /* ICH_LR*_EL2 bit definitions */ 993 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 994 995 #define ICH_LR_EOI (1ULL << 41) 996 #define ICH_LR_GROUP (1ULL << 60) 997 #define ICH_LR_HW (1ULL << 61) 998 #define ICH_LR_STATE (3ULL << 62) 999 #define ICH_LR_PENDING_BIT (1ULL << 62) 1000 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 1001 #define ICH_LR_PHYS_ID_SHIFT 32 1002 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 1003 #define ICH_LR_PRIORITY_SHIFT 48 1004 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 1005 1006 /* ICH_VMCR_EL2 bit definitions */ 1007 #define ICH_VMCR_ACK_CTL_SHIFT 2 1008 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) 1009 #define ICH_VMCR_FIQ_EN_SHIFT 3 1010 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) 1011 #define ICH_VMCR_CBPR_SHIFT 4 1012 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) 1013 #define ICH_VMCR_EOIM_SHIFT 9 1014 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) 1015 #define ICH_VMCR_BPR1_SHIFT 18 1016 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) 1017 #define ICH_VMCR_BPR0_SHIFT 21 1018 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) 1019 #define ICH_VMCR_PMR_SHIFT 24 1020 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) 1021 #define ICH_VMCR_ENG0_SHIFT 0 1022 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) 1023 #define ICH_VMCR_ENG1_SHIFT 1 1024 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) 1025 1026 /* 1027 * Permission Indirection Extension (PIE) permission encodings. 1028 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). 1029 */ 1030 #define PIE_NONE_O UL(0x0) 1031 #define PIE_R_O UL(0x1) 1032 #define PIE_X_O UL(0x2) 1033 #define PIE_RX_O UL(0x3) 1034 #define PIE_RW_O UL(0x5) 1035 #define PIE_RWnX_O UL(0x6) 1036 #define PIE_RWX_O UL(0x7) 1037 #define PIE_R UL(0x8) 1038 #define PIE_GCS UL(0x9) 1039 #define PIE_RX UL(0xa) 1040 #define PIE_RW UL(0xc) 1041 #define PIE_RWX UL(0xe) 1042 #define PIE_MASK UL(0xf) 1043 1044 #define PIRx_ELx_BITS_PER_IDX 4 1045 #define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX) 1046 #define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx)) 1047 1048 /* 1049 * Permission Overlay Extension (POE) permission encodings. 1050 */ 1051 #define POE_NONE UL(0x0) 1052 #define POE_R UL(0x1) 1053 #define POE_X UL(0x2) 1054 #define POE_RX UL(0x3) 1055 #define POE_W UL(0x4) 1056 #define POE_RW UL(0x5) 1057 #define POE_WX UL(0x6) 1058 #define POE_RWX UL(0x7) 1059 #define POE_MASK UL(0xf) 1060 1061 #define POR_ELx_BITS_PER_IDX 4 1062 #define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX) 1063 #define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK) 1064 #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx)) 1065 1066 /* 1067 * Definitions for Guarded Control Stack 1068 */ 1069 1070 #define GCS_CAP_ADDR_MASK GENMASK(63, 12) 1071 #define GCS_CAP_ADDR_SHIFT 12 1072 #define GCS_CAP_ADDR_WIDTH 52 1073 #define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x) 1074 1075 #define GCS_CAP_TOKEN_MASK GENMASK(11, 0) 1076 #define GCS_CAP_TOKEN_SHIFT 0 1077 #define GCS_CAP_TOKEN_WIDTH 12 1078 #define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x) 1079 1080 #define GCS_CAP_VALID_TOKEN 0x1 1081 #define GCS_CAP_IN_PROGRESS_TOKEN 0x5 1082 1083 #define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \ 1084 GCS_CAP_VALID_TOKEN) 1085 /* 1086 * Definitions for GICv5 instructions 1087 */ 1088 #define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3) 1089 #define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0) 1090 #define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0) 1091 #define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1) 1092 #define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1) 1093 #define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7) 1094 #define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4) 1095 #define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2) 1096 #define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5) 1097 #define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0) 1098 1099 /* Definitions for GIC CDAFF */ 1100 #define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32) 1101 #define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29) 1102 #define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28) 1103 #define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0) 1104 1105 /* Definitions for GIC CDDI */ 1106 #define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29) 1107 #define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0) 1108 1109 /* Definitions for GIC CDDIS */ 1110 #define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29) 1111 #define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r) 1112 #define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0) 1113 #define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r) 1114 1115 /* Definitions for GIC CDEN */ 1116 #define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29) 1117 #define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0) 1118 1119 /* Definitions for GIC CDHM */ 1120 #define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32) 1121 #define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29) 1122 #define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0) 1123 1124 /* Definitions for GIC CDPEND */ 1125 #define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32) 1126 #define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29) 1127 #define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0) 1128 1129 /* Definitions for GIC CDPRI */ 1130 #define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35) 1131 #define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29) 1132 #define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0) 1133 1134 /* Definitions for GIC CDRCFG */ 1135 #define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29) 1136 #define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0) 1137 1138 /* Definitions for GICR CDIA */ 1139 #define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32) 1140 #define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r) 1141 #define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29) 1142 #define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0) 1143 1144 #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) 1145 #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) 1146 1147 #define ARM64_FEATURE_FIELD_BITS 4 1148 1149 #ifdef __ASSEMBLY__ 1150 1151 .macro mrs_s, rt, sreg 1152 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) 1153 .endm 1154 1155 .macro msr_s, sreg, rt 1156 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) 1157 .endm 1158 1159 .macro msr_hcr_el2, reg 1160 #if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) 1161 dsb nsh 1162 msr hcr_el2, \reg 1163 isb 1164 #else 1165 msr hcr_el2, \reg 1166 #endif 1167 .endm 1168 #else 1169 1170 #include <linux/bitfield.h> 1171 #include <linux/build_bug.h> 1172 #include <linux/types.h> 1173 #include <asm/alternative.h> 1174 1175 #define DEFINE_MRS_S \ 1176 __DEFINE_ASM_GPR_NUMS \ 1177 " .macro mrs_s, rt, sreg\n" \ 1178 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1179 " .endm\n" 1180 1181 #define DEFINE_MSR_S \ 1182 __DEFINE_ASM_GPR_NUMS \ 1183 " .macro msr_s, sreg, rt\n" \ 1184 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1185 " .endm\n" 1186 1187 #define UNDEFINE_MRS_S \ 1188 " .purgem mrs_s\n" 1189 1190 #define UNDEFINE_MSR_S \ 1191 " .purgem msr_s\n" 1192 1193 #define __mrs_s(v, r) \ 1194 DEFINE_MRS_S \ 1195 " mrs_s " v ", " __stringify(r) "\n" \ 1196 UNDEFINE_MRS_S 1197 1198 #define __msr_s(r, v) \ 1199 DEFINE_MSR_S \ 1200 " msr_s " __stringify(r) ", " v "\n" \ 1201 UNDEFINE_MSR_S 1202 1203 /* 1204 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1205 * optimized away or replaced with synthetic values. 1206 */ 1207 #define read_sysreg(r) ({ \ 1208 u64 __val; \ 1209 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1210 __val; \ 1211 }) 1212 1213 /* 1214 * The "Z" constraint normally means a zero immediate, but when combined with 1215 * the "%x0" template means XZR. 1216 */ 1217 #define write_sysreg(v, r) do { \ 1218 u64 __val = (u64)(v); \ 1219 asm volatile("msr " __stringify(r) ", %x0" \ 1220 : : "rZ" (__val)); \ 1221 } while (0) 1222 1223 /* 1224 * For registers without architectural names, or simply unsupported by 1225 * GAS. 1226 * 1227 * __check_r forces warnings to be generated by the compiler when 1228 * evaluating r which wouldn't normally happen due to being passed to 1229 * the assembler via __stringify(r). 1230 */ 1231 #define read_sysreg_s(r) ({ \ 1232 u64 __val; \ 1233 u32 __maybe_unused __check_r = (u32)(r); \ 1234 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1235 __val; \ 1236 }) 1237 1238 #define write_sysreg_s(v, r) do { \ 1239 u64 __val = (u64)(v); \ 1240 u32 __maybe_unused __check_r = (u32)(r); \ 1241 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 1242 } while (0) 1243 1244 /* 1245 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1246 * set mask are set. Other bits are left as-is. 1247 */ 1248 #define sysreg_clear_set(sysreg, clear, set) do { \ 1249 u64 __scs_val = read_sysreg(sysreg); \ 1250 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1251 if (__scs_new != __scs_val) \ 1252 write_sysreg(__scs_new, sysreg); \ 1253 } while (0) 1254 1255 #define sysreg_clear_set_hcr(clear, set) do { \ 1256 u64 __scs_val = read_sysreg(hcr_el2); \ 1257 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1258 if (__scs_new != __scs_val) \ 1259 write_sysreg_hcr(__scs_new); \ 1260 } while (0) 1261 1262 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1263 u64 __scs_val = read_sysreg_s(sysreg); \ 1264 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1265 if (__scs_new != __scs_val) \ 1266 write_sysreg_s(__scs_new, sysreg); \ 1267 } while (0) 1268 1269 #define write_sysreg_hcr(__val) do { \ 1270 if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \ 1271 (!system_capabilities_finalized() || \ 1272 alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \ 1273 asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \ 1274 : : "rZ" (__val)); \ 1275 else \ 1276 asm volatile("msr hcr_el2, %x0" \ 1277 : : "rZ" (__val)); \ 1278 } while (0) 1279 1280 #define read_sysreg_par() ({ \ 1281 u64 par; \ 1282 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1283 par = read_sysreg(par_el1); \ 1284 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1285 par; \ 1286 }) 1287 1288 #define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val 1289 1290 #define SYS_FIELD_GET(reg, field, val) \ 1291 FIELD_GET(reg##_##field##_MASK, val) 1292 1293 #define SYS_FIELD_PREP(reg, field, val) \ 1294 FIELD_PREP(reg##_##field##_MASK, val) 1295 1296 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 1297 FIELD_PREP(reg##_##field##_MASK, \ 1298 SYS_FIELD_VALUE(reg, field, val)) 1299 1300 #endif 1301 1302 #endif /* __ASM_SYSREG_H */ 1303