1 /* 2 * Based on arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PTRACE_H 20 #define __ASM_PTRACE_H 21 22 #include <uapi/asm/ptrace.h> 23 24 /* AArch32-specific ptrace requests */ 25 #define COMPAT_PTRACE_GETREGS 12 26 #define COMPAT_PTRACE_SETREGS 13 27 #define COMPAT_PTRACE_GET_THREAD_AREA 22 28 #define COMPAT_PTRACE_SET_SYSCALL 23 29 #define COMPAT_PTRACE_GETVFPREGS 27 30 #define COMPAT_PTRACE_SETVFPREGS 28 31 #define COMPAT_PTRACE_GETHBPREGS 29 32 #define COMPAT_PTRACE_SETHBPREGS 30 33 34 /* AArch32 CPSR bits */ 35 #define COMPAT_PSR_MODE_MASK 0x0000001f 36 #define COMPAT_PSR_MODE_USR 0x00000010 37 #define COMPAT_PSR_MODE_FIQ 0x00000011 38 #define COMPAT_PSR_MODE_IRQ 0x00000012 39 #define COMPAT_PSR_MODE_SVC 0x00000013 40 #define COMPAT_PSR_MODE_ABT 0x00000017 41 #define COMPAT_PSR_MODE_HYP 0x0000001a 42 #define COMPAT_PSR_MODE_UND 0x0000001b 43 #define COMPAT_PSR_MODE_SYS 0x0000001f 44 #define COMPAT_PSR_T_BIT 0x00000020 45 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 46 /* 47 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 48 * process is located in memory. 49 */ 50 #define COMPAT_PT_TEXT_ADDR 0x10000 51 #define COMPAT_PT_DATA_ADDR 0x10004 52 #define COMPAT_PT_TEXT_END_ADDR 0x10008 53 #ifndef __ASSEMBLY__ 54 55 /* sizeof(struct user) for AArch32 */ 56 #define COMPAT_USER_SZ 296 57 58 /* Architecturally defined mapping between AArch32 and AArch64 registers */ 59 #define compat_usr(x) regs[(x)] 60 #define compat_sp regs[13] 61 #define compat_lr regs[14] 62 #define compat_sp_hyp regs[15] 63 #define compat_sp_irq regs[16] 64 #define compat_lr_irq regs[17] 65 #define compat_sp_svc regs[18] 66 #define compat_lr_svc regs[19] 67 #define compat_sp_abt regs[20] 68 #define compat_lr_abt regs[21] 69 #define compat_sp_und regs[22] 70 #define compat_lr_und regs[23] 71 #define compat_r8_fiq regs[24] 72 #define compat_r9_fiq regs[25] 73 #define compat_r10_fiq regs[26] 74 #define compat_r11_fiq regs[27] 75 #define compat_r12_fiq regs[28] 76 #define compat_sp_fiq regs[29] 77 #define compat_lr_fiq regs[30] 78 79 /* 80 * This struct defines the way the registers are stored on the stack during an 81 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 82 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 83 */ 84 struct pt_regs { 85 union { 86 struct user_pt_regs user_regs; 87 struct { 88 u64 regs[31]; 89 u64 sp; 90 u64 pc; 91 u64 pstate; 92 }; 93 }; 94 u64 orig_x0; 95 u64 syscallno; 96 }; 97 98 #define arch_has_single_step() (1) 99 100 #ifdef CONFIG_COMPAT 101 #define compat_thumb_mode(regs) \ 102 (((regs)->pstate & COMPAT_PSR_T_BIT)) 103 #else 104 #define compat_thumb_mode(regs) (0) 105 #endif 106 107 #define user_mode(regs) \ 108 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 109 110 #define compat_user_mode(regs) \ 111 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 112 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 113 114 #define processor_mode(regs) \ 115 ((regs)->pstate & PSR_MODE_MASK) 116 117 #define interrupts_enabled(regs) \ 118 (!((regs)->pstate & PSR_I_BIT)) 119 120 #define fast_interrupts_enabled(regs) \ 121 (!((regs)->pstate & PSR_F_BIT)) 122 123 #define user_stack_pointer(regs) \ 124 ((regs)->sp) 125 126 /* 127 * Are the current registers suitable for user mode? (used to maintain 128 * security in signal handlers) 129 */ 130 static inline int valid_user_regs(struct user_pt_regs *regs) 131 { 132 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { 133 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); 134 135 /* The T bit is reserved for AArch64 */ 136 if (!(regs->pstate & PSR_MODE32_BIT)) 137 regs->pstate &= ~COMPAT_PSR_T_BIT; 138 139 return 1; 140 } 141 142 /* 143 * Force PSR to something logical... 144 */ 145 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ 146 COMPAT_PSR_T_BIT | PSR_MODE32_BIT; 147 148 if (!(regs->pstate & PSR_MODE32_BIT)) { 149 regs->pstate &= ~COMPAT_PSR_T_BIT; 150 regs->pstate |= PSR_MODE_EL0t; 151 } 152 153 return 0; 154 } 155 156 #define instruction_pointer(regs) (regs)->pc 157 158 #ifdef CONFIG_SMP 159 extern unsigned long profile_pc(struct pt_regs *regs); 160 #else 161 #define profile_pc(regs) instruction_pointer(regs) 162 #endif 163 164 extern int aarch32_break_trap(struct pt_regs *regs); 165 166 #endif /* __ASSEMBLY__ */ 167 #endif 168