1 /* 2 * Based on arch/arm/include/asm/ptrace.h 3 * 4 * Copyright (C) 1996-2003 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_PTRACE_H 20 #define __ASM_PTRACE_H 21 22 #include <uapi/asm/ptrace.h> 23 24 /* Current Exception Level values, as contained in CurrentEL */ 25 #define CurrentEL_EL1 (1 << 2) 26 #define CurrentEL_EL2 (2 << 2) 27 28 /* AArch32-specific ptrace requests */ 29 #define COMPAT_PTRACE_GETREGS 12 30 #define COMPAT_PTRACE_SETREGS 13 31 #define COMPAT_PTRACE_GET_THREAD_AREA 22 32 #define COMPAT_PTRACE_SET_SYSCALL 23 33 #define COMPAT_PTRACE_GETVFPREGS 27 34 #define COMPAT_PTRACE_SETVFPREGS 28 35 #define COMPAT_PTRACE_GETHBPREGS 29 36 #define COMPAT_PTRACE_SETHBPREGS 30 37 38 /* AArch32 CPSR bits */ 39 #define COMPAT_PSR_MODE_MASK 0x0000001f 40 #define COMPAT_PSR_MODE_USR 0x00000010 41 #define COMPAT_PSR_MODE_FIQ 0x00000011 42 #define COMPAT_PSR_MODE_IRQ 0x00000012 43 #define COMPAT_PSR_MODE_SVC 0x00000013 44 #define COMPAT_PSR_MODE_ABT 0x00000017 45 #define COMPAT_PSR_MODE_HYP 0x0000001a 46 #define COMPAT_PSR_MODE_UND 0x0000001b 47 #define COMPAT_PSR_MODE_SYS 0x0000001f 48 #define COMPAT_PSR_T_BIT 0x00000020 49 #define COMPAT_PSR_E_BIT 0x00000200 50 #define COMPAT_PSR_F_BIT 0x00000040 51 #define COMPAT_PSR_I_BIT 0x00000080 52 #define COMPAT_PSR_A_BIT 0x00000100 53 #define COMPAT_PSR_E_BIT 0x00000200 54 #define COMPAT_PSR_J_BIT 0x01000000 55 #define COMPAT_PSR_Q_BIT 0x08000000 56 #define COMPAT_PSR_V_BIT 0x10000000 57 #define COMPAT_PSR_C_BIT 0x20000000 58 #define COMPAT_PSR_Z_BIT 0x40000000 59 #define COMPAT_PSR_N_BIT 0x80000000 60 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */ 61 62 #ifdef CONFIG_CPU_BIG_ENDIAN 63 #define COMPAT_PSR_ENDSTATE COMPAT_PSR_E_BIT 64 #else 65 #define COMPAT_PSR_ENDSTATE 0 66 #endif 67 68 /* 69 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a 70 * process is located in memory. 71 */ 72 #define COMPAT_PT_TEXT_ADDR 0x10000 73 #define COMPAT_PT_DATA_ADDR 0x10004 74 #define COMPAT_PT_TEXT_END_ADDR 0x10008 75 #ifndef __ASSEMBLY__ 76 77 /* sizeof(struct user) for AArch32 */ 78 #define COMPAT_USER_SZ 296 79 80 /* Architecturally defined mapping between AArch32 and AArch64 registers */ 81 #define compat_usr(x) regs[(x)] 82 #define compat_fp regs[11] 83 #define compat_sp regs[13] 84 #define compat_lr regs[14] 85 #define compat_sp_hyp regs[15] 86 #define compat_sp_irq regs[16] 87 #define compat_lr_irq regs[17] 88 #define compat_sp_svc regs[18] 89 #define compat_lr_svc regs[19] 90 #define compat_sp_abt regs[20] 91 #define compat_lr_abt regs[21] 92 #define compat_sp_und regs[22] 93 #define compat_lr_und regs[23] 94 #define compat_r8_fiq regs[24] 95 #define compat_r9_fiq regs[25] 96 #define compat_r10_fiq regs[26] 97 #define compat_r11_fiq regs[27] 98 #define compat_r12_fiq regs[28] 99 #define compat_sp_fiq regs[29] 100 #define compat_lr_fiq regs[30] 101 102 /* 103 * This struct defines the way the registers are stored on the stack during an 104 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for 105 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. 106 */ 107 struct pt_regs { 108 union { 109 struct user_pt_regs user_regs; 110 struct { 111 u64 regs[31]; 112 u64 sp; 113 u64 pc; 114 u64 pstate; 115 }; 116 }; 117 u64 orig_x0; 118 u64 syscallno; 119 }; 120 121 #define arch_has_single_step() (1) 122 123 #ifdef CONFIG_COMPAT 124 #define compat_thumb_mode(regs) \ 125 (((regs)->pstate & COMPAT_PSR_T_BIT)) 126 #else 127 #define compat_thumb_mode(regs) (0) 128 #endif 129 130 #define user_mode(regs) \ 131 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) 132 133 #define compat_user_mode(regs) \ 134 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ 135 (PSR_MODE32_BIT | PSR_MODE_EL0t)) 136 137 #define processor_mode(regs) \ 138 ((regs)->pstate & PSR_MODE_MASK) 139 140 #define interrupts_enabled(regs) \ 141 (!((regs)->pstate & PSR_I_BIT)) 142 143 #define fast_interrupts_enabled(regs) \ 144 (!((regs)->pstate & PSR_F_BIT)) 145 146 #define user_stack_pointer(regs) \ 147 (!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp) 148 149 static inline unsigned long regs_return_value(struct pt_regs *regs) 150 { 151 return regs->regs[0]; 152 } 153 154 /* 155 * Are the current registers suitable for user mode? (used to maintain 156 * security in signal handlers) 157 */ 158 static inline int valid_user_regs(struct user_pt_regs *regs) 159 { 160 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) { 161 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT); 162 163 /* The T bit is reserved for AArch64 */ 164 if (!(regs->pstate & PSR_MODE32_BIT)) 165 regs->pstate &= ~COMPAT_PSR_T_BIT; 166 167 return 1; 168 } 169 170 /* 171 * Force PSR to something logical... 172 */ 173 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \ 174 COMPAT_PSR_T_BIT | PSR_MODE32_BIT; 175 176 if (!(regs->pstate & PSR_MODE32_BIT)) { 177 regs->pstate &= ~COMPAT_PSR_T_BIT; 178 regs->pstate |= PSR_MODE_EL0t; 179 } 180 181 return 0; 182 } 183 184 #define instruction_pointer(regs) ((unsigned long)(regs)->pc) 185 186 extern unsigned long profile_pc(struct pt_regs *regs); 187 188 #endif /* __ASSEMBLY__ */ 189 #endif 190