1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Based on arch/arm/include/asm/processor.h 4 * 5 * Copyright (C) 1995-1999 Russell King 6 * Copyright (C) 2012 ARM Ltd. 7 */ 8 #ifndef __ASM_PROCESSOR_H 9 #define __ASM_PROCESSOR_H 10 11 /* 12 * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is 13 * no point in shifting all network buffers by 2 bytes just to make some IP 14 * header fields appear aligned in memory, potentially sacrificing some DMA 15 * performance on some platforms. 16 */ 17 #define NET_IP_ALIGN 0 18 19 #ifndef __ASSEMBLY__ 20 21 #include <linux/build_bug.h> 22 #include <linux/cache.h> 23 #include <linux/init.h> 24 #include <linux/stddef.h> 25 #include <linux/string.h> 26 #include <linux/thread_info.h> 27 28 #include <vdso/processor.h> 29 30 #include <asm/alternative.h> 31 #include <asm/cpufeature.h> 32 #include <asm/hw_breakpoint.h> 33 #include <asm/kasan.h> 34 #include <asm/lse.h> 35 #include <asm/pgtable-hwdef.h> 36 #include <asm/pointer_auth.h> 37 #include <asm/ptrace.h> 38 #include <asm/spectre.h> 39 #include <asm/types.h> 40 41 /* 42 * TASK_SIZE - the maximum size of a user space task. 43 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area. 44 */ 45 46 #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN) 47 #define TASK_SIZE_64 (UL(1) << vabits_actual) 48 #define TASK_SIZE_MAX (UL(1) << VA_BITS) 49 50 #ifdef CONFIG_COMPAT 51 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS) 52 /* 53 * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied 54 * by the compat vectors page. 55 */ 56 #define TASK_SIZE_32 UL(0x100000000) 57 #else 58 #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE) 59 #endif /* CONFIG_ARM64_64K_PAGES */ 60 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ 61 TASK_SIZE_32 : TASK_SIZE_64) 62 #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \ 63 TASK_SIZE_32 : TASK_SIZE_64) 64 #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \ 65 TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64) 66 #else 67 #define TASK_SIZE TASK_SIZE_64 68 #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64 69 #endif /* CONFIG_COMPAT */ 70 71 #ifdef CONFIG_ARM64_FORCE_52BIT 72 #define STACK_TOP_MAX TASK_SIZE_64 73 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4)) 74 #else 75 #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64 76 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4)) 77 #endif /* CONFIG_ARM64_FORCE_52BIT */ 78 79 #ifdef CONFIG_COMPAT 80 #define AARCH32_VECTORS_BASE 0xffff0000 81 #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \ 82 AARCH32_VECTORS_BASE : STACK_TOP_MAX) 83 #else 84 #define STACK_TOP STACK_TOP_MAX 85 #endif /* CONFIG_COMPAT */ 86 87 #ifndef CONFIG_ARM64_FORCE_52BIT 88 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\ 89 DEFAULT_MAP_WINDOW) 90 91 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \ 92 base + TASK_SIZE - DEFAULT_MAP_WINDOW :\ 93 base) 94 #endif /* CONFIG_ARM64_FORCE_52BIT */ 95 96 extern phys_addr_t arm64_dma_phys_limit; 97 extern phys_addr_t arm64_dma32_phys_limit; 98 #define ARCH_LOW_ADDRESS_LIMIT ((arm64_dma_phys_limit ? : arm64_dma32_phys_limit) - 1) 99 100 struct debug_info { 101 #ifdef CONFIG_HAVE_HW_BREAKPOINT 102 /* Have we suspended stepping by a debugger? */ 103 int suspended_step; 104 /* Allow breakpoints and watchpoints to be disabled for this thread. */ 105 int bps_disabled; 106 int wps_disabled; 107 /* Hardware breakpoints pinned to this task. */ 108 struct perf_event *hbp_break[ARM_MAX_BRP]; 109 struct perf_event *hbp_watch[ARM_MAX_WRP]; 110 #endif 111 }; 112 113 struct cpu_context { 114 unsigned long x19; 115 unsigned long x20; 116 unsigned long x21; 117 unsigned long x22; 118 unsigned long x23; 119 unsigned long x24; 120 unsigned long x25; 121 unsigned long x26; 122 unsigned long x27; 123 unsigned long x28; 124 unsigned long fp; 125 unsigned long sp; 126 unsigned long pc; 127 }; 128 129 struct thread_struct { 130 struct cpu_context cpu_context; /* cpu context */ 131 132 /* 133 * Whitelisted fields for hardened usercopy: 134 * Maintainers must ensure manually that this contains no 135 * implicit padding. 136 */ 137 struct { 138 unsigned long tp_value; /* TLS register */ 139 unsigned long tp2_value; 140 struct user_fpsimd_state fpsimd_state; 141 } uw; 142 143 unsigned int fpsimd_cpu; 144 void *sve_state; /* SVE registers, if any */ 145 unsigned int sve_vl; /* SVE vector length */ 146 unsigned int sve_vl_onexec; /* SVE vl after next exec */ 147 unsigned long fault_address; /* fault info */ 148 unsigned long fault_code; /* ESR_EL1 value */ 149 struct debug_info debug; /* debugging */ 150 #ifdef CONFIG_ARM64_PTR_AUTH 151 struct ptrauth_keys_user keys_user; 152 struct ptrauth_keys_kernel keys_kernel; 153 #endif 154 #ifdef CONFIG_ARM64_MTE 155 u64 sctlr_tcf0; 156 u64 gcr_user_excl; 157 #endif 158 }; 159 160 static inline void arch_thread_struct_whitelist(unsigned long *offset, 161 unsigned long *size) 162 { 163 /* Verify that there is no padding among the whitelisted fields: */ 164 BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) != 165 sizeof_field(struct thread_struct, uw.tp_value) + 166 sizeof_field(struct thread_struct, uw.tp2_value) + 167 sizeof_field(struct thread_struct, uw.fpsimd_state)); 168 169 *offset = offsetof(struct thread_struct, uw); 170 *size = sizeof_field(struct thread_struct, uw); 171 } 172 173 #ifdef CONFIG_COMPAT 174 #define task_user_tls(t) \ 175 ({ \ 176 unsigned long *__tls; \ 177 if (is_compat_thread(task_thread_info(t))) \ 178 __tls = &(t)->thread.uw.tp2_value; \ 179 else \ 180 __tls = &(t)->thread.uw.tp_value; \ 181 __tls; \ 182 }) 183 #else 184 #define task_user_tls(t) (&(t)->thread.uw.tp_value) 185 #endif 186 187 /* Sync TPIDR_EL0 back to thread_struct for current */ 188 void tls_preserve_current_state(void); 189 190 #define INIT_THREAD { \ 191 .fpsimd_cpu = NR_CPUS, \ 192 } 193 194 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) 195 { 196 memset(regs, 0, sizeof(*regs)); 197 forget_syscall(regs); 198 regs->pc = pc; 199 200 if (system_uses_irq_prio_masking()) 201 regs->pmr_save = GIC_PRIO_IRQON; 202 } 203 204 static inline void start_thread(struct pt_regs *regs, unsigned long pc, 205 unsigned long sp) 206 { 207 start_thread_common(regs, pc); 208 regs->pstate = PSR_MODE_EL0t; 209 spectre_v4_enable_task_mitigation(current); 210 regs->sp = sp; 211 } 212 213 #ifdef CONFIG_COMPAT 214 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc, 215 unsigned long sp) 216 { 217 start_thread_common(regs, pc); 218 regs->pstate = PSR_AA32_MODE_USR; 219 if (pc & 1) 220 regs->pstate |= PSR_AA32_T_BIT; 221 222 #ifdef __AARCH64EB__ 223 regs->pstate |= PSR_AA32_E_BIT; 224 #endif 225 226 spectre_v4_enable_task_mitigation(current); 227 regs->compat_sp = sp; 228 } 229 #endif 230 231 static inline bool is_ttbr0_addr(unsigned long addr) 232 { 233 /* entry assembly clears tags for TTBR0 addrs */ 234 return addr < TASK_SIZE; 235 } 236 237 static inline bool is_ttbr1_addr(unsigned long addr) 238 { 239 /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */ 240 return arch_kasan_reset_tag(addr) >= PAGE_OFFSET; 241 } 242 243 /* Forward declaration, a strange C thing */ 244 struct task_struct; 245 246 /* Free all resources held by a thread. */ 247 extern void release_thread(struct task_struct *); 248 249 unsigned long get_wchan(struct task_struct *p); 250 251 /* Thread switching */ 252 extern struct task_struct *cpu_switch_to(struct task_struct *prev, 253 struct task_struct *next); 254 255 #define task_pt_regs(p) \ 256 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1) 257 258 #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc) 259 #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) 260 261 /* 262 * Prefetching support 263 */ 264 #define ARCH_HAS_PREFETCH 265 static inline void prefetch(const void *ptr) 266 { 267 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr)); 268 } 269 270 #define ARCH_HAS_PREFETCHW 271 static inline void prefetchw(const void *ptr) 272 { 273 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr)); 274 } 275 276 #define ARCH_HAS_SPINLOCK_PREFETCH 277 static inline void spin_lock_prefetch(const void *ptr) 278 { 279 asm volatile(ARM64_LSE_ATOMIC_INSN( 280 "prfm pstl1strm, %a0", 281 "nop") : : "p" (ptr)); 282 } 283 284 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */ 285 extern void __init minsigstksz_setup(void); 286 287 /* 288 * Not at the top of the file due to a direct #include cycle between 289 * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include 290 * ensures that contents of processor.h are visible to fpsimd.h even if 291 * processor.h is included first. 292 * 293 * These prctl helpers are the only things in this file that require 294 * fpsimd.h. The core code expects them to be in this header. 295 */ 296 #include <asm/fpsimd.h> 297 298 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */ 299 #define SVE_SET_VL(arg) sve_set_current_vl(arg) 300 #define SVE_GET_VL() sve_get_current_vl() 301 302 /* PR_PAC_RESET_KEYS prctl */ 303 #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg) 304 305 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI 306 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */ 307 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg); 308 long get_tagged_addr_ctrl(struct task_struct *task); 309 #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg) 310 #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current) 311 #endif 312 313 /* 314 * For CONFIG_GCC_PLUGIN_STACKLEAK 315 * 316 * These need to be macros because otherwise we get stuck in a nightmare 317 * of header definitions for the use of task_stack_page. 318 */ 319 320 #define current_top_of_stack() \ 321 ({ \ 322 struct stack_info _info; \ 323 BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info)); \ 324 _info.high; \ 325 }) 326 #define on_thread_stack() (on_task_stack(current, current_stack_pointer, NULL)) 327 328 #endif /* __ASSEMBLY__ */ 329 #endif /* __ASM_PROCESSOR_H */ 330