xref: /linux/arch/arm64/include/asm/pgtable-prot.h (revision 4745dc8abb0a0a9851c07265eea01d844886d5c8)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2016 ARM Ltd.
4  */
5 #ifndef __ASM_PGTABLE_PROT_H
6 #define __ASM_PGTABLE_PROT_H
7 
8 #include <asm/memory.h>
9 #include <asm/pgtable-hwdef.h>
10 
11 #include <linux/const.h>
12 
13 /*
14  * Software defined PTE bits definition.
15  */
16 #define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */
17 #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
18 #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
19 #define PTE_PROT_NONE		(_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
20 
21 #ifndef __ASSEMBLY__
22 
23 #include <asm/pgtable-types.h>
24 
25 #define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
26 #define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
27 
28 #define PTE_MAYBE_NG		(arm64_kernel_use_ng_mappings() ? PTE_NG : 0)
29 #define PMD_MAYBE_NG		(arm64_kernel_use_ng_mappings() ? PMD_SECT_NG : 0)
30 
31 #define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
32 #define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
33 
34 #define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
35 #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
36 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
37 #define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
38 #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
39 
40 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
41 #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
42 #define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
43 
44 #define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
45 #define _HYP_PAGE_DEFAULT	_PAGE_DEFAULT
46 
47 #define PAGE_KERNEL		__pgprot(PROT_NORMAL)
48 #define PAGE_KERNEL_RO		__pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
49 #define PAGE_KERNEL_ROX		__pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
50 #define PAGE_KERNEL_EXEC	__pgprot(PROT_NORMAL & ~PTE_PXN)
51 #define PAGE_KERNEL_EXEC_CONT	__pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
52 
53 #define PAGE_HYP		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN)
54 #define PAGE_HYP_EXEC		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY)
55 #define PAGE_HYP_RO		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN)
56 #define PAGE_HYP_DEVICE		__pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
57 
58 #define PAGE_S2_MEMATTR(attr)						\
59 	({								\
60 		u64 __val;						\
61 		if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))		\
62 			__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr);	\
63 		else							\
64 			__val = PTE_S2_MEMATTR(MT_S2_ ## attr);		\
65 		__val;							\
66 	 })
67 
68 #define PAGE_S2_XN							\
69 	({								\
70 		u64 __val;						\
71 		if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))		\
72 			__val = 0;					\
73 		else							\
74 			__val = PTE_S2_XN;				\
75 		__val;							\
76 	})
77 
78 #define PAGE_S2			__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
79 #define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
80 
81 #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
82 #define PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
83 #define PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
84 #define PAGE_READONLY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
85 #define PAGE_READONLY_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
86 #define PAGE_EXECONLY		__pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
87 
88 #define __P000  PAGE_NONE
89 #define __P001  PAGE_READONLY
90 #define __P010  PAGE_READONLY
91 #define __P011  PAGE_READONLY
92 #define __P100  PAGE_EXECONLY
93 #define __P101  PAGE_READONLY_EXEC
94 #define __P110  PAGE_READONLY_EXEC
95 #define __P111  PAGE_READONLY_EXEC
96 
97 #define __S000  PAGE_NONE
98 #define __S001  PAGE_READONLY
99 #define __S010  PAGE_SHARED
100 #define __S011  PAGE_SHARED
101 #define __S100  PAGE_EXECONLY
102 #define __S101  PAGE_READONLY_EXEC
103 #define __S110  PAGE_SHARED_EXEC
104 #define __S111  PAGE_SHARED_EXEC
105 
106 #endif /* __ASSEMBLY__ */
107 
108 #endif /* __ASM_PGTABLE_PROT_H */
109